1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef STM32G0xx_LL_RCC_H
20 #define STM32G0xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32g0xx.h"
28
29 /** @addtogroup STM32G0xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
42 * @{
43 */
44
45
46 /**
47 * @}
48 */
49
50 /* Private constants ---------------------------------------------------------*/
51 /* Private macros ------------------------------------------------------------*/
52 #if defined(USE_FULL_LL_DRIVER)
53 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
54 * @{
55 */
56 /**
57 * @}
58 */
59 #endif /*USE_FULL_LL_DRIVER*/
60
61 /* Exported types ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
64 * @{
65 */
66
67 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
68 * @{
69 */
70
71 /**
72 * @brief RCC Clocks Frequency Structure
73 */
74 typedef struct
75 {
76 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
77 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
78 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
79 } LL_RCC_ClocksTypeDef;
80
81 /**
82 * @}
83 */
84
85 /**
86 * @}
87 */
88 #endif /* USE_FULL_LL_DRIVER */
89
90 /* Exported constants --------------------------------------------------------*/
91 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
92 * @{
93 */
94
95 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
96 * @brief Defines used to adapt values of different oscillators
97 * @note These values could be modified in the user environment according to
98 * HW set-up.
99 * @{
100 */
101 #if !defined (HSE_VALUE)
102 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
103 #endif /* HSE_VALUE */
104
105 #if !defined (HSI_VALUE)
106 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
107 #endif /* HSI_VALUE */
108
109 #if !defined (LSE_VALUE)
110 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
111 #endif /* LSE_VALUE */
112
113 #if !defined (LSI_VALUE)
114 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
115 #endif /* LSI_VALUE */
116 #if !defined (EXTERNAL_CLOCK_VALUE)
117 #define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */
118 #endif /* EXTERNAL_CLOCK_VALUE */
119
120 #if defined(RCC_HSI48_SUPPORT)
121 #if !defined (HSI48_VALUE)
122 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
123 #endif /* HSI48_VALUE */
124 #endif /* RCC_HSI48_SUPPORT */
125 /**
126 * @}
127 */
128
129 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
130 * @brief Flags defines which can be used with LL_RCC_WriteReg function
131 * @{
132 */
133 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
134 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
135 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
136 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
137 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
138 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
139 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
140 #if defined(RCC_HSI48_SUPPORT)
141 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
142 #endif /* RCC_HSI48_SUPPORT */
143 /**
144 * @}
145 */
146
147 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
148 * @brief Flags defines which can be used with LL_RCC_ReadReg function
149 * @{
150 */
151 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
152 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
153 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
154 #if defined(RCC_HSI48_SUPPORT)
155 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
156 #endif /* RCC_HSI48_SUPPORT */
157 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
158 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
159 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
160 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
161 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
162 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
163 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
164 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
165 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
166 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
167 #define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */
168 /**
169 * @}
170 */
171
172 /** @defgroup RCC_LL_EC_IT IT Defines
173 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
174 * @{
175 */
176 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
177 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
178 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
179 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
180 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
181 #if defined(RCC_HSI48_SUPPORT)
182 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
183 #endif /* RCC_HSI48_SUPPORT */
184 /**
185 * @}
186 */
187
188 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
189 * @{
190 */
191 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
192 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
193 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
194 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
195 /**
196 * @}
197 */
198
199 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
200 * @{
201 */
202 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
203 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
204 /**
205 * @}
206 */
207
208 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
209 * @{
210 */
211 #define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */
212 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */
213 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1 /*!< PLL selection as system clock */
214 #define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */
215 #define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */
216 /**
217 * @}
218 */
219
220 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
221 * @{
222 */
223 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */
224 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */
225 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1 /*!< PLL used as system clock */
226 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */
227 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */
228 /**
229 * @}
230 */
231
232 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
233 * @{
234 */
235 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
236 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
237 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
238 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
239 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
240 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
241 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
242 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
243 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
244 /**
245 * @}
246 */
247
248 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
249 * @{
250 */
251 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */
252 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */
253 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */
254 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */
255 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
256 /**
257 * @}
258 */
259
260 /** @defgroup RCC_LL_EC_HSI_DIV HSI division factor
261 * @{
262 */
263 #define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */
264 #define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */
265 #define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */
266 #define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */
267 #define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */
268 #define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */
269 #define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */
270 #define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */
271 /**
272 * @}
273 */
274
275 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
276 * @{
277 */
278 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
279 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
280 #if defined(RCC_HSI48_SUPPORT)
281 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 selection as MCO1 source */
282 #endif /* RCC_HSI48_SUPPORT */
283 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
284 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
285 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
286 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
287 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
288 #if defined(RCC_CFGR_MCOSEL_3)
289 #define LL_RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK selection as MCO1 source */
290 #define LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK selection as MCO1 source */
291 #define LL_RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selection as MCO1 source */
292 #define LL_RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */
293 #endif /* RCC_CFGR_MCOSEL_3 */
294 /**
295 * @}
296 */
297
298 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
299 * @{
300 */
301 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */
302 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */
303 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */
304 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */
305 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */
306 #define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */
307 #define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */
308 #define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */
309 #if defined(RCC_CFGR_MCOPRE_3)
310 #define LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */
311 #define LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */
312 #define LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024 */
313 #endif /* RCC_CFGR_MCOPRE_3 */
314 /**
315 * @}
316 */
317
318 #if defined(RCC_MCO2_SUPPORT)
319 /** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection
320 * @{
321 */
322 #define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
323 #define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */
324 #if defined(RCC_HSI48_SUPPORT)
325 #define LL_RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 /*!< HSI48 selection as MCO2 source */
326 #endif /* RCC_HSI48_SUPPORT */
327 #define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< HSI16 selection as MCO2 source */
328 #define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */
329 #define LL_RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0) /*!< Main PLL "R" clock selection as MCO2 source */
330 #define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */
331 #define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */
332 #define LL_RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLL "P" clock selection as MCO2 source */
333 #define LL_RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0) /*!< PLL "Q" clock selection as MCO2 source */
334 #define LL_RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1) /*!< RTC Clock selection as MCO2 source */
335 #define LL_RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< RTC Wakeup timer selection as MCO2 source */
336 /**
337 * @}
338 */
339
340 /** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler
341 * @{
342 */
343 #define LL_RCC_MCO2_DIV_1 0x00000000U /*!< MCO2 not divided */
344 #define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */
345 #define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */
346 #define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */
347 #define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */
348 #define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */
349 #define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */
350 #define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */
351 #define LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO2 divided by 256 */
352 #define LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 512 */
353 #define LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 1024 */
354 /**
355 * @}
356 */
357 #endif /* RCC_MCO2_SUPPORT */
358
359 #if defined(USE_FULL_LL_DRIVER)
360 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
361 * @{
362 */
363 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
364 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
365 /**
366 * @}
367 */
368 #endif /* USE_FULL_LL_DRIVER */
369
370 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
371 * @{
372 */
373 #define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART1 clock source */
374 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
375 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
376 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
377 #if defined(RCC_CCIPR_USART2SEL)
378 #define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
379 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
380 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
381 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
382 #endif /* RCC_CCIPR_USART2SEL */
383 #if defined(RCC_CCIPR_USART3SEL)
384 #define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
385 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
386 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
387 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
388 #endif /* RCC_CCIPR_USART3SEL */
389 /**
390 * @}
391 */
392
393 #if defined(LPUART1) || defined(LPUART2)
394 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
395 * @{
396 */
397 #if defined(LPUART2)
398 #define LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as LPUART2 clock source */
399 #define LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0) /*!< SYSCLK clock used as LPUART2 clock source */
400 #define LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1) /*!< HSI clock used as LPUART2 clock source */
401 #define LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL) /*!< LSE clock used as LPUART2 clock source */
402 #endif /* LPUART2 */
403 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as LPUART1 clock source */
404 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0) /*!< SYSCLK clock used as LPUART1 clock source */
405 #define LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1) /*!< HSI clock used as LPUART1 clock source */
406 #define LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL) /*!< LSE clock used as LPUART1 clock source */
407 /**
408 * @}
409 */
410 #endif /* LPUART1 || LPUART2 */
411
412 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
413 * @{
414 */
415 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */
416 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0) /*!< SYSCLK clock used as I2C1 clock source */
417 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1) /*!< HSI clock used as I2C1 clock source */
418 #if defined(RCC_CCIPR_I2C2SEL)
419 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */
420 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0) /*!< SYSCLK clock used as I2C2 clock source */
421 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1) /*!< HSI clock used as I2C2 clock source */
422 #endif /* RCC_CCIPR_I2C2SEL */
423 /**
424 * @}
425 */
426
427 /** @defgroup RCC_LL_EC_I2Sx_CLKSOURCE Peripheral I2S clock source selection
428 * @{
429 */
430 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
431 #define LL_RCC_I2S1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U) /*!< SYSCLK clock used as I2S1 clock source */
432 #define LL_RCC_I2S1_CLKSOURCE_PLL ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0) /*!< PLL clock used as I2S1 clock source */
433 #define LL_RCC_I2S1_CLKSOURCE_HSI ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1) /*!< HSI clock used as I2S1 clock source */
434 #define LL_RCC_I2S1_CLKSOURCE_PIN ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL) /*!< External clock used as I2S1 clock source */
435 #define LL_RCC_I2S2_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U) /*!< SYSCLK clock used as I2S2 clock source */
436 #define LL_RCC_I2S2_CLKSOURCE_PLL ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0) /*!< PLL clock used as I2S2 clock source */
437 #define LL_RCC_I2S2_CLKSOURCE_HSI ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1) /*!< HSI clock used as I2S2 clock source */
438 #define LL_RCC_I2S2_CLKSOURCE_PIN ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL) /*!< External clock used as I2S2 clock source */
439 #else
440 #define LL_RCC_I2S1_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as I2S1 clock source */
441 #define LL_RCC_I2S1_CLKSOURCE_PLL RCC_CCIPR_I2S1SEL_0 /*!< PLL clock used as I2S1 clock source */
442 #define LL_RCC_I2S1_CLKSOURCE_HSI RCC_CCIPR_I2S1SEL_1 /*!< HSI clock used as I2S1 clock source */
443 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CCIPR_I2S1SEL /*!< External clock used as I2S1 clock source */
444 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
445
446 /**
447 * @}
448 */
449
450 #if defined(RCC_CCIPR_TIM1SEL)
451 /** @defgroup RCC_LL_EC_TIMx_CLKSOURCE Peripheral TIM clock source selection
452 * @{
453 */
454 #define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 clock used as TIM1 clock source */
455 #define LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U)) /*!< PLL used as TIM1 clock source */
456 /**
457 * @}
458 */
459 #endif /* RCC_CCIPR_TIM1SEL */
460
461 #if defined(RCC_CCIPR_TIM15SEL)
462 /** @addtogroup RCC_LL_EC_TIMx_CLKSOURCE
463 * @{
464 */
465 #define LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U)) /*!< PCLK1 clock used as TIM15 clock source */
466 #define LL_RCC_TIM15_CLKSOURCE_PLL (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U)) /*!< PLL used as TIM15 clock source */
467 /**
468 * @}
469 */
470 #endif /* RCC_CCIPR_TIM15SEL */
471
472 #if defined(LPTIM1) && defined(LPTIM2)
473 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
474 * @{
475 */
476 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM1 clock */
477 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */
478 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI selected as LPTIM1 clock */
479 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE selected as LPTIM1 clock */
480 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM2 clock */
481 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI selected as LPTIM2 clock */
482 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI selected as LPTIM2 clock */
483 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE selected as LPTIM2 clock */
484 /**
485 * @}
486 */
487 #endif /* LPTIM1 && LPTIM2*/
488
489 #if defined(CEC)
490 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE_HSI Peripheral CEC clock source selection
491 * @{
492 */
493 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */
494 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CCIPR_CECSEL /*!< LSE oscillator clock used as CEC clock */
495
496 /**
497 * @}
498 */
499 #endif /* CEC */
500
501 #if defined(FDCAN1) || defined(FDCAN2)
502 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE_HSI Peripheral FDCAN clock source selection
503 * @{
504 */
505 #define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 oscillator clock used as FDCAN clock */
506 #define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0 /*!< PLL "Q" oscillator clock used as FDCAN clock */
507 #define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1 /*!< HSE oscillator clock used as FDCAN clock */
508
509 /**
510 * @}
511 */
512 #endif /* FDCAN1 || FDCAN2 */
513
514 #if defined(RNG)
515 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
516 * @{
517 */
518 #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock */
519 #define LL_RCC_RNG_CLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0 /*!< HSI oscillator clock divided by 8 used as RNG clock, available on cut2.0 */
520 #define LL_RCC_RNG_CLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1 /*!< SYSCLK divided by 1 used as RNG clock */
521 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_RNGSEL /*!< PLL used as RNG clock */
522 /**
523 * @}
524 */
525 #endif /* RNG */
526
527 #if defined(RNG)
528 /** @defgroup RCC_LL_EC_RNG_CLK_DIV Peripheral RNG clock division factor
529 * @{
530 */
531 #define LL_RCC_RNG_CLK_DIV1 0x00000000U /*!< RNG clock not divided */
532 #define LL_RCC_RNG_CLK_DIV2 RCC_CCIPR_RNGDIV_0 /*!< RNG clock divided by 2 */
533 #define LL_RCC_RNG_CLK_DIV4 RCC_CCIPR_RNGDIV_1 /*!< RNG clock divided by 4 */
534 #define LL_RCC_RNG_CLK_DIV8 RCC_CCIPR_RNGDIV /*!< RNG clock divided by 8 */
535 /**
536 * @}
537 */
538 #endif /* RNG */
539
540 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
541 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
542 * @{
543 */
544 #if defined(RCC_HSI48_SUPPORT)
545 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
546 #endif /* RCC_HSI48_SUPPORT */
547 #define LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL_0 /*!< PLL clock used as USB clock source */
548 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR2_USBSEL_1 /*!< PLL clock used as USB clock source */
549 /**
550 * @}
551 */
552 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
553
554 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
555 * @{
556 */
557 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */
558 #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_0 /*!< PLL used as ADC clock */
559 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI used as ADC clock */
560 /**
561 * @}
562 */
563
564 /** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source
565 * @{
566 */
567 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
568 #if defined(RCC_CCIPR_USART2SEL)
569 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
570 #endif /* RCC_CCIPR_USART2SEL */
571 #if defined(RCC_CCIPR_USART3SEL)
572 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
573 #endif /* RCC_CCIPR_USART3SEL */
574 /**
575 * @}
576 */
577
578 #if defined(LPUART1)
579 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
580 * @{
581 */
582 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
583 #if defined(LPUART2)
584 #define LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL /*!< LPUART2 Clock source selection */
585 #endif /* LPUART2 */
586 /**
587 * @}
588 */
589 #endif /* LPUART1 */
590
591 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
592 * @{
593 */
594 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */
595 #if defined(RCC_CCIPR_I2C2SEL)
596 #define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */
597 #endif /* RCC_CCIPR_I2C2SEL */
598 /**
599 * @}
600 */
601
602 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
603 * @{
604 */
605 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
606 #define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR2_I2S1SEL /*!< I2S1 Clock source selection */
607 #define LL_RCC_I2S2_CLKSOURCE RCC_CCIPR2_I2S2SEL /*!< I2S2 Clock source selection */
608 #else
609 #define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */
610 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
611 /**
612 * @}
613 */
614
615 #if defined(RCC_CCIPR_TIM1SEL)
616 /** @defgroup RCC_LL_EC_TIMx Peripheral TIMx get clock source
617 * @{
618 */
619 #define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL /*!< TIM1 Clock source selection */
620 #if defined(RCC_CCIPR_TIM15SEL)
621 #define LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL /*!< TIM15 Clock source selection */
622 #endif /* RCC_CCIPR_TIM15SEL */
623 /**
624 * @}
625 */
626 #endif /* RCC_CCIPR_TIM1SEL */
627
628 #if defined(LPTIM1) && defined(LPTIM2)
629 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
630 * @{
631 */
632 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM2 Clock source selection */
633 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
634 /**
635 * @}
636 */
637 #endif /* LPTIM1 && LPTIM2 */
638
639 #if defined(CEC)
640 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
641 * @{
642 */
643 #define LL_RCC_CEC_CLKSOURCE RCC_CCIPR_CECSEL /*!< CEC Clock source selection */
644 /**
645 * @}
646 */
647 #endif /* CEC */
648
649 #if defined(FDCAN1) || defined(FDCAN2)
650 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
651 * @{
652 */
653 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL /*!< FDCAN Clock source selection */
654 /**
655 * @}
656 */
657 #endif /* FDCAN1 */
658
659 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
660 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
661 * @{
662 */
663 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL /*!< USB Clock source selection */
664 /**
665 * @}
666 */
667 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
668
669 #if defined(RNG)
670 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
671 * @{
672 */
673 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG Clock source selection */
674 /**
675 * @}
676 */
677
678 /** @defgroup RCC_LL_EC_RNG_DIV Peripheral RNG get clock division factor
679 * @{
680 */
681 #define LL_RCC_RNG_CLKDIV RCC_CCIPR_RNGDIV /*!< RNG Clock division factor */
682 /**
683 * @}
684 */
685 #endif /* RNG */
686
687 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
688 * @{
689 */
690 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
691 /**
692 * @}
693 */
694
695 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
696 * @{
697 */
698 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
699 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
700 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
701 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
702 /**
703 * @}
704 */
705
706
707 /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
708 * @{
709 */
710 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
711 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
712 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
713 /**
714 * @}
715 */
716
717 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor (PLLM)
718 * @{
719 */
720 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
721 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 2 */
722 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 3 */
723 #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 4 */
724 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 5 */
725 #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 6 */
726 #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL division factor by 7 */
727 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL division factor by 8 */
728 /**
729 * @}
730 */
731
732 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
733 * @{
734 */
735 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
736 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
737 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
738 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
739 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
740 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
741 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
742 /**
743 * @}
744 */
745
746 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
747 * @{
748 */
749 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
750 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
751 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
752 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
753 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
754 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
755 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
756 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
757 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
758 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
759 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
760 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
761 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
762 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
763 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
764 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
765 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
766 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
767 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
768 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
769 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
770 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
771 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
772 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
773 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
774 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/
775 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
776 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
777 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
778 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
779 #define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
780 /**
781 * @}
782 */
783
784 #if defined(RCC_PLLQ_SUPPORT)
785 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
786 * @{
787 */
788 #define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */
789 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */
790 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
791 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */
792 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
793 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
794 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
795 /**
796 * @}
797 */
798 #endif /* RCC_PLLQ_SUPPORT */
799
800 /**
801 * @}
802 */
803
804 /* Exported macro ------------------------------------------------------------*/
805 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
806 * @{
807 */
808
809 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
810 * @{
811 */
812
813 /**
814 * @brief Write a value in RCC register
815 * @param __REG__ Register to be written
816 * @param __VALUE__ Value to be written in the register
817 * @retval None
818 */
819 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__))
820
821 /**
822 * @brief Read a value in RCC register
823 * @param __REG__ Register to be read
824 * @retval Register value
825 */
826 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
827 /**
828 * @}
829 */
830
831 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
832 * @{
833 */
834
835 /**
836 * @brief Helper macro to calculate the PLLCLK frequency on system domain
837 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
838 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
839 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
840 * @param __PLLM__ This parameter can be one of the following values:
841 * @arg @ref LL_RCC_PLLM_DIV_1
842 * @arg @ref LL_RCC_PLLM_DIV_2
843 * @arg @ref LL_RCC_PLLM_DIV_3
844 * @arg @ref LL_RCC_PLLM_DIV_4
845 * @arg @ref LL_RCC_PLLM_DIV_5
846 * @arg @ref LL_RCC_PLLM_DIV_6
847 * @arg @ref LL_RCC_PLLM_DIV_7
848 * @arg @ref LL_RCC_PLLM_DIV_8
849 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
850 * @param __PLLR__ This parameter can be one of the following values:
851 * @arg @ref LL_RCC_PLLR_DIV_2
852 * @arg @ref LL_RCC_PLLR_DIV_3
853 * @arg @ref LL_RCC_PLLR_DIV_4
854 * @arg @ref LL_RCC_PLLR_DIV_5
855 * @arg @ref LL_RCC_PLLR_DIV_6
856 * @arg @ref LL_RCC_PLLR_DIV_7
857 * @arg @ref LL_RCC_PLLR_DIV_8
858 * @retval PLL clock frequency (in Hz)
859 */
860 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \
861 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
862 (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
863
864 /**
865 * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain
866 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
867 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
868 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
869 * @param __PLLM__ This parameter can be one of the following values:
870 * @arg @ref LL_RCC_PLLM_DIV_1
871 * @arg @ref LL_RCC_PLLM_DIV_2
872 * @arg @ref LL_RCC_PLLM_DIV_3
873 * @arg @ref LL_RCC_PLLM_DIV_4
874 * @arg @ref LL_RCC_PLLM_DIV_5
875 * @arg @ref LL_RCC_PLLM_DIV_6
876 * @arg @ref LL_RCC_PLLM_DIV_7
877 * @arg @ref LL_RCC_PLLM_DIV_8
878 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
879 * @param __PLLP__ This parameter can be one of the following values:
880 * @arg @ref LL_RCC_PLLP_DIV_2
881 * @arg @ref LL_RCC_PLLP_DIV_3
882 * @arg @ref LL_RCC_PLLP_DIV_4
883 * @arg @ref LL_RCC_PLLP_DIV_5
884 * @arg @ref LL_RCC_PLLP_DIV_6
885 * @arg @ref LL_RCC_PLLP_DIV_7
886 * @arg @ref LL_RCC_PLLP_DIV_8
887 * @arg @ref LL_RCC_PLLP_DIV_9
888 * @arg @ref LL_RCC_PLLP_DIV_10
889 * @arg @ref LL_RCC_PLLP_DIV_11
890 * @arg @ref LL_RCC_PLLP_DIV_12
891 * @arg @ref LL_RCC_PLLP_DIV_13
892 * @arg @ref LL_RCC_PLLP_DIV_14
893 * @arg @ref LL_RCC_PLLP_DIV_15
894 * @arg @ref LL_RCC_PLLP_DIV_16
895 * @arg @ref LL_RCC_PLLP_DIV_17
896 * @arg @ref LL_RCC_PLLP_DIV_18
897 * @arg @ref LL_RCC_PLLP_DIV_19
898 * @arg @ref LL_RCC_PLLP_DIV_20
899 * @arg @ref LL_RCC_PLLP_DIV_21
900 * @arg @ref LL_RCC_PLLP_DIV_22
901 * @arg @ref LL_RCC_PLLP_DIV_23
902 * @arg @ref LL_RCC_PLLP_DIV_24
903 * @arg @ref LL_RCC_PLLP_DIV_25
904 * @arg @ref LL_RCC_PLLP_DIV_26
905 * @arg @ref LL_RCC_PLLP_DIV_27
906 * @arg @ref LL_RCC_PLLP_DIV_28
907 * @arg @ref LL_RCC_PLLP_DIV_29
908 * @arg @ref LL_RCC_PLLP_DIV_30
909 * @arg @ref LL_RCC_PLLP_DIV_31
910 * @arg @ref LL_RCC_PLLP_DIV_32
911 * @retval PLL clock frequency (in Hz)
912 */
913 #define __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
914 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
915 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
916
917 #if defined(RCC_CCIPR2_I2S2SEL)
918 /**
919 * @brief Helper macro to calculate the PLLPCLK frequency used on I2S2 domain
920 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
921 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
922 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
923 * @param __PLLM__ This parameter can be one of the following values:
924 * @arg @ref LL_RCC_PLLM_DIV_1
925 * @arg @ref LL_RCC_PLLM_DIV_2
926 * @arg @ref LL_RCC_PLLM_DIV_3
927 * @arg @ref LL_RCC_PLLM_DIV_4
928 * @arg @ref LL_RCC_PLLM_DIV_5
929 * @arg @ref LL_RCC_PLLM_DIV_6
930 * @arg @ref LL_RCC_PLLM_DIV_7
931 * @arg @ref LL_RCC_PLLM_DIV_8
932 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
933 * @param __PLLP__ This parameter can be one of the following values:
934 * @arg @ref LL_RCC_PLLP_DIV_2
935 * @arg @ref LL_RCC_PLLP_DIV_3
936 * @arg @ref LL_RCC_PLLP_DIV_4
937 * @arg @ref LL_RCC_PLLP_DIV_5
938 * @arg @ref LL_RCC_PLLP_DIV_6
939 * @arg @ref LL_RCC_PLLP_DIV_7
940 * @arg @ref LL_RCC_PLLP_DIV_8
941 * @arg @ref LL_RCC_PLLP_DIV_9
942 * @arg @ref LL_RCC_PLLP_DIV_10
943 * @arg @ref LL_RCC_PLLP_DIV_11
944 * @arg @ref LL_RCC_PLLP_DIV_12
945 * @arg @ref LL_RCC_PLLP_DIV_13
946 * @arg @ref LL_RCC_PLLP_DIV_14
947 * @arg @ref LL_RCC_PLLP_DIV_15
948 * @arg @ref LL_RCC_PLLP_DIV_16
949 * @arg @ref LL_RCC_PLLP_DIV_17
950 * @arg @ref LL_RCC_PLLP_DIV_18
951 * @arg @ref LL_RCC_PLLP_DIV_19
952 * @arg @ref LL_RCC_PLLP_DIV_20
953 * @arg @ref LL_RCC_PLLP_DIV_21
954 * @arg @ref LL_RCC_PLLP_DIV_22
955 * @arg @ref LL_RCC_PLLP_DIV_23
956 * @arg @ref LL_RCC_PLLP_DIV_24
957 * @arg @ref LL_RCC_PLLP_DIV_25
958 * @arg @ref LL_RCC_PLLP_DIV_26
959 * @arg @ref LL_RCC_PLLP_DIV_27
960 * @arg @ref LL_RCC_PLLP_DIV_28
961 * @arg @ref LL_RCC_PLLP_DIV_29
962 * @arg @ref LL_RCC_PLLP_DIV_30
963 * @arg @ref LL_RCC_PLLP_DIV_31
964 * @arg @ref LL_RCC_PLLP_DIV_32
965 * @retval PLL clock frequency (in Hz)
966 */
967 #define __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
968 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
969 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
970 #endif /* RCC_CCIPR2_I2S2SEL */
971
972 /**
973 * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain
974 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
975 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
976 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
977 * @param __PLLM__ This parameter can be one of the following values:
978 * @arg @ref LL_RCC_PLLM_DIV_1
979 * @arg @ref LL_RCC_PLLM_DIV_2
980 * @arg @ref LL_RCC_PLLM_DIV_3
981 * @arg @ref LL_RCC_PLLM_DIV_4
982 * @arg @ref LL_RCC_PLLM_DIV_5
983 * @arg @ref LL_RCC_PLLM_DIV_6
984 * @arg @ref LL_RCC_PLLM_DIV_7
985 * @arg @ref LL_RCC_PLLM_DIV_8
986 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
987 * @param __PLLP__ This parameter can be one of the following values:
988 * @arg @ref LL_RCC_PLLP_DIV_2
989 * @arg @ref LL_RCC_PLLP_DIV_3
990 * @arg @ref LL_RCC_PLLP_DIV_4
991 * @arg @ref LL_RCC_PLLP_DIV_5
992 * @arg @ref LL_RCC_PLLP_DIV_6
993 * @arg @ref LL_RCC_PLLP_DIV_7
994 * @arg @ref LL_RCC_PLLP_DIV_8
995 * @arg @ref LL_RCC_PLLP_DIV_9
996 * @arg @ref LL_RCC_PLLP_DIV_10
997 * @arg @ref LL_RCC_PLLP_DIV_11
998 * @arg @ref LL_RCC_PLLP_DIV_12
999 * @arg @ref LL_RCC_PLLP_DIV_13
1000 * @arg @ref LL_RCC_PLLP_DIV_14
1001 * @arg @ref LL_RCC_PLLP_DIV_15
1002 * @arg @ref LL_RCC_PLLP_DIV_16
1003 * @arg @ref LL_RCC_PLLP_DIV_17
1004 * @arg @ref LL_RCC_PLLP_DIV_18
1005 * @arg @ref LL_RCC_PLLP_DIV_19
1006 * @arg @ref LL_RCC_PLLP_DIV_20
1007 * @arg @ref LL_RCC_PLLP_DIV_21
1008 * @arg @ref LL_RCC_PLLP_DIV_22
1009 * @arg @ref LL_RCC_PLLP_DIV_23
1010 * @arg @ref LL_RCC_PLLP_DIV_24
1011 * @arg @ref LL_RCC_PLLP_DIV_25
1012 * @arg @ref LL_RCC_PLLP_DIV_26
1013 * @arg @ref LL_RCC_PLLP_DIV_27
1014 * @arg @ref LL_RCC_PLLP_DIV_28
1015 * @arg @ref LL_RCC_PLLP_DIV_29
1016 * @arg @ref LL_RCC_PLLP_DIV_30
1017 * @arg @ref LL_RCC_PLLP_DIV_31
1018 * @arg @ref LL_RCC_PLLP_DIV_32
1019 * @retval PLL clock frequency (in Hz)
1020 */
1021 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
1022 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1023 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
1024
1025 #if defined(RNG)
1026 /**
1027 * @brief Helper macro to calculate the PLLQCLK frequency used on RNG domain
1028 * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1029 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1030 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1031 * @param __PLLM__ This parameter can be one of the following values:
1032 * @arg @ref LL_RCC_PLLM_DIV_1
1033 * @arg @ref LL_RCC_PLLM_DIV_2
1034 * @arg @ref LL_RCC_PLLM_DIV_3
1035 * @arg @ref LL_RCC_PLLM_DIV_4
1036 * @arg @ref LL_RCC_PLLM_DIV_5
1037 * @arg @ref LL_RCC_PLLM_DIV_6
1038 * @arg @ref LL_RCC_PLLM_DIV_7
1039 * @arg @ref LL_RCC_PLLM_DIV_8
1040 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1041 * @param __PLLQ__ This parameter can be one of the following values:
1042 * @arg @ref LL_RCC_PLLQ_DIV_2
1043 * @arg @ref LL_RCC_PLLQ_DIV_3
1044 * @arg @ref LL_RCC_PLLQ_DIV_4
1045 * @arg @ref LL_RCC_PLLQ_DIV_5
1046 * @arg @ref LL_RCC_PLLQ_DIV_6
1047 * @arg @ref LL_RCC_PLLQ_DIV_7
1048 * @arg @ref LL_RCC_PLLQ_DIV_8
1049 * @retval PLL clock frequency (in Hz)
1050 */
1051 #define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1052 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1053 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1054 #endif /* RNG */
1055
1056 #if defined(RCC_PLLQ_SUPPORT)
1057 /**
1058 * @brief Helper macro to calculate the PLLQCLK frequency used on TIM1 domain
1059 * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1060 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1061 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1062 * @param __PLLM__ This parameter can be one of the following values:
1063 * @arg @ref LL_RCC_PLLM_DIV_1
1064 * @arg @ref LL_RCC_PLLM_DIV_2
1065 * @arg @ref LL_RCC_PLLM_DIV_3
1066 * @arg @ref LL_RCC_PLLM_DIV_4
1067 * @arg @ref LL_RCC_PLLM_DIV_5
1068 * @arg @ref LL_RCC_PLLM_DIV_6
1069 * @arg @ref LL_RCC_PLLM_DIV_7
1070 * @arg @ref LL_RCC_PLLM_DIV_8
1071 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1072 * @param __PLLQ__ This parameter can be one of the following values:
1073 * @arg @ref LL_RCC_PLLQ_DIV_2
1074 * @arg @ref LL_RCC_PLLQ_DIV_3
1075 * @arg @ref LL_RCC_PLLQ_DIV_4
1076 * @arg @ref LL_RCC_PLLQ_DIV_5
1077 * @arg @ref LL_RCC_PLLQ_DIV_6
1078 * @arg @ref LL_RCC_PLLQ_DIV_7
1079 * @arg @ref LL_RCC_PLLQ_DIV_8
1080 * @retval PLL clock frequency (in Hz)
1081 */
1082 #define __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1083 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1084 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1085 #if defined(TIM15)
1086 /**
1087 * @brief Helper macro to calculate the PLLQCLK frequency used on TIM15 domain
1088 * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM15_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1089 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1090 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1091 * @param __PLLM__ This parameter can be one of the following values:
1092 * @arg @ref LL_RCC_PLLM_DIV_1
1093 * @arg @ref LL_RCC_PLLM_DIV_2
1094 * @arg @ref LL_RCC_PLLM_DIV_3
1095 * @arg @ref LL_RCC_PLLM_DIV_4
1096 * @arg @ref LL_RCC_PLLM_DIV_5
1097 * @arg @ref LL_RCC_PLLM_DIV_6
1098 * @arg @ref LL_RCC_PLLM_DIV_7
1099 * @arg @ref LL_RCC_PLLM_DIV_8
1100 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1101 * @param __PLLQ__ This parameter can be one of the following values:
1102 * @arg @ref LL_RCC_PLLQ_DIV_2
1103 * @arg @ref LL_RCC_PLLQ_DIV_3
1104 * @arg @ref LL_RCC_PLLQ_DIV_4
1105 * @arg @ref LL_RCC_PLLQ_DIV_5
1106 * @arg @ref LL_RCC_PLLQ_DIV_6
1107 * @arg @ref LL_RCC_PLLQ_DIV_7
1108 * @arg @ref LL_RCC_PLLQ_DIV_8
1109 * @retval PLL clock frequency (in Hz)
1110 */
1111 #define __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1112 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1113 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1114 #endif /* TIM15 */
1115 #endif /* RCC_PLLQ_SUPPORT */
1116
1117 #if defined(FDCAN1) || defined(FDCAN2)
1118 /**
1119 * @brief Helper macro to calculate the PLLQCLK frequency used on FDCAN domain
1120 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FDCAN_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1121 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1122 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1123 * @param __PLLM__ This parameter can be one of the following values:
1124 * @arg @ref LL_RCC_PLLM_DIV_1
1125 * @arg @ref LL_RCC_PLLM_DIV_2
1126 * @arg @ref LL_RCC_PLLM_DIV_3
1127 * @arg @ref LL_RCC_PLLM_DIV_4
1128 * @arg @ref LL_RCC_PLLM_DIV_5
1129 * @arg @ref LL_RCC_PLLM_DIV_6
1130 * @arg @ref LL_RCC_PLLM_DIV_7
1131 * @arg @ref LL_RCC_PLLM_DIV_8
1132 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1133 * @param __PLLQ__ This parameter can be one of the following values:
1134 * @arg @ref LL_RCC_PLLQ_DIV_2
1135 * @arg @ref LL_RCC_PLLQ_DIV_3
1136 * @arg @ref LL_RCC_PLLQ_DIV_4
1137 * @arg @ref LL_RCC_PLLQ_DIV_5
1138 * @arg @ref LL_RCC_PLLQ_DIV_6
1139 * @arg @ref LL_RCC_PLLQ_DIV_7
1140 * @arg @ref LL_RCC_PLLQ_DIV_8
1141 * @retval PLL clock frequency (in Hz)
1142 */
1143 #define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1144 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1145 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1146 #endif /* FDCAN1 || FDCAN2 */
1147
1148 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
1149 /**
1150 * @brief Helper macro to calculate the PLLQCLK frequency used on USB domain
1151 * @note ex: @ref __LL_RCC_CALC_PLLCLK_USB_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1152 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1153 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1154 * @param __PLLM__ This parameter can be one of the following values:
1155 * @arg @ref LL_RCC_PLLM_DIV_1
1156 * @arg @ref LL_RCC_PLLM_DIV_2
1157 * @arg @ref LL_RCC_PLLM_DIV_3
1158 * @arg @ref LL_RCC_PLLM_DIV_4
1159 * @arg @ref LL_RCC_PLLM_DIV_5
1160 * @arg @ref LL_RCC_PLLM_DIV_6
1161 * @arg @ref LL_RCC_PLLM_DIV_7
1162 * @arg @ref LL_RCC_PLLM_DIV_8
1163 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1164 * @param __PLLQ__ This parameter can be one of the following values:
1165 * @arg @ref LL_RCC_PLLQ_DIV_2
1166 * @arg @ref LL_RCC_PLLQ_DIV_3
1167 * @arg @ref LL_RCC_PLLQ_DIV_4
1168 * @arg @ref LL_RCC_PLLQ_DIV_5
1169 * @arg @ref LL_RCC_PLLQ_DIV_6
1170 * @arg @ref LL_RCC_PLLQ_DIV_7
1171 * @arg @ref LL_RCC_PLLQ_DIV_8
1172 * @retval PLL clock frequency (in Hz)
1173 */
1174 #define __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1175 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1176 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1177 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
1178
1179 /**
1180 * @brief Helper macro to calculate the HCLK frequency
1181 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
1182 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1183 * @arg @ref LL_RCC_SYSCLK_DIV_1
1184 * @arg @ref LL_RCC_SYSCLK_DIV_2
1185 * @arg @ref LL_RCC_SYSCLK_DIV_4
1186 * @arg @ref LL_RCC_SYSCLK_DIV_8
1187 * @arg @ref LL_RCC_SYSCLK_DIV_16
1188 * @arg @ref LL_RCC_SYSCLK_DIV_64
1189 * @arg @ref LL_RCC_SYSCLK_DIV_128
1190 * @arg @ref LL_RCC_SYSCLK_DIV_256
1191 * @arg @ref LL_RCC_SYSCLK_DIV_512
1192 * @retval HCLK clock frequency (in Hz)
1193 */
1194 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \
1195 ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
1196
1197 /**
1198 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1199 * @param __HCLKFREQ__ HCLK frequency
1200 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1201 * @arg @ref LL_RCC_APB1_DIV_1
1202 * @arg @ref LL_RCC_APB1_DIV_2
1203 * @arg @ref LL_RCC_APB1_DIV_4
1204 * @arg @ref LL_RCC_APB1_DIV_8
1205 * @arg @ref LL_RCC_APB1_DIV_16
1206 * @retval PCLK1 clock frequency (in Hz)
1207 */
1208 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \
1209 ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU))
1210
1211 /**
1212 * @brief Helper macro to calculate the HSISYS frequency
1213 * @param __HSIDIV__ This parameter can be one of the following values:
1214 * @arg @ref LL_RCC_HSI_DIV_1
1215 * @arg @ref LL_RCC_HSI_DIV_2
1216 * @arg @ref LL_RCC_HSI_DIV_4
1217 * @arg @ref LL_RCC_HSI_DIV_8
1218 * @arg @ref LL_RCC_HSI_DIV_16
1219 * @arg @ref LL_RCC_HSI_DIV_32
1220 * @arg @ref LL_RCC_HSI_DIV_64
1221 * @arg @ref LL_RCC_HSI_DIV_128
1222 * @retval HSISYS clock frequency (in Hz)
1223 */
1224 #define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))
1225
1226 /**
1227 * @}
1228 */
1229
1230 /**
1231 * @}
1232 */
1233
1234 /* Exported functions --------------------------------------------------------*/
1235 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1236 * @{
1237 */
1238
1239 /** @defgroup RCC_LL_EF_HSE HSE
1240 * @{
1241 */
1242
1243 /**
1244 * @brief Enable the Clock Security System.
1245 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1246 * @retval None
1247 */
LL_RCC_HSE_EnableCSS(void)1248 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1249 {
1250 SET_BIT(RCC->CR, RCC_CR_CSSON);
1251 }
1252
1253 /**
1254 * @brief Enable HSE external oscillator (HSE Bypass)
1255 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1256 * @retval None
1257 */
LL_RCC_HSE_EnableBypass(void)1258 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1259 {
1260 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1261 }
1262
1263 /**
1264 * @brief Disable HSE external oscillator (HSE Bypass)
1265 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1266 * @retval None
1267 */
LL_RCC_HSE_DisableBypass(void)1268 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1269 {
1270 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1271 }
1272
1273 /**
1274 * @brief Enable HSE crystal oscillator (HSE ON)
1275 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1276 * @retval None
1277 */
LL_RCC_HSE_Enable(void)1278 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1279 {
1280 SET_BIT(RCC->CR, RCC_CR_HSEON);
1281 }
1282
1283 /**
1284 * @brief Disable HSE crystal oscillator (HSE ON)
1285 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1286 * @retval None
1287 */
LL_RCC_HSE_Disable(void)1288 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1289 {
1290 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1291 }
1292
1293 /**
1294 * @brief Check if HSE oscillator Ready
1295 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1296 * @retval State of bit (1 or 0).
1297 */
LL_RCC_HSE_IsReady(void)1298 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1299 {
1300 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
1301 }
1302
1303 /**
1304 * @}
1305 */
1306
1307 /** @defgroup RCC_LL_EF_HSI HSI
1308 * @{
1309 */
1310
1311 /**
1312 * @brief Enable HSI even in stop mode
1313 * @note HSI oscillator is forced ON even in Stop mode
1314 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1315 * @retval None
1316 */
LL_RCC_HSI_EnableInStopMode(void)1317 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1318 {
1319 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1320 }
1321
1322 /**
1323 * @brief Disable HSI in stop mode
1324 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1325 * @retval None
1326 */
LL_RCC_HSI_DisableInStopMode(void)1327 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1328 {
1329 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1330 }
1331
1332 /**
1333 * @brief Check if HSI in stop mode is enabled
1334 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1335 * @retval State of bit (1 or 0).
1336 */
LL_RCC_HSI_IsEnabledInStopMode(void)1337 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1338 {
1339 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
1340 }
1341
1342 /**
1343 * @brief Enable HSI oscillator
1344 * @rmtoll CR HSION LL_RCC_HSI_Enable
1345 * @retval None
1346 */
LL_RCC_HSI_Enable(void)1347 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1348 {
1349 SET_BIT(RCC->CR, RCC_CR_HSION);
1350 }
1351
1352 /**
1353 * @brief Disable HSI oscillator
1354 * @rmtoll CR HSION LL_RCC_HSI_Disable
1355 * @retval None
1356 */
LL_RCC_HSI_Disable(void)1357 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1358 {
1359 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1360 }
1361
1362 /**
1363 * @brief Check if HSI clock is ready
1364 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1365 * @retval State of bit (1 or 0).
1366 */
LL_RCC_HSI_IsReady(void)1367 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1368 {
1369 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1370 }
1371
1372 /**
1373 * @brief Get HSI Calibration value
1374 * @note When HSITRIM is written, HSICAL is updated with the sum of
1375 * HSITRIM and the factory trim value
1376 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1377 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1378 */
LL_RCC_HSI_GetCalibration(void)1379 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1380 {
1381 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1382 }
1383
1384 /**
1385 * @brief Set HSI Calibration trimming
1386 * @note user-programmable trimming value that is added to the HSICAL
1387 * @note Default value is 64, which, when added to the HSICAL value,
1388 * should trim the HSI to 16 MHz +/- 1 %
1389 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1390 * @param Value Between Min_Data = 0 and Max_Data = 127
1391 * @retval None
1392 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1393 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1394 {
1395 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1396 }
1397
1398 /**
1399 * @brief Get HSI Calibration trimming
1400 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1401 * @retval Between Min_Data = 0 and Max_Data = 127
1402 */
LL_RCC_HSI_GetCalibTrimming(void)1403 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1404 {
1405 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1406 }
1407
1408 /**
1409 * @}
1410 */
1411
1412 #if defined(RCC_HSI48_SUPPORT)
1413 /** @defgroup RCC_LL_EF_HSI48 HSI48
1414 * @{
1415 */
1416
1417 /**
1418 * @brief Enable HSI48
1419 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
1420 * @retval None
1421 */
LL_RCC_HSI48_Enable(void)1422 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1423 {
1424 SET_BIT(RCC->CR, RCC_CR_HSI48ON);
1425 }
1426
1427 /**
1428 * @brief Disable HSI48
1429 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
1430 * @retval None
1431 */
LL_RCC_HSI48_Disable(void)1432 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1433 {
1434 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
1435 }
1436
1437 /**
1438 * @brief Check if HSI48 oscillator Ready
1439 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
1440 * @retval State of bit (1 or 0).
1441 */
LL_RCC_HSI48_IsReady(void)1442 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1443 {
1444 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
1445 }
1446
1447 /**
1448 * @brief Get HSI48 Calibration value
1449 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1450 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1451 */
LL_RCC_HSI48_GetCalibration(void)1452 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1453 {
1454 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1455 }
1456
1457 /**
1458 * @}
1459 */
1460 #endif /* RCC_HSI48_SUPPORT */
1461
1462 /** @defgroup RCC_LL_EF_LSE LSE
1463 * @{
1464 */
1465
1466 /**
1467 * @brief Enable Low Speed External (LSE) crystal.
1468 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1469 * @retval None
1470 */
LL_RCC_LSE_Enable(void)1471 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1472 {
1473 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1474 }
1475
1476 /**
1477 * @brief Disable Low Speed External (LSE) crystal.
1478 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1479 * @retval None
1480 */
LL_RCC_LSE_Disable(void)1481 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1482 {
1483 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1484 }
1485
1486 /**
1487 * @brief Enable external clock source (LSE bypass).
1488 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1489 * @retval None
1490 */
LL_RCC_LSE_EnableBypass(void)1491 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1492 {
1493 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1494 }
1495
1496 /**
1497 * @brief Disable external clock source (LSE bypass).
1498 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1499 * @retval None
1500 */
LL_RCC_LSE_DisableBypass(void)1501 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1502 {
1503 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1504 }
1505
1506 /**
1507 * @brief Set LSE oscillator drive capability
1508 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1509 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1510 * @param LSEDrive This parameter can be one of the following values:
1511 * @arg @ref LL_RCC_LSEDRIVE_LOW
1512 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1513 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1514 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1515 * @retval None
1516 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1517 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1518 {
1519 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1520 }
1521
1522 /**
1523 * @brief Get LSE oscillator drive capability
1524 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1525 * @retval Returned value can be one of the following values:
1526 * @arg @ref LL_RCC_LSEDRIVE_LOW
1527 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1528 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1529 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1530 */
LL_RCC_LSE_GetDriveCapability(void)1531 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1532 {
1533 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1534 }
1535
1536 /**
1537 * @brief Enable Clock security system on LSE.
1538 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1539 * @retval None
1540 */
LL_RCC_LSE_EnableCSS(void)1541 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1542 {
1543 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1544 }
1545
1546 /**
1547 * @brief Disable Clock security system on LSE.
1548 * @note Clock security system can be disabled only after a LSE
1549 * failure detection. In that case it MUST be disabled by software.
1550 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1551 * @retval None
1552 */
LL_RCC_LSE_DisableCSS(void)1553 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1554 {
1555 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1556 }
1557
1558 /**
1559 * @brief Check if LSE oscillator Ready
1560 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1561 * @retval State of bit (1 or 0).
1562 */
LL_RCC_LSE_IsReady(void)1563 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1564 {
1565 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1566 }
1567
1568 /**
1569 * @brief Check if CSS on LSE failure Detection
1570 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1571 * @retval State of bit (1 or 0).
1572 */
LL_RCC_LSE_IsCSSDetected(void)1573 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1574 {
1575 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1576 }
1577
1578 /**
1579 * @}
1580 */
1581
1582 /** @defgroup RCC_LL_EF_LSI LSI
1583 * @{
1584 */
1585
1586 /**
1587 * @brief Enable LSI Oscillator
1588 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1589 * @retval None
1590 */
LL_RCC_LSI_Enable(void)1591 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1592 {
1593 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1594 }
1595
1596 /**
1597 * @brief Disable LSI Oscillator
1598 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1599 * @retval None
1600 */
LL_RCC_LSI_Disable(void)1601 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1602 {
1603 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1604 }
1605
1606 /**
1607 * @brief Check if LSI is Ready
1608 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1609 * @retval State of bit (1 or 0).
1610 */
LL_RCC_LSI_IsReady(void)1611 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1612 {
1613 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
1614 }
1615
1616 /**
1617 * @}
1618 */
1619
1620 /** @defgroup RCC_LL_EF_LSCO LSCO
1621 * @{
1622 */
1623
1624 /**
1625 * @brief Enable Low speed clock
1626 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1627 * @retval None
1628 */
LL_RCC_LSCO_Enable(void)1629 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1630 {
1631 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1632 }
1633
1634 /**
1635 * @brief Disable Low speed clock
1636 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1637 * @retval None
1638 */
LL_RCC_LSCO_Disable(void)1639 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1640 {
1641 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1642 }
1643
1644 /**
1645 * @brief Configure Low speed clock selection
1646 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
1647 * @param Source This parameter can be one of the following values:
1648 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1649 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1650 * @retval None
1651 */
LL_RCC_LSCO_SetSource(uint32_t Source)1652 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1653 {
1654 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
1655 }
1656
1657 /**
1658 * @brief Get Low speed clock selection
1659 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
1660 * @retval Returned value can be one of the following values:
1661 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1662 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1663 */
LL_RCC_LSCO_GetSource(void)1664 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1665 {
1666 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
1667 }
1668
1669 /**
1670 * @}
1671 */
1672
1673 /** @defgroup RCC_LL_EF_System System
1674 * @{
1675 */
1676
1677 /**
1678 * @brief Configure the system clock source
1679 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1680 * @param Source This parameter can be one of the following values:
1681 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1682 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1683 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1684 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI
1685 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE
1686 * @retval None
1687 */
LL_RCC_SetSysClkSource(uint32_t Source)1688 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1689 {
1690 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1691 }
1692
1693 /**
1694 * @brief Get the system clock source
1695 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1696 * @retval Returned value can be one of the following values:
1697 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1698 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1699 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1700 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI
1701 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE
1702 */
LL_RCC_GetSysClkSource(void)1703 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1704 {
1705 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1706 }
1707
1708 /**
1709 * @brief Set AHB prescaler
1710 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1711 * @param Prescaler This parameter can be one of the following values:
1712 * @arg @ref LL_RCC_SYSCLK_DIV_1
1713 * @arg @ref LL_RCC_SYSCLK_DIV_2
1714 * @arg @ref LL_RCC_SYSCLK_DIV_4
1715 * @arg @ref LL_RCC_SYSCLK_DIV_8
1716 * @arg @ref LL_RCC_SYSCLK_DIV_16
1717 * @arg @ref LL_RCC_SYSCLK_DIV_64
1718 * @arg @ref LL_RCC_SYSCLK_DIV_128
1719 * @arg @ref LL_RCC_SYSCLK_DIV_256
1720 * @arg @ref LL_RCC_SYSCLK_DIV_512
1721 * @retval None
1722 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1723 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1724 {
1725 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1726 }
1727
1728 /**
1729 * @brief Set APB1 prescaler
1730 * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler
1731 * @param Prescaler This parameter can be one of the following values:
1732 * @arg @ref LL_RCC_APB1_DIV_1
1733 * @arg @ref LL_RCC_APB1_DIV_2
1734 * @arg @ref LL_RCC_APB1_DIV_4
1735 * @arg @ref LL_RCC_APB1_DIV_8
1736 * @arg @ref LL_RCC_APB1_DIV_16
1737 * @retval None
1738 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1739 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1740 {
1741 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
1742 }
1743
1744 /**
1745 * @brief Set HSI16 division factor
1746 * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv
1747 * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
1748 * system clock source.
1749 * @param HSIDiv This parameter can be one of the following values:
1750 * @arg @ref LL_RCC_HSI_DIV_1
1751 * @arg @ref LL_RCC_HSI_DIV_2
1752 * @arg @ref LL_RCC_HSI_DIV_4
1753 * @arg @ref LL_RCC_HSI_DIV_8
1754 * @arg @ref LL_RCC_HSI_DIV_16
1755 * @arg @ref LL_RCC_HSI_DIV_32
1756 * @arg @ref LL_RCC_HSI_DIV_64
1757 * @arg @ref LL_RCC_HSI_DIV_128
1758 * @retval None
1759 */
LL_RCC_SetHSIDiv(uint32_t HSIDiv)1760 __STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv)
1761 {
1762 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv);
1763 }
1764 /**
1765 * @brief Get AHB prescaler
1766 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1767 * @retval Returned value can be one of the following values:
1768 * @arg @ref LL_RCC_SYSCLK_DIV_1
1769 * @arg @ref LL_RCC_SYSCLK_DIV_2
1770 * @arg @ref LL_RCC_SYSCLK_DIV_4
1771 * @arg @ref LL_RCC_SYSCLK_DIV_8
1772 * @arg @ref LL_RCC_SYSCLK_DIV_16
1773 * @arg @ref LL_RCC_SYSCLK_DIV_64
1774 * @arg @ref LL_RCC_SYSCLK_DIV_128
1775 * @arg @ref LL_RCC_SYSCLK_DIV_256
1776 * @arg @ref LL_RCC_SYSCLK_DIV_512
1777 */
LL_RCC_GetAHBPrescaler(void)1778 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1779 {
1780 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1781 }
1782
1783 /**
1784 * @brief Get APB1 prescaler
1785 * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler
1786 * @retval Returned value can be one of the following values:
1787 * @arg @ref LL_RCC_APB1_DIV_1
1788 * @arg @ref LL_RCC_APB1_DIV_2
1789 * @arg @ref LL_RCC_APB1_DIV_4
1790 * @arg @ref LL_RCC_APB1_DIV_8
1791 * @arg @ref LL_RCC_APB1_DIV_16
1792 */
LL_RCC_GetAPB1Prescaler(void)1793 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1794 {
1795 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
1796 }
1797
1798 /**
1799 * @brief Get HSI16 Division factor
1800 * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv
1801 * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
1802 * system clock source.
1803 * @retval Returned value can be one of the following values:
1804 * @arg @ref LL_RCC_HSI_DIV_1
1805 * @arg @ref LL_RCC_HSI_DIV_2
1806 * @arg @ref LL_RCC_HSI_DIV_4
1807 * @arg @ref LL_RCC_HSI_DIV_8
1808 * @arg @ref LL_RCC_HSI_DIV_16
1809 * @arg @ref LL_RCC_HSI_DIV_32
1810 * @arg @ref LL_RCC_HSI_DIV_64
1811 * @arg @ref LL_RCC_HSI_DIV_128
1812 */
LL_RCC_GetHSIDiv(void)1813 __STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void)
1814 {
1815 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1816 }
1817 /**
1818 * @}
1819 */
1820
1821 /** @defgroup RCC_LL_EF_MCO1 MCO1
1822 * @{
1823 */
1824
1825 /**
1826 * @brief Configure MCOx
1827 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
1828 * CFGR MCOPRE LL_RCC_ConfigMCO
1829 * @param MCOxSource This parameter can be one of the following values:
1830 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1831 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1832 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1833 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
1834 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1835 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1836 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1837 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1838 * @arg @ref LL_RCC_MCO1SOURCE_PLLPCLK (*)
1839 * @arg @ref LL_RCC_MCO1SOURCE_PLLQCLK (*)
1840 * @arg @ref LL_RCC_MCO1SOURCE_RTCCLK (*)
1841 * @arg @ref LL_RCC_MCO1SOURCE_RTC_WKUP (*)
1842 *
1843 * (*) value not defined in all devices.
1844 * @param MCOxPrescaler This parameter can be one of the following values:
1845 * @arg @ref LL_RCC_MCO1_DIV_1
1846 * @arg @ref LL_RCC_MCO1_DIV_2
1847 * @arg @ref LL_RCC_MCO1_DIV_4
1848 * @arg @ref LL_RCC_MCO1_DIV_8
1849 * @arg @ref LL_RCC_MCO1_DIV_32
1850 * @arg @ref LL_RCC_MCO1_DIV_64
1851 * @arg @ref LL_RCC_MCO1_DIV_128
1852 * @retval None
1853 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1854 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1855 {
1856 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1857 }
1858
1859 /**
1860 * @}
1861 */
1862
1863 #if defined(RCC_MCO2_SUPPORT)
1864 /** @defgroup RCC_LL_EF_MCO2 MCO2
1865 * @{
1866 */
1867
1868 /**
1869 * @brief Configure MCO2
1870 * @rmtoll CFGR MCO2SEL LL_RCC_ConfigMCO2\n
1871 * CFGR MCO2PRE LL_RCC_ConfigMCO2
1872 * @note feature not available in all devices.
1873 * @param MCOxSource This parameter can be one of the following values:
1874 * @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK
1875 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
1876 * @arg @ref LL_RCC_MCO2SOURCE_HSI
1877 * @arg @ref LL_RCC_MCO2SOURCE_HSI48
1878 * @arg @ref LL_RCC_MCO2SOURCE_HSE
1879 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
1880 * @arg @ref LL_RCC_MCO2SOURCE_LSI
1881 * @arg @ref LL_RCC_MCO2SOURCE_LSE
1882 * @arg @ref LL_RCC_MCO2SOURCE_PLLPCLK
1883 * @arg @ref LL_RCC_MCO2SOURCE_PLLQCLK
1884 * @arg @ref LL_RCC_MCO2SOURCE_RTCCLK
1885 * @arg @ref LL_RCC_MCO2SOURCE_RTC_WKUP
1886 *
1887 * @param MCOxPrescaler This parameter can be one of the following values:
1888 * @arg @ref LL_RCC_MCO2_DIV_1
1889 * @arg @ref LL_RCC_MCO2_DIV_2
1890 * @arg @ref LL_RCC_MCO2_DIV_4
1891 * @arg @ref LL_RCC_MCO2_DIV_8
1892 * @arg @ref LL_RCC_MCO2_DIV_16
1893 * @arg @ref LL_RCC_MCO2_DIV_32
1894 * @arg @ref LL_RCC_MCO2_DIV_64
1895 * @arg @ref LL_RCC_MCO2_DIV_128
1896 * @arg @ref LL_RCC_MCO2_DIV_256
1897 * @arg @ref LL_RCC_MCO2_DIV_512
1898 * @arg @ref LL_RCC_MCO2_DIV_1024
1899 * @retval None
1900 */
LL_RCC_ConfigMCO2(uint32_t MCOxSource,uint32_t MCOxPrescaler)1901 __STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1902 {
1903 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler);
1904 }
1905
1906 /**
1907 * @}
1908 */
1909 #endif /* RCC_MCO2_SUPPORT */
1910
1911 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1912 * @{
1913 */
1914
1915 /**
1916 * @brief Configure USARTx clock source
1917 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1918 * @param USARTxSource This parameter can be one of the following values:
1919 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
1920 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1921 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1922 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1923 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
1924 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
1925 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
1926 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
1927 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
1928 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
1929 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
1930 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
1931 *
1932 * (*) value not defined in all devices.
1933 * @retval None
1934 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1935 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1936 {
1937 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
1938 }
1939
1940 #if defined(LPUART1)
1941 /**
1942 * @brief Configure LPUARTx clock source
1943 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
1944 * @rmtoll CCIPR LPUART2SEL LL_RCC_SetLPUARTClockSource
1945 * @param LPUARTxSource This parameter can be one of the following values:
1946 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1947 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1948 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1949 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1950 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
1951 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
1952 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*)
1953 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*)
1954 * (*) feature not available on all devices
1955 * @retval None
1956 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1957 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1958 {
1959 MODIFY_REG(RCC->CCIPR, (LPUARTxSource >> 16U), (LPUARTxSource & 0x0000FFFFU));
1960 }
1961 #endif /* LPUART1 */
1962
1963 /**
1964 * @brief Configure I2Cx clock source
1965 * @rmtoll CCIPR I2C1SEL LL_RCC_SetI2CClockSource
1966 * @param I2CxSource This parameter can be one of the following values:
1967 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1968 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1969 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1970 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
1971 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
1972 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
1973 * (*) value not defined in all devices.
1974 * @retval None
1975 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1976 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1977 {
1978 MODIFY_REG(RCC->CCIPR, (I2CxSource >> 16U), (I2CxSource & 0x0000FFFFU));
1979 }
1980
1981 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
1982 /**
1983 * @brief Configure TIMx clock source
1984 * @rmtoll CCIPR TIMxSEL LL_RCC_SetTIMClockSource
1985 * @param TIMxSource This parameter can be one of the following values:
1986 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
1987 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
1988 * @if defined(STM32G081xx)
1989 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL
1990 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
1991 * @endif
1992 * @retval None
1993 */
LL_RCC_SetTIMClockSource(uint32_t TIMxSource)1994 __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
1995 {
1996 MODIFY_REG(RCC->CCIPR, (TIMxSource & 0xFFFF0000U), (TIMxSource << 16));
1997 }
1998 #endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */
1999
2000 #if defined(LPTIM1) && defined(LPTIM2)
2001 /**
2002 * @brief Configure LPTIMx clock source
2003 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
2004 * @param LPTIMxSource This parameter can be one of the following values:
2005 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2006 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2007 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2008 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2009 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2010 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2011 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2012 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2013 * @retval None
2014 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2015 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2016 {
2017 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
2018 }
2019 #endif /* LPTIM1 && LPTIM2 */
2020
2021 #if defined(CEC)
2022 /**
2023 * @brief Configure CEC clock source
2024 * @rmtoll CCIPR CECSEL LL_RCC_SetCECClockSource
2025 * @param CECxSource This parameter can be one of the following values:
2026 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2027 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2028 * @retval None
2029 */
LL_RCC_SetCECClockSource(uint32_t CECxSource)2030 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
2031 {
2032 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, CECxSource);
2033 }
2034 #endif /* CEC */
2035
2036 #if defined(RCC_CCIPR_RNGDIV)
2037 /**
2038 * @brief Configure RNG division factor
2039 * @rmtoll CCIPR RNGDIV LL_RCC_SetRNGClockDiv
2040 * @param RNGxDiv This parameter can be one of the following values:
2041 * @arg @ref LL_RCC_RNG_CLK_DIV1
2042 * @arg @ref LL_RCC_RNG_CLK_DIV2
2043 * @arg @ref LL_RCC_RNG_CLK_DIV4
2044 * @arg @ref LL_RCC_RNG_CLK_DIV8
2045 * @retval None
2046 */
LL_RCC_SetRNGClockDiv(uint32_t RNGxDiv)2047 __STATIC_INLINE void LL_RCC_SetRNGClockDiv(uint32_t RNGxDiv)
2048 {
2049 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, RNGxDiv);
2050 }
2051 #endif /* RNG */
2052
2053 #if defined (RCC_CCIPR_RNGSEL)
2054 /**
2055 * @brief Configure RNG clock source
2056 * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource
2057 * @param RNGxSource This parameter can be one of the following values:
2058 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
2059 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8
2060 * @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK
2061 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2062 * @retval None
2063 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)2064 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2065 {
2066 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
2067 }
2068 #endif /* RNG */
2069
2070 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2071 /**
2072 * @brief Configure USB clock source
2073 * @rmtoll CCIPR2 CK48MSEL LL_RCC_SetUSBClockSource
2074 * @param USBxSource This parameter can be one of the following values:
2075 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2076 * @arg @ref LL_RCC_USB_CLKSOURCE_HSE
2077 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2078 *
2079 * (*) value not defined in all devices.
2080 * @retval None
2081 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)2082 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2083 {
2084 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, USBxSource);
2085 }
2086 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2087
2088 #if defined (FDCAN1) || defined (FDCAN2)
2089 /**
2090 * @brief Configure FDCAN clock source
2091 * @rmtoll CCIPR2 FDCANSEL LL_RCC_SetFDCANClockSource
2092 * @param FDCANxSource This parameter can be one of the following values:
2093 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2094 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
2095 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
2096 * @retval None
2097 */
LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)2098 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
2099 {
2100 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, FDCANxSource);
2101 }
2102 #endif /* FDCAN1 || FDCAN2 */
2103
2104 /**
2105 * @brief Configure ADC clock source
2106 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
2107 * @param ADCxSource This parameter can be one of the following values:
2108 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2109 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2110 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2111 * @retval None
2112 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)2113 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
2114 {
2115 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
2116 }
2117
2118 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2119 /**
2120 * @brief Configure I2Sx clock source
2121 * @rmtoll CCIPR2 I2SxSEL LL_RCC_SetI2SClockSource
2122 * @param I2SxSource This parameter can be one of the following values:
2123 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
2124 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2125 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
2126 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
2127 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
2128 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
2129 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
2130 * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
2131 * @retval None
2132 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)2133 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
2134 {
2135 MODIFY_REG(RCC->CCIPR2, (I2SxSource >> 16U), (I2SxSource & 0x0000FFFFU));
2136 }
2137
2138 #else
2139 /**
2140 * @brief Configure I2Sx clock source
2141 * @rmtoll CCIPR I2S1SEL LL_RCC_SetI2SClockSource
2142 * @param I2SxSource This parameter can be one of the following values:
2143 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
2144 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2145 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
2146 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
2147 * @retval None
2148 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)2149 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
2150 {
2151 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource);
2152 }
2153 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2154
2155 /**
2156 * @brief Get USARTx clock source
2157 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
2158 * @param USARTx This parameter can be one of the following values:
2159 * @arg @ref LL_RCC_USART1_CLKSOURCE
2160 * @arg @ref LL_RCC_USART2_CLKSOURCE
2161 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
2162 * @retval Returned value can be one of the following values:
2163 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
2164 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2165 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2166 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2167 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
2168 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
2169 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
2170 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
2171 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
2172 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
2173 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
2174 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
2175 * (*) feature not available on all devices
2176 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2177 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2178 {
2179 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
2180 }
2181
2182 #if defined (LPUART2) || defined (LPUART1)
2183 /**
2184 * @brief Get LPUARTx clock source
2185 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource\n
2186 * CCIPR LPUART2SEL LL_RCC_GetLPUARTClockSource
2187 * @param LPUARTx This parameter can be one of the following values:
2188 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2189 * @arg @ref LL_RCC_LPUART2_CLKSOURCE (*)
2190 * @retval Returned value can be one of the following values:
2191 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2192 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2193 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2194 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2195 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
2196 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
2197 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*)
2198 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*)
2199 * (*) feature not available on all devices
2200 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)2201 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
2202 {
2203 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx) | (LPUARTx << 16U));
2204 }
2205 #endif /* LPUART2 || LPUART1 */
2206
2207 /**
2208 * @brief Get I2Cx clock source
2209 * @rmtoll CCIPR I2C1SEL LL_RCC_GetI2CClockSource\n
2210 * CCIPR I2C2SEL LL_RCC_GetI2CClockSource
2211 * @param I2Cx This parameter can be one of the following values:
2212 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2213 * @arg @ref LL_RCC_I2C2_CLKSOURCE
2214 * @retval Returned value can be one of the following values:
2215 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2216 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2217 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2218 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2219 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2220 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2221 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2222 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2223 {
2224 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx) | (I2Cx << 16U));
2225 }
2226
2227 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
2228 /**
2229 * @brief Get TIMx clock source
2230 * @rmtoll CCIPR TIMxSEL LL_RCC_GetTIMClockSource
2231 * @param TIMx This parameter can be one of the following values:
2232 * @arg @ref LL_RCC_TIM1_CLKSOURCE
2233 * @arg @ref LL_RCC_TIM15_CLKSOURCE
2234 * @retval Returned value can be one of the following values:
2235 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
2236 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
2237 * @if defined(STM32G081xx)
2238 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL
2239 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
2240 * @endif
2241 */
LL_RCC_GetTIMClockSource(uint32_t TIMx)2242 __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
2243 {
2244 return (uint32_t)((READ_BIT(RCC->CCIPR, TIMx) >> 16U) | TIMx);
2245 }
2246 #endif /* RCC_CCIPR_TIM1SEL || RCC_CCIPR_TIM15SEL */
2247
2248 #if defined(LPTIM1) && defined(LPTIM2)
2249 /**
2250 * @brief Get LPTIMx clock source
2251 * @rmtoll CCIPR LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
2252 CCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource
2253 * @param LPTIMx This parameter can be one of the following values:
2254 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2255 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2256 * @retval Returned value can be one of the following values:
2257 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2258 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2259 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2260 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2261 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2262 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2263 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2264 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2265 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2266 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2267 {
2268 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
2269 }
2270 #endif /* LPTIM1 && LPTIM2 */
2271
2272 #if defined (RCC_CCIPR_CECSEL)
2273 /**
2274 * @brief Get CEC clock source
2275 * @rmtoll CCIPR CECSEL LL_RCC_GetCECClockSource
2276 * @param CECx This parameter can be one of the following values:
2277 * @arg @ref LL_RCC_CEC_CLKSOURCE
2278 * @retval Returned value can be one of the following values:
2279 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2280 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2281 */
LL_RCC_GetCECClockSource(uint32_t CECx)2282 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
2283 {
2284 return (uint32_t)(READ_BIT(RCC->CCIPR, CECx));
2285 }
2286 #endif /* CEC */
2287
2288 #if defined(RCC_CCIPR2_FDCANSEL)
2289 /**
2290 * @brief Get FDCAN clock source
2291 * @rmtoll CCIPR2 FDCANSEL LL_RCC_GetFDCANClockSource
2292 * @param FDCANx This parameter can be one of the following values:
2293 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
2294 * @retval Returned value can be one of the following values:
2295 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
2296 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2297 */
LL_RCC_GetFDCANClockSource(uint32_t FDCANx)2298 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
2299 {
2300 return (uint32_t)(READ_BIT(RCC->CCIPR2, FDCANx));
2301 }
2302 #endif /* RCC_CCIPR2_FDCANSEL */
2303
2304 #if defined(RNG)
2305 /**
2306 * @brief Get RNGx clock source
2307 * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource
2308 * @param RNGx This parameter can be one of the following values:
2309 * @arg @ref LL_RCC_RNG_CLKSOURCE
2310 * @retval Returned value can be one of the following values:
2311 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
2312 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8
2313 * @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK
2314 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2315 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2316 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2317 {
2318 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
2319 }
2320 #endif /* RNG */
2321
2322 #if defined(RNG)
2323 /**
2324 * @brief Get RNGx clock division factor
2325 * @rmtoll CCIPR RNGDIV LL_RCC_GetRNGClockDiv
2326 * @retval Returned value can be one of the following values:
2327 * @arg @ref LL_RCC_RNG_CLK_DIV1
2328 * @arg @ref LL_RCC_RNG_CLK_DIV2
2329 * @arg @ref LL_RCC_RNG_CLK_DIV4
2330 * @arg @ref LL_RCC_RNG_CLK_DIV8
2331 */
LL_RCC_GetRNGClockDiv(void)2332 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockDiv(void)
2333 {
2334 return (uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV));
2335 }
2336 #endif /* RNG */
2337
2338 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2339 /**
2340 * @brief Get USBx clock source
2341 * @rmtoll CCIPR2 CK48MSEL LL_RCC_GetUSBClockSource
2342 * @param USBx This parameter can be one of the following values:
2343 * @arg @ref LL_RCC_USB_CLKSOURCE
2344 * @retval Returned value can be one of the following values:
2345 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2346 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2347 */
LL_RCC_GetUSBClockSource(uint32_t USBx)2348 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2349 {
2350 return (uint32_t)(READ_BIT(RCC->CCIPR2, USBx));
2351 }
2352 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2353
2354 /**
2355 * @brief Get ADCx clock source
2356 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
2357 * @param ADCx This parameter can be one of the following values:
2358 * @arg @ref LL_RCC_ADC_CLKSOURCE
2359 * @retval Returned value can be one of the following values:
2360 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2361 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2362 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2363 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2364 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2365 {
2366 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
2367 }
2368
2369 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2370 /**
2371 * @brief Get I2Sx clock source
2372 * @rmtoll CCIPR2 I2S1SEL LL_RCC_GetI2SClockSource\n
2373 * CCIPR2 I2S2SEL LL_RCC_GetI2SClockSource
2374 * @param I2Sx This parameter can be one of the following values:
2375 * @arg @ref LL_RCC_I2S1_CLKSOURCE
2376 * @arg @ref LL_RCC_I2S2_CLKSOURCE
2377 * @retval Returned value can be one of the following values:
2378 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2379 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
2380 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
2381 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
2382 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
2383 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
2384 * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
2385 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
2386 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)2387 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
2388 {
2389 return (uint32_t)(READ_BIT(RCC->CCIPR2, I2Sx) | (I2Sx << 16U));
2390 }
2391 #else
2392 /**
2393 * @brief Get I2Sx clock source
2394 * @rmtoll CCIPR I2S1SEL LL_RCC_GetI2SClockSource
2395 * @param I2Sx This parameter can be one of the following values:
2396 * @arg @ref LL_RCC_I2S1_CLKSOURCE
2397 * @retval Returned value can be one of the following values:
2398 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2399 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
2400 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
2401 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
2402 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)2403 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
2404 {
2405 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
2406 }
2407 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2408 /**
2409 * @}
2410 */
2411
2412 /** @defgroup RCC_LL_EF_RTC RTC
2413 * @{
2414 */
2415
2416 /**
2417 * @brief Set RTC Clock Source
2418 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2419 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2420 * set). The BDRST bit can be used to reset them.
2421 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2422 * @param Source This parameter can be one of the following values:
2423 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2424 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2425 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2426 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2427 * @retval None
2428 */
LL_RCC_SetRTCClockSource(uint32_t Source)2429 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2430 {
2431 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2432 }
2433
2434 /**
2435 * @brief Get RTC Clock Source
2436 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2437 * @retval Returned value can be one of the following values:
2438 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2439 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2440 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2441 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2442 */
LL_RCC_GetRTCClockSource(void)2443 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2444 {
2445 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2446 }
2447
2448 /**
2449 * @brief Enable RTC
2450 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2451 * @retval None
2452 */
LL_RCC_EnableRTC(void)2453 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2454 {
2455 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2456 }
2457
2458 /**
2459 * @brief Disable RTC
2460 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2461 * @retval None
2462 */
LL_RCC_DisableRTC(void)2463 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2464 {
2465 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2466 }
2467
2468 /**
2469 * @brief Check if RTC has been enabled or not
2470 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2471 * @retval State of bit (1 or 0).
2472 */
LL_RCC_IsEnabledRTC(void)2473 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2474 {
2475 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2476 }
2477
2478 /**
2479 * @brief Force the Backup domain reset
2480 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2481 * @retval None
2482 */
LL_RCC_ForceBackupDomainReset(void)2483 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2484 {
2485 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2486 }
2487
2488 /**
2489 * @brief Release the Backup domain reset
2490 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2491 * @retval None
2492 */
LL_RCC_ReleaseBackupDomainReset(void)2493 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2494 {
2495 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2496 }
2497
2498 /**
2499 * @}
2500 */
2501
2502
2503 /** @defgroup RCC_LL_EF_PLL PLL
2504 * @{
2505 */
2506
2507 /**
2508 * @brief Enable PLL
2509 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2510 * @retval None
2511 */
LL_RCC_PLL_Enable(void)2512 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2513 {
2514 SET_BIT(RCC->CR, RCC_CR_PLLON);
2515 }
2516
2517 /**
2518 * @brief Disable PLL
2519 * @note Cannot be disabled if the PLL clock is used as the system clock
2520 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2521 * @retval None
2522 */
LL_RCC_PLL_Disable(void)2523 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2524 {
2525 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2526 }
2527
2528 /**
2529 * @brief Check if PLL Ready
2530 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2531 * @retval State of bit (1 or 0).
2532 */
LL_RCC_PLL_IsReady(void)2533 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2534 {
2535 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2536 }
2537
2538 /**
2539 * @brief Configure PLL used for SYSCLK Domain
2540 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2541 * @note PLLN/PLLR can be written only when PLL is disabled
2542 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2543 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2544 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2545 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2546 * @param Source This parameter can be one of the following values:
2547 * @arg @ref LL_RCC_PLLSOURCE_NONE
2548 * @arg @ref LL_RCC_PLLSOURCE_HSI
2549 * @arg @ref LL_RCC_PLLSOURCE_HSE
2550 * @param PLLM This parameter can be one of the following values:
2551 * @arg @ref LL_RCC_PLLM_DIV_1
2552 * @arg @ref LL_RCC_PLLM_DIV_2
2553 * @arg @ref LL_RCC_PLLM_DIV_3
2554 * @arg @ref LL_RCC_PLLM_DIV_4
2555 * @arg @ref LL_RCC_PLLM_DIV_5
2556 * @arg @ref LL_RCC_PLLM_DIV_6
2557 * @arg @ref LL_RCC_PLLM_DIV_7
2558 * @arg @ref LL_RCC_PLLM_DIV_8
2559 * @param PLLN Between 8 and 86
2560 * @param PLLR This parameter can be one of the following values:
2561 * @arg @ref LL_RCC_PLLR_DIV_2
2562 * @arg @ref LL_RCC_PLLR_DIV_3
2563 * @arg @ref LL_RCC_PLLR_DIV_4
2564 * @arg @ref LL_RCC_PLLR_DIV_5
2565 * @arg @ref LL_RCC_PLLR_DIV_6
2566 * @arg @ref LL_RCC_PLLR_DIV_7
2567 * @arg @ref LL_RCC_PLLR_DIV_8
2568 * @retval None
2569 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2570 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2571 {
2572 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2573 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
2574 }
2575
2576 /**
2577 * @brief Configure PLL used for ADC domain clock
2578 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2579 * @note PLLN/PLLP can be written only when PLL is disabled
2580 * @note User shall verify whether the PLL configuration is not done through
2581 * other functions (ex: I2S1)
2582 * @note This can be selected for ADC
2583 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
2584 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
2585 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
2586 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC
2587 * @param Source This parameter can be one of the following values:
2588 * @arg @ref LL_RCC_PLLSOURCE_NONE
2589 * @arg @ref LL_RCC_PLLSOURCE_HSI
2590 * @arg @ref LL_RCC_PLLSOURCE_HSE
2591 * @param PLLM This parameter can be one of the following values:
2592 * @arg @ref LL_RCC_PLLM_DIV_1
2593 * @arg @ref LL_RCC_PLLM_DIV_2
2594 * @arg @ref LL_RCC_PLLM_DIV_3
2595 * @arg @ref LL_RCC_PLLM_DIV_4
2596 * @arg @ref LL_RCC_PLLM_DIV_5
2597 * @arg @ref LL_RCC_PLLM_DIV_6
2598 * @arg @ref LL_RCC_PLLM_DIV_7
2599 * @arg @ref LL_RCC_PLLM_DIV_8
2600 * @param PLLN Between 8 and 86
2601 * @param PLLP This parameter can be one of the following values:
2602 * @arg @ref LL_RCC_PLLP_DIV_2
2603 * @arg @ref LL_RCC_PLLP_DIV_3
2604 * @arg @ref LL_RCC_PLLP_DIV_4
2605 * @arg @ref LL_RCC_PLLP_DIV_5
2606 * @arg @ref LL_RCC_PLLP_DIV_6
2607 * @arg @ref LL_RCC_PLLP_DIV_7
2608 * @arg @ref LL_RCC_PLLP_DIV_8
2609 * @arg @ref LL_RCC_PLLP_DIV_9
2610 * @arg @ref LL_RCC_PLLP_DIV_10
2611 * @arg @ref LL_RCC_PLLP_DIV_11
2612 * @arg @ref LL_RCC_PLLP_DIV_12
2613 * @arg @ref LL_RCC_PLLP_DIV_13
2614 * @arg @ref LL_RCC_PLLP_DIV_14
2615 * @arg @ref LL_RCC_PLLP_DIV_15
2616 * @arg @ref LL_RCC_PLLP_DIV_16
2617 * @arg @ref LL_RCC_PLLP_DIV_17
2618 * @arg @ref LL_RCC_PLLP_DIV_18
2619 * @arg @ref LL_RCC_PLLP_DIV_19
2620 * @arg @ref LL_RCC_PLLP_DIV_20
2621 * @arg @ref LL_RCC_PLLP_DIV_21
2622 * @arg @ref LL_RCC_PLLP_DIV_22
2623 * @arg @ref LL_RCC_PLLP_DIV_23
2624 * @arg @ref LL_RCC_PLLP_DIV_24
2625 * @arg @ref LL_RCC_PLLP_DIV_25
2626 * @arg @ref LL_RCC_PLLP_DIV_26
2627 * @arg @ref LL_RCC_PLLP_DIV_27
2628 * @arg @ref LL_RCC_PLLP_DIV_28
2629 * @arg @ref LL_RCC_PLLP_DIV_29
2630 * @arg @ref LL_RCC_PLLP_DIV_30
2631 * @arg @ref LL_RCC_PLLP_DIV_31
2632 * @arg @ref LL_RCC_PLLP_DIV_32
2633 * @retval None
2634 */
LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2635 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2636 {
2637 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
2638 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2639 }
2640
2641 /**
2642 * @brief Configure PLL used for I2S1 domain clock
2643 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2644 * @note PLLN/PLLP can be written only when PLL is disabled
2645 * @note User shall verify whether the PLL configuration is not done through
2646 * other functions (ex: ADC)
2647 * @note This can be selected for I2S1
2648 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S1\n
2649 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S1\n
2650 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S1\n
2651 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S1
2652 * @param Source This parameter can be one of the following values:
2653 * @arg @ref LL_RCC_PLLSOURCE_NONE
2654 * @arg @ref LL_RCC_PLLSOURCE_HSI
2655 * @arg @ref LL_RCC_PLLSOURCE_HSE
2656 * @param PLLM This parameter can be one of the following values:
2657 * @arg @ref LL_RCC_PLLM_DIV_1
2658 * @arg @ref LL_RCC_PLLM_DIV_2
2659 * @arg @ref LL_RCC_PLLM_DIV_3
2660 * @arg @ref LL_RCC_PLLM_DIV_4
2661 * @arg @ref LL_RCC_PLLM_DIV_5
2662 * @arg @ref LL_RCC_PLLM_DIV_6
2663 * @arg @ref LL_RCC_PLLM_DIV_7
2664 * @arg @ref LL_RCC_PLLM_DIV_8
2665 * @param PLLN Between 8 and 86
2666 * @param PLLP This parameter can be one of the following values:
2667 * @arg @ref LL_RCC_PLLP_DIV_2
2668 * @arg @ref LL_RCC_PLLP_DIV_3
2669 * @arg @ref LL_RCC_PLLP_DIV_4
2670 * @arg @ref LL_RCC_PLLP_DIV_5
2671 * @arg @ref LL_RCC_PLLP_DIV_6
2672 * @arg @ref LL_RCC_PLLP_DIV_7
2673 * @arg @ref LL_RCC_PLLP_DIV_8
2674 * @arg @ref LL_RCC_PLLP_DIV_9
2675 * @arg @ref LL_RCC_PLLP_DIV_10
2676 * @arg @ref LL_RCC_PLLP_DIV_11
2677 * @arg @ref LL_RCC_PLLP_DIV_12
2678 * @arg @ref LL_RCC_PLLP_DIV_13
2679 * @arg @ref LL_RCC_PLLP_DIV_14
2680 * @arg @ref LL_RCC_PLLP_DIV_15
2681 * @arg @ref LL_RCC_PLLP_DIV_16
2682 * @arg @ref LL_RCC_PLLP_DIV_17
2683 * @arg @ref LL_RCC_PLLP_DIV_18
2684 * @arg @ref LL_RCC_PLLP_DIV_19
2685 * @arg @ref LL_RCC_PLLP_DIV_20
2686 * @arg @ref LL_RCC_PLLP_DIV_21
2687 * @arg @ref LL_RCC_PLLP_DIV_22
2688 * @arg @ref LL_RCC_PLLP_DIV_23
2689 * @arg @ref LL_RCC_PLLP_DIV_24
2690 * @arg @ref LL_RCC_PLLP_DIV_25
2691 * @arg @ref LL_RCC_PLLP_DIV_26
2692 * @arg @ref LL_RCC_PLLP_DIV_27
2693 * @arg @ref LL_RCC_PLLP_DIV_28
2694 * @arg @ref LL_RCC_PLLP_DIV_29
2695 * @arg @ref LL_RCC_PLLP_DIV_30
2696 * @arg @ref LL_RCC_PLLP_DIV_31
2697 * @arg @ref LL_RCC_PLLP_DIV_32
2698 * @retval None
2699 */
LL_RCC_PLL_ConfigDomain_I2S1(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2700 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2701 {
2702 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
2703 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2704 }
2705
2706 #if defined(RCC_CCIPR2_I2S2SEL)
2707 /**
2708 * @brief Configure PLL used for I2S2 domain clock
2709 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2710 * @note PLLN/PLLP can be written only when PLL is disabled
2711 * @note User shall verify whether the PLL configuration is not done through
2712 * other functions (ex: ADC)
2713 * @note This can be selected for I2S2
2714 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S2\n
2715 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S2\n
2716 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S2\n
2717 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S2
2718 * @param Source This parameter can be one of the following values:
2719 * @arg @ref LL_RCC_PLLSOURCE_NONE
2720 * @arg @ref LL_RCC_PLLSOURCE_HSI
2721 * @arg @ref LL_RCC_PLLSOURCE_HSE
2722 * @param PLLM This parameter can be one of the following values:
2723 * @arg @ref LL_RCC_PLLM_DIV_1
2724 * @arg @ref LL_RCC_PLLM_DIV_2
2725 * @arg @ref LL_RCC_PLLM_DIV_3
2726 * @arg @ref LL_RCC_PLLM_DIV_4
2727 * @arg @ref LL_RCC_PLLM_DIV_5
2728 * @arg @ref LL_RCC_PLLM_DIV_6
2729 * @arg @ref LL_RCC_PLLM_DIV_7
2730 * @arg @ref LL_RCC_PLLM_DIV_8
2731 * @param PLLN Between 8 and 86
2732 * @param PLLP This parameter can be one of the following values:
2733 * @arg @ref LL_RCC_PLLP_DIV_2
2734 * @arg @ref LL_RCC_PLLP_DIV_3
2735 * @arg @ref LL_RCC_PLLP_DIV_4
2736 * @arg @ref LL_RCC_PLLP_DIV_5
2737 * @arg @ref LL_RCC_PLLP_DIV_6
2738 * @arg @ref LL_RCC_PLLP_DIV_7
2739 * @arg @ref LL_RCC_PLLP_DIV_8
2740 * @arg @ref LL_RCC_PLLP_DIV_9
2741 * @arg @ref LL_RCC_PLLP_DIV_10
2742 * @arg @ref LL_RCC_PLLP_DIV_11
2743 * @arg @ref LL_RCC_PLLP_DIV_12
2744 * @arg @ref LL_RCC_PLLP_DIV_13
2745 * @arg @ref LL_RCC_PLLP_DIV_14
2746 * @arg @ref LL_RCC_PLLP_DIV_15
2747 * @arg @ref LL_RCC_PLLP_DIV_16
2748 * @arg @ref LL_RCC_PLLP_DIV_17
2749 * @arg @ref LL_RCC_PLLP_DIV_18
2750 * @arg @ref LL_RCC_PLLP_DIV_19
2751 * @arg @ref LL_RCC_PLLP_DIV_20
2752 * @arg @ref LL_RCC_PLLP_DIV_21
2753 * @arg @ref LL_RCC_PLLP_DIV_22
2754 * @arg @ref LL_RCC_PLLP_DIV_23
2755 * @arg @ref LL_RCC_PLLP_DIV_24
2756 * @arg @ref LL_RCC_PLLP_DIV_25
2757 * @arg @ref LL_RCC_PLLP_DIV_26
2758 * @arg @ref LL_RCC_PLLP_DIV_27
2759 * @arg @ref LL_RCC_PLLP_DIV_28
2760 * @arg @ref LL_RCC_PLLP_DIV_29
2761 * @arg @ref LL_RCC_PLLP_DIV_30
2762 * @arg @ref LL_RCC_PLLP_DIV_31
2763 * @arg @ref LL_RCC_PLLP_DIV_32
2764 * @retval None
2765 */
LL_RCC_PLL_ConfigDomain_I2S2(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2766 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S2(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2767 {
2768 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
2769 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2770 }
2771 #endif /* RCC_CCIPR2_I2S2SEL */
2772
2773 #if defined(RNG)
2774 /**
2775 * @brief Configure PLL used for RNG domain clock
2776 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2777 * @note PLLN/PLLQ can be written only when PLL is disabled
2778 * @note User shall verify whether the PLL configuration is not done through
2779 * other functions (ex: TIM1, TIM15)
2780 * @note This can be selected for RNG
2781 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_RNG\n
2782 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_RNG\n
2783 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_RNG\n
2784 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_RNG
2785 * @param Source This parameter can be one of the following values:
2786 * @arg @ref LL_RCC_PLLSOURCE_NONE
2787 * @arg @ref LL_RCC_PLLSOURCE_HSI
2788 * @arg @ref LL_RCC_PLLSOURCE_HSE
2789 * @param PLLM This parameter can be one of the following values:
2790 * @arg @ref LL_RCC_PLLM_DIV_1
2791 * @arg @ref LL_RCC_PLLM_DIV_2
2792 * @arg @ref LL_RCC_PLLM_DIV_3
2793 * @arg @ref LL_RCC_PLLM_DIV_4
2794 * @arg @ref LL_RCC_PLLM_DIV_5
2795 * @arg @ref LL_RCC_PLLM_DIV_6
2796 * @arg @ref LL_RCC_PLLM_DIV_7
2797 * @arg @ref LL_RCC_PLLM_DIV_8
2798 * @param PLLN Between 8 and 86
2799 * @param PLLQ This parameter can be one of the following values:
2800 * @arg @ref LL_RCC_PLLQ_DIV_2
2801 * @arg @ref LL_RCC_PLLQ_DIV_3
2802 * @arg @ref LL_RCC_PLLQ_DIV_4
2803 * @arg @ref LL_RCC_PLLQ_DIV_5
2804 * @arg @ref LL_RCC_PLLQ_DIV_6
2805 * @arg @ref LL_RCC_PLLQ_DIV_7
2806 * @arg @ref LL_RCC_PLLQ_DIV_8
2807 * @retval None
2808 */
LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2809 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2810 {
2811 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2812 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2813 }
2814 #endif /* RNG */
2815
2816 #if defined(FDCAN1) || defined(FDCAN2)
2817 /**
2818 * @brief Configure PLL used for FDCAN domain clock
2819 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2820 * @note PLLN/PLLQ can be written only when PLL is disabled
2821 * @note User shall verify whether the PLL configuration is not done through
2822 * other functions (ex: TIM1, TIM15)
2823 * @note This can be selected for FDCAN
2824 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_FDCAN\n
2825 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_FDCAN\n
2826 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_FDCAN\n
2827 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_FDCAN
2828 * @param Source This parameter can be one of the following values:
2829 * @arg @ref LL_RCC_PLLSOURCE_NONE
2830 * @arg @ref LL_RCC_PLLSOURCE_HSI
2831 * @arg @ref LL_RCC_PLLSOURCE_HSE
2832 * @param PLLM This parameter can be one of the following values:
2833 * @arg @ref LL_RCC_PLLM_DIV_1
2834 * @arg @ref LL_RCC_PLLM_DIV_2
2835 * @arg @ref LL_RCC_PLLM_DIV_3
2836 * @arg @ref LL_RCC_PLLM_DIV_4
2837 * @arg @ref LL_RCC_PLLM_DIV_5
2838 * @arg @ref LL_RCC_PLLM_DIV_6
2839 * @arg @ref LL_RCC_PLLM_DIV_7
2840 * @arg @ref LL_RCC_PLLM_DIV_8
2841 * @param PLLN Between 8 and 86
2842 * @param PLLQ This parameter can be one of the following values:
2843 * @arg @ref LL_RCC_PLLQ_DIV_2
2844 * @arg @ref LL_RCC_PLLQ_DIV_3
2845 * @arg @ref LL_RCC_PLLQ_DIV_4
2846 * @arg @ref LL_RCC_PLLQ_DIV_5
2847 * @arg @ref LL_RCC_PLLQ_DIV_6
2848 * @arg @ref LL_RCC_PLLQ_DIV_7
2849 * @arg @ref LL_RCC_PLLQ_DIV_8
2850 * @retval None
2851 */
LL_RCC_PLL_ConfigDomain_FDCAN(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2852 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_FDCAN(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2853 {
2854 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2855 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2856 }
2857 #endif /* FDCAN1 || FDCAN2 */
2858
2859 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2860 /**
2861 * @brief Configure PLL used for USB domain clock
2862 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2863 * @note PLLN/PLLQ can be written only when PLL is disabled
2864 * @note User shall verify whether the PLL configuration is not done through
2865 * other functions (ex: TIM1, TIM15)
2866 * @note This can be selected for USB
2867 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_USB\n
2868 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_USB\n
2869 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_USB\n
2870 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_USB
2871 * @param Source This parameter can be one of the following values:
2872 * @arg @ref LL_RCC_PLLSOURCE_NONE
2873 * @arg @ref LL_RCC_PLLSOURCE_HSI
2874 * @arg @ref LL_RCC_PLLSOURCE_HSE
2875 * @param PLLM This parameter can be one of the following values:
2876 * @arg @ref LL_RCC_PLLM_DIV_1
2877 * @arg @ref LL_RCC_PLLM_DIV_2
2878 * @arg @ref LL_RCC_PLLM_DIV_3
2879 * @arg @ref LL_RCC_PLLM_DIV_4
2880 * @arg @ref LL_RCC_PLLM_DIV_5
2881 * @arg @ref LL_RCC_PLLM_DIV_6
2882 * @arg @ref LL_RCC_PLLM_DIV_7
2883 * @arg @ref LL_RCC_PLLM_DIV_8
2884 * @param PLLN Between 8 and 86
2885 * @param PLLQ This parameter can be one of the following values:
2886 * @arg @ref LL_RCC_PLLQ_DIV_2
2887 * @arg @ref LL_RCC_PLLQ_DIV_3
2888 * @arg @ref LL_RCC_PLLQ_DIV_4
2889 * @arg @ref LL_RCC_PLLQ_DIV_5
2890 * @arg @ref LL_RCC_PLLQ_DIV_6
2891 * @arg @ref LL_RCC_PLLQ_DIV_7
2892 * @arg @ref LL_RCC_PLLQ_DIV_8
2893 * @retval None
2894 */
LL_RCC_PLL_ConfigDomain_USB(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2895 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_USB(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2896 {
2897 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2898 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2899 }
2900 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2901
2902 #if defined(RCC_PLLQ_SUPPORT)
2903 /**
2904 * @brief Configure PLL used for TIM1 domain clock
2905 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2906 * @note PLLN/PLLQ can be written only when PLL is disabled
2907 * @note User shall verify whether the PLL configuration is not done through
2908 * other functions (ex: RNG, TIM15)
2909 * @note This can be selected for TIM1
2910 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM1\n
2911 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM1\n
2912 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM1\n
2913 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM1
2914 * @param Source This parameter can be one of the following values:
2915 * @arg @ref LL_RCC_PLLSOURCE_NONE
2916 * @arg @ref LL_RCC_PLLSOURCE_HSI
2917 * @arg @ref LL_RCC_PLLSOURCE_HSE
2918 * @param PLLM This parameter can be one of the following values:
2919 * @arg @ref LL_RCC_PLLM_DIV_1
2920 * @arg @ref LL_RCC_PLLM_DIV_2
2921 * @arg @ref LL_RCC_PLLM_DIV_3
2922 * @arg @ref LL_RCC_PLLM_DIV_4
2923 * @arg @ref LL_RCC_PLLM_DIV_5
2924 * @arg @ref LL_RCC_PLLM_DIV_6
2925 * @arg @ref LL_RCC_PLLM_DIV_7
2926 * @arg @ref LL_RCC_PLLM_DIV_8
2927 * @param PLLN Between 8 and 86
2928 * @param PLLQ This parameter can be one of the following values:
2929 * @arg @ref LL_RCC_PLLQ_DIV_2
2930 * @arg @ref LL_RCC_PLLQ_DIV_3
2931 * @arg @ref LL_RCC_PLLQ_DIV_4
2932 * @arg @ref LL_RCC_PLLQ_DIV_5
2933 * @arg @ref LL_RCC_PLLQ_DIV_6
2934 * @arg @ref LL_RCC_PLLQ_DIV_7
2935 * @arg @ref LL_RCC_PLLQ_DIV_8
2936 * @retval None
2937 */
LL_RCC_PLL_ConfigDomain_TIM1(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2938 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2939 {
2940 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2941 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2942 }
2943 #endif /* RCC_PLLQ_SUPPORT */
2944
2945 #if defined(RCC_PLLQ_SUPPORT) && defined(TIM15)
2946 /**
2947 * @brief Configure PLL used for TIM15 domain clock
2948 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2949 * @note PLLN/PLLQ can be written only when PLL is disabled
2950 * @note User shall verify whether the PLL configuration is not done through
2951 * other functions (ex: RNG, TIM1)
2952 * @note This can be selected for TIM15
2953 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM15\n
2954 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM15\n
2955 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM15\n
2956 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM15
2957 * @param Source This parameter can be one of the following values:
2958 * @arg @ref LL_RCC_PLLSOURCE_NONE
2959 * @arg @ref LL_RCC_PLLSOURCE_HSI
2960 * @arg @ref LL_RCC_PLLSOURCE_HSE
2961 * @param PLLM This parameter can be one of the following values:
2962 * @arg @ref LL_RCC_PLLM_DIV_1
2963 * @arg @ref LL_RCC_PLLM_DIV_2
2964 * @arg @ref LL_RCC_PLLM_DIV_3
2965 * @arg @ref LL_RCC_PLLM_DIV_4
2966 * @arg @ref LL_RCC_PLLM_DIV_5
2967 * @arg @ref LL_RCC_PLLM_DIV_6
2968 * @arg @ref LL_RCC_PLLM_DIV_7
2969 * @arg @ref LL_RCC_PLLM_DIV_8
2970 * @param PLLN Between 8 and 86
2971 * @param PLLQ This parameter can be one of the following values:
2972 * @arg @ref LL_RCC_PLLQ_DIV_2
2973 * @arg @ref LL_RCC_PLLQ_DIV_3
2974 * @arg @ref LL_RCC_PLLQ_DIV_4
2975 * @arg @ref LL_RCC_PLLQ_DIV_5
2976 * @arg @ref LL_RCC_PLLQ_DIV_6
2977 * @arg @ref LL_RCC_PLLQ_DIV_7
2978 * @arg @ref LL_RCC_PLLQ_DIV_8
2979 * @retval None
2980 */
LL_RCC_PLL_ConfigDomain_TIM15(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2981 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM15(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2982 {
2983 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2984 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2985 }
2986 #endif /* RCC_PLLQ_SUPPORT && TIM15 */
2987
2988 /**
2989 * @brief Get Main PLL multiplication factor for VCO
2990 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
2991 * @retval Between 8 and 86
2992 */
LL_RCC_PLL_GetN(void)2993 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
2994 {
2995 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
2996 }
2997
2998 /**
2999 * @brief Get Main PLL division factor for PLLP
3000 * @note used for PLLPCLK (ADC & I2S clock)
3001 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
3002 * @retval Returned value can be one of the following values:
3003 * @arg @ref LL_RCC_PLLP_DIV_2
3004 * @arg @ref LL_RCC_PLLP_DIV_3
3005 * @arg @ref LL_RCC_PLLP_DIV_4
3006 * @arg @ref LL_RCC_PLLP_DIV_5
3007 * @arg @ref LL_RCC_PLLP_DIV_6
3008 * @arg @ref LL_RCC_PLLP_DIV_7
3009 * @arg @ref LL_RCC_PLLP_DIV_8
3010 * @arg @ref LL_RCC_PLLP_DIV_9
3011 * @arg @ref LL_RCC_PLLP_DIV_10
3012 * @arg @ref LL_RCC_PLLP_DIV_11
3013 * @arg @ref LL_RCC_PLLP_DIV_12
3014 * @arg @ref LL_RCC_PLLP_DIV_13
3015 * @arg @ref LL_RCC_PLLP_DIV_14
3016 * @arg @ref LL_RCC_PLLP_DIV_15
3017 * @arg @ref LL_RCC_PLLP_DIV_16
3018 * @arg @ref LL_RCC_PLLP_DIV_17
3019 * @arg @ref LL_RCC_PLLP_DIV_18
3020 * @arg @ref LL_RCC_PLLP_DIV_19
3021 * @arg @ref LL_RCC_PLLP_DIV_20
3022 * @arg @ref LL_RCC_PLLP_DIV_21
3023 * @arg @ref LL_RCC_PLLP_DIV_22
3024 * @arg @ref LL_RCC_PLLP_DIV_23
3025 * @arg @ref LL_RCC_PLLP_DIV_24
3026 * @arg @ref LL_RCC_PLLP_DIV_25
3027 * @arg @ref LL_RCC_PLLP_DIV_26
3028 * @arg @ref LL_RCC_PLLP_DIV_27
3029 * @arg @ref LL_RCC_PLLP_DIV_28
3030 * @arg @ref LL_RCC_PLLP_DIV_29
3031 * @arg @ref LL_RCC_PLLP_DIV_30
3032 * @arg @ref LL_RCC_PLLP_DIV_31
3033 * @arg @ref LL_RCC_PLLP_DIV_32
3034 */
LL_RCC_PLL_GetP(void)3035 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3036 {
3037 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
3038 }
3039
3040 #if defined(RCC_PLLQ_SUPPORT)
3041 /**
3042 * @brief Get Main PLL division factor for PLLQ
3043 * @note used for PLLQCLK selected for RNG, TIM1, TIM15 clock
3044 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3045 * @retval Returned value can be one of the following values:
3046 * @arg @ref LL_RCC_PLLQ_DIV_2
3047 * @arg @ref LL_RCC_PLLQ_DIV_3
3048 * @arg @ref LL_RCC_PLLQ_DIV_4
3049 * @arg @ref LL_RCC_PLLQ_DIV_5
3050 * @arg @ref LL_RCC_PLLQ_DIV_6
3051 * @arg @ref LL_RCC_PLLQ_DIV_7
3052 * @arg @ref LL_RCC_PLLQ_DIV_8
3053 */
LL_RCC_PLL_GetQ(void)3054 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3055 {
3056 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3057 }
3058 #endif /* RCC_PLLQ_SUPPORT */
3059
3060 /**
3061 * @brief Get Main PLL division factor for PLLR
3062 * @note used for PLLCLK (system clock)
3063 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3064 * @retval Returned value can be one of the following values:
3065 * @arg @ref LL_RCC_PLLR_DIV_2
3066 * @arg @ref LL_RCC_PLLR_DIV_3
3067 * @arg @ref LL_RCC_PLLR_DIV_4
3068 * @arg @ref LL_RCC_PLLR_DIV_5
3069 * @arg @ref LL_RCC_PLLR_DIV_6
3070 * @arg @ref LL_RCC_PLLR_DIV_7
3071 * @arg @ref LL_RCC_PLLR_DIV_8
3072 */
LL_RCC_PLL_GetR(void)3073 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3074 {
3075 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3076 }
3077
3078 /**
3079 * @brief Configure PLL clock source
3080 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3081 * @param PLLSource This parameter can be one of the following values:
3082 * @arg @ref LL_RCC_PLLSOURCE_HSI
3083 * @arg @ref LL_RCC_PLLSOURCE_HSE
3084 * @retval None
3085 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3086 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3087 {
3088 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3089 }
3090
3091 /**
3092 * @brief Get the oscillator used as PLL clock source.
3093 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3094 * @retval Returned value can be one of the following values:
3095 * @arg @ref LL_RCC_PLLSOURCE_NONE
3096 * @arg @ref LL_RCC_PLLSOURCE_HSI
3097 * @arg @ref LL_RCC_PLLSOURCE_HSE
3098 */
LL_RCC_PLL_GetMainSource(void)3099 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3100 {
3101 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3102 }
3103
3104 /**
3105 * @brief Get Division factor for the main PLL and other PLL
3106 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3107 * @retval Returned value can be one of the following values:
3108 * @arg @ref LL_RCC_PLLM_DIV_1
3109 * @arg @ref LL_RCC_PLLM_DIV_2
3110 * @arg @ref LL_RCC_PLLM_DIV_3
3111 * @arg @ref LL_RCC_PLLM_DIV_4
3112 * @arg @ref LL_RCC_PLLM_DIV_5
3113 * @arg @ref LL_RCC_PLLM_DIV_6
3114 * @arg @ref LL_RCC_PLLM_DIV_7
3115 * @arg @ref LL_RCC_PLLM_DIV_8
3116 */
LL_RCC_PLL_GetDivider(void)3117 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3118 {
3119 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3120 }
3121
3122 /**
3123 * @brief Enable PLL output mapped on ADC domain clock
3124 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
3125 * @note User shall check that PLL enable is not done through
3126 * other functions (ex: I2S1)
3127 * @retval None
3128 */
LL_RCC_PLL_EnableDomain_ADC(void)3129 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
3130 {
3131 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3132 }
3133
3134 /**
3135 * @brief Disable PLL output mapped on ADC domain clock
3136 * @note Cannot be disabled if the PLL clock is used as the system clock
3137 * @note User shall check that PLL is not used by any other peripheral
3138 * (ex: I2S1)
3139 * @note In order to save power, when the PLLCLK of the PLL is
3140 * not used, should be 0
3141 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
3142 * @retval None
3143 */
LL_RCC_PLL_DisableDomain_ADC(void)3144 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
3145 {
3146 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3147 }
3148
3149 /**
3150 * @brief Check if PLL output mapped on ADC domain clock is enabled
3151 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
3152 * @retval State of bit (1 or 0).
3153 */
LL_RCC_PLL_IsEnabledDomain_ADC(void)3154 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
3155 {
3156 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3157 }
3158
3159 /**
3160 * @brief Enable PLL output mapped on I2S domain clock
3161 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S1
3162 * @note User shall check that PLL enable is not done through
3163 * other functions (ex: ADC)
3164 * @retval None
3165 */
LL_RCC_PLL_EnableDomain_I2S1(void)3166 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1(void)
3167 {
3168 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3169 }
3170
3171 #if defined(RCC_CCIPR2_I2S2SEL)
3172 /**
3173 * @brief Enable PLL output mapped on I2S2 domain clock
3174 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S2
3175 * @note User shall check that PLL enable is not done through
3176 * other functions (ex: ADC)
3177 * @retval None
3178 */
LL_RCC_PLL_EnableDomain_I2S2(void)3179 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S2(void)
3180 {
3181 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3182 }
3183 #endif /* RCC_CCIPR2_I2S2SEL */
3184
3185 /**
3186 * @brief Disable PLL output mapped on I2S1 domain clock
3187 * @note Cannot be disabled if the PLL clock is used as the system clock
3188 * @note User shall check that PLL is not used by any other peripheral
3189 * (ex: RNG)
3190 * @note In order to save power, when the PLLCLK of the PLL is
3191 * not used, should be 0
3192 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S1
3193 * @retval None
3194 */
LL_RCC_PLL_DisableDomain_I2S1(void)3195 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S1(void)
3196 {
3197 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3198 }
3199
3200 /**
3201 * @brief Check if PLL output mapped on I2S1 domain clock is enabled
3202 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_I2S1
3203 * @retval State of bit (1 or 0).
3204 */
LL_RCC_PLL_IsEnabledDomain_I2S1(void)3205 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S1(void)
3206 {
3207 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3208 }
3209
3210 #if defined(RCC_CCIPR2_I2S2SEL)
3211 /**
3212 * @brief Disable PLL output mapped on I2S2 domain clock
3213 * @note Cannot be disabled if the PLL clock is used as the system clock
3214 * @note User shall check that PLL is not used by any other peripheral
3215 * (ex: RNG)
3216 * @note In order to save power, when the PLLCLK of the PLL is
3217 * not used, should be 0
3218 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S2
3219 * @retval None
3220 */
LL_RCC_PLL_DisableDomain_I2S2(void)3221 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S2(void)
3222 {
3223 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3224 }
3225
3226 /**
3227 * @brief Check if PLL output mapped on I2S2 domain clock is enabled
3228 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_I2S2
3229 * @retval State of bit (1 or 0).
3230 */
LL_RCC_PLL_IsEnabledDomain_I2S2(void)3231 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S2(void)
3232 {
3233 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3234 }
3235 #endif /* RCC_CCIPR2_I2S2SEL */
3236
3237 #if defined(RNG)
3238 /**
3239 * @brief Enable PLL output mapped on RNG domain clock
3240 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_RNG
3241 * @note User shall check that PLL enable is not done through
3242 * other functions (ex: TIM1, TIM15)
3243 * @retval None
3244 */
LL_RCC_PLL_EnableDomain_RNG(void)3245 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void)
3246 {
3247 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3248 }
3249
3250 /**
3251 * @brief Disable PLL output mapped on RNG domain clock
3252 * @note Cannot be disabled if the PLL clock is used as the system clock
3253 * @note User shall check that PLL is not used by any other peripheral
3254 * (ex: TIM, TIM15)
3255 * @note In order to save power, when the PLLCLK of the PLL is
3256 * not used, should be 0
3257 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_RNG
3258 * @retval None
3259 */
LL_RCC_PLL_DisableDomain_RNG(void)3260 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void)
3261 {
3262 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3263 }
3264
3265 /**
3266 * @brief Check if PLL output mapped on RNG domain clock is enabled
3267 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_RNG
3268 * @retval State of bit (1 or 0).
3269 */
LL_RCC_PLL_IsEnabledDomain_RNG(void)3270 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_RNG(void)
3271 {
3272 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3273 }
3274 #endif /* RNG */
3275
3276 #if defined(FDCAN1) || defined(FDCAN2)
3277 /**
3278 * @brief Enable PLL output mapped on FDCAN domain clock
3279 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_FDCAN
3280 * @note User shall check that PLL enable is not done through
3281 * other functions (ex: TIM1, TIM15)
3282 * @retval None
3283 */
LL_RCC_PLL_EnableDomain_FDCAN(void)3284 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_FDCAN(void)
3285 {
3286 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3287 }
3288
3289 /**
3290 * @brief Disable PLL output mapped on FDCAN domain clock
3291 * @note Cannot be disabled if the PLL clock is used as the system clock
3292 * @note User shall check that PLL is not used by any other peripheral
3293 * (ex: TIM, TIM15)
3294 * @note In order to save power, when the PLLCLK of the PLL is
3295 * not used, should be 0
3296 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_FDCAN
3297 * @retval None
3298 */
LL_RCC_PLL_DisableDomain_FDCAN(void)3299 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_FDCAN(void)
3300 {
3301 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3302 }
3303
3304 /**
3305 * @brief Check if PLL output mapped on FDCAN domain clock is enabled
3306 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_FDCAN
3307 * @retval State of bit (1 or 0).
3308 */
LL_RCC_PLL_IsEnabledDomain_FDCAN(void)3309 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_FDCAN(void)
3310 {
3311 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3312 }
3313 #endif /* FDCAN1 || FDCAN2 */
3314
3315 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
3316 /**
3317 * @brief Enable PLL output mapped on USB domain clock
3318 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_USB
3319 * @note User shall check that PLL enable is not done through
3320 * other functions (ex: TIM1, TIM15)
3321 * @retval None
3322 */
LL_RCC_PLL_EnableDomain_USB(void)3323 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_USB(void)
3324 {
3325 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3326 }
3327
3328 /**
3329 * @brief Disable PLL output mapped on USB domain clock
3330 * @note Cannot be disabled if the PLL clock is used as the system clock
3331 * @note User shall check that PLL is not used by any other peripheral
3332 * (ex: TIM, TIM15)
3333 * @note In order to save power, when the PLLCLK of the PLL is
3334 * not used, should be 0
3335 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_USB
3336 * @retval None
3337 */
LL_RCC_PLL_DisableDomain_USB(void)3338 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_USB(void)
3339 {
3340 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3341 }
3342
3343 /**
3344 * @brief Check if PLL output mapped on USB domain clock is enabled
3345 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_USB
3346 * @retval State of bit (1 or 0).
3347 */
LL_RCC_PLL_IsEnabledDomain_USB(void)3348 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_USB(void)
3349 {
3350 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3351 }
3352 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
3353
3354 #if defined(RCC_PLLQ_SUPPORT)
3355 /**
3356 * @brief Enable PLL output mapped on TIM1 domain clock
3357 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM1
3358 * @note User shall check that PLL enable is not done through
3359 * other functions (ex: RNG, TIM15)
3360 * @retval None
3361 */
LL_RCC_PLL_EnableDomain_TIM1(void)3362 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1(void)
3363 {
3364 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3365 }
3366
3367 /**
3368 * @brief Disable PLL output mapped on TIM1 domain clock
3369 * @note Cannot be disabled if the PLL clock is used as the system clock
3370 * @note User shall check that PLL is not used by any other peripheral
3371 * (ex: RNG, TIM15)
3372 * @note In order to save power, when the PLLCLK of the PLL is
3373 * not used, should be 0
3374 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM1
3375 * @retval None
3376 */
LL_RCC_PLL_DisableDomain_TIM1(void)3377 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM1(void)
3378 {
3379 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3380 }
3381
3382 /**
3383 * @brief Check if PLL output mapped on TIM1 domain clock is enabled
3384 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_TIM1
3385 * @retval State of bit (1 or 0).
3386 */
LL_RCC_PLL_IsEnabledDomain_TIM1(void)3387 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_TIM1(void)
3388 {
3389 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3390 }
3391 #endif /* RCC_PLLQ_SUPPORT */
3392
3393 #if defined(RCC_PLLQ_SUPPORT) && defined(TIM15)
3394 /**
3395 * @brief Enable PLL output mapped on TIM15 domain clock
3396 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM15
3397 * @note User shall check that PLL enable is not done through
3398 * other functions (ex: RNG, TIM1)
3399 * @retval None
3400 */
LL_RCC_PLL_EnableDomain_TIM15(void)3401 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15(void)
3402 {
3403 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3404 }
3405
3406 /**
3407 * @brief Disable PLL output mapped on TIM15 domain clock
3408 * @note Cannot be disabled if the PLL clock is used as the system clock
3409 * @note User shall check that PLL is not used by any other peripheral
3410 * (ex: RNG, TIM1)
3411 * @note In order to save power, when the PLLCLK of the PLL is
3412 * not used, should be 0
3413 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM15
3414 * @retval None
3415 */
LL_RCC_PLL_DisableDomain_TIM15(void)3416 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM15(void)
3417 {
3418 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3419 }
3420
3421 /**
3422 * @brief Check if PLL output mapped on TIM15 domain clock is enabled
3423 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_TIM15
3424 * @retval State of bit (1 or 0).
3425 */
LL_RCC_PLL_IsEnabledDomain_TIM15(void)3426 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_TIM15(void)
3427 {
3428 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3429 }
3430 #endif /* RCC_PLLQ_SUPPORT && TIM15 */
3431
3432 /**
3433 * @brief Enable PLL output mapped on SYSCLK domain
3434 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
3435 * @retval None
3436 */
LL_RCC_PLL_EnableDomain_SYS(void)3437 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
3438 {
3439 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3440 }
3441
3442 /**
3443 * @brief Disable PLL output mapped on SYSCLK domain
3444 * @note Cannot be disabled if the PLL clock is used as the system clock
3445 * @note In order to save power, when the PLLCLK of the PLL is
3446 * not used, Main PLL should be 0
3447 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
3448 * @retval None
3449 */
LL_RCC_PLL_DisableDomain_SYS(void)3450 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
3451 {
3452 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3453 }
3454
3455 /**
3456 * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
3457 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
3458 * @retval State of bit (1 or 0).
3459 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)3460 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
3461 {
3462 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
3463 }
3464
3465 /**
3466 * @}
3467 */
3468
3469
3470
3471 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
3472 * @{
3473 */
3474
3475 /**
3476 * @brief Clear LSI ready interrupt flag
3477 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
3478 * @retval None
3479 */
LL_RCC_ClearFlag_LSIRDY(void)3480 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
3481 {
3482 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
3483 }
3484
3485 /**
3486 * @brief Clear LSE ready interrupt flag
3487 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
3488 * @retval None
3489 */
LL_RCC_ClearFlag_LSERDY(void)3490 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
3491 {
3492 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
3493 }
3494
3495 /**
3496 * @brief Clear HSI ready interrupt flag
3497 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
3498 * @retval None
3499 */
LL_RCC_ClearFlag_HSIRDY(void)3500 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
3501 {
3502 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
3503 }
3504
3505 /**
3506 * @brief Clear HSE ready interrupt flag
3507 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
3508 * @retval None
3509 */
LL_RCC_ClearFlag_HSERDY(void)3510 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
3511 {
3512 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
3513 }
3514
3515 /**
3516 * @brief Clear PLL ready interrupt flag
3517 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
3518 * @retval None
3519 */
LL_RCC_ClearFlag_PLLRDY(void)3520 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
3521 {
3522 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
3523 }
3524
3525 #if defined(RCC_HSI48_SUPPORT)
3526 /**
3527 * @brief Clear HSI48 ready interrupt flag
3528 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
3529 * @retval None
3530 */
LL_RCC_ClearFlag_HSI48RDY(void)3531 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
3532 {
3533 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
3534 }
3535 #endif /* RCC_HSI48_SUPPORT */
3536 /**
3537 * @brief Clear Clock security system interrupt flag
3538 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
3539 * @retval None
3540 */
LL_RCC_ClearFlag_HSECSS(void)3541 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
3542 {
3543 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
3544 }
3545
3546 /**
3547 * @brief Clear LSE Clock security system interrupt flag
3548 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
3549 * @retval None
3550 */
LL_RCC_ClearFlag_LSECSS(void)3551 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
3552 {
3553 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
3554 }
3555
3556 /**
3557 * @brief Check if LSI ready interrupt occurred or not
3558 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
3559 * @retval State of bit (1 or 0).
3560 */
LL_RCC_IsActiveFlag_LSIRDY(void)3561 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
3562 {
3563 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
3564 }
3565
3566 /**
3567 * @brief Check if LSE ready interrupt occurred or not
3568 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
3569 * @retval State of bit (1 or 0).
3570 */
LL_RCC_IsActiveFlag_LSERDY(void)3571 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
3572 {
3573 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
3574 }
3575
3576 /**
3577 * @brief Check if HSI ready interrupt occurred or not
3578 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
3579 * @retval State of bit (1 or 0).
3580 */
LL_RCC_IsActiveFlag_HSIRDY(void)3581 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
3582 {
3583 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
3584 }
3585
3586 /**
3587 * @brief Check if HSE ready interrupt occurred or not
3588 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
3589 * @retval State of bit (1 or 0).
3590 */
LL_RCC_IsActiveFlag_HSERDY(void)3591 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
3592 {
3593 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
3594 }
3595
3596 /**
3597 * @brief Check if PLL ready interrupt occurred or not
3598 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
3599 * @retval State of bit (1 or 0).
3600 */
LL_RCC_IsActiveFlag_PLLRDY(void)3601 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
3602 {
3603 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
3604 }
3605
3606 #if defined(RCC_HSI48_SUPPORT)
3607 /**
3608 * @brief Check if HSI48 ready interrupt occurred or not
3609 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
3610 * @retval State of bit (1 or 0).
3611 */
LL_RCC_IsActiveFlag_HSI48RDY(void)3612 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
3613 {
3614 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
3615 }
3616 #endif /* RCC_HSI48_SUPPORT */
3617
3618 /**
3619 * @brief Check if Clock security system interrupt occurred or not
3620 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
3621 * @retval State of bit (1 or 0).
3622 */
LL_RCC_IsActiveFlag_HSECSS(void)3623 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
3624 {
3625 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
3626 }
3627
3628 /**
3629 * @brief Check if LSE Clock security system interrupt occurred or not
3630 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
3631 * @retval State of bit (1 or 0).
3632 */
LL_RCC_IsActiveFlag_LSECSS(void)3633 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
3634 {
3635 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
3636 }
3637
3638 /**
3639 * @brief Check if RCC flag Independent Watchdog reset is set or not.
3640 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
3641 * @retval State of bit (1 or 0).
3642 */
LL_RCC_IsActiveFlag_IWDGRST(void)3643 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
3644 {
3645 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
3646 }
3647
3648 /**
3649 * @brief Check if RCC flag Low Power reset is set or not.
3650 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
3651 * @retval State of bit (1 or 0).
3652 */
LL_RCC_IsActiveFlag_LPWRRST(void)3653 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
3654 {
3655 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
3656 }
3657
3658 /**
3659 * @brief Check if RCC flag Option byte reset is set or not.
3660 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
3661 * @retval State of bit (1 or 0).
3662 */
LL_RCC_IsActiveFlag_OBLRST(void)3663 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
3664 {
3665 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
3666 }
3667
3668 /**
3669 * @brief Check if RCC flag Pin reset is set or not.
3670 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
3671 * @retval State of bit (1 or 0).
3672 */
LL_RCC_IsActiveFlag_PINRST(void)3673 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
3674 {
3675 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
3676 }
3677
3678 /**
3679 * @brief Check if RCC flag Software reset is set or not.
3680 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
3681 * @retval State of bit (1 or 0).
3682 */
LL_RCC_IsActiveFlag_SFTRST(void)3683 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
3684 {
3685 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
3686 }
3687
3688 /**
3689 * @brief Check if RCC flag Window Watchdog reset is set or not.
3690 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
3691 * @retval State of bit (1 or 0).
3692 */
LL_RCC_IsActiveFlag_WWDGRST(void)3693 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
3694 {
3695 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
3696 }
3697
3698 /**
3699 * @brief Check if RCC flag BOR or POR/PDR reset is set or not.
3700 * @rmtoll CSR PWRRSTF LL_RCC_IsActiveFlag_PWRRST
3701 * @retval State of bit (1 or 0).
3702 */
LL_RCC_IsActiveFlag_PWRRST(void)3703 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void)
3704 {
3705 return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL);
3706 }
3707
3708 /**
3709 * @brief Set RMVF bit to clear the reset flags.
3710 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
3711 * @retval None
3712 */
LL_RCC_ClearResetFlags(void)3713 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
3714 {
3715 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
3716 }
3717
3718 /**
3719 * @}
3720 */
3721
3722 /** @defgroup RCC_LL_EF_IT_Management IT Management
3723 * @{
3724 */
3725
3726 /**
3727 * @brief Enable LSI ready interrupt
3728 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
3729 * @retval None
3730 */
LL_RCC_EnableIT_LSIRDY(void)3731 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
3732 {
3733 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
3734 }
3735
3736 /**
3737 * @brief Enable LSE ready interrupt
3738 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
3739 * @retval None
3740 */
LL_RCC_EnableIT_LSERDY(void)3741 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
3742 {
3743 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3744 }
3745
3746 /**
3747 * @brief Enable HSI ready interrupt
3748 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
3749 * @retval None
3750 */
LL_RCC_EnableIT_HSIRDY(void)3751 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
3752 {
3753 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3754 }
3755
3756 /**
3757 * @brief Enable HSE ready interrupt
3758 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
3759 * @retval None
3760 */
LL_RCC_EnableIT_HSERDY(void)3761 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
3762 {
3763 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3764 }
3765
3766 /**
3767 * @brief Enable PLL ready interrupt
3768 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
3769 * @retval None
3770 */
LL_RCC_EnableIT_PLLRDY(void)3771 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
3772 {
3773 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
3774 }
3775
3776 #if defined(RCC_HSI48_SUPPORT)
3777 /**
3778 * @brief Enable HSI48 ready interrupt
3779 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
3780 * @retval None
3781 */
LL_RCC_EnableIT_HSI48RDY(void)3782 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
3783 {
3784 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
3785 }
3786 #endif /* RCC_HSI48_SUPPORT */
3787
3788 /**
3789 * @brief Disable LSI ready interrupt
3790 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
3791 * @retval None
3792 */
LL_RCC_DisableIT_LSIRDY(void)3793 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
3794 {
3795 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
3796 }
3797
3798 /**
3799 * @brief Disable LSE ready interrupt
3800 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
3801 * @retval None
3802 */
LL_RCC_DisableIT_LSERDY(void)3803 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
3804 {
3805 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3806 }
3807
3808 /**
3809 * @brief Disable HSI ready interrupt
3810 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
3811 * @retval None
3812 */
LL_RCC_DisableIT_HSIRDY(void)3813 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
3814 {
3815 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3816 }
3817
3818 /**
3819 * @brief Disable HSE ready interrupt
3820 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
3821 * @retval None
3822 */
LL_RCC_DisableIT_HSERDY(void)3823 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
3824 {
3825 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3826 }
3827
3828 /**
3829 * @brief Disable PLL ready interrupt
3830 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
3831 * @retval None
3832 */
LL_RCC_DisableIT_PLLRDY(void)3833 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
3834 {
3835 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
3836 }
3837
3838 #if defined(RCC_HSI48_SUPPORT)
3839 /**
3840 * @brief Disable HSI48 ready interrupt
3841 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
3842 * @retval None
3843 */
LL_RCC_DisableIT_HSI48RDY(void)3844 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
3845 {
3846 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
3847 }
3848 #endif /* RCC_HSI48_SUPPORT */
3849
3850 /**
3851 * @brief Checks if LSI ready interrupt source is enabled or disabled.
3852 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
3853 * @retval State of bit (1 or 0).
3854 */
LL_RCC_IsEnabledIT_LSIRDY(void)3855 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
3856 {
3857 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
3858 }
3859
3860 /**
3861 * @brief Checks if LSE ready interrupt source is enabled or disabled.
3862 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
3863 * @retval State of bit (1 or 0).
3864 */
LL_RCC_IsEnabledIT_LSERDY(void)3865 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
3866 {
3867 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
3868 }
3869
3870 /**
3871 * @brief Checks if HSI ready interrupt source is enabled or disabled.
3872 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
3873 * @retval State of bit (1 or 0).
3874 */
LL_RCC_IsEnabledIT_HSIRDY(void)3875 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
3876 {
3877 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
3878 }
3879
3880 #if defined(RCC_HSI48_SUPPORT)
3881 /**
3882 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
3883 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
3884 * @retval State of bit (1 or 0).
3885 */
LL_RCC_IsEnabledIT_HSI48RDY(void)3886 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
3887 {
3888 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
3889 }
3890 #endif /* RCC_HSI48_SUPPORT */
3891
3892 /**
3893 * @brief Checks if HSE ready interrupt source is enabled or disabled.
3894 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
3895 * @retval State of bit (1 or 0).
3896 */
LL_RCC_IsEnabledIT_HSERDY(void)3897 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
3898 {
3899 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
3900 }
3901
3902 /**
3903 * @brief Checks if PLL ready interrupt source is enabled or disabled.
3904 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
3905 * @retval State of bit (1 or 0).
3906 */
LL_RCC_IsEnabledIT_PLLRDY(void)3907 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
3908 {
3909 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
3910 }
3911
3912 /**
3913 * @}
3914 */
3915
3916 #if defined(USE_FULL_LL_DRIVER)
3917 /** @defgroup RCC_LL_EF_Init De-initialization function
3918 * @{
3919 */
3920 ErrorStatus LL_RCC_DeInit(void);
3921 /**
3922 * @}
3923 */
3924
3925 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
3926 * @{
3927 */
3928 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
3929 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
3930 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
3931 #if defined(LPUART1) || defined(LPUART2)
3932 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
3933 #endif /* LPUART1 */
3934 #if defined(LPTIM1) && defined(LPTIM2)
3935 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
3936 #endif /* LPTIM1 && LPTIM2 */
3937 #if defined(RNG)
3938 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
3939 #endif /* RNG */
3940 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
3941 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
3942 #if defined(CEC)
3943 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
3944 #endif /* CEC */
3945 #if defined(FDCAN1) || defined(FDCAN2)
3946 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
3947 #endif /* FDCAN1 */
3948 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
3949 uint32_t LL_RCC_GetRTCClockFreq(void);
3950 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
3951 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
3952 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
3953 /**
3954 * @}
3955 */
3956 #endif /* USE_FULL_LL_DRIVER */
3957
3958 /**
3959 * @}
3960 */
3961
3962 /**
3963 * @}
3964 */
3965
3966 #endif /* RCC */
3967
3968 /**
3969 * @}
3970 */
3971
3972 #ifdef __cplusplus
3973 }
3974 #endif
3975
3976 #endif /* STM32G0xx_LL_RCC_H */
3977
3978
