1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_RCC_H
21 #define STM32WBAxx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
44 * @{
45 */
46 /* Defines used to perform offsets*/
47 /* Offset used to access to RCC_CCIPR1, RCC_CCIPR2 and RCC_CCIPR3 registers */
48 #define RCC_OFFSET_CCIPR1 0U
49 #define RCC_OFFSET_CCIPR2 0x04U
50 #define RCC_OFFSET_CCIPR3 0x08U
51
52 /* Defines used for security configuration extension */
53 #define RCC_SECURE_MASK 0x10FBU
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /* Exported types ------------------------------------------------------------*/
60 #if defined(USE_FULL_LL_DRIVER)
61 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
62 * @{
63 */
64
65 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
66 * @{
67 */
68
69 /**
70 * @brief RCC Clocks Frequency Structure
71 */
72 typedef struct
73 {
74 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
75 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
76 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
77 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
78 uint32_t PCLK7_Frequency; /*!< PCLK7 clock frequency */
79 } LL_RCC_ClocksTypeDef;
80
81 /**
82 * @}
83 */
84
85 /**
86 * @}
87 */
88 #endif /* USE_FULL_LL_DRIVER */
89
90 /* Exported constants --------------------------------------------------------*/
91 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
92 * @{
93 */
94
95 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
96 * @brief Defines used to adapt values of different oscillators
97 * @note These values could be modified in the user environment according to
98 * HW set-up.
99 * @{
100 */
101 #if !defined (HSE_VALUE)
102 #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */
103 #endif /* HSE_VALUE */
104
105 #if !defined (HSI_VALUE)
106 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
107 #endif /* HSI_VALUE */
108
109 #if !defined (LSE_VALUE)
110 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
111 #endif /* LSE_VALUE */
112
113 #if !defined (LSI_VALUE)
114 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
115 #endif /* LSI_VALUE */
116
117 #if defined (RCC_LSI2_SUPPORT)
118 #if !defined (LSI2_VALUE)
119 #define LSI2_VALUE 32000U /*!< Value of the LSI2 oscillator in Hz */
120 #endif /* LSI_VALUE */
121 #endif
122
123 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
124 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
125 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
126
127 /**
128 * @}
129 */
130
131 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
132 * @brief Flags defines which can be used with LL_RCC_WriteReg function
133 * @{
134 */
135 #define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */
136 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
137 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
138 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
139 #define LL_RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC /*!< PLL1 Ready Interrupt Clear */
140 #define LL_RCC_CICR_HSECSSC RCC_CICR_HSECSSC /*!< HSE Clock Security System Interrupt Clear */
141 #define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI2 Ready Interrupt Clear */
142 /**
143 * @}
144 */
145
146 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
147 * @brief Flags defines which can be used with LL_RCC_ReadReg function
148 * @{
149 */
150 #define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */
151 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
152 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
153 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
154 #define LL_RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */
155 #define LL_RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt flag */
156 #define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */
157 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< Option byte loader reset flag */
158 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< NRST pin reset flag */
159 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
160 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software reset flag */
161 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent watchdog reset flag */
162 #if defined(WWDG)
163 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
164 #endif /* defined(WWDG) */
165 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-power reset flag */
166 /**
167 * @}
168 */
169
170 /** @defgroup RCC_LL_EC_IT IT Defines
171 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
172 * @{
173 */
174 #define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */
175 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
176 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
177 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
178 #define LL_RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE /*!< PLL1 Ready Interrupt Enable */
179 #define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI2 Ready Interrupt Enable */
180 /**
181 * @}
182 */
183
184 /** @defgroup RCC_LL_EC_LSIPRE LSI prescaler
185 * @{
186 */
187 #define LL_RCC_LSI_DIV_1 0U /*!< LSI1 divided by 1 */
188 #define LL_RCC_LSI_DIV_128 RCC_BDCR1_LSI1PREDIV /*!< LSI1 divided by 128 */
189 /**
190 * @}
191 */
192
193 #if defined(RCC_BDCR2_LSI2CFG)
194 /** @defgroup RCC_LL_EC_LSI2CFG LSI2 oscillator temperature sensitivity configuration
195 * @{
196 */
197 #define LL_RCC_LSI2_TEMP_SENSITIVITY_80 0U /*!< LSI2 frequency temperature sensitivity is close to zero at +80 degrees C */
198 #define LL_RCC_LSI2_TEMP_SENSITIVITY_50 RCC_BDCR2_LSI2CFG_0 /*!< LSI2 frequency temperature sensitivity is close to zero at +50 degrees C */
199 #define LL_RCC_LSI2_TEMP_SENSITIVITY_20 RCC_BDCR2_LSI2CFG_1 /*!< LSI2 frequency temperature sensitivity is close to zero at +20 degrees C */
200 /**
201 * @}
202 */
203 #endif /* RCC_BDCR2_LSI2CFG */
204
205 #if defined(RCC_BDCR2_LSI2MODE)
206 /** @defgroup RCC_LL_EC_LSI2MODE LSI2 oscillator operating mode configuration
207 * @{
208 */
209 #define LL_RCC_LSI2_NOMINAL_MODE 0U /*!< LSI2 nominal power, high accuracy */
210 #define LL_RCC_LSI2_LOWPOWER_MODE RCC_BDCR2_LSI2MODE_0 /*!< LSI2 low power, medium accuracy */
211 #define LL_RCC_LSI2_ULTRALOWPOWER_MODE RCC_BDCR2_LSI2MODE_1 /*!< LSI2 ultra low power, low accuracy */
212 /**
213 * @}
214 */
215 #endif /* RCC_BDCR2_LSI2MODE */
216
217 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
218 * @{
219 */
220 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR1_LSEDRV_0 /*!< Xtal mode medium low driving capability */
221 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR1_LSEDRV_1 /*!< Xtal mode medium high driving capability */
222 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR1_LSEDRV /*!< Xtal mode higher driving capability */
223 /**
224 * @}
225 */
226
227 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
228 * @{
229 */
230 #define LL_RCC_LSCO_CLKSOURCE_LSI 0U /*!< LSI selection for low speed clock */
231 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR1_LSCOSEL /*!< LSE selection for low speed clock */
232 /**
233 * @}
234 */
235
236
237 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
238 * @{
239 */
240 #define LL_RCC_SYS_CLKSOURCE_HSI 0U /*!< HSI selection as system clock */
241 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */
242 #define LL_RCC_SYS_CLKSOURCE_PLL1R (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1R selection as system clock */
243 /**
244 * @}
245 */
246
247
248 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
249 * @{
250 */
251 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as system clock */
252 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */
253 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1R used as system clock */
254 /**
255 * @}
256 */
257
258
259 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
260 * @{
261 */
262 #define LL_RCC_SYSCLK_DIV_1 0U /*!< SYSCLK not divided */
263 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_2 /*!< SYSCLK divided by 2 */
264 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */
265 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */
266 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */
267 /**
268 * @}
269 */
270
271
272 /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection
273 * @{
274 */
275 #define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */
276 #define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */
277 #define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */
278 /**
279 * @}
280 */
281
282 /** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler
283 * @{
284 */
285 #define LL_RCC_APB1_DIV_1 0U /*!< HCLK not divided */
286 #define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */
287 #define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */
288 #define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */
289 #define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */
290 /**
291 * @}
292 */
293
294
295 /** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler
296 * @{
297 */
298 #define LL_RCC_APB2_DIV_1 0U /*!< HCLK not divided */
299 #define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */
300 #define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */
301 #define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */
302 #define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */
303 /**
304 * @}
305 */
306
307 /** @defgroup RCC_LL_EC_APB7_DIV APB7 prescaler
308 * @{
309 */
310 #define LL_RCC_APB7_DIV_1 0U /*!< HCLK not divided */
311 #define LL_RCC_APB7_DIV_2 RCC_CFGR3_PPRE7_2 /*!< HCLK divided by 2 */
312 #define LL_RCC_APB7_DIV_4 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_0) /*!< HCLK divided by 4 */
313 #define LL_RCC_APB7_DIV_8 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_1) /*!< HCLK divided by 8 */
314 #define LL_RCC_APB7_DIV_16 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_1 | RCC_CFGR3_PPRE7_0) /*!< HCLK divided by 16 */
315 /**
316 * @}
317 */
318
319 /** @defgroup RCC_LL_EC_AHB5_DIV AHB5 prescaler when SYSCLK is PLL1R
320 * @{
321 */
322 #define LL_RCC_AHB5_DIV_1 0U /*!< SYSCLK not divided */
323 #define LL_RCC_AHB5_DIV_2 RCC_CFGR4_HPRE5_2 /*!< SYSCLK divided by 2 */
324 #define LL_RCC_AHB5_DIV_3 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK divided by 3 */
325 #define LL_RCC_AHB5_DIV_4 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1) /*!< SYSCLK divided by 4 */
326 #define LL_RCC_AHB5_DIV_6 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK divided by 6 */
327 /**
328 * @}
329 */
330
331 /** @defgroup RCC_LL_EC_AHB5_DIVIDER AHB5 divider when SYSCLK is HSI or HSE
332 * @{
333 */
334 #define LL_RCC_AHB5_DIVIDER_1 0U /*!< SYSCLK not divided */
335 #define LL_RCC_AHB5_DIVIDER_2 RCC_CFGR4_HDIV5 /*!< SYSCLK divided by 2 */
336 /**
337 * @}
338 */
339
340 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
341 * @{
342 */
343 #define LL_RCC_MCO1SOURCE_NOCLOCK 0U /*!< MCO output disabled, no clock on MCO */
344 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
345 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */
346 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */
347 #define LL_RCC_MCO1SOURCE_PLL1R (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< PLL1RCLK selection as MCO1 source */
348 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */
349 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */
350 #define LL_RCC_MCO1SOURCE_PLL1P RCC_CFGR1_MCOSEL_3 /*!< PLL1PCLK selection as MCO1 source */
351 #define LL_RCC_MCO1SOURCE_PLL1Q (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< PLL1QCLK selection as MCO1 source */
352 #define LL_RCC_MCO1SOURCE_HCLK5 (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_3) /*!< HCLK5 selection as MCO1 source */
353 /**
354 * @}
355 */
356
357 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
358 * @{
359 */
360 #define LL_RCC_MCO1_DIV_1 0U /*!< MCO not divided */
361 #define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */
362 #define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */
363 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */
364 #define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */
365 /**
366 * @}
367 */
368
369 #if defined(USE_FULL_LL_DRIVER)
370 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
371 * @{
372 */
373 #define LL_RCC_PERIPH_FREQUENCY_NO 0U /*!< No clock enabled for the peripheral */
374 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
375 /**
376 * @}
377 */
378 #endif /* USE_FULL_LL_DRIVER */
379
380 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
381 * @{
382 */
383 #define LL_RCC_RTC_CLKSOURCE_NONE 0U /*!< No clock used as RTC clock */
384 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
385 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
386 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
387 /**
388 * @}
389 */
390
391 /** @defgroup RCC_LL_EC_RADIO_SLEEPTIMER_CLKSOURCE RADIO Sleep Timer Clock source
392 * @{
393 */
394 #define LL_RCC_RADIOSLEEPSOURCE_NONE 0U /*!< No clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled */
395 #define LL_RCC_RADIOSLEEPSOURCE_LSE RCC_BDCR1_RADIOSTSEL_0 /*!< LSE oscillator clock selected */
396 #define LL_RCC_RADIOSLEEPSOURCE_LSI RCC_BDCR1_RADIOSTSEL_1 /*!< LSI oscillator clock selected */
397 #define LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000 RCC_BDCR1_RADIOSTSEL /*!< HSE oscillator clock divided by 1000 selected */
398 /**
399 * @}
400 */
401
402 /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection
403 * @{
404 */
405 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR1_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
406 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
407 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
408 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL) /*!< LSE clock used as USART1 clock source */
409 #if defined(USART2)
410 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
411 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
412 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
413 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */
414 #endif /* USART2 */
415 /**
416 * @}
417 */
418
419 /** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
420 * @{
421 */
422 #define LL_RCC_LPUART1_CLKSOURCE_PCLK7 0U /*!< PCLK3 clock used as LPUART1 clock source */
423 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
424 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
425 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */
426 /**
427 * @}
428 */
429
430 /** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
431 * @{
432 */
433 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
434 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
435 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
436 #define LL_RCC_I2C3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK7 clock used as I2C3 clock source */
437 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
438 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
439 /**
440 * @}
441 */
442
443 /** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection
444 * @{
445 */
446 #if defined(SPI1)
447 #define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */
448 #define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */
449 #define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */
450 #endif /* SPI1 */
451 #define LL_RCC_SPI3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK7 clock used as SPI3 clock source */
452 #define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */
453 #define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */
454 /**
455 * @}
456 */
457
458 /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection
459 * @{
460 */
461 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< PCLK7 clock used as LPTIM1 clock source */
462 #define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */
463 #define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */
464 #define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */
465 #if defined(LPTIM2)
466 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */
467 #define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */
468 #define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */
469 #define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */
470 #endif /* LPTIM2 */
471 /**
472 * @}
473 */
474
475 #if defined(SAI1)
476 /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection
477 * @{
478 */
479 #define LL_RCC_SAI1_CLKSOURCE_PLL1P (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL1P clock used as SAI1 clock source */
480 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL1Q clock used as SAI1 clock source */
481 #define LL_RCC_SAI1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< System clock used as SAI1 clock source */
482 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
483 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
484 /**
485 * @}
486 */
487 #endif /* SAI1 */
488
489
490 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
491 * @{
492 */
493 #define LL_RCC_RNG_CLKSOURCE_LSE 0U /*!< LSE clock used as RNG clock source */
494 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR2_RNGSEL_0 /*!< LSI clock used as RNG clock source */
495 #define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */
496 #define LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 (RCC_CCIPR2_RNGSEL_1 | RCC_CCIPR2_RNGSEL_0) /*!< PLL1Q/2 clock used as RNG clock source */
497 /**
498 * @}
499 */
500 /** Legacy definitions for compatibility purpose
501 @cond 0
502 */
503 #define LL_RCC_RNG_CLKSOURCE_PLL1Q LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2
504 /**
505 @endcond
506 */
507
508 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC4 clock source selection
509 * @{
510 */
511 #define LL_RCC_ADC_CLKSOURCE_HCLK 0U /*!< HCLK1 clock used as ADC4 clock source */
512 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCSEL_0 /*!< SYSCLK clock used as ADC4 clock source */
513 #define LL_RCC_ADC_CLKSOURCE_PLL1P RCC_CCIPR3_ADCSEL_1 /*!< PLL1P clock used as ADC4 clock source */
514 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR3_ADCSEL_2 /*!< HSI clock used as ADC4 clock source */
515 #define LL_RCC_ADC_CLKSOURCE_HSE (RCC_CCIPR3_ADCSEL_1 | RCC_CCIPR3_ADCSEL_0) /*!< HSE clock used as ADC4 clock source */
516 /**
517 * @}
518 */
519
520
521
522 /** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection
523 * @{
524 */
525 #define LL_RCC_TIMIC_CLKSOURCE_NONE 0U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */
526 #define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */
527 /**
528 * @}
529 */
530
531 /** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source
532 * @{
533 */
534 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR1_USART1SEL /*!< USART1 Clock source selection */
535 #if defined(USART2)
536 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR1_USART2SEL /*!< USART2 Clock source selection */
537 #endif /* USART2 */
538 /**
539 * @}
540 */
541
542 /** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source
543 * @{
544 */
545 #if defined(SPI1)
546 #define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */
547 #endif /* SPI1 */
548 #define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */
549 /**
550 * @}
551 */
552
553 /** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source
554 * @{
555 */
556 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */
557 /**
558 * @}
559 */
560
561 /** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
562 * @{
563 */
564 #if defined(I2C1)
565 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
566 #endif /* I2C1 */
567 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
568
569 /**
570 * @}
571 */
572
573 /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source
574 * @{
575 */
576 #define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */
577 #if defined(LPTIM2)
578 #define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */
579 #endif /* LPTIM2 */
580 /**
581 * @}
582 */
583
584 #if defined(SAI1)
585 /** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source
586 * @{
587 */
588 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
589 /**
590 * @}
591 */
592 #endif /* SAI1 */
593
594 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
595 * @{
596 */
597 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */
598 /**
599 * @}
600 */
601
602 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
603 * @{
604 */
605 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR3_ADCSEL /*!< ADCs Clock source selection */
606 /**
607 * @}
608 */
609
610
611 /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source
612 * @{
613 */
614 #define LL_RCC_PLL1SOURCE_NONE 0U /*!< No clock selected as PLL1 entry clock source */
615 #define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as PLL1 entry clock source */
616 #define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as PLL1 entry clock source */
617 /**
618 * @}
619 */
620
621 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges
622 * @{
623 */
624 #define LL_RCC_PLLINPUTRANGE_4_8 2U /*!< VCO input range: 4 to 8 MHz */
625 #define LL_RCC_PLLINPUTRANGE_8_16 3U /*!< VCO input range: 8 to 16 MHz */
626 /**
627 * @}
628 */
629
630 /** @defgroup RCC_LL_EC_PLL1RCLKPRESTEP PLL1RCLK prescaler steps division
631 * @{
632 */
633 #define LL_RCC_PLL1RCLK_2_STEP_DIV 0U /*!< PLL1RCLK 2-step division */
634 #define LL_RCC_PLL1RCLK_3_STEP_DIV RCC_PLL1CFGR_PLL1RCLKPRESTEP /*!< PLL1RCLK 3-step division */
635 /**
636 * @}
637 */
638
639 /** @defgroup RCC_LSE_Trimming LSE Trimming
640 * @{
641 */
642 #define LL_RCC_LSETRIMMING_R 0U /*!< Current source resistance R */
643 #define LL_RCC_LSETRIMMING_3_4_R RCC_BDCR1_LSETRIM_0 /*!< Current source resistance 3/4 * R */
644 #define LL_RCC_LSETRIMMING_2_3_R RCC_BDCR1_LSETRIM_1 /*!< Current source resistance 2/3 * R */
645 #define LL_RCC_LSETRIMMING_1_2_R RCC_BDCR1_LSETRIM /*!< Current source resistance 1/2 * R */
646 /**
647 * @}
648 */
649
650 /** @defgroup RCC_LL_EF_Security_Services Security Services
651 * @note Only available when system implements security (TZEN=1)
652 * @{
653 */
654 #define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */
655 #define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */
656
657 #define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration secure-only access */
658 #define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */
659 #define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration secure-only access */
660 #define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */
661 #define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration secure-only access */
662 #define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */
663 #define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration secure-only access */
664 #define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */
665 #define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure-only access */
666 #define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */
667 #define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration secure-only access */
668 #define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */
669 #define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration secure-only access */
670 #define LL_RCC_PLL1_NSEC 0U /*!< PLL1 clock configuration secure/non-secure access */
671 #define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag secure-only access */
672 #define LL_RCC_RESET_FLAGS_NSEC 0U /*!< Remove reset flag secure/non-secure access */
673 /**
674 * @}
675 */
676
677 /**
678 * @}
679 */
680
681 /* Exported macro ------------------------------------------------------------*/
682 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
683 * @{
684 */
685
686 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
687 * @{
688 */
689
690 /**
691 * @brief Write a value in RCC register
692 * @param __REG__ Register to be written
693 * @param __VALUE__ Value to be written in the register
694 * @retval None
695 */
696 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
697
698 /**
699 * @brief Read a value in RCC register
700 * @param __REG__ Register to be read
701 * @retval Register value
702 */
703 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
704 /**
705 * @}
706 */
707
708 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
709 * @{
710 */
711
712 /**
713 * @brief Helper macro to calculate the PLL1RCLK frequency on system domain
714 * @note ex: @ref __LL_RCC_CALC_PLL1RCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
715 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ());
716 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
717 * @param __PLL1M__ parameter can be a value between 1 and 16
718 * @param __PLL1N__ parameter can be a value between 4 and 512
719 * @param __PLL1R__ parameter can be a value between 1 and 128
720 * @retval PLL1R clock frequency (in Hz)
721 */
722
723 #define __LL_RCC_CALC_PLL1RCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1R__))
724
725 /**
726 * @brief Helper macro to calculate the PLL1PCLK frequency
727 * @note ex: @ref __LL_RCC_CALC_PLL1PCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
728 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ());
729 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
730 * @param __PLL1M__ parameter can be a value between 1 and 16
731 * @param __PLL1N__ parameter can be a value between 4 and 512
732 * @param __PLL1P__ parameter can be a value between 2 and 128
733 * @retval PLL1P clock frequency (in Hz)
734 */
735 #define __LL_RCC_CALC_PLL1PCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__))
736
737 /**
738 * @brief Helper macro to calculate the PLL1QCLK frequency
739 * @note ex: @ref __LL_RCC_CALC_PLL1QCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
740 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ());
741 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
742 * @param __PLL1M__ parameter can be a value between 1 and 16
743 * @param __PLL1N__ parameter can be a value between 4 and 512
744 * @param __PLL1Q__ parameter can be a value between 1 and 128
745 * @retval PLL1 clock frequency (in Hz)
746 */
747 #define __LL_RCC_CALC_PLL1QCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__))
748
749 /**
750 * @brief Helper macro to calculate the HCLK frequency
751 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
752 * @param __AHBPRESCALER__ This parameter can be one of the following values:
753 * @arg @ref LL_RCC_SYSCLK_DIV_1
754 * @arg @ref LL_RCC_SYSCLK_DIV_2
755 * @arg @ref LL_RCC_SYSCLK_DIV_4
756 * @arg @ref LL_RCC_SYSCLK_DIV_8
757 * @arg @ref LL_RCC_SYSCLK_DIV_16
758 * @retval HCLK clock frequency (in Hz)
759 */
760 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos])
761
762 /**
763 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
764 * @param __HCLKFREQ__ HCLK frequency
765 * @param __APB1PRESCALER__ This parameter can be one of the following values:
766 * @arg @ref LL_RCC_APB1_DIV_1
767 * @arg @ref LL_RCC_APB1_DIV_2
768 * @arg @ref LL_RCC_APB1_DIV_4
769 * @arg @ref LL_RCC_APB1_DIV_8
770 * @arg @ref LL_RCC_APB1_DIV_16
771 * @retval PCLK1 clock frequency (in Hz)
772 */
773 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[((__APB1PRESCALER__) & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]))
774
775 /**
776 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
777 * @param __HCLKFREQ__ HCLK frequency
778 * @param __APB2PRESCALER__ This parameter can be one of the following values:
779 * @arg @ref LL_RCC_APB2_DIV_1
780 * @arg @ref LL_RCC_APB2_DIV_2
781 * @arg @ref LL_RCC_APB2_DIV_4
782 * @arg @ref LL_RCC_APB2_DIV_8
783 * @arg @ref LL_RCC_APB2_DIV_16
784 * @retval PCLK2 clock frequency (in Hz)
785 */
786 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR2_PPRE2_Pos])
787
788
789 /**
790 * @brief Helper macro to calculate the PCLK7 frequency (ABP7)
791 * @param __HCLKFREQ__ HCLK frequency
792 * @param __APB7PRESCALER__ This parameter can be one of the following values:
793 * @arg @ref LL_RCC_APB7_DIV_1
794 * @arg @ref LL_RCC_APB7_DIV_2
795 * @arg @ref LL_RCC_APB7_DIV_4
796 * @arg @ref LL_RCC_APB7_DIV_8
797 * @arg @ref LL_RCC_APB7_DIV_16
798 * @retval PCLK3 clock frequency (in Hz)
799 */
800 #define __LL_RCC_CALC_PCLK7_FREQ(__HCLKFREQ__, __APB7PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB7PRESCALER__) >> RCC_CFGR3_PPRE7_Pos])
801
802 /**
803 * @}
804 */
805
806 /**
807 * @}
808 */
809
810 /* Exported functions --------------------------------------------------------*/
811 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
812 * @{
813 */
814
815 /** @defgroup RCC_LL_EF_HSE HSE
816 * @{
817 */
818
819 /**
820 * @brief Enable HSE crystal oscillator (HSE ON)
821 * @rmtoll CR HSEON LL_RCC_HSE_Enable
822 * @retval None
823 */
LL_RCC_HSE_Enable(void)824 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
825 {
826 SET_BIT(RCC->CR, RCC_CR_HSEON);
827 }
828
829 /**
830 * @brief Disable HSE crystal oscillator (HSE ON)
831 * @rmtoll CR HSEON LL_RCC_HSE_Disable
832 * @retval None
833 */
LL_RCC_HSE_Disable(void)834 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
835 {
836 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
837 }
838
839 /**
840 * @brief Check if HSE oscillator Ready
841 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
842 * @retval State of bit (1 or 0).
843 */
LL_RCC_HSE_IsReady(void)844 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
845 {
846 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
847 }
848
849 /**
850 * @brief Enable HSE clock prescaler for sysclk
851 * @rmtoll CR HSEPRE LL_RCC_HSE_EnablePrescaler
852 * @note Control the division factor of the HSE32 clock for sysclk
853 * @retval None
854 */
LL_RCC_HSE_EnablePrescaler(void)855 __STATIC_INLINE void LL_RCC_HSE_EnablePrescaler(void)
856 {
857 SET_BIT(RCC->CR, RCC_CR_HSEPRE);
858 }
859
860 /**
861 * @brief Check if HSE clock prescaler for sysclk is enabled
862 * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledPrescaler
863 * @note Check if the HSE32 clock for sysclk is divided by 2 or not
864 * @retval State of bit (1 or 0).
865 */
LL_RCC_HSE_IsEnabledPrescaler(void)866 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledPrescaler(void)
867 {
868 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == RCC_CR_HSEPRE) ? 1UL : 0UL);
869 }
870
871 /**
872 * @brief Disable HSE clock prescaler for sysclk
873 * @rmtoll CR HSEPRE LL_RCC_HSE_DisablePrescaler
874 * @note Control the division factor of the HSE32 clock for sysclk
875 * @retval None
876 */
LL_RCC_HSE_DisablePrescaler(void)877 __STATIC_INLINE void LL_RCC_HSE_DisablePrescaler(void)
878 {
879 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE);
880 }
881
882 /**
883 * @brief Enable the Clock Security System.
884 * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS
885 * @retval None
886 */
LL_RCC_HSE_EnableCSS(void)887 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
888 {
889 SET_BIT(RCC->CR, RCC_CR_HSECSSON);
890 }
891
892 /**
893 * @brief Set HSE clock trimming
894 * @note user-programmable capacitor trimming value.
895 * @rmtoll ECSCR1 HSETRIM LL_RCC_HSE_SetClockTrimming
896 * @param Value Between Min_Data = 0 and Max_Data = 63
897 * @retval None
898 */
LL_RCC_HSE_SetClockTrimming(uint32_t Value)899 __STATIC_INLINE void LL_RCC_HSE_SetClockTrimming(uint32_t Value)
900 {
901 MODIFY_REG(RCC->ECSCR1, RCC_ECSCR1_HSETRIM, Value << RCC_ECSCR1_HSETRIM_Pos);
902 }
903
904 /**
905 * @brief Get HSE clock trimming
906 * @rmtoll ECSCR1 HSETRIM LL_RCC_HSE_GetClockTrimming
907 * @retval Between Min_Data = 0 and Max_Data = 63
908 */
LL_RCC_HSE_GetClockTrimming(void)909 __STATIC_INLINE uint32_t LL_RCC_HSE_GetClockTrimming(void)
910 {
911 return (uint32_t)(READ_BIT(RCC->ECSCR1, RCC_ECSCR1_HSETRIM) >> RCC_ECSCR1_HSETRIM_Pos);
912 }
913 /**
914 * @}
915 */
916
917 /** @defgroup RCC_LL_EF_HSI HSI
918 * @{
919 */
920
921 /**
922 * @brief Enable HSI even in stop mode
923 * @note HSI oscillator is forced ON even in Stop mode
924 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
925 * @retval None
926 */
LL_RCC_HSI_EnableInStopMode(void)927 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
928 {
929 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
930 }
931
932 /**
933 * @brief Disable HSI in stop mode
934 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
935 * @retval None
936 */
LL_RCC_HSI_DisableInStopMode(void)937 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
938 {
939 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
940 }
941
942 /**
943 * @brief Check if HSI is enabled in stop mode
944 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
945 * @retval State of bit (1 or 0).
946 */
LL_RCC_HSI_IsEnabledInStopMode(void)947 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
948 {
949 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
950 }
951
952 /**
953 * @brief Enable HSI oscillator
954 * @rmtoll CR HSION LL_RCC_HSI_Enable
955 * @retval None
956 */
LL_RCC_HSI_Enable(void)957 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
958 {
959 SET_BIT(RCC->CR, RCC_CR_HSION);
960 }
961
962 /**
963 * @brief Disable HSI oscillator
964 * @rmtoll CR HSION LL_RCC_HSI_Disable
965 * @retval None
966 */
LL_RCC_HSI_Disable(void)967 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
968 {
969 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
970 }
971
972 /**
973 * @brief Check if HSI clock is ready
974 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
975 * @retval State of bit (1 or 0).
976 */
LL_RCC_HSI_IsReady(void)977 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
978 {
979 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
980 }
981
982 /**
983 * @brief Get HSI Calibration value
984 * @note When HSITRIM is written, HSICAL is updated with the sum of
985 * HSITRIM and the factory trim value
986 * @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration
987 * @retval Between Min_Data = 0 and Max_Data = 4095
988 */
LL_RCC_HSI_GetCalibration(void)989 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
990 {
991 return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos);
992 }
993
994 /**
995 * @brief Set HSI Calibration trimming
996 * @note user-programmable trimming value that is added to the HSICAL
997 * @note Default value is 16, which, when added to the HSICAL value,
998 * should trim the HSI to 16 MHz +/- 1 %
999 * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming
1000 * @param Value Between Min_Data = 0 and Max_Data = 31
1001 * @retval None
1002 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1003 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1004 {
1005 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos);
1006 }
1007
1008 /**
1009 * @brief Get HSI Calibration trimming
1010 * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_GetCalibTrimming
1011 * @retval Between Min_Data = 0 and Max_Data = 31
1012 */
LL_RCC_HSI_GetCalibTrimming(void)1013 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1014 {
1015 return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
1016 }
1017
1018 /**
1019 * @}
1020 */
1021
1022 /** @defgroup RCC_LL_EF_LSE LSE
1023 * @{
1024 */
1025
1026 /**
1027 * @brief Enable Low Speed External (LSE) crystal.
1028 * @rmtoll BDCR1 LSEON LL_RCC_LSE_Enable
1029 * @retval None
1030 */
LL_RCC_LSE_Enable(void)1031 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1032 {
1033 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON);
1034 }
1035
1036 /**
1037 * @brief Disable Low Speed External (LSE) crystal.
1038 * @rmtoll BDCR1 LSEON LL_RCC_LSE_Disable
1039 * @retval None
1040 */
LL_RCC_LSE_Disable(void)1041 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1042 {
1043 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEON);
1044 }
1045
1046 /**
1047 * @brief Enable external clock source (LSE bypass).
1048 * @rmtoll BDCR1 LSEBYP LL_RCC_LSE_EnableBypass
1049 * @retval None
1050 */
LL_RCC_LSE_EnableBypass(void)1051 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1052 {
1053 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP);
1054 }
1055
1056 /**
1057 * @brief Disable external clock source (LSE bypass).
1058 * @rmtoll BDCR1 LSEBYP LL_RCC_LSE_DisableBypass
1059 * @retval None
1060 */
LL_RCC_LSE_DisableBypass(void)1061 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1062 {
1063 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP);
1064 }
1065
1066 /**
1067 * @brief Enable LSE clock glitch filter.
1068 * @rmtoll BDCR1 LSEGFON LL_RCC_LSE_EnableGlitchFilter
1069 * @retval None
1070 */
LL_RCC_LSE_EnableGlitchFilter(void)1071 __STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void)
1072 {
1073 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON);
1074 }
1075
1076 /**
1077 * @brief Disable LSE clock glitch filter.
1078 * @rmtoll BDCR1 LSEGFON LL_RCC_LSE_DisableGlitchFilter
1079 * @retval None
1080 */
LL_RCC_LSE_DisableGlitchFilter(void)1081 __STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void)
1082 {
1083 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON);
1084 }
1085
1086 /**
1087 * @brief Set LSE trimming
1088 * @rmtoll BDCR1 LSETRIM LL_RCC_LSE_SetClockTrimming
1089 * @param LSETrim This parameter can be one of the following values:
1090 * @arg @ref LL_RCC_LSETRIMMING_R
1091 * @arg @ref LL_RCC_LSETRIMMING_3_4_R
1092 * @arg @ref LL_RCC_LSETRIMMING_2_3_R
1093 * @arg @ref LL_RCC_LSETRIMMING_1_2_R
1094 * @retval None
1095 */
LL_RCC_LSE_SetClockTrimming(uint32_t LSETrim)1096 __STATIC_INLINE void LL_RCC_LSE_SetClockTrimming(uint32_t LSETrim)
1097 {
1098 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, LSETrim);
1099 }
1100
1101 /**
1102 * @brief Get LSE trimming
1103 * @rmtoll BDCR1 LSETRIM LL_RCC_LSE_GetClockTrimming
1104 * @retval Returned value can be one of the following values:
1105 * @arg @ref LL_RCC_LSETRIMMING_R
1106 * @arg @ref LL_RCC_LSETRIMMING_3_4_R
1107 * @arg @ref LL_RCC_LSETRIMMING_2_3_R
1108 * @arg @ref LL_RCC_LSETRIMMING_1_2_R
1109 * @retval None
1110 */
LL_RCC_LSE_GetClockTrimming(void)1111 __STATIC_INLINE uint32_t LL_RCC_LSE_GetClockTrimming(void)
1112 {
1113 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSETRIM));
1114 }
1115
1116 /**
1117 * @brief Set LSE oscillator drive capability
1118 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1119 * @rmtoll BDCR1 LSEDRV LL_RCC_LSE_SetDriveCapability
1120 * @param LSEDrive This parameter can be one of the following values:
1121 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1122 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1123 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1124 * @retval None
1125 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1126 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1127 {
1128 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSEDRV, LSEDrive);
1129 }
1130
1131 /**
1132 * @brief Get LSE oscillator drive capability
1133 * @rmtoll BDCR1 LSEDRV LL_RCC_LSE_GetDriveCapability
1134 * @retval Returned value can be one of the following values:
1135 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1136 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1137 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1138 */
LL_RCC_LSE_GetDriveCapability(void)1139 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1140 {
1141 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSEDRV));
1142 }
1143
1144 /**
1145 * @brief Enable Clock security system on LSE.
1146 * @rmtoll BDCR1 LSECSSON LL_RCC_LSE_EnableCSS
1147 * @retval None
1148 */
LL_RCC_LSE_EnableCSS(void)1149 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1150 {
1151 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1152 }
1153
1154 /**
1155 * @brief Disable Clock security system on LSE.
1156 * @note Clock security system can be disabled only after a LSE
1157 * failure detection. In that case it MUST be disabled by software.
1158 * @rmtoll BDCR1 LSECSSON LL_RCC_LSE_DisableCSS
1159 * @retval None
1160 */
LL_RCC_LSE_DisableCSS(void)1161 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1162 {
1163 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1164 }
1165
1166 /**
1167 * @brief Check if LSE oscillator Ready
1168 * @rmtoll BDCR1 LSERDY LL_RCC_LSE_IsReady
1169 * @retval State of bit (1 or 0).
1170 */
LL_RCC_LSE_IsReady(void)1171 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1172 {
1173 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSERDY) == RCC_BDCR1_LSERDY) ? 1UL : 0UL);
1174 }
1175
1176 /**
1177 * @brief Enable LSE oscillator propagation for system clock
1178 * @rmtoll BDCR1 LSESYSEN LL_RCC_LSE_EnablePropagation
1179 * @retval None
1180 */
LL_RCC_LSE_EnablePropagation(void)1181 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
1182 {
1183 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN);
1184 }
1185
1186 /**
1187 * @brief Disable LSE oscillator propagation for system clock
1188 * @rmtoll BDCR1 LSESYSEN LL_RCC_LSE_DisablePropagation
1189 * @retval None
1190 */
LL_RCC_LSE_DisablePropagation(void)1191 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
1192 {
1193 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN);
1194 }
1195
1196 /**
1197 * @brief Check if LSE oscillator propagation for system clock Ready
1198 * @rmtoll BDCR1 LSESYSRDY LL_RCC_LSE_IsPropagationReady
1199 * @retval State of bit (1 or 0).
1200 */
LL_RCC_LSE_IsPropagationReady(void)1201 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void)
1202 {
1203 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSRDY) == RCC_BDCR1_LSESYSRDY) ? 1UL : 0UL);
1204 }
1205
1206 /**
1207 * @brief Check if CSS on LSE failure Detection
1208 * @rmtoll BDCR1 LSECSSD LL_RCC_LSE_IsCSSDetected
1209 * @retval State of bit (1 or 0).
1210 */
LL_RCC_LSE_IsCSSDetected(void)1211 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1212 {
1213 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSD) == RCC_BDCR1_LSECSSD) ? 1UL : 0UL);
1214 }
1215
1216 /**
1217 * @}
1218 */
1219
1220 /** @defgroup RCC_LL_EF_LSI1 LSI1
1221 * @{
1222 */
1223
1224 /**
1225 * @brief Enable LSI1 Oscillator
1226 * @rmtoll BDCR1 LSI1ON LL_RCC_LSI1_Enable
1227 * @retval None
1228 */
LL_RCC_LSI1_Enable(void)1229 __STATIC_INLINE void LL_RCC_LSI1_Enable(void)
1230 {
1231 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON);
1232 }
1233
1234 /**
1235 * @brief Disable LSI1 Oscillator
1236 * @rmtoll BDCR1 LSI1ON LL_RCC_LSI1_Disable
1237 * @retval None
1238 */
LL_RCC_LSI1_Disable(void)1239 __STATIC_INLINE void LL_RCC_LSI1_Disable(void)
1240 {
1241 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON);
1242 }
1243
1244 /**
1245 * @brief Check if LSI1 is Ready
1246 * @rmtoll BDCR1 LSI1RDY LL_RCC_LSI1_IsReady
1247 * @retval State of bit (1 or 0).
1248 */
LL_RCC_LSI1_IsReady(void)1249 __STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady(void)
1250 {
1251 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1RDY) == RCC_BDCR1_LSI1RDY) ? 1UL : 0UL);
1252 }
1253
1254 /**
1255 * @brief Set LSI1 prescaler
1256 * @rmtoll BDCR1 LSI1PREDIV LL_RCC_LSI1_SetPrescaler
1257 * @param LSI1Prescaler This parameter can be one of the following values:
1258 * @arg @ref LL_RCC_LSI_DIV_1
1259 * @arg @ref LL_RCC_LSI_DIV_128
1260 * @retval None
1261 */
LL_RCC_LSI1_SetPrescaler(uint32_t LSI1Prescaler)1262 __STATIC_INLINE void LL_RCC_LSI1_SetPrescaler(uint32_t LSI1Prescaler)
1263 {
1264 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV, LSI1Prescaler);
1265 }
1266
1267 /**
1268 * @brief Get LSI1 prescaler
1269 * @rmtoll BDCR1 LSI1PREDIV LL_RCC_LSI1_GetPrescaler
1270 * @retval Returned value can be one of the following values:
1271 * @arg @ref LL_RCC_LSI_DIV_1
1272 * @arg @ref LL_RCC_LSI_DIV_128
1273 */
LL_RCC_LSI1_GetPrescaler(void)1274 __STATIC_INLINE uint32_t LL_RCC_LSI1_GetPrescaler(void)
1275 {
1276 return (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV));
1277 }
1278
1279 /**
1280 * @}
1281 */
1282
1283 #if defined(RCC_LSI2_SUPPORT)
1284 /** @defgroup RCC_LL_EF_LSI2 LSI2
1285 * @{
1286 */
1287
1288 /**
1289 * @brief Enable LSI2 Oscillator
1290 * @rmtoll BDCR1 LSI2ON LL_RCC_LSI2_Enable
1291 * @retval None
1292 */
LL_RCC_LSI2_Enable(void)1293 __STATIC_INLINE void LL_RCC_LSI2_Enable(void)
1294 {
1295 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON);
1296 }
1297
1298 /**
1299 * @brief Disable LSI2 Oscillator
1300 * @rmtoll BDCR1 LSI2ON LL_RCC_LSI2_Disable
1301 * @retval None
1302 */
LL_RCC_LSI2_Disable(void)1303 __STATIC_INLINE void LL_RCC_LSI2_Disable(void)
1304 {
1305 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON);
1306 }
1307
1308 /**
1309 * @brief Check if LSI2 is Ready
1310 * @rmtoll BDCR1 LSI2RDY LL_RCC_LSI2_IsReady
1311 * @retval State of bit (1 or 0).
1312 */
LL_RCC_LSI2_IsReady(void)1313 __STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady(void)
1314 {
1315 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI2RDY) == RCC_BDCR1_LSI2RDY) ? 1UL : 0UL);
1316 }
1317
1318 /**
1319 * @brief Configure LSI2 oscillator temperature sensitivity
1320 * @rmtoll BDCR2 LSI2CFG LL_RCC_LSI2_SetTempSensitivity
1321 * @param Sensitivity This parameter can be one of the following values:
1322 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_80
1323 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_50
1324 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_20
1325 * @retval None
1326 */
LL_RCC_LSI2_SetTempSensitivity(uint32_t Sensitivity)1327 __STATIC_INLINE void LL_RCC_LSI2_SetTempSensitivity(uint32_t Sensitivity)
1328 {
1329 MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2CFG, Sensitivity);
1330 }
1331
1332 /**
1333 * @brief Get LSI2 oscillator temperature sensitivity
1334 * @rmtoll BDCR2 LSI2CFG LL_RCC_LSI2_GetTempSensitivity
1335 * @retval Returned value can be one of the following values:
1336 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_80
1337 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_50
1338 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_20
1339 */
LL_RCC_LSI2_GetTempSensitivity(void)1340 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetTempSensitivity(void)
1341 {
1342 return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2CFG));
1343 }
1344
1345 /**
1346 * @brief Configure LSI2 operating mode configuration
1347 * @rmtoll BDCR2 LSI2MODE LL_RCC_LSI2_SetOperatingMode
1348 * @param Mode This parameter can be one of the following values:
1349 * @arg @ref LL_RCC_LSI2_NOMINAL_MODE
1350 * @arg @ref LL_RCC_LSI2_LOWPOWER_MODE
1351 * @arg @ref LL_RCC_LSI2_ULTRALOWPOWER_MODE
1352 * @retval None
1353 */
LL_RCC_LSI2_SetOperatingMode(uint32_t Mode)1354 __STATIC_INLINE void LL_RCC_LSI2_SetOperatingMode(uint32_t Mode)
1355 {
1356 MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2MODE, Mode);
1357 }
1358
1359 /**
1360 * @brief Get LSI2 oscillator operating mode
1361 * @rmtoll BDCR2 LSI2MODE LL_RCC_LSI2_GetOperatingMode
1362 * @retval Returned value can be one of the following values:
1363 * @arg @ref LL_RCC_LSI2_NOMINAL_MODE
1364 * @arg @ref LL_RCC_LSI2_LOWPOWER_MODE
1365 * @arg @ref LL_RCC_LSI2_ULTRALOWPOWER_MODE
1366 */
LL_RCC_LSI2_GetOperatingMode(void)1367 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetOperatingMode(void)
1368 {
1369 return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2MODE));
1370 }
1371
1372 /**
1373 * @}
1374 */
1375 #endif /* LSI2 */
1376
1377 /** @defgroup RCC_LL_EF_LSCO LSCO
1378 * @{
1379 */
1380
1381 /**
1382 * @brief Enable Low speed clock
1383 * @rmtoll BDCR1 LSCOEN LL_RCC_LSCO_Enable
1384 * @retval None
1385 */
LL_RCC_LSCO_Enable(void)1386 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1387 {
1388 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN);
1389 }
1390
1391 /**
1392 * @brief Disable Low speed clock
1393 * @rmtoll BDCR1 LSCOEN LL_RCC_LSCO_Disable
1394 * @retval None
1395 */
LL_RCC_LSCO_Disable(void)1396 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1397 {
1398 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN);
1399 }
1400
1401 /**
1402 * @brief Configure Low speed clock selection
1403 * @rmtoll BDCR1 LSCOSEL LL_RCC_LSCO_SetSource
1404 * @param Source This parameter can be one of the following values:
1405 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1406 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1407 * @retval None
1408 */
LL_RCC_LSCO_SetSource(uint32_t Source)1409 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1410 {
1411 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSCOSEL, Source);
1412 }
1413
1414 /**
1415 * @brief Get Low speed clock selection
1416 * @rmtoll BDCR1 LSCOSEL LL_RCC_LSCO_GetSource
1417 * @retval Returned value can be one of the following values:
1418 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1419 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1420 */
LL_RCC_LSCO_GetSource(void)1421 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1422 {
1423 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSCOSEL));
1424 }
1425
1426 /**
1427 * @}
1428 */
1429
1430 /** @defgroup RCC_LL_EF_System System
1431 * @{
1432 */
1433
1434 /**
1435 * @brief Configure the system clock source
1436 * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource
1437 * @param Source This parameter can be one of the following values:
1438 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1439 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1440 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1R
1441 * @retval None
1442 */
LL_RCC_SetSysClkSource(uint32_t Source)1443 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1444 {
1445 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source);
1446 }
1447
1448 /**
1449 * @brief Get the system clock source
1450 * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource
1451 * @retval Returned value can be one of the following values:
1452 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1453 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1454 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R
1455 */
LL_RCC_GetSysClkSource(void)1456 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1457 {
1458 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS));
1459 }
1460
1461 /**
1462 * @brief Set AHB prescaler
1463 * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler
1464 * @param Prescaler This parameter can be one of the following values:
1465 * @arg @ref LL_RCC_SYSCLK_DIV_1
1466 * @arg @ref LL_RCC_SYSCLK_DIV_2
1467 * @arg @ref LL_RCC_SYSCLK_DIV_4
1468 * @arg @ref LL_RCC_SYSCLK_DIV_8
1469 * @arg @ref LL_RCC_SYSCLK_DIV_16
1470 * @retval None
1471 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1472 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1473 {
1474 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
1475 }
1476
1477 /**
1478 * @brief Set Systick clock source
1479 * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
1480 * @param SystickSource This parameter can be one of the following values:
1481 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
1482 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
1483 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
1484 * @retval None
1485 */
LL_RCC_SetSystickClockSource(uint32_t SystickSource)1486 __STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource)
1487 {
1488 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource);
1489 }
1490
1491 /**
1492 * @brief Set APB1 prescaler
1493 * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler
1494 * @param Prescaler This parameter can be one of the following values:
1495 * @arg @ref LL_RCC_APB1_DIV_1
1496 * @arg @ref LL_RCC_APB1_DIV_2
1497 * @arg @ref LL_RCC_APB1_DIV_4
1498 * @arg @ref LL_RCC_APB1_DIV_8
1499 * @arg @ref LL_RCC_APB1_DIV_16
1500 * @retval None
1501 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1502 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1503 {
1504 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
1505 }
1506
1507 /**
1508 * @brief Set APB2 prescaler
1509 * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler
1510 * @param Prescaler This parameter can be one of the following values:
1511 * @arg @ref LL_RCC_APB2_DIV_1
1512 * @arg @ref LL_RCC_APB2_DIV_2
1513 * @arg @ref LL_RCC_APB2_DIV_4
1514 * @arg @ref LL_RCC_APB2_DIV_8
1515 * @arg @ref LL_RCC_APB2_DIV_16
1516 * @retval None
1517 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1518 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1519 {
1520 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
1521 }
1522
1523 /**
1524 * @brief Set APB7 prescaler
1525 * @rmtoll CFGR3 PPRE7 LL_RCC_SetAPB7Prescaler
1526 * @param Prescaler This parameter can be one of the following values:
1527 * @arg @ref LL_RCC_APB7_DIV_1
1528 * @arg @ref LL_RCC_APB7_DIV_2
1529 * @arg @ref LL_RCC_APB7_DIV_4
1530 * @arg @ref LL_RCC_APB7_DIV_8
1531 * @arg @ref LL_RCC_APB7_DIV_16
1532 * @retval None
1533 */
LL_RCC_SetAPB7Prescaler(uint32_t Prescaler)1534 __STATIC_INLINE void LL_RCC_SetAPB7Prescaler(uint32_t Prescaler)
1535 {
1536 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE7, Prescaler);
1537 }
1538
1539 /**
1540 * @brief Set AHB5 prescaler when SYSCLK is PLL1R
1541 * @rmtoll CFGR4 HPRE5 LL_RCC_SetAHB5Prescaler
1542 * @param Prescaler This parameter can be one of the following values:
1543 * @arg @ref LL_RCC_AHB5_DIV_1
1544 * @arg @ref LL_RCC_AHB5_DIV_2
1545 * @arg @ref LL_RCC_AHB5_DIV_3
1546 * @arg @ref LL_RCC_AHB5_DIV_4
1547 * @arg @ref LL_RCC_AHB5_DIV_6
1548 * @retval None
1549 */
LL_RCC_SetAHB5Prescaler(uint32_t Prescaler)1550 __STATIC_INLINE void LL_RCC_SetAHB5Prescaler(uint32_t Prescaler)
1551 {
1552 MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HPRE5, Prescaler);
1553 }
1554
1555 /**
1556 * @brief Set AHB5 divider when SYSCLK is HSI or HSE
1557 * @rmtoll CFGR4 HDIV5 LL_RCC_SetAHB5Divider
1558 * @param Divider This parameter can be one of the following values:
1559 * @arg @ref LL_RCC_AHB5_DIVIDER_1
1560 * @arg @ref LL_RCC_AHB5_DIVIDER_2
1561 * @retval None
1562 */
LL_RCC_SetAHB5Divider(uint32_t Divider)1563 __STATIC_INLINE void LL_RCC_SetAHB5Divider(uint32_t Divider)
1564 {
1565 MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HDIV5, Divider);
1566 }
1567
1568 /**
1569 * @brief Get AHB prescaler
1570 * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler
1571 * @retval Returned value can be one of the following values:
1572 * @arg @ref LL_RCC_SYSCLK_DIV_1
1573 * @arg @ref LL_RCC_SYSCLK_DIV_2
1574 * @arg @ref LL_RCC_SYSCLK_DIV_4
1575 * @arg @ref LL_RCC_SYSCLK_DIV_8
1576 * @arg @ref LL_RCC_SYSCLK_DIV_16
1577 */
LL_RCC_GetAHBPrescaler(void)1578 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1579 {
1580 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
1581 }
1582
1583 /**
1584 * @brief Get Sysctick clock source
1585 * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
1586 * @retval Returned value can be one of the following values:
1587 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
1588 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
1589 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
1590 */
LL_RCC_GetSystickClockSource(void)1591 __STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void)
1592 {
1593 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL));
1594 }
1595
1596 /**
1597 * @brief Get APB1 prescaler
1598 * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler
1599 * @retval Returned value can be one of the following values:
1600 * @arg @ref LL_RCC_APB1_DIV_1
1601 * @arg @ref LL_RCC_APB1_DIV_2
1602 * @arg @ref LL_RCC_APB1_DIV_4
1603 * @arg @ref LL_RCC_APB1_DIV_8
1604 * @arg @ref LL_RCC_APB1_DIV_16
1605 */
LL_RCC_GetAPB1Prescaler(void)1606 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1607 {
1608 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
1609 }
1610
1611 /**
1612 * @brief Get APB2 prescaler
1613 * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler
1614 * @retval Returned value can be one of the following values:
1615 * @arg @ref LL_RCC_APB2_DIV_1
1616 * @arg @ref LL_RCC_APB2_DIV_2
1617 * @arg @ref LL_RCC_APB2_DIV_4
1618 * @arg @ref LL_RCC_APB2_DIV_8
1619 * @arg @ref LL_RCC_APB2_DIV_16
1620 */
LL_RCC_GetAPB2Prescaler(void)1621 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1622 {
1623 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
1624 }
1625
1626 /**
1627 * @brief Get APB7 prescaler
1628 * @rmtoll CFGR3 PPRE7 LL_RCC_GetAPB7Prescaler
1629 * @retval Returned value can be one of the following values:
1630 * @arg @ref LL_RCC_APB7_DIV_1
1631 * @arg @ref LL_RCC_APB7_DIV_2
1632 * @arg @ref LL_RCC_APB7_DIV_4
1633 * @arg @ref LL_RCC_APB7_DIV_8
1634 * @arg @ref LL_RCC_APB7_DIV_16
1635 */
LL_RCC_GetAPB7Prescaler(void)1636 __STATIC_INLINE uint32_t LL_RCC_GetAPB7Prescaler(void)
1637 {
1638 return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE7));
1639 }
1640
1641 /**
1642 * @brief Get AHB5 prescaler when SYSCLK is PLL1R
1643 * @rmtoll CFGR4 HPRE5 LL_RCC_GetAHB5Prescaler
1644 * @retval Returned value can be one of the following values:
1645 * @arg @ref LL_RCC_AHB5_DIV_1
1646 * @arg @ref LL_RCC_AHB5_DIV_2
1647 * @arg @ref LL_RCC_AHB5_DIV_3
1648 * @arg @ref LL_RCC_AHB5_DIV_4
1649 * @arg @ref LL_RCC_AHB5_DIV_6
1650 */
LL_RCC_GetAHB5Prescaler(void)1651 __STATIC_INLINE uint32_t LL_RCC_GetAHB5Prescaler(void)
1652 {
1653 return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HPRE5));
1654 }
1655
1656 /**
1657 * @brief Get AHB5 divider when SYSCLK is HSI or HSE
1658 * @rmtoll CFGR4 HDIV5 LL_RCC_GetAHB5Divider
1659 * @retval Returned value can be one of the following values:
1660 * @arg @ref LL_RCC_AHB5_DIVIDER_1
1661 * @arg @ref LL_RCC_AHB5_DIVIDER_2
1662 */
LL_RCC_GetAHB5Divider(void)1663 __STATIC_INLINE uint32_t LL_RCC_GetAHB5Divider(void)
1664 {
1665 return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HDIV5));
1666 }
1667 /**
1668 * @}
1669 */
1670
1671 /** @defgroup RCC_LL_EF_RADIO RADIO
1672 * @{
1673 */
1674
1675 /**
1676 * @brief Enable the 2.4 GHz RADIO baseband clock
1677 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_EnableBasebandClock
1678 * @retval None
1679 */
LL_RCC_RADIO_EnableBasebandClock(void)1680 __STATIC_INLINE void LL_RCC_RADIO_EnableBasebandClock(void)
1681 {
1682 SET_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1683 }
1684
1685 /**
1686 * @brief Disable the 2.4 GHz RADIO baseband clock
1687 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_DisableBasebandClock
1688 * @retval None
1689 */
LL_RCC_RADIO_DisableBasebandClock(void)1690 __STATIC_INLINE void LL_RCC_RADIO_DisableBasebandClock(void)
1691 {
1692 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1693 }
1694
1695 /**
1696 * @brief Check if 2.4 GHz RADIO baseband clock is enabled
1697 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_IsEnabledBasebandClock
1698 * @retval State of bit (1 or 0).
1699 */
LL_RCC_RADIO_IsEnabledBasebandClock(void)1700 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsEnabledBasebandClock(void)
1701 {
1702 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN) == RCC_RADIOENR_BBCLKEN) ? 1UL : 0UL);
1703 }
1704
1705 /**
1706 * @brief Disable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event
1707 * @rmtoll RADIOENR STRADIOCLKON LL_RCC_RADIO_DisableSleepTimerClock
1708 * @retval None
1709 */
LL_RCC_RADIO_DisableSleepTimerClock(void)1710 __STATIC_INLINE void LL_RCC_RADIO_DisableSleepTimerClock(void)
1711 {
1712 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON);
1713 }
1714
1715 /**
1716 * @brief Check if 2.4 GHz RADIO bus clock and HSE32 oscillator are enabled by 2.4 GHz RADIO sleep timer wakeup event
1717 * @rmtoll RADIOENR STRADIOCLKON LL_RCC_RADIO_IsEnabledSleepTimerClock
1718 * @retval State of bit (1 or 0).
1719 */
LL_RCC_RADIO_IsEnabledSleepTimerClock(void)1720 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsEnabledSleepTimerClock(void)
1721 {
1722 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON) == RCC_RADIOENR_STRADIOCLKON) ? 1UL : 0UL);
1723 }
1724
1725 /**
1726 * @brief Check if 2.4 GHz RADIO bus clock is ready
1727 * @rmtoll RADIOENR RADIOCLKRDY LL_RCC_RADIO_IsBusClockReady
1728 * @retval State of bit (1 or 0).
1729 */
LL_RCC_RADIO_IsBusClockReady(void)1730 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsBusClockReady(void)
1731 {
1732 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_RADIOCLKRDY) == RCC_RADIOENR_RADIOCLKRDY) ? 1UL : 0UL);
1733 }
1734
1735 /**
1736 * @brief Set the 2.4 GHz RADIO sleep timer kernel clock
1737 * @rmtoll BDCR1 RADIOSTSEL LL_RCC_RADIO_SetSleepTimerClockSource
1738 * @param Source This parameter can be one of the following values:
1739 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_NONE
1740 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSE
1741 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSI (*)
1742 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000
1743 *
1744 * (*) value not defined in all devices.
1745 * @retval None
1746 */
LL_RCC_RADIO_SetSleepTimerClockSource(uint32_t Source)1747 __STATIC_INLINE void LL_RCC_RADIO_SetSleepTimerClockSource(uint32_t Source)
1748 {
1749 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL, Source);
1750 }
1751
1752 /**
1753 * @brief Get the 2.4 GHz RADIO sleep timer kernel clock
1754 * @rmtoll BDCR1 RADIOSTSEL LL_RCC_RADIO_GetSleepTimerClockSource
1755 * @retval Returned value can be one of the following values:
1756 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_NONE
1757 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSE
1758 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSI (*)
1759 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000
1760 *
1761 * (*) value not defined in all devices.
1762 */
LL_RCC_RADIO_GetSleepTimerClockSource(void)1763 __STATIC_INLINE uint32_t LL_RCC_RADIO_GetSleepTimerClockSource(void)
1764 {
1765 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL));
1766 }
1767
1768 /**
1769 * @}
1770 */
1771
1772 /** @defgroup RCC_LL_EF_MCO MCO
1773 * @{
1774 */
1775
1776 /**
1777 * @brief Configure MCOx
1778 * @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n
1779 * CFGR1 MCOPRE LL_RCC_ConfigMCO
1780 * @param MCOxSource This parameter can be one of the following values:
1781 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1782 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1783 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1784 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1785 * @arg @ref LL_RCC_MCO1SOURCE_PLL1R
1786 * @arg @ref LL_RCC_MCO1SOURCE_PLL1Q
1787 * @arg @ref LL_RCC_MCO1SOURCE_PLL1P
1788 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1789 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1790 * @arg @ref LL_RCC_MCO1SOURCE_HCLK5
1791 * @param MCOxPrescaler This parameter can be one of the following values:
1792 * @arg @ref LL_RCC_MCO1_DIV_1
1793 * @arg @ref LL_RCC_MCO1_DIV_2
1794 * @arg @ref LL_RCC_MCO1_DIV_4
1795 * @arg @ref LL_RCC_MCO1_DIV_8
1796 * @arg @ref LL_RCC_MCO1_DIV_16
1797 * @retval None
1798 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1799 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1800 {
1801 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler);
1802 }
1803
1804 /**
1805 * @}
1806 */
1807
1808 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1809 * @{
1810 */
1811
1812 /**
1813 * @brief Configure USARTx clock source
1814 * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n
1815 * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n
1816 * @param USARTxSource This parameter can be one of the following values:
1817 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1818 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1819 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1820 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1821 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1822 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1823 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1824 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1825 * @retval None
1826 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1827 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1828 {
1829 MODIFY_REG(RCC->CCIPR1, USARTxSource >> 16U, (USARTxSource & 0x0000FFFFU));
1830 }
1831
1832 /**
1833 * @brief Configure LPUARTx clock source
1834 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource
1835 * @param LPUARTxSource This parameter can be one of the following values:
1836 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK7
1837 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1838 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1839 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1840 * @retval None
1841 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1842 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1843 {
1844 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource);
1845 }
1846
1847 /**
1848 * @brief Configure I2Cx clock source
1849 * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n
1850 * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n
1851 * @param I2CxSource This parameter can be one of the following values:
1852 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1853 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1854 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1855 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7
1856 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1857 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1858 * @retval None
1859 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1860 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1861 {
1862 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U));
1863 MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1864 }
1865
1866 /**
1867 * @brief Configure SPIx clock source
1868 * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n
1869 * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource\n
1870 * @param SPIxSource This parameter can be one of the following values:
1871 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
1872 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
1873 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
1874 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7
1875 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
1876 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
1877 * @retval None
1878 */
LL_RCC_SetSPIClockSource(uint32_t SPIxSource)1879 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource)
1880 {
1881 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U));
1882 MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1883 }
1884
1885 /**
1886 * @brief Configure LPTIMx clock source
1887 * @rmtoll CCIPR3 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n
1888 * CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
1889 * @param LPTIMxSource This parameter can be one of the following values:
1890 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK7
1891 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1892 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1893 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1894 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
1895 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
1896 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
1897 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
1898 * @retval None
1899 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)1900 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
1901 {
1902 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U));
1903 MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1904 }
1905
1906
1907 /**
1908 * @brief Configure SAIx clock source
1909 * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n
1910 * @param SAIxSource This parameter can be one of the following values:
1911 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1P(*)
1912 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q(*)
1913 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK(*)
1914 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN(*)
1915 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI(*)
1916 * (*) Feature not available on all devices of the family
1917 * @retval None
1918 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)1919 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
1920 {
1921 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
1922 }
1923
1924 /**
1925 * @brief Configure RNG clock source
1926 * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource
1927 * @param RNGxSource This parameter can be one of the following values:
1928 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
1929 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
1930 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
1931 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2
1932 * @retval None
1933 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)1934 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
1935 {
1936 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource);
1937 }
1938
1939 /**
1940 * @brief Configure ADC clock source
1941 * @rmtoll CCIPR3 ADCSEL LL_RCC_SetADCClockSource
1942 * @param ADC4Source This parameter can be one of the following values:
1943 * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
1944 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
1945 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL1P
1946 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSE
1947 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
1948 * @retval None
1949 */
LL_RCC_SetADCClockSource(uint32_t ADC4Source)1950 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADC4Source)
1951 {
1952 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCSEL, ADC4Source);
1953 }
1954
1955
1956 /**
1957 * @brief Get USARTx clock source
1958 * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n
1959 * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n
1960 * @param USARTx This parameter can be one of the following values:
1961 * @arg @ref LL_RCC_USART1_CLKSOURCE
1962 * @arg @ref LL_RCC_USART2_CLKSOURCE
1963 * @retval Returned value can be one of the following values:
1964 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1965 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1966 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1967 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1968 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1969 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1970 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1971 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1972 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1973 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1974 {
1975 return (uint32_t)(READ_BIT(RCC->CCIPR1, USARTx) | (USARTx << 16U));
1976 }
1977
1978 /**
1979 * @brief Get LPUARTx clock source
1980 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_GetLPUARTClockSource
1981 * @param LPUARTx This parameter can be one of the following values:
1982 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
1983 * @retval Returned value can be one of the following values:
1984 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK7
1985 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1986 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1987 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1988 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)1989 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
1990 {
1991 return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx));
1992 }
1993
1994 /**
1995 * @brief Get I2Cx clock source
1996 * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n
1997 * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n
1998 * @param I2Cx This parameter can be one of the following values:
1999 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2000 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2001 * @retval Returned value can be one of the following values:
2002 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2003 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2004 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2005 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7
2006 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2007 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2008 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2009 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2010 {
2011 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U));
2012 return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL));
2013 }
2014
2015 /**
2016 * @brief Get SPIx clock source
2017 * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n
2018 * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource
2019 * @param SPIx This parameter can be one of the following values:
2020 * @arg @ref LL_RCC_SPI1_CLKSOURCE
2021 * @arg @ref LL_RCC_SPI3_CLKSOURCE
2022 * @retval Returned value can be one of the following values:
2023 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
2024 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
2025 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
2026 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7
2027 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
2028 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
2029 */
LL_RCC_GetSPIClockSource(uint32_t SPIx)2030 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx)
2031 {
2032 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U));
2033 return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL));
2034 }
2035
2036 /**
2037 * @brief Get LPTIMx clock source
2038 * @rmtoll CCIPR3 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
2039 * CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
2040 * @param LPTIMx This parameter can be one of the following values:
2041 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2042 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2043 * @retval Returned value can be one of the following values:
2044 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK7
2045 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2046 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2047 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2048 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2049 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2050 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2051 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2052 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2053 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2054 {
2055 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U));
2056 return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL));
2057 }
2058
2059 /**
2060 * @brief Set Tim Input capture clock source
2061 * @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource
2062 * @param TIMICSource This parameter can be one of the following combined values:
2063 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
2064 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
2065 * @note HSI clock without division is also available when TIMICSEL[2] is 1.
2066 * @retval None
2067 */
LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)2068 __STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)
2069 {
2070 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource);
2071 }
2072
2073 /**
2074 * @brief Get Tim Input capture clock source
2075 * @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource
2076 * @retval Returned value can be one of the following combined values:
2077 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
2078 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
2079 */
LL_RCC_GetTIMICClockSource(void)2080 __STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void)
2081 {
2082 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL));
2083 }
2084
2085 /**
2086 * @brief Get SAIx clock source
2087 * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n
2088 * @param SAIx This parameter can be one of the following values:
2089 * @arg @ref LL_RCC_SAI1_CLKSOURCE(*)
2090 * @retval Returned value can be one of the following values:
2091 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1P(*)
2092 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q(*)
2093 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK(*)
2094 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN(*)
2095 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI(*)
2096 * (*) Feature not available on all devices of the family
2097 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)2098 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2099 {
2100 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
2101 }
2102
2103 /**
2104 * @brief Get RNGx clock source
2105 * @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource
2106 * @param RNGx This parameter can be one of the following values:
2107 * @arg @ref LL_RCC_RNG_CLKSOURCE
2108 * @retval Returned value can be one of the following values:
2109 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2110 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2111 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
2112 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2
2113 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2114 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2115 {
2116 return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx));
2117 }
2118
2119 /**
2120 * @brief Get ADCx clock source
2121 * @rmtoll CCIPR3 ADCSEL LL_RCC_GetADCClockSource
2122 * @param ADCx This parameter can be one of the following values:
2123 * @arg @ref LL_RCC_ADC_CLKSOURCE
2124 * @retval Returned value can be one of the following values:
2125 * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
2126 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2127 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL1P
2128 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSE
2129 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2130 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2131 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2132 {
2133 return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCx));
2134 }
2135
2136
2137 /**
2138 * @}
2139 */
2140
2141 /** @defgroup RCC_LL_EF_RTC RTC
2142 * @{
2143 */
2144
2145 /**
2146 * @brief Set RTC Clock Source
2147 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2148 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2149 * set). The BDRST bit can be used to reset them.
2150 * @rmtoll BDCR1 RTCSEL LL_RCC_SetRTCClockSource
2151 * @param Source This parameter can be one of the following values:
2152 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2153 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2154 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2155 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2156 * @retval None
2157 */
LL_RCC_SetRTCClockSource(uint32_t Source)2158 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2159 {
2160 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RTCSEL, Source);
2161 }
2162
2163 /**
2164 * @brief Get RTC Clock Source
2165 * @rmtoll BDCR1 RTCSEL LL_RCC_GetRTCClockSource
2166 * @retval Returned value can be one of the following values:
2167 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2168 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2169 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2170 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2171 */
LL_RCC_GetRTCClockSource(void)2172 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2173 {
2174 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_RTCSEL));
2175 }
2176
2177 /**
2178 * @brief Force the Backup domain reset
2179 * @rmtoll BDCR1 BDRST LL_RCC_ForceBackupDomainReset
2180 * @retval None
2181 */
LL_RCC_ForceBackupDomainReset(void)2182 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2183 {
2184 SET_BIT(RCC->BDCR1, RCC_BDCR1_BDRST);
2185 }
2186
2187 /**
2188 * @brief Release the Backup domain reset
2189 * @rmtoll BDCR1 BDRST LL_RCC_ReleaseBackupDomainReset
2190 * @retval None
2191 */
LL_RCC_ReleaseBackupDomainReset(void)2192 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2193 {
2194 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_BDRST);
2195 }
2196
2197 /**
2198 * @}
2199 */
2200
2201 /** @defgroup RCC_LL_EF_PLL1 PLL1
2202 * @{
2203 */
2204
2205 /**
2206 * @brief Enable PLL1
2207 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
2208 * @retval None
2209 */
LL_RCC_PLL1_Enable(void)2210 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
2211 {
2212 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
2213 }
2214
2215 /**
2216 * @brief Disable PLL1
2217 * @note Cannot be disabled if the PLL1 clock is used as the system clock
2218 * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable
2219 * @retval None
2220 */
LL_RCC_PLL1_Disable(void)2221 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
2222 {
2223 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
2224 }
2225
2226 /**
2227 * @brief Check if PLL1 Ready
2228 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
2229 * @retval State of bit (1 or 0).
2230 */
LL_RCC_PLL1_IsReady(void)2231 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
2232 {
2233 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL);
2234 }
2235
2236 /**
2237 * @brief Enable prescaler division on PLL1RCLK for SYSCLK
2238 * @rmtoll PLL1CFGR PLL1RCLKPRE LL_RCC_PLL1_EnablePLL1RCLKDivision
2239 * @retval None
2240 */
LL_RCC_PLL1_EnablePLL1RCLKDivision(void)2241 __STATIC_INLINE void LL_RCC_PLL1_EnablePLL1RCLKDivision(void)
2242 {
2243 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE);
2244 }
2245
2246 /**
2247 * @brief Disable PLL1RCLK for SYSCLK prescaler division
2248 * @rmtoll PLL1CFGR PLL1RCLKPRE LL_RCC_PLL1_DisablePLL1RCLKDivision
2249 * @retval None
2250 */
LL_RCC_PLL1_DisablePLL1RCLKDivision(void)2251 __STATIC_INLINE void LL_RCC_PLL1_DisablePLL1RCLKDivision(void)
2252 {
2253 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE);
2254 }
2255
2256 /**
2257 * @brief Set the division step of PLL1RCLK clock for SYSCLK
2258 * @rmtoll PLL1CFGR PLL1RCLKPRESTEP LL_RCC_PLL1_SetPLL1RCLKDivisionStep
2259 * @param Step This parameter can be one of the following values:
2260 * @arg @ref LL_RCC_PLL1RCLK_2_STEP_DIV
2261 * @arg @ref LL_RCC_PLL1RCLK_3_STEP_DIV
2262 * @retval None
2263 */
LL_RCC_PLL1_SetPLL1RCLKDivisionStep(uint32_t Step)2264 __STATIC_INLINE void LL_RCC_PLL1_SetPLL1RCLKDivisionStep(uint32_t Step)
2265 {
2266 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP, Step);
2267 }
2268
2269 /**
2270 * @brief Get the division step of PLL1RCLK clock for SYSCLK
2271 * @rmtoll PLL1CFGR PLL1RCLKPRESTEP LL_RCC_PLL1_GetPLL1RCLKDivisionStep
2272 * @retval Returned value can be one of the following values:
2273 * @arg @ref LL_RCC_PLL1RCLK_2_STEP_DIV
2274 * @arg @ref LL_RCC_PLL1RCLK_3_STEP_DIV
2275 */
LL_RCC_PLL1_GetPLL1RCLKDivisionStep(void)2276 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetPLL1RCLKDivisionStep(void)
2277 {
2278 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP));
2279 }
2280
2281 /**
2282 * @brief Check if prescaler division on PLL1RCLK for SYSCLK is ready
2283 * @rmtoll PLL1CFGR PLL1RCLKPRERDY LL_RCC_PLL1_IsPLL1RCLKDivisionReady
2284 * @retval State of bit (1 or 0).
2285 */
LL_RCC_PLL1_IsPLL1RCLKDivisionReady(void)2286 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsPLL1RCLKDivisionReady(void)
2287 {
2288 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRERDY) == RCC_PLL1CFGR_PLL1RCLKPRERDY) ? 1UL : 0UL);
2289 }
2290
2291 /**
2292 * @brief Configure PLL1R used for SYSCLK Domain
2293 * @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled.
2294 * @note PLLN/PLLR can be written only when PLL1 is disabled.
2295 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1R\n
2296 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1R\n
2297 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1R\n
2298 * PLL1DIVR PLL1R LL_RCC_PLL1_ConfigDomain_PLL1R
2299 * @param Source This parameter can be one of the following values:
2300 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2301 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2302 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2303 * @param PLLM parameter can be a value between 1 and 16
2304 * @param PLLR parameter can be a value between 1 and 128
2305 * @param PLLN parameter can be a value between 4 and 512
2306 * @retval None
2307 */
LL_RCC_PLL1_ConfigDomain_PLL1R(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2308 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1R(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2309 {
2310 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2311 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << RCC_PLL1DIVR_PLL1R_Pos));
2312 }
2313
2314 /**
2315 * @brief Configure PLL1P
2316 * @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled.
2317 * @note This can be selected for ADC and SAI
2318 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1P\n
2319 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1P\n
2320 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1P\n
2321 * PLL1DIVR PLL1P LL_RCC_PLL1_ConfigDomain_PLL1P
2322 * @param Source This parameter can be one of the following values:
2323 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2324 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2325 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2326 * @param PLLM parameter can be a value between 1 and 16
2327 * @param PLLN parameter can be a value between 4 and 512
2328 * @param PLLP parameter can be a value between 2 and 128
2329 * @retval None
2330 */
LL_RCC_PLL1_ConfigDomain_PLL1P(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2331 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1P(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2332 {
2333 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2334 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << RCC_PLL1DIVR_PLL1P_Pos));
2335 }
2336
2337 /**
2338 * @brief Configure PLL1Q
2339 * @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled.
2340 * @note This can be selected for RNG and SAI
2341 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2342 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2343 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2344 * PLL1DIVR PLL1Q LL_RCC_PLL1_ConfigDomain_PLL1Q
2345 * @param Source This parameter can be one of the following values:
2346 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2347 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2348 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2349 * @param PLLM parameter can be a value between 1 and 16
2350 * @param PLLN parameter can be a value between 4 and 512
2351 * @param PLLQ parameter can be a value between 1 and 128
2352 * @retval None
2353 */
LL_RCC_PLL1_ConfigDomain_PLL1Q(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2354 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1Q(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2355 {
2356 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2357 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos));
2358 }
2359
2360 /**
2361 * @brief Configure PLL1 clock source
2362 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource
2363 * @param PLL1Source This parameter can be one of the following values:
2364 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2365 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2366 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2367 * @retval None
2368 */
LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)2369 __STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)
2370 {
2371 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source);
2372 }
2373
2374 /**
2375 * @brief Get the oscillator used as PLL1 clock source.
2376 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource
2377 * @retval Returned value can be one of the following values:
2378 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2379 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2380 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2381 */
LL_RCC_PLL1_GetMainSource(void)2382 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void)
2383 {
2384 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC));
2385 }
2386
2387 /**
2388 * @brief Set PLL1 multiplication factor for VCO
2389 * @rmtoll PLL1DIVR PLL1N LL_RCC_PLL1_SetN
2390 * @param PLL1N parameter can be a value between 4 and 512
2391 */
LL_RCC_PLL1_SetN(uint32_t PLL1N)2392 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N)
2393 {
2394 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos);
2395 }
2396
2397 /**
2398 * @brief Get PLL1 multiplication factor for VCO
2399 * @rmtoll PLL1DIVR PLL1N LL_RCC_PLL1_GetN
2400 * @retval Between 4 and 512
2401 */
LL_RCC_PLL1_GetN(void)2402 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
2403 {
2404 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL);
2405 }
2406
2407
2408 /**
2409 * @brief Set PLL1 division factor for PLL1P
2410 * @note Used for PLL1PCLK selected ADC and SAI
2411 * @rmtoll PLL1DIVR PLL1P LL_RCC_PLL1_SetP
2412 * @param PLL1P parameter can be a value between 2 and 128
2413 */
LL_RCC_PLL1_SetP(uint32_t PLL1P)2414 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P)
2415 {
2416 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos);
2417 }
2418
2419 /**
2420 * @brief Get PLL1 division factor for PLL1P
2421 * @note Used for PLL1PCLK selected ADC and SAI
2422 * @rmtoll PLL1DIVR PLL1P LL_RCC_PLL1_GetP
2423 * @retval Between 2 and 128
2424 */
LL_RCC_PLL1_GetP(void)2425 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
2426 {
2427 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL);
2428 }
2429
2430
2431 /**
2432 * @brief Set PLL1 division factor for PLL1Q
2433 * @note Used for PLL1QCLK selected for RNG and SAI
2434 * @rmtoll PLL1DIVR PLL1Q LL_RCC_PLL1_SetQ
2435 * @param PLL1Q parameter can be a value between 1 and 128
2436 */
LL_RCC_PLL1_SetQ(uint32_t PLL1Q)2437 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q)
2438 {
2439 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos);
2440 }
2441
2442 /**
2443 * @brief Get PLL1 division factor for PLL1Q
2444 * @note Used for PLL1QCLK selected for RNG and SAI
2445 * @rmtoll PLL1DIVR PLL1Q LL_RCC_PLL1_GetQ
2446 * @retval Between 1 and 128
2447 */
LL_RCC_PLL1_GetQ(void)2448 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
2449 {
2450 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL);
2451 }
2452
2453 /**
2454 * @brief Set PLL1 division factor for PLL1R
2455 * @note Used for PLL1RCLK selected for system clock
2456 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR
2457 * @param PLL1R parameter can be a value between 1 and 128
2458 */
LL_RCC_PLL1_SetR(uint32_t PLL1R)2459 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R)
2460 {
2461 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos);
2462 }
2463
2464 /**
2465 * @brief Get PLL1 division factor for PLL1R
2466 * @note Used for PLL1RCLK selected for system clock
2467 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR
2468 * @retval Between 1 and 128
2469 */
LL_RCC_PLL1_GetR(void)2470 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
2471 {
2472 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL);
2473 }
2474
2475 /**
2476 * @brief Set Division factor for PLL1
2477 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider
2478 * @param PLL1M parameter can be a value between 1 and 8
2479 */
LL_RCC_PLL1_SetDivider(uint32_t PLL1M)2480 __STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M)
2481 {
2482 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos);
2483 }
2484
2485 /**
2486 * @brief Get Division factor for PLL1
2487 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider
2488 * @retval Between 1 and 8
2489 */
LL_RCC_PLL1_GetDivider(void)2490 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void)
2491 {
2492 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL);
2493 }
2494
2495 /**
2496 * @brief Enable PLL1P output
2497 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_PLL1P
2498 * @retval None
2499 */
LL_RCC_PLL1_EnableDomain_PLL1P(void)2500 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1P(void)
2501 {
2502 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
2503 }
2504
2505 /**
2506 * @brief Disable PLL1P output
2507 * @note In order to save power, when the PLL1PCLK of the PLL1 is
2508 * not used, should be 0
2509 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_PLL1P
2510 * @retval None
2511 */
LL_RCC_PLL1_DisableDomain_PLL1P(void)2512 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1P(void)
2513 {
2514 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
2515 }
2516
2517 /**
2518 * @brief Check if PLL1P output is enabled
2519 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_PLL1P
2520 * @retval State of bit (1 or 0).
2521 */
LL_RCC_PLL1_IsEnabledDomain_PLL1P(void)2522 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1P(void)
2523 {
2524 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == RCC_PLL1CFGR_PLL1PEN) ? 1UL : 0UL);
2525 }
2526
2527 /**
2528 * @brief Enable PLL1Q output
2529 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_PLL1Q
2530 * @retval None
2531 */
LL_RCC_PLL1_EnableDomain_PLL1Q(void)2532 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1Q(void)
2533 {
2534 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
2535 }
2536
2537 /**
2538 * @brief Disable PLL1Q output
2539 * @note In order to save power, when the PLL1QCLK of the PLL1 is
2540 * not used, should be 0
2541 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_PLL1Q
2542 * @retval None
2543 */
LL_RCC_PLL1_DisableDomain_PLL1Q(void)2544 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1Q(void)
2545 {
2546 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
2547 }
2548
2549 /**
2550 * @brief Check if PLL1Q output is enabled
2551 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_PLL1Q
2552 * @retval State of bit (1 or 0).
2553 */
LL_RCC_PLL1_IsEnabledDomain_PLL1Q(void)2554 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1Q(void)
2555 {
2556 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == RCC_PLL1CFGR_PLL1QEN) ? 1UL : 0UL);
2557 }
2558
2559 /**
2560 * @brief Enable PLL1R output mapped on SYSCLK domain
2561 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_PLL1R
2562 * @retval None
2563 */
LL_RCC_PLL1_EnableDomain_PLL1R(void)2564 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1R(void)
2565 {
2566 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
2567 }
2568
2569 /**
2570 * @brief Disable PLL1 output mapped on SYSCLK domain
2571 * @note Cannot be disabled if the PLL1 clock is used as the system
2572 * clock
2573 * @note In order to save power, when the PLL1RCLK of the PLL1 is
2574 * not used, PLL1 should be 0
2575 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_PLL1R
2576 * @retval None
2577 */
LL_RCC_PLL1_DisableDomain_PLL1R(void)2578 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1R(void)
2579 {
2580 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
2581 }
2582
2583 /**
2584 * @brief Check if PLL1R output mapped on SYSCLK domain clock is enabled
2585 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_PLL1R
2586 * @retval State of bit (1 or 0).
2587 */
LL_RCC_PLL1_IsEnabledDomain_PLL1R(void)2588 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1R(void)
2589 {
2590 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL);
2591 }
2592
2593 /**
2594 * @brief Enable PLL1 FRACN
2595 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
2596 * @retval None
2597 */
LL_RCC_PLL1FRACN_Enable(void)2598 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
2599 {
2600 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
2601 }
2602
2603 /**
2604 * @brief Check if PLL1 FRACN is enabled
2605 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
2606 * @retval State of bit (1 or 0).
2607 */
LL_RCC_PLL1FRACN_IsEnabled(void)2608 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
2609 {
2610 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL);
2611 }
2612
2613 /**
2614 * @brief Disable PLL1 FRACN
2615 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable
2616 * @retval None
2617 */
LL_RCC_PLL1FRACN_Disable(void)2618 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
2619 {
2620 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
2621 }
2622
2623 /**
2624 * @brief Set PLL1 FRACN Coefficient
2625 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN
2626 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
2627 */
LL_RCC_PLL1_SetFRACN(uint32_t FRACN)2628 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
2629 {
2630 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos);
2631 }
2632
2633 /**
2634 * @brief Get PLL1 FRACN Coefficient
2635 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN
2636 * @retval A value between 0 and 8191 (0x1FFF)
2637 */
LL_RCC_PLL1_GetFRACN(void)2638 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
2639 {
2640 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos);
2641 }
2642
2643 /**
2644 * @brief Set PLL1 VCO Input Range
2645 * @note This API shall be called only when PLL1 is disabled.
2646 * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
2647 * @param InputRange This parameter can be one of the following values:
2648 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
2649 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
2650 * @retval None
2651 */
LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)2652 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
2653 {
2654 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos);
2655 }
2656
2657 /**
2658 * @}
2659 */
2660
2661 #if defined(RCC_PRIVCFGR_NSPRIV)
2662 /** @defgroup RCC_LL_EF_PRIV Privileged mode
2663 * @{
2664 */
2665
2666 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2667 /**
2668 * @brief Enable Secure Privileged mode
2669 * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode
2670 * @retval None
2671 */
LL_RCC_EnableSecPrivilegedMode(void)2672 __STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void)
2673 {
2674 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2675 }
2676
2677 /**
2678 * @brief Disable Secure Privileged mode
2679 * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode
2680 * @retval None
2681 */
LL_RCC_DisableSecPrivilegedMode(void)2682 __STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void)
2683 {
2684 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2685 }
2686
2687 /**
2688 * @brief Check if Secure Privileged mode has been enabled or not
2689 * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode
2690 * @retval State of bit (1 or 0).
2691 */
LL_RCC_IsEnabledSecPrivilegedMode(void)2692 __STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void)
2693 {
2694 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL);
2695 }
2696 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
2697
2698 /**
2699 * @brief Enable Non Secure Privileged mode
2700 * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode
2701 * @retval None
2702 */
LL_RCC_EnableNSecPrivilegedMode(void)2703 __STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void)
2704 {
2705 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2706 }
2707
2708 /**
2709 * @brief Disable Non Secure Privileged mode
2710 * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode
2711 * @retval None
2712 */
LL_RCC_DisableNSecPrivilegedMode(void)2713 __STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void)
2714 {
2715 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2716 }
2717
2718 /**
2719 * @brief Check if Non Secure Privileged mode has been enabled or not
2720 * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode
2721 * @retval State of bit (1 or 0).
2722 */
LL_RCC_IsEnabledNSecPrivilegedMode(void)2723 __STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void)
2724 {
2725 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
2726 }
2727
2728 /**
2729 * @}
2730 */
2731 #endif /* RCC_PRIVCFGR_NSPRIV */
2732
2733 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2734 * @{
2735 */
2736
2737 /**
2738 * @brief Clear LSI1 ready interrupt flag
2739 * @rmtoll CICR LSI1RDYC LL_RCC_ClearFlag_LSI1RDY
2740 * @retval None
2741 */
LL_RCC_ClearFlag_LSI1RDY(void)2742 __STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY(void)
2743 {
2744 SET_BIT(RCC->CICR, RCC_CICR_LSI1RDYC);
2745 }
2746
2747 #if defined(RCC_LSI2_SUPPORT)
2748 /**
2749 * @brief Clear LSI2 ready interrupt flag
2750 * @rmtoll CICR LSI2RDYC LL_RCC_ClearFlag_LSI2RDY
2751 * @retval None
2752 */
LL_RCC_ClearFlag_LSI2RDY(void)2753 __STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY(void)
2754 {
2755 SET_BIT(RCC->CICR, RCC_CICR_LSI2RDYC);
2756 }
2757 #endif /* RCC_BDCR1_LSI2ON */
2758
2759 /**
2760 * @brief Clear LSE ready interrupt flag
2761 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
2762 * @retval None
2763 */
LL_RCC_ClearFlag_LSERDY(void)2764 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2765 {
2766 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
2767 }
2768
2769 /**
2770 * @brief Clear HSI ready interrupt flag
2771 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2772 * @retval None
2773 */
LL_RCC_ClearFlag_HSIRDY(void)2774 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2775 {
2776 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
2777 }
2778
2779 /**
2780 * @brief Clear HSE ready interrupt flag
2781 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
2782 * @retval None
2783 */
LL_RCC_ClearFlag_HSERDY(void)2784 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2785 {
2786 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
2787 }
2788
2789 /**
2790 * @brief Clear PLL1 ready interrupt flag
2791 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
2792 * @retval None
2793 */
LL_RCC_ClearFlag_PLL1RDY(void)2794 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
2795 {
2796 SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC);
2797 }
2798
2799 /**
2800 * @brief Clear Clock security system interrupt flag
2801 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
2802 * @retval None
2803 */
LL_RCC_ClearFlag_HSECSS(void)2804 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2805 {
2806 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
2807 }
2808
2809
2810 /**
2811 * @brief Check if LSI1 ready interrupt occurred or not
2812 * @rmtoll CIFR LSI1RDYF LL_RCC_IsActiveFlag_LSI1RDY
2813 * @retval State of bit (1 or 0).
2814 */
LL_RCC_IsActiveFlag_LSI1RDY(void)2815 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY(void)
2816 {
2817 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI1RDYF) == RCC_CIFR_LSI1RDYF) ? 1UL : 0UL);
2818 }
2819
2820 #if defined(RCC_LSI2_SUPPORT)
2821 /**
2822 * @brief Check if LSI2 ready interrupt occurred or not
2823 * @rmtoll CIFR LSI2RDYF LL_RCC_IsActiveFlag_LSI2RDY
2824 * @retval State of bit (1 or 0).
2825 */
LL_RCC_IsActiveFlag_LSI2RDY(void)2826 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY(void)
2827 {
2828 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI2RDYF) == RCC_CIFR_LSI2RDYF) ? 1UL : 0UL);
2829 }
2830 #endif /* RCC_BDCR1_LSI2ON */
2831
2832 /**
2833 * @brief Check if LSE ready interrupt occurred or not
2834 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2835 * @retval State of bit (1 or 0).
2836 */
LL_RCC_IsActiveFlag_LSERDY(void)2837 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2838 {
2839 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
2840 }
2841
2842 /**
2843 * @brief Check if HSI ready interrupt occurred or not
2844 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2845 * @retval State of bit (1 or 0).
2846 */
LL_RCC_IsActiveFlag_HSIRDY(void)2847 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2848 {
2849 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
2850 }
2851
2852 /**
2853 * @brief Check if HSE ready interrupt occurred or not
2854 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2855 * @retval State of bit (1 or 0).
2856 */
LL_RCC_IsActiveFlag_HSERDY(void)2857 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2858 {
2859 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
2860 }
2861
2862 /**
2863 * @brief Check if PLL1 ready interrupt occurred or not
2864 * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
2865 * @retval State of bit (1 or 0).
2866 */
LL_RCC_IsActiveFlag_PLL1RDY(void)2867 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
2868 {
2869 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
2870 }
2871
2872 /**
2873 * @brief Check if Clock security system interrupt occurred or not
2874 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
2875 * @retval State of bit (1 or 0).
2876 */
LL_RCC_IsActiveFlag_HSECSS(void)2877 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2878 {
2879 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL);
2880 }
2881
2882 /**
2883 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2884 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2885 * @retval State of bit (1 or 0).
2886 */
LL_RCC_IsActiveFlag_IWDGRST(void)2887 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2888 {
2889 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
2890 }
2891
2892 /**
2893 * @brief Check if RCC flag Low Power reset is set or not.
2894 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2895 * @retval State of bit (1 or 0).
2896 */
LL_RCC_IsActiveFlag_LPWRRST(void)2897 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2898 {
2899 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
2900 }
2901
2902 /**
2903 * @brief Check if RCC flag is set or not.
2904 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2905 * @retval State of bit (1 or 0).
2906 */
LL_RCC_IsActiveFlag_OBLRST(void)2907 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2908 {
2909 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
2910 }
2911
2912 /**
2913 * @brief Check if RCC flag Pin reset is set or not.
2914 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2915 * @retval State of bit (1 or 0).
2916 */
LL_RCC_IsActiveFlag_PINRST(void)2917 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2918 {
2919 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
2920 }
2921
2922 /**
2923 * @brief Check if RCC flag Software reset is set or not.
2924 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2925 * @retval State of bit (1 or 0).
2926 */
LL_RCC_IsActiveFlag_SFTRST(void)2927 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2928 {
2929 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
2930 }
2931
2932 #if defined(WWDG)
2933 /**
2934 * @brief Check if RCC flag Window Watchdog reset is set or not.
2935 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2936 * @retval State of bit (1 or 0).
2937 */
LL_RCC_IsActiveFlag_WWDGRST(void)2938 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2939 {
2940 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
2941 }
2942 #endif /* WWDG */
2943
2944 /**
2945 * @brief Check if RCC flag BOR reset is set or not.
2946 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
2947 * @retval State of bit (1 or 0).
2948 */
LL_RCC_IsActiveFlag_BORRST(void)2949 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
2950 {
2951 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
2952 }
2953
2954 /**
2955 * @brief Set RMVF bit to clear the reset flags.
2956 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2957 * @retval None
2958 */
LL_RCC_ClearResetFlags(void)2959 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2960 {
2961 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2962 }
2963
2964 /* Alias for portability */
2965 #define LL_RCC_PLL1_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_PLL1R
2966
2967 /**
2968 * @}
2969 */
2970
2971 /** @defgroup RCC_LL_EF_IT_Management IT Management
2972 * @{
2973 */
2974
2975 /**
2976 * @brief Enable LSI1 ready interrupt
2977 * @rmtoll CIER LSI1RDYIE LL_RCC_EnableIT_LSI1RDY
2978 * @retval None
2979 */
LL_RCC_EnableIT_LSI1RDY(void)2980 __STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY(void)
2981 {
2982 SET_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
2983 }
2984
2985 #if defined(RCC_LSI2_SUPPORT)
2986 /**
2987 * @brief Enable LSI2 ready interrupt
2988 * @rmtoll CIER LSI2RDYIE LL_RCC_EnableIT_LSI2RDY
2989 * @retval None
2990 */
LL_RCC_EnableIT_LSI2RDY(void)2991 __STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY(void)
2992 {
2993 SET_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
2994 }
2995 #endif /* RCC_BDCR1_LSI2ON */
2996
2997 /**
2998 * @brief Enable LSE ready interrupt
2999 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
3000 * @retval None
3001 */
LL_RCC_EnableIT_LSERDY(void)3002 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
3003 {
3004 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3005 }
3006
3007 /**
3008 * @brief Enable HSI ready interrupt
3009 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
3010 * @retval None
3011 */
LL_RCC_EnableIT_HSIRDY(void)3012 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
3013 {
3014 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3015 }
3016
3017 /**
3018 * @brief Enable HSE ready interrupt
3019 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
3020 * @retval None
3021 */
LL_RCC_EnableIT_HSERDY(void)3022 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
3023 {
3024 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3025 }
3026
3027 /**
3028 * @brief Enable PLL1 ready interrupt
3029 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
3030 * @retval None
3031 */
LL_RCC_EnableIT_PLL1RDY(void)3032 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
3033 {
3034 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
3035 }
3036
3037 /**
3038 * @brief Disable LSI1 ready interrupt
3039 * @rmtoll CIER LSI1RDYIE LL_RCC_DisableIT_LSI1RDY
3040 * @retval None
3041 */
LL_RCC_DisableIT_LSI1RDY(void)3042 __STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY(void)
3043 {
3044 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
3045 }
3046
3047 #if defined(RCC_LSI2_SUPPORT)
3048 /**
3049 * @brief Disable LSI2 ready interrupt
3050 * @rmtoll CIER LSI2RDYIE LL_RCC_DisableIT_LSI2RDY
3051 * @retval None
3052 */
LL_RCC_DisableIT_LSI2RDY(void)3053 __STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY(void)
3054 {
3055 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
3056 }
3057 #endif /* RCC_BDCR1_LSI2ON */
3058
3059 /**
3060 * @brief Disable LSE ready interrupt
3061 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
3062 * @retval None
3063 */
LL_RCC_DisableIT_LSERDY(void)3064 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
3065 {
3066 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3067 }
3068
3069 /**
3070 * @brief Disable HSI ready interrupt
3071 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
3072 * @retval None
3073 */
LL_RCC_DisableIT_HSIRDY(void)3074 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
3075 {
3076 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3077 }
3078
3079 /**
3080 * @brief Disable HSE ready interrupt
3081 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
3082 * @retval None
3083 */
LL_RCC_DisableIT_HSERDY(void)3084 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
3085 {
3086 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3087 }
3088
3089 /**
3090 * @brief Disable PLL1 ready interrupt
3091 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
3092 * @retval None
3093 */
LL_RCC_DisableIT_PLL1RDY(void)3094 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
3095 {
3096 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
3097 }
3098
3099 /**
3100 * @brief Checks if LSI1 ready interrupt source is enabled or disabled.
3101 * @rmtoll CIER LSI1RDYIE LL_RCC_IsEnabledIT_LSI1RDY
3102 * @retval State of bit (1 or 0).
3103 */
LL_RCC_IsEnabledIT_LSI1RDY(void)3104 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY(void)
3105 {
3106 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE) == RCC_CIER_LSI1RDYIE) ? 1UL : 0UL);
3107 }
3108
3109 #if defined(RCC_LSI2_SUPPORT)
3110 /**
3111 * @brief Checks if LSI2 ready interrupt source is enabled or disabled.
3112 * @rmtoll CIER LSI2RDYIE LL_RCC_IsEnabledIT_LSI2RDY
3113 * @retval State of bit (1 or 0).
3114 */
LL_RCC_IsEnabledIT_LSI2RDY(void)3115 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY(void)
3116 {
3117 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE) == RCC_CIER_LSI2RDYIE) ? 1UL : 0UL);
3118 }
3119 #endif /* RCC_BDCR1_LSI2ON */
3120
3121 /**
3122 * @brief Checks if LSE ready interrupt source is enabled or disabled.
3123 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
3124 * @retval State of bit (1 or 0).
3125 */
LL_RCC_IsEnabledIT_LSERDY(void)3126 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
3127 {
3128 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
3129 }
3130
3131
3132 /**
3133 * @brief Checks if HSI ready interrupt source is enabled or disabled.
3134 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
3135 * @retval State of bit (1 or 0).
3136 */
LL_RCC_IsEnabledIT_HSIRDY(void)3137 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
3138 {
3139 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
3140 }
3141
3142 /**
3143 * @brief Checks if HSE ready interrupt source is enabled or disabled.
3144 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
3145 * @retval State of bit (1 or 0).
3146 */
LL_RCC_IsEnabledIT_HSERDY(void)3147 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
3148 {
3149 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
3150 }
3151
3152 /**
3153 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
3154 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY
3155 * @retval State of bit (1 or 0).
3156 */
LL_RCC_IsEnabledIT_PLL1RDY(void)3157 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
3158 {
3159 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
3160 }
3161
3162 /**
3163 * @}
3164 */
3165
3166 /** @defgroup RCC_LL_EF_Security_Services Security Services
3167 * @{
3168 */
3169
3170 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3171 /**
3172 * @brief Configure RCC resources security
3173 * @note Only available from secure state when system implements security (TZEN=1)
3174 * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n
3175 * SECCFGR HSESEC LL_RCC_ConfigSecure\n
3176 * SECCFGR LSISEC LL_RCC_ConfigSecure\n
3177 * SECCFGR LSESEC LL_RCC_ConfigSecure\n
3178 * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n
3179 * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n
3180 * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n
3181 * SECCFGR RMVFSEC LL_RCC_ConfigSecure
3182 * @param SecureConfig This parameter can be one or a combination of the following values:
3183 * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
3184 * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
3185 * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
3186 * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
3187 * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
3188 * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
3189 * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
3190 * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
3191 * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
3192 * @retval None
3193 */
LL_RCC_ConfigSecure(uint32_t SecureConfig)3194 __STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig)
3195 {
3196 WRITE_REG(RCC->SECCFGR, SecureConfig);
3197 }
3198 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
3199
3200 /**
3201 * @brief Get RCC resources security status
3202 * @note Only available from secure state when system implements security (TZEN=1)
3203 * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n
3204 * SECCFGR HSESEC LL_RCC_GetConfigSecure\n
3205 * SECCFGR LSISEC LL_RCC_GetConfigSecure\n
3206 * SECCFGR LSESEC LL_RCC_GetConfigSecure\n
3207 * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n
3208 * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n
3209 * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n
3210 * SECCFGR RMVFSEC LL_RCC_GetConfigSecure
3211 * @retval Returned value can be one or a combination of the following values:
3212 * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
3213 * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
3214 * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
3215 * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
3216 * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
3217 * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
3218 * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
3219 * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
3220 * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
3221 * @retval None
3222 */
LL_RCC_GetConfigSecure(void)3223 __STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void)
3224 {
3225 return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK));
3226 }
3227
3228 /**
3229 * @}
3230 */
3231
3232 #if defined(USE_FULL_LL_DRIVER)
3233 /** @defgroup RCC_LL_EF_Init De-initialization function
3234 * @{
3235 */
3236 ErrorStatus LL_RCC_DeInit(void);
3237 /**
3238 * @}
3239 */
3240
3241 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
3242 * @{
3243 */
3244 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
3245 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
3246 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
3247 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
3248 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
3249 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
3250 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
3251 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
3252 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
3253 /**
3254 * @}
3255 */
3256
3257 #endif /* USE_FULL_LL_DRIVER */
3258
3259 /**
3260 * @}
3261 */
3262
3263 /**
3264 * @}
3265 */
3266
3267 #endif /* defined(RCC) */
3268
3269 /**
3270 * @}
3271 */
3272
3273 #ifdef __cplusplus
3274 }
3275 #endif
3276
3277 #endif /* STM32WBAxx_LL_RCC_H */
3278
3279
