1 /**
2   ******************************************************************************
3   * @file    stm32n6xx_ll_pwr.h
4   * @author  MCD Application Team
5   * @brief   Header file of PWR LL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2023 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32N6xx_LL_PWR_H
21 #define STM32N6xx_LL_PWR_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32n6xx.h"
29 
30 /** @addtogroup STM32N6xx_LL_Driver
31   * @{
32   */
33 
34 #if defined (PWR)
35 
36 /** @defgroup PWR_LL PWR
37   * @{
38   */
39 
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 
44 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
45   * @{
46   */
47 
48 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
49   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
50   * @{
51   */
52 /* Wake-Up Pins PWR register offsets */
53 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    (2UL)
54 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       (0x1FU)
55 /**
56   * @}
57   */
58 
59 /**
60   * @}
61   */
62 
63 
64 /* Private macros ------------------------------------------------------------*/
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 
68 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
69   * @{
70   */
71 
72 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
73   * @{
74   */
75 #define LL_PWR_SMPS_SUPPLY             PWR_CR1_SDEN                            /*!< Core domains are supplied from the SMPS                                     */
76 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY  (0U)                                    /*!< The SMPS is Bypassed. The Core domains are supplied from an external source */
77 /**
78   * @}
79   */
80 
81 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
82   * @{
83   */
84 #define LL_PWR_VCOREMON_LEVEL_SCALE1  (0U)                                     /*!< VDDCORE low-voltage threshold 1 selected (VOS 1) */
85 #define LL_PWR_VCOREMON_LEVEL_SCALE0  PWR_CR3_VCORELLS                         /*!< VDDCORE low-voltage threshold 2 selected (VOS 0) */
86 /**
87   * @}
88   */
89 
90 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
91   * @{
92   */
93 #define LL_PWR_REGU_VOLTAGE_SCALE0     PWR_VOSCR_VOS                           /*!< Voltage scaling range 0 (highest frequency) */
94 #define LL_PWR_REGU_VOLTAGE_SCALE1     (0U)                                    /*!< Voltage scaling range 1 (lowest power)      */
95 /**
96   * @}
97   */
98 
99 /** @defgroup PWR_LL_EC_MODE_PWR Power Down Mode In Deep Sleep Mode
100   * @{
101   */
102 #define LL_PWR_POWERDOWN_MODE_DS_STOP     (0U)                                 /*!< Enter to Stop mode when the CPU enters deepsleep    */
103 #define LL_PWR_POWERDOWN_MODE_DS_STANDBY  PWR_CPUCR_PDDS                       /*!< Enter to Standby mode when the CPU enters deepsleep */
104 /**
105   * @}
106   */
107 
108 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
109   * @{
110   */
111 #define LL_PWR_REGU_STOP_VOLTAGE_SCALE3     PWR_CPUCR_SVOS                     /*!< Voltage scaling range 3 (highest frequency) when system enters STOP mode */
112 #define LL_PWR_REGU_STOP_VOLTAGE_SCALE5     (0U)                               /*!< Voltage scaling range 5 (lowest power) when system enters STOP mode      */
113 /**
114   * @}
115   */
116 
117 /** @defgroup PWR_LL_EC_VDDIO_VOLTAGE_RANGE VDD I/O voltage range selection
118   * @{
119   */
120 #define LL_PWR_VDDIO_VOLTAGE_RANGE_1V8    (1U)                                 /*!< 1v8 voltage range */
121 #define LL_PWR_VDDIO_VOLTAGE_RANGE_3V3    (0U)                                 /*!< 3v3 voltage range  */
122 /**
123   * @}
124   */
125 
126 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
127   * @{
128   */
129 #define LL_PWR_WAKEUP_PIN1             PWR_WKUPEPR_WKUPEN1                     /*!< Wake-Up pin 1 : PA0  */
130 #define LL_PWR_WAKEUP_PIN2             PWR_WKUPEPR_WKUPEN2                     /*!< Wake-Up pin 2 : PA2  */
131 #define LL_PWR_WAKEUP_PIN3             PWR_WKUPEPR_WKUPEN3                     /*!< Wake-Up pin 3 : PC13 */
132 #define LL_PWR_WAKEUP_PIN4             PWR_WKUPEPR_WKUPEN4                     /*!< Wake-Up pin 4 : PD2  */
133 /**
134   * @}
135   */
136 
137 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration
138   * @{
139   */
140 #define LL_PWR_WAKEUP_PIN_NOPULL       (0UL)                                   /*!< Configure Wake-Up pin in no pull   */
141 #define LL_PWR_WAKEUP_PIN_PULLUP       (1UL)                                   /*!< Configure Wake-Up pin in pull Up   */
142 #define LL_PWR_WAKEUP_PIN_PULLDOWN     (2UL)                                   /*!< Configure Wake-Up pin in pull Down */
143 /**
144   * @}
145   */
146 
147 /** @defgroup PWR_LL_EC_ITEMS_PRIVILEGE_ATTRIBUTE PWR Items Privilege Attribute
148   * @{
149   */
150 #define LL_PWR_PRIV0_NPRIV             (0U)                                    /*!< System supply configuration non privilege mode                       */
151 #define LL_PWR_PRIV0_PRIV              PWR_PRIVCFGR_PRIV0                      /*!< System supply configuration privilege mode                           */
152 #define LL_PWR_PRIV1_NPRIV             (0U)                                    /*!< Programmable voltage detector non privilege mode                     */
153 #define LL_PWR_PRIV1_PRIV              PWR_PRIVCFGR_PRIV1                      /*!< Programmable voltage detect privilege mode                           */
154 #define LL_PWR_PRIV2_NPRIV             (0U)                                    /*!< VDDCORE monitor non privilege mode                                   */
155 #define LL_PWR_PRIV2_PRIV              PWR_PRIVCFGR_PRIV2                      /*!< VDDCORE monitor privilege mode                                       */
156 #define LL_PWR_PRIV3_NPRIV             (0U)                                    /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control non privilege mode */
157 #define LL_PWR_PRIV3_PRIV              PWR_PRIVCFGR_PRIV3                      /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control privilege mode     */
158 #define LL_PWR_PRIV4_NPRIV             (0U)                                    /*!< Voltage scaling selection nprivilege mode                            */
159 #define LL_PWR_PRIV4_PRIV              PWR_PRIVCFGR_PRIV4                      /*!< Voltage scaling selection privilege mode                             */
160 #define LL_PWR_PRIV5_NPRIV             (0U)                                    /*!< Backup domain non privilege mode                                     */
161 #define LL_PWR_PRIV5_PRIV              PWR_PRIVCFGR_PRIV5                      /*!< Backup domain privilege mode                                         */
162 #define LL_PWR_PRIV6_NPRIV             (0U)                                    /*!< CPU power control non privilege mode                                 */
163 #define LL_PWR_PRIV6_PRIV              PWR_PRIVCFGR_PRIV6                      /*!< CPU power control privilege mode                                     */
164 #define LL_PWR_PRIV7_NPRIV             (0U)                                    /*!< Peripheral voltage monitor non privilege mode                        */
165 #define LL_PWR_PRIV7_PRIV              PWR_PRIVCFGR_PRIV7                      /*!< Peripheral voltage monitor privilege mode                            */
166 #define LL_PWR_WAKEUP_PIN1_NPRIV       (0U)                                    /*!< Wake up pin 1 non privilege mode                                     */
167 #define LL_PWR_WAKEUP_PIN1_PRIV        PWR_PRIVCFGR_WKUPPRIV1                  /*!< Wake up pin 1 privilege mode                                         */
168 #define LL_PWR_WAKEUP_PIN2_NPRIV       (0U)                                    /*!< Wake up pin 2 non privilege mode                                     */
169 #define LL_PWR_WAKEUP_PIN2_PRIV        PWR_PRIVCFGR_WKUPPRIV2                  /*!< Wake up pin 2 privilege mode                                         */
170 #define LL_PWR_WAKEUP_PIN3_NPRIV       (0U)                                    /*!< Wake up pin 3 non privilege mode                                     */
171 #define LL_PWR_WAKEUP_PIN3_PRIV        PWR_PRIVCFGR_WKUPPRIV3                  /*!< Wake up pin 3 privilege mode                                         */
172 #define LL_PWR_WAKEUP_PIN4_NPRIV       (0U)                                    /*!< Wake up pin 4 non privilege mode                                     */
173 #define LL_PWR_WAKEUP_PIN4_PRIV        PWR_PRIVCFGR_WKUPPRIV4                  /*!< Wake up pin 4 privilege mode                                         */
174 /**
175   * @}
176   */
177 
178 /** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
179   * @{
180   */
181 #define LL_PWR_SEC0_NSEC               (0U)                                    /*!< System supply configuration non secure mode                       */
182 #define LL_PWR_SEC0_SEC                PWR_SECCFGR_SEC0                        /*!< System supply configuration secure mode                           */
183 #define LL_PWR_SEC1_NSEC               (0U)                                    /*!< Programmable voltage detector non secure mode                     */
184 #define LL_PWR_SEC1_SEC                PWR_SECCFGR_SEC1                        /*!< Programmable voltage detect secure mode                           */
185 #define LL_PWR_SEC2_NSEC               (0U)                                    /*!< VDDCORE monitor non secure mode                                   */
186 #define LL_PWR_SEC2_SEC                PWR_SECCFGR_SEC2                        /*!< VDDCORE monitor secure mode                                       */
187 #define LL_PWR_SEC3_NSEC               (0U)                                    /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control non secure mode */
188 #define LL_PWR_SEC3_SEC                PWR_SECCFGR_SEC3                        /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control secure mode     */
189 #define LL_PWR_SEC4_NSEC               (0U)                                    /*!< Voltage scaling selection nsecure mode                            */
190 #define LL_PWR_SEC4_SEC                PWR_SECCFGR_SEC4                        /*!< Voltage scaling selection secure mode                             */
191 #define LL_PWR_SEC5_NSEC               (0U)                                    /*!< Backup domain non secure mode                                     */
192 #define LL_PWR_SEC5_SEC                PWR_SECCFGR_SEC5                        /*!< Backup domain secure mode                                         */
193 #define LL_PWR_SEC6_NSEC               (0U)                                    /*!< CPU power control non secure mode                                 */
194 #define LL_PWR_SEC6_SEC                PWR_SECCFGR_SEC6                        /*!< CPU power control secure mode                                     */
195 #define LL_PWR_SEC7_NSEC               (0U)                                    /*!< Peripheral voltage monitor non secure mode                        */
196 #define LL_PWR_SEC7_SEC                PWR_SECCFGR_SEC7                        /*!< Peripheral voltage monitor secure mode                            */
197 #define LL_PWR_WAKEUP_PIN1_NSEC        (0U)                                    /*!< Wake up pin 1 non secure mode                                     */
198 #define LL_PWR_WAKEUP_PIN1_SEC         PWR_SECCFGR_WKUPSEC1                    /*!< Wake up pin 1 secure mode                                         */
199 #define LL_PWR_WAKEUP_PIN2_NSEC        (0U)                                    /*!< Wake up pin 2 non secure mode                                     */
200 #define LL_PWR_WAKEUP_PIN2_SEC         PWR_SECCFGR_WKUPSEC2                    /*!< Wake up pin 2 secure mode                                         */
201 #define LL_PWR_WAKEUP_PIN3_NSEC        (0U)                                    /*!< Wake up pin 3 non secure mode                                     */
202 #define LL_PWR_WAKEUP_PIN3_SEC         PWR_SECCFGR_WKUPSEC3                    /*!< Wake up pin 3 secure mode                                         */
203 #define LL_PWR_WAKEUP_PIN4_NSEC        (0U)                                    /*!< Wake up pin 4 non secure mode                                     */
204 #define LL_PWR_WAKEUP_PIN4_SEC         PWR_SECCFGR_WKUPSEC4                    /*!< Wake up pin 4 secure mode                                         */
205 /**
206   * @}
207   */
208 
209 /**
210   * @}
211   */
212 
213 /* Exported functions --------------------------------------------------------*/
214 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
215   * @{
216   */
217 
218 /** @defgroup PWR_LL_EF_Configuration PWR Configuration
219   * @{
220   */
221 
222 /**
223   * @brief  Configure the PWR supply
224   * @rmtoll CR1       SDEN             LL_PWR_ConfigSupply
225   * @param  SupplySource This parameter can be one of the following values:
226   *         @arg @ref LL_PWR_SMPS_SUPPLY
227   *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
228   * @retval None
229   */
LL_PWR_ConfigSupply(uint32_t SupplySource)230 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
231 {
232   /* Set the power supply configuration */
233   MODIFY_REG(PWR->CR1, PWR_CR1_SDEN, SupplySource);
234 }
235 
236 /**
237   * @brief  Get the PWR supply
238   * @rmtoll CR1       SDEN             LL_PWR_GetSupply
239   * @retval Returned value can be one of the following values:
240   *         @arg @ref LL_PWR_SMPS_SUPPLY
241   *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
242   */
LL_PWR_GetSupply(void)243 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
244 {
245   /* Get the power supply configuration */
246   return READ_BIT(PWR->CR1, PWR_CR1_SDEN);
247 }
248 
249 /**
250   * @brief  Enable the SMPS low-power mode.
251   * @rmtoll CR1        LPDS08V         LL_PWR_EnableSMPSLPMode
252   * @note This bit is used to keep the SMPS in PWM mode (MR)
253   * in Stop SVOS 3.
254   * @retval None
255   */
LL_PWR_EnableSMPSLPMode(void)256 __STATIC_INLINE void LL_PWR_EnableSMPSLPMode(void)
257 {
258   SET_BIT(PWR->CR1, PWR_CR1_LPDS08V);
259 }
260 
261 /**
262   * @brief  Disable the SMPS low-power mode.
263   * @rmtoll CR1        LPDS08V         LL_PWR_DisableSMPSLPMode
264   * @retval None
265   */
LL_PWR_DisableSMPSLPMode(void)266 __STATIC_INLINE void LL_PWR_DisableSMPSLPMode(void)
267 {
268   CLEAR_BIT(PWR->CR1, PWR_CR1_LPDS08V);
269 }
270 
271 /**
272   * @brief  Check if the SMPS low-power mode is enabled.
273   * @rmtoll CR1        LPDS08V         LL_PWR_IsEnabledSMPSLPMode
274   * @retval State of bit (1 or 0).
275   */
LL_PWR_IsEnabledSMPSLPMode(void)276 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSLPMode(void)
277 {
278   return ((READ_BIT(PWR->CR1, PWR_CR1_LPDS08V) == (PWR_CR1_LPDS08V)) ? 1UL : 0UL);
279 }
280 
281 /**
282   * @brief  Enable the pull down on output voltage during power-down mode.
283   * @rmtoll CR2        MODE_PDN         LL_PWR_EnablePullDown
284   * @retval None
285   */
LL_PWR_EnablePullDown(void)286 __STATIC_INLINE void LL_PWR_EnablePullDown(void)
287 {
288   SET_BIT(PWR->CR1, PWR_CR1_MODE_PDN);
289 }
290 
291 /**
292   * @brief  Disable the pull down on output voltage during power-down mode.
293   * @rmtoll CR1        MODE_PDN         LL_PWR_DisablePullDown
294   * @retval None
295   */
LL_PWR_DisablePullDown(void)296 __STATIC_INLINE void LL_PWR_DisablePullDown(void)
297 {
298   CLEAR_BIT(PWR->CR1, PWR_CR1_MODE_PDN);
299 }
300 
301 /**
302   * @brief  Check if the pull down on output voltage during power-down mode is enabled.
303   * @rmtoll CR1        MODE_PDN         LL_PWR_IsEnabledPullDown
304   * @retval State of bit (1 or 0).
305   */
LL_PWR_IsEnabledPullDown(void)306 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPullDown(void)
307 {
308   return ((READ_BIT(PWR->CR1, PWR_CR1_MODE_PDN) == (PWR_CR1_MODE_PDN)) ? 1UL : 0UL);
309 }
310 
311 /**
312   * @brief  Set the pwr_on pulse low time
313   * @rmtoll CR1        POPL            LL_PWR_SetPwrONPulseLowTime
314   * @param  PulseTime Value between Min_Data = 0 and Max_Data = 31
315   * @retval None
316   */
LL_PWR_SetPwrONPulseLowTime(uint32_t PulseTime)317 __STATIC_INLINE void LL_PWR_SetPwrONPulseLowTime(uint32_t PulseTime)
318 {
319   MODIFY_REG(PWR->CR1, PWR_CR1_POPL, (PulseTime << PWR_CR1_POPL_Pos));
320 }
321 
322 /**
323   * @brief  Get the pwr_on pulse low time
324   * @rmtoll CR1        POPL            LL_PWR_GetPwrONPulseLowTime
325   * @retval Value between Min_Data = 0 and Max_Data = 31
326   */
LL_PWR_GetPwrONPulseLowTime(void)327 __STATIC_INLINE uint32_t LL_PWR_GetPwrONPulseLowTime(void)
328 {
329   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_POPL) >> PWR_CR1_POPL_Pos);
330 }
331 
332 /**
333   * @brief  Enable Power Voltage Detector
334   * @rmtoll CR2        PVDEN           LL_PWR_EnablePVD
335   * @retval None
336   */
LL_PWR_EnablePVD(void)337 __STATIC_INLINE void LL_PWR_EnablePVD(void)
338 {
339   SET_BIT(PWR->CR2, PWR_CR2_PVDEN);
340 }
341 
342 /**
343   * @brief  Disable Power Voltage Detector
344   * @rmtoll CR2        PVDEN           LL_PWR_DisablePVD
345   * @retval None
346   */
LL_PWR_DisablePVD(void)347 __STATIC_INLINE void LL_PWR_DisablePVD(void)
348 {
349   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDEN);
350 }
351 
352 /**
353   * @brief  Check if Power Voltage Detector is enabled
354   * @rmtoll CR2        PVDEN           LL_PWR_IsEnabledPVD
355   * @retval State of bit (1 or 0).
356   */
LL_PWR_IsEnabledPVD(void)357 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
358 {
359   return ((READ_BIT(PWR->CR2, PWR_CR2_PVDEN) == (PWR_CR2_PVDEN)) ? 1UL : 0UL);
360 }
361 
362 /**
363   * @brief  Enable VCORE monitoring
364   * @rmtoll CR3        VCOREMONEN      LL_PWR_EnableVCOREMonitoring
365   * @retval None
366   */
LL_PWR_EnableVCOREMonitoring(void)367 __STATIC_INLINE void LL_PWR_EnableVCOREMonitoring(void)
368 {
369   SET_BIT(PWR->CR3, PWR_CR3_VCOREMONEN);
370 }
371 
372 /**
373   * @brief  Disable VCORE monitoring
374   * @rmtoll CR3        VCOREMONEN      LL_PWR_DisableVCOREMonitoring
375   * @retval None
376   */
LL_PWR_DisableVCOREMonitoring(void)377 __STATIC_INLINE void LL_PWR_DisableVCOREMonitoring(void)
378 {
379   CLEAR_BIT(PWR->CR3, PWR_CR3_VCOREMONEN);
380 }
381 
382 /**
383   * @brief  Check if the VCORE monitoring is enabled
384   * @rmtoll CR3        VCOREMONEN      LL_PWR_IsEnabledVCOREMonitoring
385   * @retval State of bit (1 or 0).
386   */
LL_PWR_IsEnabledVCOREMonitoring(void)387 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVCOREMonitoring(void)
388 {
389   return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREMONEN) == (PWR_CR3_VCOREMONEN)) ? 1UL : 0UL);
390 }
391 
392 /**
393   * @brief  Set the VDDCORE voltage detector low-level selection
394   * @rmtoll CR3        VCORELLS        LL_PWR_SetVCORELowLevelDetection
395   * @param  Lowlevel This parameter can be one of the following values:
396   *         @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE1
397   *         @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE0
398   * @retval None
399   */
LL_PWR_SetVCORELowLevelDetection(uint32_t Lowlevel)400 __STATIC_INLINE void LL_PWR_SetVCORELowLevelDetection(uint32_t Lowlevel)
401 {
402   MODIFY_REG(PWR->CR3, PWR_CR3_VCORELLS, Lowlevel);
403 }
404 
405 /**
406   * @brief  Get the VDDCORE voltage detector low-level selection
407   * @rmtoll CR3        VCORELLS        LL_PWR_GetVCORELowLevelDetection
408   * @retval Returned value can be one of the following values:
409   *         @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE1
410   *         @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE0
411   */
LL_PWR_GetVCORELowLevelDetection(void)412 __STATIC_INLINE uint32_t LL_PWR_GetVCORELowLevelDetection(void)
413 {
414   return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VCORELLS));
415 }
416 
417 /**
418   * @brief  Enable I-TCM and D-TCM RAMs retention in Standby mode.
419   * @rmtoll CR4        TCMRBSEN        LL_PWR_EnableTCMSBRetention
420   * @note   When this bit is set, I-TCM and D-TCM RAMs are supplied
421   *         from backup regulator in Standby mode.
422   *         When this bit is reset, I-TCM and D-TCM RAMs can still
423   *         be used in Run and Stop modes, but their content is lost
424   *         in Standby mode.
425   * @retval None
426   */
LL_PWR_EnableTCMSBRetention(void)427 __STATIC_INLINE void LL_PWR_EnableTCMSBRetention(void)
428 {
429   SET_BIT(PWR->CR4, PWR_CR4_TCMRBSEN);
430 }
431 
432 /**
433   * @brief  Disable I-TCM and D-TCM RAMs retention in Standby mode.
434   * @rmtoll CR4        TCMRBSEN        LL_PWR_DisableTCMSBRetention
435   * @retval None
436   */
LL_PWR_DisableTCMSBRetention(void)437 __STATIC_INLINE void LL_PWR_DisableTCMSBRetention(void)
438 {
439   CLEAR_BIT(PWR->CR4, PWR_CR4_TCMRBSEN);
440 }
441 
442 /**
443   * @brief  Check if the I-TCM and D-TCM RAMs retention in Standby mode is enabled
444   * @rmtoll CR4        TCMRBSEN          LL_PWR_IsEnabledTCMSBRetention
445   * @retval State of bit (1 or 0).
446   */
LL_PWR_IsEnabledTCMSBRetention(void)447 __STATIC_INLINE uint32_t LL_PWR_IsEnabledTCMSBRetention(void)
448 {
449   return ((READ_BIT(PWR->CR4, PWR_CR4_TCMRBSEN) == (PWR_CR4_TCMRBSEN)) ? 1UL : 0UL);
450 }
451 
452 /**
453   * @brief  Enable I-TCM FLEXMEM retention in Standby mode.
454   * @rmtoll CR4        TCMFLXRBSEN     LL_PWR_EnableTCMFLXSBRetention
455   * @note   When this bit is set, the I-TCM FLEXMEM is supplied
456   *         from backup regulator in Standby mode.
457   *         When this bit is reset, the I-TCM FLEXMEM can still
458   *         be used in Run and Stop modes, but its content is lost
459   *         in Standby mode.
460   * @retval None
461   */
LL_PWR_EnableTCMFLXSBRetention(void)462 __STATIC_INLINE void LL_PWR_EnableTCMFLXSBRetention(void)
463 {
464   SET_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN);
465 }
466 
467 /**
468   * @brief  Disable I-TCM FLEXMEM RAMs retention in Standby mode.
469   * @rmtoll CR4        TCMFLXRBSEN     LL_PWR_DisableTCMFLXSBRetention
470   * @retval None
471   */
LL_PWR_DisableTCMFLXSBRetention(void)472 __STATIC_INLINE void LL_PWR_DisableTCMFLXSBRetention(void)
473 {
474   CLEAR_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN);
475 }
476 
477 /**
478   * @brief  Check if the I-TCM FLEXMEM retention in Standby mode is enabled
479   * @rmtoll CR4        TCMFLXRBSEN     LL_PWR_IsEnabledTCMFLXSBRetention
480   * @retval State of bit (1 or 0).
481   */
LL_PWR_IsEnabledTCMFLXSBRetention(void)482 __STATIC_INLINE uint32_t LL_PWR_IsEnabledTCMFLXSBRetention(void)
483 {
484   return ((READ_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN) == (PWR_CR4_TCMFLXRBSEN)) ? 1UL : 0UL);
485 }
486 
487 /**
488   * @brief  Set the main internal Regulator output voltage
489   * @rmtoll VOSCR       VOS            LL_PWR_SetRegulVoltageScaling
490   * @param  VoltageScaling This parameter can be one of the following values:
491   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
492   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
493   * @retval None
494   */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)495 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
496 {
497   MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling);
498 }
499 
500 /**
501   * @brief  Get the main internal Regulator output voltage. Reflecting the last
502   *         VOS value applied to the PMU.
503   * @rmtoll VOSCR       ACTVOS         LL_PWR_GetRegulVoltageScaling
504   * @retval Returned value can be one of the following values:
505   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
506   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
507   */
LL_PWR_GetRegulVoltageScaling(void)508 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
509 {
510   return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_ACTVOS) == (PWR_VOSCR_ACTVOS)) ? 1UL : 0UL);
511 }
512 
513 /**
514   * @brief  Enable VBAT and Temperature monitoring
515   * @rmtoll BDCR1      MONEN           LL_PWR_EnableMonitoring
516   * @retval None
517   */
LL_PWR_EnableMonitoring(void)518 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
519 {
520   SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
521 }
522 
523 /**
524   * @brief  Disable VBAT and Temperature monitoring
525   * @rmtoll BDCR1      MONEN           LL_PWR_DisableMonitoring
526   * @retval None
527   */
LL_PWR_DisableMonitoring(void)528 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
529 {
530   CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
531 }
532 
533 /**
534   * @brief  Check if the VBAT and Temperature monitoring is enabled
535   * @rmtoll BDCR1      MONEN           LL_PWR_IsEnabledMonitoring
536   * @retval State of bit (1 or 0).
537   */
LL_PWR_IsEnabledMonitoring(void)538 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
539 {
540   return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL);
541 }
542 
543 /**
544   * @brief  Enable BKPSRAM retention in Standby mode.
545   * @rmtoll BDCR2      BKPRBSEN        LL_PWR_EnableBkpSRAMSBRetention
546   * @note   When this bit is set, the backup ram is supplied from backup regulator in Standby and
547   *         VBAT modes.
548   *         When this bit is reset, the backup ram can still be used in Run and Stop modes,
549   *         but its content is lost in Standby and VBAT modes.
550   * @retval None
551   */
LL_PWR_EnableBkpSRAMSBRetention(void)552 __STATIC_INLINE void LL_PWR_EnableBkpSRAMSBRetention(void)
553 {
554   SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN);
555 }
556 
557 /**
558   * @brief  Disable BKPSRAM retention in Standby mode.
559   * @rmtoll BDCR2      BKPRBSEN           LL_PWR_DisableBkpSRAMSBRetention
560   * @retval None
561   */
LL_PWR_DisableBkpSRAMSBRetention(void)562 __STATIC_INLINE void LL_PWR_DisableBkpSRAMSBRetention(void)
563 {
564   CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN);
565 }
566 
567 /**
568   * @brief  Check if the BKPSRAM retention in Standby mode is enabled
569   * @rmtoll BDCR2      BKPRBSEN           LL_PWR_IsEnabledBkpSRAMSBRetention
570   * @retval State of bit (1 or 0).
571   */
LL_PWR_IsEnabledBkpSRAMSBRetention(void)572 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkpSRAMSBRetention(void)
573 {
574   return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN) == (PWR_BDCR2_BKPRBSEN)) ? 1UL : 0UL);
575 }
576 
577 /**
578   * @brief  Enable access to the backup domain
579   * @rmtoll DBPCR      DBP             LL_PWR_EnableBkUpAccess
580   * @retval None
581   */
LL_PWR_EnableBkUpAccess(void)582 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
583 {
584   SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
585 }
586 
587 /**
588   * @brief  Disable access to the backup domain
589   * @rmtoll DBPCR      DBP             LL_PWR_DisableBkUpAccess
590   * @retval None
591   */
LL_PWR_DisableBkUpAccess(void)592 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
593 {
594   CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
595 }
596 
597 /**
598   * @brief  Check if the backup domain is enabled
599   * @rmtoll DBPCR      DBP             LL_PWR_IsEnabledBkUpAccess
600   * @retval State of bit (1 or 0).
601   */
LL_PWR_IsEnabledBkUpAccess(void)602 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
603 {
604   return ((READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == (PWR_DBPCR_DBP)) ? 1UL : 0UL);
605 }
606 
607 /**
608   * @brief  Set the internal Regulator output voltage in STOP mode
609   * @rmtoll CPUCR      SVOS            LL_PWR_SetStopModeRegulVoltageScaling
610   * @param  VoltageScaling This parameter can be one of the following values:
611   *         @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3
612   *         @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5
613   * @retval None
614   */
LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)615 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
616 {
617   MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling);
618 }
619 
620 /**
621   * @brief  Get the internal Regulator output voltage in STOP mode
622   * @rmtoll CPUCR      SVOS            LL_PWR_GetStopModeRegulVoltageScaling
623   * @retval Returned value can be one of the following values:
624   *         @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3
625   *         @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5
626   */
LL_PWR_GetStopModeRegulVoltageScaling(void)627 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
628 {
629   return READ_BIT(PWR->CPUCR, PWR_CPUCR_SVOS);
630 }
631 
632 /**
633   * @brief  Set the Power Down mode when device enters deepsleep mode
634   * @rmtoll CPUCR      PDDS            LL_PWR_SetPowerDownModeDS
635   * @param  PDMode This parameter can be one of the following values:
636   *         @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP
637   *         @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY
638   * @retval None
639   */
LL_PWR_SetPowerDownModeDS(uint32_t PDMode)640 __STATIC_INLINE void LL_PWR_SetPowerDownModeDS(uint32_t PDMode)
641 {
642   MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS, PDMode);
643 }
644 
645 /**
646   * @brief  Get the Power Down mode when device enters deepsleep mode
647   * @rmtoll CPUCR      PDDS            LL_PWR_GetPowerDownModeDS
648   * @retval Returned value can be one of the following values:
649   *         @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP
650   *         @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY
651   */
LL_PWR_GetPowerDownModeDS(void)652 __STATIC_INLINE uint32_t LL_PWR_GetPowerDownModeDS(void)
653 {
654   return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS));
655 }
656 
657 /**
658   * @brief  Enable Vdd IO2 voltage supply
659   * @rmtoll SVMCR3     VDDIO2SV        LL_PWR_EnableVddIO2
660   * @retval None
661   */
LL_PWR_EnableVddIO2(void)662 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
663 {
664   SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV);
665 }
666 
667 /**
668   * @brief  Disable Vdd IO2 voltage supply
669   * @rmtoll SVMCR3     VDDIO2SV        LL_PWR_DisableVddIO2
670   * @retval None
671   */
LL_PWR_DisableVddIO2(void)672 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
673 {
674   CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV);
675 }
676 
677 /**
678   * @brief  Check if the Vdd IO2 voltage supply is enabled
679   * @rmtoll SVMCR3     VDDIO2SV        LL_PWR_IsEnabledVddIO2
680   * @retval State of bit (1 or 0).
681   */
LL_PWR_IsEnabledVddIO2(void)682 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
683 {
684   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV) == (PWR_SVMCR3_VDDIO2SV)) ? 1UL : 0UL);
685 }
686 
687 /**
688   * @brief  Enable Vdd IO3 voltage supply
689   * @rmtoll SVMCR3     VDDIO3SV        LL_PWR_EnableVddIO3
690   * @retval None
691   */
LL_PWR_EnableVddIO3(void)692 __STATIC_INLINE void LL_PWR_EnableVddIO3(void)
693 {
694   SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV);
695 }
696 
697 /**
698   * @brief  Disable Vdd IO3 voltage supply
699   * @rmtoll SVMCR3     VDDIO3SV        LL_PWR_DisableVddIO3
700   * @retval None
701   */
LL_PWR_DisableVddIO3(void)702 __STATIC_INLINE void LL_PWR_DisableVddIO3(void)
703 {
704   CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV);
705 }
706 
707 /**
708   * @brief  Check if the Vdd IO3 voltage supply is enabled
709   * @rmtoll SVMCR3     VDDIO3SV        LL_PWR_IsEnabledVddIO3
710   * @retval State of bit (1 or 0).
711   */
LL_PWR_IsEnabledVddIO3(void)712 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO3(void)
713 {
714   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV) == (PWR_SVMCR3_VDDIO3SV)) ? 1UL : 0UL);
715 }
716 
717 /**
718   * @brief  Enable Vdd IO4 voltage supply
719   * @rmtoll SVMCR1     VDDIO4SV        LL_PWR_EnableVddIO4
720   * @retval None
721   */
LL_PWR_EnableVddIO4(void)722 __STATIC_INLINE void LL_PWR_EnableVddIO4(void)
723 {
724   SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV);
725 }
726 
727 /**
728   * @brief  Disable Vdd IO4 voltage supply
729   * @rmtoll SVMCR1     VDDIO4SV        LL_PWR_DisableVddIO4
730   * @retval None
731   */
LL_PWR_DisableVddIO4(void)732 __STATIC_INLINE void LL_PWR_DisableVddIO4(void)
733 {
734   CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV);
735 }
736 
737 /**
738   * @brief  Check if the Vdd IO4 voltage supply is enabled
739   * @rmtoll SVMCR1     VDDIO4SV        LL_PWR_IsEnabledVddIO4
740   * @retval State of bit (1 or 0).
741   */
LL_PWR_IsEnabledVddIO4(void)742 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4(void)
743 {
744   return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV) == (PWR_SVMCR1_VDDIO4SV)) ? 1UL : 0UL);
745 }
746 
747 /**
748   * @brief  Enable Vdd IO5 voltage supply
749   * @rmtoll SVMCR2     VDDIO5SV        LL_PWR_EnableVddIO5
750   * @retval None
751   */
LL_PWR_EnableVddIO5(void)752 __STATIC_INLINE void LL_PWR_EnableVddIO5(void)
753 {
754   SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV);
755 }
756 
757 /**
758   * @brief  Disable Vdd IO5 voltage supply
759   * @rmtoll SVMCR2     VDDIO5SV        LL_PWR_DisableVddIO5
760   * @retval None
761   */
LL_PWR_DisableVddIO5(void)762 __STATIC_INLINE void LL_PWR_DisableVddIO5(void)
763 {
764   CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV);
765 }
766 
767 /**
768   * @brief  Check if the Vdd IO5 voltage supply is enabled
769   * @rmtoll SVMCR2     VDDIO5SV        LL_PWR_IsEnabledVddIO5
770   * @retval State of bit (1 or 0).
771   */
LL_PWR_IsEnabledVddIO5(void)772 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5(void)
773 {
774   return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV) == (PWR_SVMCR2_VDDIO5SV)) ? 1UL : 0UL);
775 }
776 
777 /**
778   * @brief  Enable Vdd USB voltage supply
779   * @rmtoll SVMCR3     USB33SV         LL_PWR_EnableVddUSB
780   * @retval None
781   */
LL_PWR_EnableVddUSB(void)782 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
783 {
784   SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV);
785 }
786 
787 /**
788   * @brief  Disable Vdd USB voltage supply
789   * @rmtoll SVMCR3     USB33SV         LL_PWR_DisableVddUSB
790   * @retval None
791   */
LL_PWR_DisableVddUSB(void)792 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
793 {
794   CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV);
795 }
796 
797 /**
798   * @brief  Check if the Vdd USB voltage supply is enabled
799   * @rmtoll SVMCR3     USB33SV         LL_PWR_IsEnabledVddUSB
800   * @retval State of bit (1 or 0).
801   */
LL_PWR_IsEnabledVddUSB(void)802 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
803 {
804   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV) == (PWR_SVMCR3_USB33SV)) ? 1UL : 0UL);
805 }
806 
807 /**
808   * @brief  Enable Vdd ADC voltage supply
809   * @rmtoll SVMCR3     ASV             LL_PWR_EnableVddADC
810   * @retval None
811   */
LL_PWR_EnableVddADC(void)812 __STATIC_INLINE void LL_PWR_EnableVddADC(void)
813 {
814   SET_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV);
815 }
816 
817 /**
818   * @brief  Disable Vdd ADC voltage supply
819   * @rmtoll SVMCR3     ASV             LL_PWR_DisableVddADC
820   * @retval None
821   */
LL_PWR_DisableVddADC(void)822 __STATIC_INLINE void LL_PWR_DisableVddADC(void)
823 {
824   CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV);
825 }
826 
827 /**
828   * @brief  Check if the Vdd ADC voltage supply is enabled
829   * @rmtoll SVMCR3     ASV             LL_PWR_IsEnabledVddADC
830   * @retval State of bit (1 or 0).
831   */
LL_PWR_IsEnabledVddADC(void)832 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddADC(void)
833 {
834   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV) == (PWR_SVMCR3_ASV)) ? 1UL : 0UL);
835 }
836 
837 /**
838   * @brief  Enable Vdd IO2 voltage monitoring
839   * @rmtoll SVMCR3     VDDIO2VMEN      LL_PWR_EnableVddIO2Monitoring
840   * @retval None
841   */
LL_PWR_EnableVddIO2Monitoring(void)842 __STATIC_INLINE void LL_PWR_EnableVddIO2Monitoring(void)
843 {
844   SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN);
845 }
846 
847 /**
848   * @brief  Disable Vdd IO2 voltage monitoring
849   * @rmtoll SVMCR3     VDDIO2VMEN      LL_PWR_DisableVddIO2Monitoring
850   * @retval None
851   */
LL_PWR_DisableVddIO2Monitoring(void)852 __STATIC_INLINE void LL_PWR_DisableVddIO2Monitoring(void)
853 {
854   CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN);
855 }
856 
857 /**
858   * @brief  Check if the Vdd IO2 voltage monitoring is enabled
859   * @rmtoll SVMCR3     VDDIO2VMEN      LL_PWR_IsEnabledVddIO2Monitoring
860   * @retval State of bit (1 or 0).
861   */
LL_PWR_IsEnabledVddIO2Monitoring(void)862 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2Monitoring(void)
863 {
864   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN) == (PWR_SVMCR3_VDDIO2VMEN)) ? 1UL : 0UL);
865 }
866 
867 /**
868   * @brief  Enable Vdd IO3 voltage monitoring
869   * @rmtoll SVMCR3     VDDIO3VMEN      LL_PWR_EnableVddIO3Monitoring
870   * @retval None
871   */
LL_PWR_EnableVddIO3Monitoring(void)872 __STATIC_INLINE void LL_PWR_EnableVddIO3Monitoring(void)
873 {
874   SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN);
875 }
876 
877 /**
878   * @brief  Disable Vdd IO3 voltage monitoring
879   * @rmtoll SVMCR3     VDDIO3VMEN      LL_PWR_DisableVddIO3Monitoring
880   * @retval None
881   */
LL_PWR_DisableVddIO3Monitoring(void)882 __STATIC_INLINE void LL_PWR_DisableVddIO3Monitoring(void)
883 {
884   CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN);
885 }
886 
887 /**
888   * @brief  Check if the Vdd IO3 voltage monitoring is enabled
889   * @rmtoll SVMCR3     VDDIO3VMEN      LL_PWR_IsEnabledVddIO3Monitoring
890   * @retval State of bit (1 or 0).
891   */
LL_PWR_IsEnabledVddIO3Monitoring(void)892 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO3Monitoring(void)
893 {
894   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN) == (PWR_SVMCR3_VDDIO3VMEN)) ? 1UL : 0UL);
895 }
896 
897 /**
898   * @brief  Enable Vdd IO4 voltage monitoring
899   * @rmtoll SVMCR1     VDDIO4VMEN      LL_PWR_EnableVddIO4Monitoring
900   * @retval None
901   */
LL_PWR_EnableVddIO4Monitoring(void)902 __STATIC_INLINE void LL_PWR_EnableVddIO4Monitoring(void)
903 {
904   SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN);
905 }
906 
907 /**
908   * @brief  Disable Vdd IO4 voltage monitoring
909   * @rmtoll SVMCR1     VDDIO4VMEN      LL_PWR_DisableVddIO4Monitoring
910   * @retval None
911   */
LL_PWR_DisableVddIO4Monitoring(void)912 __STATIC_INLINE void LL_PWR_DisableVddIO4Monitoring(void)
913 {
914   CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN);
915 }
916 
917 /**
918   * @brief  Check if the Vdd IO4 voltage monitoring is enabled
919   * @rmtoll SVMCR1     VDDIO4VMEN      LL_PWR_IsEnabledVddIO4Monitoring
920   * @retval State of bit (1 or 0).
921   */
LL_PWR_IsEnabledVddIO4Monitoring(void)922 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4Monitoring(void)
923 {
924   return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN) == (PWR_SVMCR1_VDDIO4VMEN)) ? 1UL : 0UL);
925 }
926 
927 /**
928   * @brief  Enable Vdd IO5 voltage monitoring
929   * @rmtoll SVMCR2     VDDIO5VMEN      LL_PWR_EnableVddIO5Monitoring
930   * @retval None
931   */
LL_PWR_EnableVddIO5Monitoring(void)932 __STATIC_INLINE void LL_PWR_EnableVddIO5Monitoring(void)
933 {
934   SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN);
935 }
936 
937 /**
938   * @brief  Disable Vdd IO5 voltage monitoring
939   * @rmtoll SVMCR2     VDDIO5VMEN      LL_PWR_DisableVddIO5Monitoring
940   * @retval None
941   */
LL_PWR_DisableVddIO5Monitoring(void)942 __STATIC_INLINE void LL_PWR_DisableVddIO5Monitoring(void)
943 {
944   CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN);
945 }
946 
947 /**
948   * @brief  Check if the Vdd IO5 voltage monitoring is enabled
949   * @rmtoll SVMCR2     VDDIO5VMEN      LL_PWR_IsEnabledVddIO5Monitoring
950   * @retval State of bit (1 or 0).
951   */
LL_PWR_IsEnabledVddIO5Monitoring(void)952 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5Monitoring(void)
953 {
954   return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN) == (PWR_SVMCR2_VDDIO5VMEN)) ? 1UL : 0UL);
955 }
956 
957 /**
958   * @brief  Enable Vdd ADC voltage monitoring
959   * @rmtoll SVMCR3     AVMEN           LL_PWR_EnableVddADCMonitoring
960   * @retval None
961   */
LL_PWR_EnableVddADCMonitoring(void)962 __STATIC_INLINE void LL_PWR_EnableVddADCMonitoring(void)
963 {
964   SET_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN);
965 }
966 
967 /**
968   * @brief  Disable Vdd ADC voltage monitoring
969   * @rmtoll SVMCR3     AVMEN           LL_PWR_DisableVddADCMonitoring
970   * @retval None
971   */
LL_PWR_DisableVddADCMonitoring(void)972 __STATIC_INLINE void LL_PWR_DisableVddADCMonitoring(void)
973 {
974   CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN);
975 }
976 
977 /**
978   * @brief  Check if the Vdd ADC voltage monitoring is enabled
979   * @rmtoll SVMCR3     AVMEN           LL_PWR_IsEnabledVddADCMonitoring
980   * @retval State of bit (1 or 0).
981   */
LL_PWR_IsEnabledVddADCMonitoring(void)982 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddADCMonitoring(void)
983 {
984   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN) == (PWR_SVMCR3_AVMEN)) ? 1UL : 0UL);
985 }
986 
987 /**
988   * @brief  Enable Vdd USB voltage monitoring
989   * @rmtoll SVMCR3     USB33VMEN       LL_PWR_EnableVddUSBMonitoring
990   * @retval None
991   */
LL_PWR_EnableVddUSBMonitoring(void)992 __STATIC_INLINE void LL_PWR_EnableVddUSBMonitoring(void)
993 {
994   SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN);
995 }
996 
997 /**
998   * @brief  Disable Vdd USB voltage monitoring
999   * @rmtoll SVMCR3     USB33VMEN       LL_PWR_DisableVddUSBMonitoring
1000   * @retval None
1001   */
LL_PWR_DisableVddUSBMonitoring(void)1002 __STATIC_INLINE void LL_PWR_DisableVddUSBMonitoring(void)
1003 {
1004   CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN);
1005 }
1006 
1007 /**
1008   * @brief  Check if the Vdd USB voltage monitoring is enabled
1009   * @rmtoll SVMCR3     USB33VMEN       LL_PWR_IsEnabledVddUSBMonitoring
1010   * @retval State of bit (1 or 0).
1011   */
LL_PWR_IsEnabledVddUSBMonitoring(void)1012 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSBMonitoring(void)
1013 {
1014   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN) == (PWR_SVMCR3_USB33VMEN)) ? 1UL : 0UL);
1015 }
1016 
1017 /**
1018   * @brief  Set the VDD I/O voltage range
1019   * @rmtoll SVMCR3     VDDIOVRSEL      LL_PWR_SetVddIOVoltageRange
1020   * @param  VoltageRange This parameter can be one of the following values:
1021   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1022   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1023   * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
1024   *         operation.
1025   *         Setting this configuration while VDD is in 3v3 range damages the device.
1026   * @retval None
1027   */
LL_PWR_SetVddIOVoltageRange(uint32_t VoltageRange)1028 __STATIC_INLINE void LL_PWR_SetVddIOVoltageRange(uint32_t VoltageRange)
1029 {
1030   MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL, (VoltageRange << PWR_SVMCR3_VDDIOVRSEL_Pos));
1031 }
1032 
1033 /**
1034   * @brief  Get the VDD IO voltage range
1035   * @rmtoll SVMCR3     VDDIOVRSEL      LL_PWR_GetVddIOVoltageRange
1036   * @retval Returned value can be one of the following values:
1037   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1038   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1039   */
LL_PWR_GetVddIOVoltageRange(void)1040 __STATIC_INLINE uint32_t LL_PWR_GetVddIOVoltageRange(void)
1041 {
1042   return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL) >> PWR_SVMCR3_VDDIOVRSEL_Pos);
1043 }
1044 
1045 /**
1046   * @brief  Set the VDD IO2 voltage range
1047   * @rmtoll SVMCR3     VDDIO2VRSEL     LL_PWR_SetVddIO2VoltageRange
1048   * @param  VoltageRange This parameter can be one of the following values:
1049   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1050   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1051   * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
1052   *         operation.
1053   *         Setting this configuration while VDD is in 3v3 range damages the device.
1054   * @retval None
1055   */
LL_PWR_SetVddIO2VoltageRange(uint32_t VoltageRange)1056 __STATIC_INLINE void LL_PWR_SetVddIO2VoltageRange(uint32_t VoltageRange)
1057 {
1058   MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL, (VoltageRange << PWR_SVMCR3_VDDIO2VRSEL_Pos));
1059 }
1060 
1061 /**
1062   * @brief  Get the VDD IO2 voltage range
1063   * @rmtoll SVMCR3     VDDIO2VRSEL     LL_PWR_GetVddIO2VoltageRange
1064   * @retval Returned value can be one of the following values:
1065   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1066   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1067   */
LL_PWR_GetVddIO2VoltageRange(void)1068 __STATIC_INLINE uint32_t LL_PWR_GetVddIO2VoltageRange(void)
1069 {
1070   return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL) >> PWR_SVMCR3_VDDIO2VRSEL_Pos);
1071 }
1072 
1073 /**
1074   * @brief  Set the VDD IO3 voltage range
1075   * @rmtoll SVMCR3     VDDIO3VRSEL     LL_PWR_SetVddIO3VoltageRange
1076   * @param  VoltageRange This parameter can be one of the following values:
1077   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1078   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1079   * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
1080   *         operation.
1081   *         Setting this configuration while VDD is in 3v3 range damages the device.
1082   * @retval None
1083   */
LL_PWR_SetVddIO3VoltageRange(uint32_t VoltageRange)1084 __STATIC_INLINE void LL_PWR_SetVddIO3VoltageRange(uint32_t VoltageRange)
1085 {
1086   MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL, (VoltageRange << PWR_SVMCR3_VDDIO3VRSEL_Pos));
1087 }
1088 
1089 /**
1090   * @brief  Get the VDD IO3 voltage range
1091   * @rmtoll SVMCR3     VDDIO3VRSEL     LL_PWR_GetVddIO3VoltageRange
1092   * @retval Returned value can be one of the following values:
1093   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1094   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1095   */
LL_PWR_GetVddIO3VoltageRange(void)1096 __STATIC_INLINE uint32_t LL_PWR_GetVddIO3VoltageRange(void)
1097 {
1098   return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL) >> PWR_SVMCR3_VDDIO3VRSEL_Pos);
1099 }
1100 
1101 /**
1102   * @brief  Set the VDD IO4 voltage range
1103   * @rmtoll SVMCR1     VDDIO4VRSEL     LL_PWR_SetVddIO4VoltageRange
1104   * @param  VoltageRange This parameter can be one of the following values:
1105   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1106   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1107   * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
1108   *         operation.
1109   *         Setting this configuration while VDD is in 3v3 range damages the device.
1110   * @retval None
1111   */
LL_PWR_SetVddIO4VoltageRange(uint32_t VoltageRange)1112 __STATIC_INLINE void LL_PWR_SetVddIO4VoltageRange(uint32_t VoltageRange)
1113 {
1114   MODIFY_REG(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL, (VoltageRange << PWR_SVMCR1_VDDIO4VRSEL_Pos));
1115 }
1116 
1117 /**
1118   * @brief  Get the VDD IO4 voltage range
1119   * @rmtoll SVMCR1     VDDIO4VRSEL     LL_PWR_GetVddIO4VoltageRange
1120   * @retval Returned value can be one of the following values:
1121   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1122   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1123   */
LL_PWR_GetVddIO4VoltageRange(void)1124 __STATIC_INLINE uint32_t LL_PWR_GetVddIO4VoltageRange(void)
1125 {
1126   return (uint32_t)(READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL) >> PWR_SVMCR1_VDDIO4VRSEL_Pos);
1127 }
1128 
1129 /**
1130   * @brief  Set the VDD IO5 voltage range
1131   * @rmtoll SVMCR2     VDDIO5VRSEL     LL_PWR_SetVddIO5VoltageRange
1132   * @param  VoltageRange This parameter can be one of the following values:
1133   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1134   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1135   * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
1136   *         operation.
1137   *         Setting this configuration while VDD is in 3v3 range damages the device.
1138   * @retval None
1139   */
LL_PWR_SetVddIO5VoltageRange(uint32_t VoltageRange)1140 __STATIC_INLINE void LL_PWR_SetVddIO5VoltageRange(uint32_t VoltageRange)
1141 {
1142   MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, (VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos));
1143 }
1144 
1145 /**
1146   * @brief  Get the VDD IO5 voltage range
1147   * @rmtoll SVMCR2     VDDIO5VRSEL     LL_PWR_GetVddIO5VoltageRange
1148   * @retval Returned value can be one of the following values:
1149   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
1150   *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
1151   */
LL_PWR_GetVddIO5VoltageRange(void)1152 __STATIC_INLINE uint32_t LL_PWR_GetVddIO5VoltageRange(void)
1153 {
1154   return (uint32_t)(READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos);
1155 }
1156 
1157 /**
1158   * @brief  Enable Vdd IO4 voltage range retained in Standby mode
1159   * @rmtoll SVMCR1     VDDIO4VRSTBY    LL_PWR_EnableVddIO4VoltageRangeSB
1160   * @retval None
1161   */
LL_PWR_EnableVddIO4VoltageRangeSB(void)1162 __STATIC_INLINE void LL_PWR_EnableVddIO4VoltageRangeSB(void)
1163 {
1164   SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY);
1165 }
1166 
1167 /**
1168   * @brief  Disable Vdd IO4 voltage range retained in Standby mode
1169   * @rmtoll SVMCR1     VDDIO4VRSTBY    LL_PWR_DisableVddIO4VoltageRangeSB
1170   * @retval None
1171   */
LL_PWR_DisableVddIO4VoltageRangeSB(void)1172 __STATIC_INLINE void LL_PWR_DisableVddIO4VoltageRangeSB(void)
1173 {
1174   CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY);
1175 }
1176 
1177 /**
1178   * @brief  Check if the Vdd IO4 voltage range retained in Standby mode  is enabled
1179   * @rmtoll SVMCR1     VDDIO4VRSTBY    LL_PWR_IsEnabledVddIO4VoltageRangeSB
1180   * @retval State of bit (1 or 0).
1181   */
LL_PWR_IsEnabledVddIO4VoltageRangeSB(void)1182 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4VoltageRangeSB(void)
1183 {
1184   return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY) == (PWR_SVMCR1_VDDIO4VRSTBY)) ? 1UL : 0UL);
1185 }
1186 
1187 /**
1188   * @brief  Enable Vdd IO5 voltage range retained in Standby mode
1189   * @rmtoll SVMCR2     VDDIO5VRSTBY    LL_PWR_EnableVddIO5VoltageRangeSB
1190   * @retval None
1191   */
LL_PWR_EnableVddIO5VoltageRangeSB(void)1192 __STATIC_INLINE void LL_PWR_EnableVddIO5VoltageRangeSB(void)
1193 {
1194   SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY);
1195 }
1196 
1197 /**
1198   * @brief  Disable Vdd IO5 voltage range retained in Standby mode
1199   * @rmtoll SVMCR2     VDDIO5VRSTBY    LL_PWR_DisableVddIO5VoltageRangeSB
1200   * @retval None
1201   */
LL_PWR_DisableVddIO5VoltageRangeSB(void)1202 __STATIC_INLINE void LL_PWR_DisableVddIO5VoltageRangeSB(void)
1203 {
1204   CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY);
1205 }
1206 
1207 /**
1208   * @brief  Check if the Vdd IO5 voltage range retained in Standby mode  is enabled
1209   * @rmtoll SVMCR2     VDDIO5VRSTBY    LL_PWR_IsEnabledVddIO5VoltageRangeSB
1210   * @retval State of bit (1 or 0).
1211   */
LL_PWR_IsEnabledVddIO5VoltageRangeSB(void)1212 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5VoltageRangeSB(void)
1213 {
1214   return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY) == (PWR_SVMCR2_VDDIO5VRSTBY)) ? 1UL : 0UL);
1215 }
1216 
1217 /**
1218   * @brief  Enable the WakeUp PINx functionality
1219   * @rmtoll WKUPEPR    WKUPEN1         LL_PWR_EnableWakeUpPin\n
1220   *         WKUPEPR    WKUPEN2         LL_PWR_EnableWakeUpPin\n
1221   *         WKUPEPR    WKUPEN3         LL_PWR_EnableWakeUpPin\n
1222   *         WKUPEPR    WKUPEN4         LL_PWR_EnableWakeUpPin
1223   * @param  WakeUpPin This parameter can be one of the following values:
1224   *         @arg @ref LL_PWR_WAKEUP_PIN1
1225   *         @arg @ref LL_PWR_WAKEUP_PIN2
1226   *         @arg @ref LL_PWR_WAKEUP_PIN3
1227   *         @arg @ref LL_PWR_WAKEUP_PIN4
1228   * @retval None
1229   */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)1230 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1231 {
1232   SET_BIT(PWR->WKUPEPR, WakeUpPin);
1233 }
1234 
1235 /**
1236   * @brief  Disable the WakeUp PINx functionality
1237   * @rmtoll WKUPEPR   WKUPEN1          LL_PWR_DisableWakeUpPin\n
1238   *         WKUPEPR   WKUPEN2          LL_PWR_DisableWakeUpPin\n
1239   *         WKUPEPR   WKUPEN3          LL_PWR_DisableWakeUpPin\n
1240   *         WKUPEPR   WKUPEN4          LL_PWR_DisableWakeUpPin
1241   * @param  WakeUpPin This parameter can be one of the following values:
1242   *         @arg @ref LL_PWR_WAKEUP_PIN1
1243   *         @arg @ref LL_PWR_WAKEUP_PIN2
1244   *         @arg @ref LL_PWR_WAKEUP_PIN3
1245   *         @arg @ref LL_PWR_WAKEUP_PIN4
1246   * @retval None
1247   */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1248 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1249 {
1250   CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
1251 }
1252 
1253 /**
1254   * @brief  Check if the WakeUp PINx functionality is enabled
1255   * @rmtoll WKUPEPR    WKUPEN1         LL_PWR_IsEnabledWakeUpPin\n
1256   *         WKUPEPR    WKUPEN2         LL_PWR_IsEnabledWakeUpPin\n
1257   *         WKUPEPR    WKUPEN3         LL_PWR_IsEnabledWakeUpPin\n
1258   *         WKUPEPR    WKUPEN4         LL_PWR_IsEnabledWakeUpPin
1259   * @param  WakeUpPin This parameter can be one of the following values:
1260   *         @arg @ref LL_PWR_WAKEUP_PIN1
1261   *         @arg @ref LL_PWR_WAKEUP_PIN2
1262   *         @arg @ref LL_PWR_WAKEUP_PIN3
1263   *         @arg @ref LL_PWR_WAKEUP_PIN4
1264   * @retval State of bit (1 or 0).
1265   */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1266 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1267 {
1268   return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1269 }
1270 
1271 /**
1272   * @brief  Set the Wake-Up pin polarity low for the event detection
1273   * @rmtoll WKUPEPR    WKUPP1          LL_PWR_SetWakeUpPinPolarityLow\n
1274   *         WKUPEPR    WKUPP2          LL_PWR_SetWakeUpPinPolarityLow\n
1275   *         WKUPEPR    WKUPP3          LL_PWR_SetWakeUpPinPolarityLow\n
1276   *         WKUPEPR    WKUPP4          LL_PWR_SetWakeUpPinPolarityLow
1277   * @param  WakeUpPin This parameter can be one of the following values:
1278   *         @arg @ref LL_PWR_WAKEUP_PIN1
1279   *         @arg @ref LL_PWR_WAKEUP_PIN2
1280   *         @arg @ref LL_PWR_WAKEUP_PIN3
1281   *         @arg @ref LL_PWR_WAKEUP_PIN4
1282   * @retval None
1283   */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1284 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1285 {
1286   SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1287 }
1288 
1289 /**
1290   * @brief  Set the Wake-Up pin polarity high for the event detection
1291   * @rmtoll WKUPEPR    WKUPP1          LL_PWR_SetWakeUpPinPolarityHigh\n
1292   *         WKUPEPR    WKUPP2          LL_PWR_SetWakeUpPinPolarityHigh\n
1293   *         WKUPEPR    WKUPP3          LL_PWR_SetWakeUpPinPolarityHigh\n
1294   *         WKUPEPR    WKUPP4          LL_PWR_SetWakeUpPinPolarityHigh
1295   * @param  WakeUpPin This parameter can be one of the following values:
1296   *         @arg @ref LL_PWR_WAKEUP_PIN1
1297   *         @arg @ref LL_PWR_WAKEUP_PIN2
1298   *         @arg @ref LL_PWR_WAKEUP_PIN3
1299   *         @arg @ref LL_PWR_WAKEUP_PIN4
1300   * @retval None
1301   */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1302 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1303 {
1304   CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1305 }
1306 
1307 /**
1308   * @brief  Check if the Wake-Up pin polarity is low for event detection
1309   * @rmtoll WKUPEPR    WKUPP1          LL_PWR_IsWakeUpPinPolarityLow\n
1310   *         WKUPEPR    WKUPP2          LL_PWR_IsWakeUpPinPolarityLow\n
1311   *         WKUPEPR    WKUPP3          LL_PWR_IsWakeUpPinPolarityLow\n
1312   *         WKUPEPR    WKUPP4          LL_PWR_IsWakeUpPinPolarityLow
1313   * @param  WakeUpPin This parameter can be one of the following values:
1314   *         @arg @ref LL_PWR_WAKEUP_PIN1
1315   *         @arg @ref LL_PWR_WAKEUP_PIN2
1316   *         @arg @ref LL_PWR_WAKEUP_PIN3
1317   *         @arg @ref LL_PWR_WAKEUP_PIN4
1318   * @retval State of bit (1 or 0).
1319   */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1320 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1321 {
1322   return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
1323 }
1324 
1325 /**
1326   * @brief  Set the Wake-Up pin Pull None
1327   * @rmtoll WKUPEPR    WKUPPUPD1       LL_PWR_SetWakeUpPinPullNone\n
1328   *         WKUPEPR    WKUPPUPD2       LL_PWR_SetWakeUpPinPullNone\n
1329   *         WKUPEPR    WKUPPUPD3       LL_PWR_SetWakeUpPinPullNone\n
1330   *         WKUPEPR    WKUPPUPD4       LL_PWR_SetWakeUpPinPullNone
1331   * @param  WakeUpPin This parameter can be one of the following values:
1332   *         @arg @ref LL_PWR_WAKEUP_PIN1
1333   *         @arg @ref LL_PWR_WAKEUP_PIN2
1334   *         @arg @ref LL_PWR_WAKEUP_PIN3
1335   *         @arg @ref LL_PWR_WAKEUP_PIN4
1336   * @retval None
1337   */
LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)1338 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
1339 {
1340   MODIFY_REG(PWR->WKUPEPR, \
1341              (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1342              (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1343 }
1344 
1345 /**
1346   * @brief  Set the Wake-Up pin Pull Up
1347   * @rmtoll WKUPEPR    WKUPPUPD1       LL_PWR_SetWakeUpPinPullUp\n
1348   *         WKUPEPR    WKUPPUPD2       LL_PWR_SetWakeUpPinPullUp\n
1349   *         WKUPEPR    WKUPPUPD3       LL_PWR_SetWakeUpPinPullUp\n
1350   *         WKUPEPR    WKUPPUPD4       LL_PWR_SetWakeUpPinPullUp
1351   * @param  WakeUpPin This parameter can be one of the following values:
1352   *         @arg @ref LL_PWR_WAKEUP_PIN1
1353   *         @arg @ref LL_PWR_WAKEUP_PIN2
1354   *         @arg @ref LL_PWR_WAKEUP_PIN3
1355   *         @arg @ref LL_PWR_WAKEUP_PIN4
1356   * @retval None
1357   */
LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)1358 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
1359 {
1360   MODIFY_REG(PWR->WKUPEPR, \
1361              (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1362              (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1363 }
1364 
1365 /**
1366   * @brief  Set the Wake-Up pin Pull Down
1367   * @rmtoll WKUPEPR    WKUPPUPD1       LL_PWR_SetWakeUpPinPullDown\n
1368   *         WKUPEPR    WKUPPUPD2       LL_PWR_SetWakeUpPinPullDown\n
1369   *         WKUPEPR    WKUPPUPD3       LL_PWR_SetWakeUpPinPullDown\n
1370   *         WKUPEPR    WKUPPUPD4       LL_PWR_SetWakeUpPinPullDown
1371   * @param  WakeUpPin This parameter can be one of the following values:
1372   *         @arg @ref LL_PWR_WAKEUP_PIN1
1373   *         @arg @ref LL_PWR_WAKEUP_PIN2
1374   *         @arg @ref LL_PWR_WAKEUP_PIN3
1375   *         @arg @ref LL_PWR_WAKEUP_PIN4
1376   * @retval None
1377   */
LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)1378 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
1379 {
1380   MODIFY_REG(PWR->WKUPEPR, \
1381              (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1382              (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1383 }
1384 
1385 /**
1386   * @brief  Get the Wake-Up pin pull
1387   * @rmtoll WKUPEPR    WKUPPUPD1       LL_PWR_GetWakeUpPinPull\n
1388   *         WKUPEPR    WKUPPUPD2       LL_PWR_GetWakeUpPinPull\n
1389   *         WKUPEPR    WKUPPUPD3       LL_PWR_GetWakeUpPinPull\n
1390   *         WKUPEPR    WKUPPUPD4       LL_PWR_GetWakeUpPinPull\
1391   * @param  WakeUpPin This parameter can be one of the following values:
1392   *         @arg @ref LL_PWR_WAKEUP_PIN1
1393   *         @arg @ref LL_PWR_WAKEUP_PIN2
1394   *         @arg @ref LL_PWR_WAKEUP_PIN3
1395   *         @arg @ref LL_PWR_WAKEUP_PIN4
1396   * @retval Returned value can be one of the following values:
1397   *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
1398   *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
1399   *         @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
1400   */
LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)1401 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
1402 {
1403   uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1404 
1405   return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(
1406                                                                  WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
1407 }
1408 
1409 /**
1410   * @}
1411   */
1412 
1413 /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
1414   * @{
1415   */
1416 
1417 /**
1418   * @brief  Indicate whether the voltage level is ready for current actual used VOS
1419   * @rmtoll VOSCR        ACTVOSRDY     LL_PWR_IsActiveFlag_ACTVOSRDY
1420   * @retval State of bit (1 or 0).
1421   */
LL_PWR_IsActiveFlag_ACTVOSRDY(void)1422 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOSRDY(void)
1423 {
1424   return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_ACTVOSRDY) == (PWR_VOSCR_ACTVOSRDY)) ? 1UL : 0UL);
1425 }
1426 
1427 /**
1428   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
1429   * @rmtoll CR2        PVDO            LL_PWR_IsActiveFlag_PVDO
1430   * @retval State of bit (1 or 0).
1431   */
LL_PWR_IsActiveFlag_PVDO(void)1432 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1433 {
1434   return ((READ_BIT(PWR->CR2, PWR_CR2_PVDO) == (PWR_CR2_PVDO)) ? 1UL : 0UL);
1435 }
1436 
1437 /**
1438   * @brief  Indicate whether the VCORE level is above or below low threshold
1439   * @rmtoll CR3      VCOREL           LL_PWR_IsActiveFlag_VCOREL
1440   * @retval State of bit (1 or 0).
1441   */
LL_PWR_IsActiveFlag_VCOREL(void)1442 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VCOREL(void)
1443 {
1444   return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREL) == (PWR_CR3_VCOREL)) ? 1UL : 0UL);
1445 }
1446 
1447 /**
1448   * @brief  Indicate whether the VCORE level is above or below high threshold
1449   * @rmtoll CR3      VCOREH           LL_PWR_IsActiveFlag_VCOREH
1450   * @retval State of bit (1 or 0).
1451   */
LL_PWR_IsActiveFlag_VCOREH(void)1452 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VCOREH(void)
1453 {
1454   return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREH) == (PWR_CR3_VCOREH)) ? 1UL : 0UL);
1455 }
1456 
1457 /**
1458   * @brief  Indicate whether the Regulator is ready in the selected voltage range
1459   *         or if its output voltage is still changing to the required voltage level
1460   * @rmtoll VOSCR      VOSRDY          LL_PWR_IsActiveFlag_VOSRDY
1461   * @retval State of bit (1 or 0).
1462   */
LL_PWR_IsActiveFlag_VOSRDY(void)1463 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSRDY(void)
1464 {
1465   return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_VOSRDY) == (PWR_VOSCR_VOSRDY)) ? 1UL : 0UL);
1466 }
1467 
1468 /**
1469   * @brief  Indicate whether the VBAT level is above or below low threshold
1470   * @rmtoll BDCR1      VBATL           LL_PWR_IsActiveFlag_VBATL
1471   * @retval State of bit (1 or 0).
1472   */
LL_PWR_IsActiveFlag_VBATL(void)1473 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
1474 {
1475   return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATL) == (PWR_BDCR1_VBATL)) ? 1UL : 0UL);
1476 }
1477 
1478 /**
1479   * @brief  Indicate whether the VBAT level is above or below high threshold
1480   * @rmtoll BDCR1      VBATH           LL_PWR_IsActiveFlag_VBATH
1481   * @retval State of bit (1 or 0).
1482   */
LL_PWR_IsActiveFlag_VBATH(void)1483 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
1484 {
1485   return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATH) == (PWR_BDCR1_VBATH)) ? 1UL : 0UL);
1486 }
1487 
1488 /**
1489   * @brief  Indicate whether the CPU temperature level is above or below low threshold
1490   * @rmtoll BDCR1      TEMPL           LL_PWR_IsActiveFlag_TEMPL
1491   * @retval State of bit (1 or 0).
1492   */
LL_PWR_IsActiveFlag_TEMPL(void)1493 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
1494 {
1495   return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPL) == (PWR_BDCR1_TEMPL)) ? 1UL : 0UL);
1496 }
1497 
1498 /**
1499   * @brief  Indicate whether the CPU temperature level is above or below high threshold
1500   * @rmtoll BDCR1      TEMPH           LL_PWR_IsActiveFlag_TEMPH
1501   * @retval State of bit (1 or 0).
1502   */
LL_PWR_IsActiveFlag_TEMPH(void)1503 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
1504 {
1505   return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPH) == (PWR_BDCR1_TEMPH)) ? 1UL : 0UL);
1506 }
1507 
1508 /**
1509   * @brief  Get System Stop Flag
1510   * @rmtoll CPUCR      STOPF           LL_PWR_IsActiveFlag_STOP
1511   * @retval State of bit (1 or 0).
1512   */
LL_PWR_IsActiveFlag_STOP(void)1513 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
1514 {
1515   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
1516 }
1517 
1518 /**
1519   * @brief  Get System Standby Flag
1520   * @rmtoll CPUCR      SBF             LL_PWR_IsActiveFlag_SB
1521   * @retval State of bit (1 or 0).
1522   */
LL_PWR_IsActiveFlag_SB(void)1523 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1524 {
1525   return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
1526 }
1527 
1528 /**
1529   * @brief  Get VDDIO2 ready Flag
1530   * @rmtoll SVMCR3     VDDIO2RDY       LL_PWR_IsActiveFlag_VDDIO2RDY
1531   * @retval State of bit (1 or 0).
1532   */
LL_PWR_IsActiveFlag_VDDIO2RDY(void)1533 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2RDY(void)
1534 {
1535   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2RDY) == (PWR_SVMCR3_VDDIO2RDY)) ? 1UL : 0UL);
1536 }
1537 
1538 /**
1539   * @brief  Get VDDIO3 ready Flag
1540   * @rmtoll SVMCR3     VDDIO3RDY       LL_PWR_IsActiveFlag_VDDIO3RDY
1541   * @retval State of bit (1 or 0).
1542   */
LL_PWR_IsActiveFlag_VDDIO3RDY(void)1543 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO3RDY(void)
1544 {
1545   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3RDY) == (PWR_SVMCR3_VDDIO3RDY)) ? 1UL : 0UL);
1546 }
1547 
1548 /**
1549   * @brief  Get VDDIO4 ready Flag
1550   * @rmtoll SVMCR1     VDDIO4RDY       LL_PWR_IsActiveFlag_VDDIO4RDY
1551   * @retval State of bit (1 or 0).
1552   */
LL_PWR_IsActiveFlag_VDDIO4RDY(void)1553 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO4RDY(void)
1554 {
1555   return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4RDY) == (PWR_SVMCR1_VDDIO4RDY)) ? 1UL : 0UL);
1556 }
1557 
1558 /**
1559   * @brief  Get VDDIO5 ready Flag
1560   * @rmtoll SVMCR2     VDDIO5RDY       LL_PWR_IsActiveFlag_VDDIO5RDY
1561   * @retval State of bit (1 or 0).
1562   */
LL_PWR_IsActiveFlag_VDDIO5RDY(void)1563 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO5RDY(void)
1564 {
1565   return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5RDY) == (PWR_SVMCR2_VDDIO5RDY)) ? 1UL : 0UL);
1566 }
1567 
1568 /**
1569   * @brief  Get VDD ADC ready Flag
1570   * @rmtoll SVMCR3     ARDY            LL_PWR_IsActiveFlag_ARDY
1571   * @retval State of bit (1 or 0).
1572   */
LL_PWR_IsActiveFlag_ARDY(void)1573 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ARDY(void)
1574 {
1575   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_ARDY) == (PWR_SVMCR3_ARDY)) ? 1UL : 0UL);
1576 }
1577 
1578 /**
1579   * @brief  Get VDD USB33 ready Flag
1580   * @rmtoll SVMCR3     USB33RDY        LL_PWR_IsActiveFlag_USB33RDY
1581   * @retval State of bit (1 or 0).
1582   */
LL_PWR_IsActiveFlag_USB33RDY(void)1583 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB33RDY(void)
1584 {
1585   return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33RDY) == (PWR_SVMCR3_USB33RDY)) ? 1UL : 0UL);
1586 }
1587 
1588 /**
1589   * @brief  Get Wake-up Flag 1
1590   * @rmtoll WKUPSR     WKUPF1          LL_PWR_IsActiveFlag_WU1
1591   * @retval State of bit (1 or 0).
1592   */
LL_PWR_IsActiveFlag_WU1(void)1593 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1594 {
1595   return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF1) == (PWR_WKUPSR_WKUPF1)) ? 1UL : 0UL);
1596 }
1597 
1598 /**
1599   * @brief  Get Wake-up Flag 2
1600   * @rmtoll WKUPSR     WKUPF2          LL_PWR_IsActiveFlag_WU2
1601   * @retval State of bit (1 or 0).
1602   */
LL_PWR_IsActiveFlag_WU2(void)1603 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1604 {
1605   return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF2) == (PWR_WKUPSR_WKUPF2)) ? 1UL : 0UL);
1606 }
1607 
1608 /**
1609   * @brief  Get Wake-up Flag 3
1610   * @rmtoll WKUPSR     WKUPF3          LL_PWR_IsActiveFlag_WU3
1611   * @retval State of bit (1 or 0).
1612   */
LL_PWR_IsActiveFlag_WU3(void)1613 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1614 {
1615   return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF3) == (PWR_WKUPSR_WKUPF3)) ? 1UL : 0UL);
1616 }
1617 
1618 /**
1619   * @brief  Get Wake-up Flag 4
1620   * @rmtoll WKUPSR     WKUPF4          LL_PWR_IsActiveFlag_WU4
1621   * @retval State of bit (1 or 0).
1622   */
LL_PWR_IsActiveFlag_WU4(void)1623 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1624 {
1625   return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF4) == (PWR_WKUPSR_WKUPF4)) ? 1UL : 0UL);
1626 }
1627 
1628 /**
1629   * @brief  Clear STOP and STANDBY and flags
1630   * @rmtoll CPUCR      CSSF            LL_PWR_ClearFlag_STOP_SB
1631   * @retval None
1632   */
LL_PWR_ClearFlag_STOP_SB(void)1633 __STATIC_INLINE void LL_PWR_ClearFlag_STOP_SB(void)
1634 {
1635   SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
1636 }
1637 
1638 /**
1639   * @brief  Clear Wake-up Flag 1
1640   * @rmtoll WKUPCR     WKUPC1          LL_PWR_ClearFlag_WU1
1641   * @retval None
1642   */
LL_PWR_ClearFlag_WU1(void)1643 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1644 {
1645   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
1646 }
1647 
1648 /**
1649   * @brief  Clear Wake-up Flag 2
1650   * @rmtoll WKUPCR     WKUPC2          LL_PWR_ClearFlag_WU2
1651   * @retval None
1652   */
LL_PWR_ClearFlag_WU2(void)1653 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1654 {
1655   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
1656 }
1657 
1658 /**
1659   * @brief  Clear Wake-up Flag 3
1660   * @rmtoll WKUPCR     WKUPC3          LL_PWR_ClearFlag_WU3
1661   * @retval None
1662   */
LL_PWR_ClearFlag_WU3(void)1663 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1664 {
1665   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
1666 }
1667 
1668 /**
1669   * @brief  Clear Wake-up Flag 4
1670   * @rmtoll WKUPCR     WKUPC4          LL_PWR_ClearFlag_WU4
1671   * @retval None
1672   */
LL_PWR_ClearFlag_WU4(void)1673 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1674 {
1675   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
1676 }
1677 
1678 /**
1679   * @brief  Clear all wake up flags.
1680   * @rmtoll WUSCR          WKUPC         LL_PWR_ClearFlag_WU
1681   * @retval None
1682   */
LL_PWR_ClearFlag_WU(void)1683 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1684 {
1685   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC);
1686 }
1687 
1688 /**
1689   * @}
1690   */
1691 
1692 /** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
1693   * @{
1694   */
1695 
1696 /**
1697   * @brief  Configure privilege attribute mode.
1698   * @note   This API can be executed only by CPU in privilege mode.
1699   * @rmtoll PRIVCFGR   PRIV0           LL_PWR_ConfigPrivilege\n
1700   *         PRIVCFGR   PRIV1           LL_PWR_ConfigPrivilege\n
1701   *         PRIVCFGR   PRIV2           LL_PWR_ConfigPrivilege\n
1702   *         PRIVCFGR   PRIV3           LL_PWR_ConfigPrivilege\n
1703   *         PRIVCFGR   PRIV4           LL_PWR_ConfigPrivilege\n
1704   *         PRIVCFGR   PRIV5           LL_PWR_ConfigPrivilege\n
1705   *         PRIVCFGR   PRIV6           LL_PWR_ConfigPrivilege\n
1706   *         PRIVCFGR   PRIV7           LL_PWR_ConfigPrivilege\n
1707   *         PRIVCFGR   WKUPPRIV1       LL_PWR_ConfigPrivilege\n
1708   *         PRIVCFGR   WKUPPRIV2       LL_PWR_ConfigPrivilege\n
1709   *         PRIVCFGR   WKUPPRIV3       LL_PWR_ConfigPrivilege\n
1710   *         PRIVCFGR   WKUPPRIV4       LL_PWR_ConfigPrivilege
1711   * @param  PrivilegeConfig This parameter can be the full combination
1712   *         of the following values:
1713   *         @arg @ref LL_PWR_PRIV0_PRIV or LL_PWR_PRIV0_NPRIV
1714   *         @arg @ref LL_PWR_PRIV1_PRIV or LL_PWR_PRIV1_NPRIV
1715   *         @arg @ref LL_PWR_PRIV2_PRIV or LL_PWR_PRIV2_NPRIV
1716   *         @arg @ref LL_PWR_PRIV3_PRIV or LL_PWR_PRIV3_NPRIV
1717   *         @arg @ref LL_PWR_PRIV4_PRIV or LL_PWR_PRIV4_NPRIV
1718   *         @arg @ref LL_PWR_PRIV5_PRIV or LL_PWR_PRIV5_NPRIV
1719   *         @arg @ref LL_PWR_PRIV6_PRIV or LL_PWR_PRIV6_NPRIV
1720   *         @arg @ref LL_PWR_PRIV7_PRIV or LL_PWR_PRIV7_NPRIV
1721   *         @arg @ref LL_PWR_WAKEUP_PIN1_NPRIV or LL_PWR_WAKEUP_PIN1_PRIV
1722   *         @arg @ref LL_PWR_WAKEUP_PIN2_NPRIV or LL_PWR_WAKEUP_PIN2_PRIV
1723   *         @arg @ref LL_PWR_WAKEUP_PIN3_NPRIV or LL_PWR_WAKEUP_PIN3_PRIV
1724   *         @arg @ref LL_PWR_WAKEUP_PIN4_NPRIV or LL_PWR_WAKEUP_PIN4_PRIV
1725   * @retval None.
1726   */
LL_PWR_ConfigPrivilege(uint32_t PrivilegeConfig)1727 __STATIC_INLINE void LL_PWR_ConfigPrivilege(uint32_t PrivilegeConfig)
1728 {
1729   WRITE_REG(PWR->PRIVCFGR, PrivilegeConfig);
1730 }
1731 
1732 /**
1733   * @brief  Get privilege attribute configuration.
1734   * @rmtoll PRIVCFGR    PRIV0            LL_PWR_GetConfigPrivilege\n
1735   *         PRIVCFGR    PRIV1            LL_PWR_GetConfigPrivilege\n
1736   *         PRIVCFGR    PRIV2            LL_PWR_GetConfigPrivilege\n
1737   *         PRIVCFGR    PRIV3            LL_PWR_GetConfigPrivilege\n
1738   *         PRIVCFGR    PRIV4            LL_PWR_GetConfigPrivilege\n
1739   *         PRIVCFGR    PRIV5            LL_PWR_GetConfigPrivilege\n
1740   *         PRIVCFGR    PRIV6            LL_PWR_GetConfigPrivilege\n
1741   *         PRIVCFGR    PRIV7            LL_PWR_GetConfigPrivilege\n
1742   *         PRIVCFGR    WKUPPRIV1        LL_PWR_GetConfigPrivilege\n
1743   *         PRIVCFGR    WKUPPRIV2        LL_PWR_GetConfigPrivilege\n
1744   *         PRIVCFGR    WKUPPRIV3        LL_PWR_GetConfigPrivilege\n
1745   *         PRIVCFGR    WKUPPRIV4        LL_PWR_GetConfigPrivilege
1746   * @retval Returned value is the combination of the following values:
1747   *         @arg @ref LL_PWR_PRIV0_PRIV or LL_PWR_PRIV0_NPRIV
1748   *         @arg @ref LL_PWR_PRIV1_PRIV or LL_PWR_PRIV1_NPRIV
1749   *         @arg @ref LL_PWR_PRIV2_PRIV or LL_PWR_PRIV2_NPRIV
1750   *         @arg @ref LL_PWR_PRIV3_PRIV or LL_PWR_PRIV3_NPRIV
1751   *         @arg @ref LL_PWR_PRIV4_PRIV or LL_PWR_PRIV4_NPRIV
1752   *         @arg @ref LL_PWR_PRIV5_PRIV or LL_PWR_PRIV5_NPRIV
1753   *         @arg @ref LL_PWR_PRIV6_PRIV or LL_PWR_PRIV6_NPRIV
1754   *         @arg @ref LL_PWR_PRIV7_PRIV or LL_PWR_PRIV7_NPRIV
1755   *         @arg @ref LL_PWR_WAKEUP_PIN1_NPRIV or LL_PWR_WAKEUP_PIN1_PRIV
1756   *         @arg @ref LL_PWR_WAKEUP_PIN2_NPRIV or LL_PWR_WAKEUP_PIN2_PRIV
1757   *         @arg @ref LL_PWR_WAKEUP_PIN3_NPRIV or LL_PWR_WAKEUP_PIN3_PRIV
1758   *         @arg @ref LL_PWR_WAKEUP_PIN4_NPRIV or LL_PWR_WAKEUP_PIN4_PRIV
1759   */
LL_PWR_GetConfigPrivilege(void)1760 __STATIC_INLINE uint32_t LL_PWR_GetConfigPrivilege(void)
1761 {
1762   return (READ_REG(PWR->PRIVCFGR));
1763 }
1764 
1765 #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
1766 /**
1767   * @brief  Configure secure attribute mode.
1768   * @note   This API can be executed only by CPU in secure mode.
1769   * @rmtoll SECCFGR    SEC0            LL_PWR_ConfigSecure\n
1770   *         SECCFGR    SEC1            LL_PWR_ConfigSecure\n
1771   *         SECCFGR    SEC2            LL_PWR_ConfigSecure\n
1772   *         SECCFGR    SEC3            LL_PWR_ConfigSecure\n
1773   *         SECCFGR    SEC4            LL_PWR_ConfigSecure\n
1774   *         SECCFGR    SEC5            LL_PWR_ConfigSecure\n
1775   *         SECCFGR    SEC6            LL_PWR_ConfigSecure\n
1776   *         SECCFGR    SEC7            LL_PWR_ConfigSecure\n
1777   *         SECCFGR    WKUPSEC1        LL_PWR_ConfigSecure\n
1778   *         SECCFGR    WKUPSEC2        LL_PWR_ConfigSecure\n
1779   *         SECCFGR    WKUPSEC3        LL_PWR_ConfigSecure\n
1780   *         SECCFGR    WKUPSEC4        LL_PWR_ConfigSecure
1781   * @param  SecureConfig This parameter can be the full combination
1782   *         of the following values:
1783   *         @arg @ref LL_PWR_SEC0_SEC or LL_PWR_SEC0_NSEC
1784   *         @arg @ref LL_PWR_SEC1_SEC or LL_PWR_SEC1_NSEC
1785   *         @arg @ref LL_PWR_SEC2_SEC or LL_PWR_SEC2_NSEC
1786   *         @arg @ref LL_PWR_SEC3_SEC or LL_PWR_SEC3_NSEC
1787   *         @arg @ref LL_PWR_SEC4_SEC or LL_PWR_SEC4_NSEC
1788   *         @arg @ref LL_PWR_SEC5_SEC or LL_PWR_SEC5_NSEC
1789   *         @arg @ref LL_PWR_SEC6_SEC or LL_PWR_SEC6_NSEC
1790   *         @arg @ref LL_PWR_SEC7_SEC or LL_PWR_SEC7_NSEC
1791   *         @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1792   *         @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1793   *         @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1794   *         @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1795   * @retval None.
1796   */
LL_PWR_ConfigSecure(uint32_t SecureConfig)1797 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
1798 {
1799   WRITE_REG(PWR->SECCFGR, SecureConfig);
1800 }
1801 
1802 /**
1803   * @brief  Get secure attribute configuration.
1804   * @note   This API can be executed only by CPU in secure mode.
1805   * @rmtoll SECCFGR    SEC0            LL_PWR_GetConfigSecure\n
1806   *         SECCFGR    SEC1            LL_PWR_GetConfigSecure\n
1807   *         SECCFGR    SEC2            LL_PWR_GetConfigSecure\n
1808   *         SECCFGR    SEC3            LL_PWR_GetConfigSecure\n
1809   *         SECCFGR    SEC4            LL_PWR_GetConfigSecure\n
1810   *         SECCFGR    SEC5            LL_PWR_GetConfigSecure\n
1811   *         SECCFGR    SEC6            LL_PWR_GetConfigSecure\n
1812   *         SECCFGR    SEC7            LL_PWR_GetConfigSecure\n
1813   *         SECCFGR    WKUPSEC1        LL_PWR_GetConfigSecure\n
1814   *         SECCFGR    WKUPSEC2        LL_PWR_GetConfigSecure\n
1815   *         SECCFGR    WKUPSEC3        LL_PWR_GetConfigSecure\n
1816   *         SECCFGR    WKUPSEC4        LL_PWR_GetConfigSecure
1817   * @retval Returned value is the combination of the following values:
1818   *         @arg @ref LL_PWR_SEC0_SEC or LL_PWR_SEC0_NSEC
1819   *         @arg @ref LL_PWR_SEC1_SEC or LL_PWR_SEC1_NSEC
1820   *         @arg @ref LL_PWR_SEC2_SEC or LL_PWR_SEC2_NSEC
1821   *         @arg @ref LL_PWR_SEC3_SEC or LL_PWR_SEC3_NSEC
1822   *         @arg @ref LL_PWR_SEC4_SEC or LL_PWR_SEC4_NSEC
1823   *         @arg @ref LL_PWR_SEC5_SEC or LL_PWR_SEC5_NSEC
1824   *         @arg @ref LL_PWR_SEC6_SEC or LL_PWR_SEC6_NSEC
1825   *         @arg @ref LL_PWR_SEC7_SEC or LL_PWR_SEC7_NSEC
1826   *         @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1827   *         @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1828   *         @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1829   *         @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1830   */
LL_PWR_GetConfigSecure(void)1831 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
1832 {
1833   return (READ_REG(PWR->SECCFGR));
1834 }
1835 #endif /* defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U) */
1836 /**
1837   * @}
1838   */
1839 
1840 #if defined (USE_FULL_LL_DRIVER)
1841 /** @defgroup PWR_LL_EF_Init De-initialization function
1842   * @{
1843   */
1844 ErrorStatus LL_PWR_DeInit(void);
1845 /**
1846   * @}
1847   */
1848 #endif /* defined (USE_FULL_LL_DRIVER) */
1849 /**
1850   * @}
1851   */
1852 
1853 /**
1854   * @}
1855   */
1856 
1857 #endif /* defined (PWR) */
1858 
1859 /**
1860   * @}
1861   */
1862 
1863 #ifdef __cplusplus
1864 }
1865 #endif /* __cplusplus */
1866 
1867 #endif /* STM32N6xx_LL_PWR_H */
1868 
1869