1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_LL_PWR_H
21 #define STM32H7RSxx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx.h"
29
30 /** @addtogroup STM32H7RSxx_LL_Driver
31 * @{
32 */
33
34 #if defined (PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
44 * @{
45 */
46
47 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
48 * @brief Flags defines which can be used with LL_PWR_WriteReg function
49 * @{
50 */
51 /* Wake-Up Pins PWR register offsets */
52 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2UL)
53 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK (0x1FU)
54 /**
55 * @}
56 */
57 /**
58 * @}
59 */
60 /* Private macros ------------------------------------------------------------*/
61 /* Exported types ------------------------------------------------------------*/
62 /* Exported constants --------------------------------------------------------*/
63 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
64 * @{
65 */
66
67 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
68 * @brief Flags defines which can be used with LL_PWR_WriteReg function
69 * @{
70 */
71 #define LL_PWR_SR_CSSF PWR_CSR3_CSSF /*!< Clear Stop and Standby flags */
72 #define LL_PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear Wakeup flag 1 */
73 #define LL_PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear Wakeup flag 2 */
74 #define LL_PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear Wakeup flag 3 */
75 #define LL_PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear Wakeup flag 4 */
76 #define LL_PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC /*!< Clear all Wakeup flags */
77 /**
78 * @}
79 */
80
81 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
82 * @brief Flags defines which can be used with LL_PWR_ReadReg function
83 * @{
84 */
85 #define LL_PWR_FLAG_VOSRDY PWR_CSR4_VOSRDY /*!< Voltage scaling ready flag */
86 #define LL_PWR_FLAG_STOPF PWR_CSR3_STOPF /*!< Stop flag */
87 #define LL_PWR_FLAG_SBF PWR_CSR3_SBF /*!< Standby flag */
88 #define LL_PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag 1 */
89 #define LL_PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag 2 */
90 #define LL_PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag 3 */
91 #define LL_PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag 4 */
92 /**
93 * @}
94 */
95
96 /** @defgroup PWR_LL_EC_MODE_PWR Power Down Mode In Deep Sleep Mode
97 * @{
98 */
99 #define LL_PWR_POWERDOWN_MODE_DS_STOP (0U) /*!< Enter to Stop mode when the CPU enters deepsleep */
100 #define LL_PWR_POWERDOWN_MODE_DS_STANDBY PWR_CSR3_PDDS /*!< Enter to Standby mode when the CPU enters deepsleep */
101 /**
102 * @}
103 */
104
105 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
106 * @{
107 */
108 #define LL_PWR_REGU_VOLTAGE_SCALE0 PWR_CSR4_VOS /*!< Voltage scaling range 0 (highest frequency) */
109 #define LL_PWR_REGU_VOLTAGE_SCALE1 (0U) /*!< Voltage scaling range 1 (lowest power) */
110 /**
111 * @}
112 */
113
114 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
115 * @{
116 */
117 #define LL_PWR_REGU_STOP_VOLTAGE_SCALE3 PWR_CR1_SVOS /*!< Voltage scaling range 3 (highest frequency) when system enters STOP mode */
118 #define LL_PWR_REGU_STOP_VOLTAGE_SCALE5 (0U) /*!< Voltage scaling range 5 (lowest power) when system enters STOP mode */
119 /**
120 * @}
121 */
122
123 /** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
124 * @{
125 */
126 #define LL_PWR_PVDLEVEL_1 (0U) /*!< PVD level 1 */
127 #define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_0 /*!< PVD level 2 */
128 #define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_1 /*!< PVD level 3 */
129 #define LL_PWR_PVDLEVEL_4 (PWR_CR1_PLS_0 | PWR_CR1_PLS_1) /*!< PVD level 4 */
130 #define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_2 /*!< PVD level 5 */
131 #define LL_PWR_PVDLEVEL_6 (PWR_CR1_PLS_0 | PWR_CR1_PLS_2) /*!< PVD level 6 */
132 #define LL_PWR_PVDLEVEL_7 (PWR_CR1_PLS_1 | PWR_CR1_PLS_2) /*!< PVD level 7 */
133 #define LL_PWR_PVDLEVEL_EXT (PWR_CR1_PLS_0 | PWR_CR1_PLS_1 | PWR_CR1_PLS_2)
134 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level */
135 /**
136 * @}
137 */
138
139 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
140 * @{
141 */
142 #define LL_PWR_AVDLEVEL_1 (0U) /*!< Analog Voltage detector level 1 */
143 #define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_0 /*!< Analog Voltage detector level 2 */
144 #define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_1 /*!< Analog Voltage detector level 3 */
145 #define LL_PWR_AVDLEVEL_4 (PWR_CR1_ALS_0 | PWR_CR1_ALS_1) /*!< Analog Voltage detector level 4 */
146 /**
147 * @}
148 */
149
150 /** @defgroup PWR_LL_EC_XSPI_CAP1 XSPI 1 capacitor
151 * @{
152 */
153 #define LL_PWR_XSPI1_CAPACITOR_OFF (0U) /*!< XSPI Port 1 Capacitor OFF */
154 #define LL_PWR_XSPI1_CAPACITOR_1_DIV_3 PWR_CSR2_XSPICAP1_0 /*!< XSPI Port 1 Capacitor set to 1/3 */
155 #define LL_PWR_XSPI1_CAPACITOR_2_DIV_3 PWR_CSR2_XSPICAP1_1 /*!< XSPI Port 1 Capacitor set to 2/3 */
156 #define LL_PWR_XSPI1_CAPACITOR_FULL (PWR_CSR2_XSPICAP1_0 | PWR_CSR2_XSPICAP1_1)
157 /*!< XSPI Port 1 Capacitor set to full capacitance */
158 /**
159 * @}
160 */
161
162 /** @defgroup PWR_LL_EC_XSPI_CAP2 XSPI 2 Capacitor
163 * @{
164 */
165 #define LL_PWR_XSPI2_CAPACITOR_OFF (0U) /*!< XSPI Port 2 Capacitor OFF */
166 #define LL_PWR_XSPI2_CAPACITOR_1_DIV_3 PWR_CSR2_XSPICAP2_0 /*!< XSPI Port 2 Capacitor set to 1/3 */
167 #define LL_PWR_XSPI2_CAPACITOR_2_DIV_3 PWR_CSR2_XSPICAP2_1 /*!< XSPI Port 2 Capacitor set to 2/3 */
168 #define LL_PWR_XSPI2_CAPACITOR_FULL (PWR_CSR2_XSPICAP2_0 | PWR_CSR2_XSPICAP2_1)
169 /*!< XSPI Port 2 Capacitor set to full capacitance */
170 /**
171 * @}
172 */
173
174 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
175 * @{
176 */
177 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0U) /*!< Charge the Battery through a 5 kO resistor */
178 #define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_CSR2_VBRS /*!< Charge the Battery through a 1.5 kO resistor */
179 /**
180 * @}
181 */
182
183 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
184 * @{
185 */
186 #define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */
187 #define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */
188 #define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PC13 */
189 #define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC1 */
190 /**
191 * @}
192 */
193
194 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
195 * @{
196 */
197 #define LL_PWR_WAKEUP_PIN_NOPULL (0UL) /*!< Configure Wake-Up pin in no pull */
198 #define LL_PWR_WAKEUP_PIN_PULLUP (1UL) /*!< Configure Wake-Up pin in pull Up */
199 #define LL_PWR_WAKEUP_PIN_PULLDOWN (2UL) /*!< Configure Wake-Up pin in pull Down */
200 /**
201 * @}
202 */
203
204 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
205 * @{
206 */
207 #define LL_PWR_LDO_SUPPLY PWR_CSR2_LDOEN /*!< Core domains are supplied from the LDO */
208 #define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CSR2_SDEN /*!< Core domains are supplied from the SMPS */
209 #define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CSR2_SDHILEVEL | PWR_CSR2_SDEN | PWR_CSR2_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
210 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
211 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
212 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CSR2_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */
213 /**
214 * @}
215 */
216
217 /** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask
218 * @{
219 */
220 #define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */
221 #define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */
222 #define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */
223 #define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */
224 #define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */
225 #define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */
226 #define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */
227 #define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */
228 #define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */
229 #define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */
230 #define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */
231 #define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */
232 #define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */
233 #define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */
234 #define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */
235 #define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */
236 /**
237 * @}
238 */
239
240 /**
241 * @}
242 */
243 /* Exported macro ------------------------------------------------------------*/
244 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
245 * @{
246 */
247
248 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
249 * @{
250 */
251
252 /**
253 * @brief Write a value in PWR register
254 * @param __REG__ Register to be written
255 * @param __VALUE__ Value to be written in the register
256 * @retval None
257 */
258 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
259
260 /**
261 * @brief Read a value in PWR register
262 * @param __REG__ Register to be read
263 * @retval Register value
264 */
265 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
266 /**
267 * @}
268 */
269
270 /**
271 * @}
272 */
273 /* Exported functions --------------------------------------------------------*/
274 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
275 * @{
276 */
277
278 /** @defgroup PWR_LL_EF_Configuration PWR Configuration
279 * @{
280 */
281
282 /**
283 * @brief Enable Power Voltage Detector
284 * @rmtoll CR1 PVDE LL_PWR_EnablePVD
285 * @retval None
286 */
LL_PWR_EnablePVD(void)287 __STATIC_INLINE void LL_PWR_EnablePVD(void)
288 {
289 SET_BIT(PWR->CR1, PWR_CR1_PVDE);
290 }
291
292 /**
293 * @brief Disable Power Voltage Detector
294 * @rmtoll CR1 PVDE LL_PWR_DisablePVD
295 * @retval None
296 */
LL_PWR_DisablePVD(void)297 __STATIC_INLINE void LL_PWR_DisablePVD(void)
298 {
299 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
300 }
301
302 /**
303 * @brief Check if Power Voltage Detector is enabled
304 * @rmtoll CR1 PVDE LL_PWR_IsEnabledPVD
305 * @retval State of bit (1 or 0).
306 */
LL_PWR_IsEnabledPVD(void)307 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
308 {
309 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE)) ? 1UL : 0UL);
310 }
311
312 /**
313 * @brief Configure the voltage threshold detected by the Power Voltage Detector
314 * @rmtoll CR1 PLS LL_PWR_SetPVDLevel
315 * @param PVDLevel This parameter can be one of the following values:
316 * @arg @ref LL_PWR_PVDLEVEL_1
317 * @arg @ref LL_PWR_PVDLEVEL_2
318 * @arg @ref LL_PWR_PVDLEVEL_3
319 * @arg @ref LL_PWR_PVDLEVEL_4
320 * @arg @ref LL_PWR_PVDLEVEL_5
321 * @arg @ref LL_PWR_PVDLEVEL_6
322 * @arg @ref LL_PWR_PVDLEVEL_7
323 * @arg @ref LL_PWR_PVDLEVEL_EXT
324 * @retval None
325 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)326 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
327 {
328 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
329 }
330
331 /**
332 * @brief Get the voltage threshold detection
333 * @rmtoll CR1 PLS LL_PWR_GetPVDLevel
334 * @retval Returned value can be one of the following values:
335 * @arg @ref LL_PWR_PVDLEVEL_1
336 * @arg @ref LL_PWR_PVDLEVEL_2
337 * @arg @ref LL_PWR_PVDLEVEL_3
338 * @arg @ref LL_PWR_PVDLEVEL_4
339 * @arg @ref LL_PWR_PVDLEVEL_5
340 * @arg @ref LL_PWR_PVDLEVEL_6
341 * @arg @ref LL_PWR_PVDLEVEL_7
342 * @arg @ref LL_PWR_PVDLEVEL_EXT
343 */
LL_PWR_GetPVDLevel(void)344 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
345 {
346 return READ_BIT(PWR->CR1, PWR_CR1_PLS);
347 }
348
349 /**
350 * @brief Enable access to the backup domain
351 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
352 * @retval None
353 */
LL_PWR_EnableBkUpAccess(void)354 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
355 {
356 SET_BIT(PWR->CR1, PWR_CR1_DBP);
357 }
358
359 /**
360 * @brief Disable access to the backup domain
361 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
362 * @retval None
363 */
LL_PWR_DisableBkUpAccess(void)364 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
365 {
366 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
367 }
368
369 /**
370 * @brief Check if the backup domain is enabled
371 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
372 * @retval State of bit (1 or 0).
373 */
LL_PWR_IsEnabledBkUpAccess(void)374 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
375 {
376 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
377 }
378
379 /**
380 * @brief Enable the Flash low-power mode in Stop Mode
381 * @rmtoll CR1 FLPS LL_PWR_EnableFlashLowPower
382 * @retval None
383 */
LL_PWR_EnableFlashLowPower(void)384 __STATIC_INLINE void LL_PWR_EnableFlashLowPower(void)
385 {
386 SET_BIT(PWR->CR1, PWR_CR1_FLPS);
387 }
388
389 /**
390 * @brief Disable the Flash low-power mode in Stop Mode
391 * @rmtoll CR1 FLPS LL_PWR_DisableFlashLowPower
392 * @retval None
393 */
LL_PWR_DisableFlashLowPower(void)394 __STATIC_INLINE void LL_PWR_DisableFlashLowPower(void)
395 {
396 CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
397 }
398
399 /**
400 * @brief Check if the Flash low-power mode in Stop Mode is enabled
401 * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashLowPower
402 * @retval State of bit (1 or 0).
403 */
LL_PWR_IsEnabledFlashLowPower(void)404 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashLowPower(void)
405 {
406 return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
407 }
408
409 /**
410 * @brief Enable the Analog Voltage Booster
411 * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster
412 * @retval None
413 */
LL_PWR_EnableAnalogBooster(void)414 __STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
415 {
416 SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
417 }
418
419 /**
420 * @brief Disable the Analog Voltage Booster
421 * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster
422 * @retval None
423 */
LL_PWR_DisableAnalogBooster(void)424 __STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
425 {
426 CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
427 }
428
429 /**
430 * @brief Check if the Analog Voltage Booster is enabled
431 * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster
432 * @retval State of bit (1 or 0).
433 */
LL_PWR_IsEnabledAnalogBooster(void)434 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
435 {
436 return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
437 }
438
439 /**
440 * @brief Enable the Analog Voltage Ready
441 * @rmtoll CR1 AVDREADY LL_PWR_EnableAnalogVoltageReady
442 * @retval None
443 */
LL_PWR_EnableAnalogVoltageReady(void)444 __STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
445 {
446 SET_BIT(PWR->CR1, PWR_CR1_AVDREADY);
447 }
448
449 /**
450 * @brief Disable the Analog Voltage Ready
451 * @rmtoll CR1 AVDREADY LL_PWR_DisableAnalogVoltageReady
452 * @retval None
453 */
LL_PWR_DisableAnalogVoltageReady(void)454 __STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
455 {
456 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDREADY);
457 }
458
459 /**
460 * @brief Check if the Analog Voltage Ready is enabled
461 * @rmtoll CR1 AVDREADY LL_PWR_IsEnabledAnalogVoltageReady
462 * @retval State of bit (1 or 0).
463 */
LL_PWR_IsEnabledAnalogVoltageReady(void)464 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
465 {
466 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDREADY) == (PWR_CR1_AVDREADY)) ? 1UL : 0UL);
467 }
468
469 /**
470 * @brief Enable Analog Power Voltage Monitor
471 * @rmtoll CR1 AVDEN LL_PWR_EnableAVD
472 * @retval None
473 */
LL_PWR_EnableAVD(void)474 __STATIC_INLINE void LL_PWR_EnableAVD(void)
475 {
476 SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
477 }
478
479 /**
480 * @brief Disable Analog Power Voltage Monitor
481 * @rmtoll CR1 AVDEN LL_PWR_DisableAVD
482 * @retval None
483 */
LL_PWR_DisableAVD(void)484 __STATIC_INLINE void LL_PWR_DisableAVD(void)
485 {
486 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
487 }
488
489 /**
490 * @brief Check if Analog Power Voltage Monitor is enabled
491 * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD
492 * @retval State of bit (1 or 0).
493 */
LL_PWR_IsEnabledAVD(void)494 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
495 {
496 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
497 }
498
499 /**
500 * @brief Set the Analog Voltage detector level
501 * @rmtoll CR1 ALS LL_PWR_SetAVDLevel
502 * @param AVDLevel This parameter can be one of the following values:
503 * @arg @ref LL_PWR_AVDLEVEL_1
504 * @arg @ref LL_PWR_AVDLEVEL_2
505 * @arg @ref LL_PWR_AVDLEVEL_3
506 * @arg @ref LL_PWR_AVDLEVEL_4
507 * @retval None
508 */
LL_PWR_SetAVDLevel(uint32_t AVDLevel)509 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
510 {
511 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
512 }
513
514 /**
515 * @brief Get the Analog Voltage detector level selected
516 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel
517 * @retval Returned value can be one of the following values:
518 * @arg @ref LL_PWR_AVDLEVEL_1
519 * @arg @ref LL_PWR_AVDLEVEL_2
520 * @arg @ref LL_PWR_AVDLEVEL_3
521 * @arg @ref LL_PWR_AVDLEVEL_4
522 */
LL_PWR_GetAVDLevel(void)523 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
524 {
525 return READ_BIT(PWR->CR1, PWR_CR1_ALS);
526 }
527
528 /**
529 * @brief Enable Backup Regulator
530 * @rmtoll CSR1 BREN LL_PWR_EnableBkUpRegulator
531 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
532 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
533 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
534 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
535 * the data written into the RAM will be maintained in the Standby and VBAT modes.
536 * @retval None
537 */
LL_PWR_EnableBkUpRegulator(void)538 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
539 {
540 SET_BIT(PWR->CSR1, PWR_CSR1_BREN);
541 }
542
543 /**
544 * @brief Disable Backup Regulator
545 * @rmtoll CSR1 BREN LL_PWR_DisableBkUpRegulator
546 * @retval None
547 */
LL_PWR_DisableBkUpRegulator(void)548 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
549 {
550 CLEAR_BIT(PWR->CSR1, PWR_CSR1_BREN);
551 }
552
553 /**
554 * @brief Check if the backup Regulator is enabled
555 * @rmtoll CSR1 BREN LL_PWR_IsEnabledBkUpRegulator
556 * @retval State of bit (1 or 0).
557 */
LL_PWR_IsEnabledBkUpRegulator(void)558 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
559 {
560 return ((READ_BIT(PWR->CSR1, PWR_CSR1_BREN) == (PWR_CSR1_BREN)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Enable VBAT and Temperature monitoring
565 * @rmtoll CSR1 MONEN LL_PWR_EnableMonitoring
566 * @retval None
567 */
LL_PWR_EnableMonitoring(void)568 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
569 {
570 SET_BIT(PWR->CSR1, PWR_CSR1_MONEN);
571 }
572
573 /**
574 * @brief Disable VBAT and Temperature monitoring
575 * @rmtoll CSR1 MONEN LL_PWR_DisableMonitoring
576 * @retval None
577 */
LL_PWR_DisableMonitoring(void)578 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
579 {
580 CLEAR_BIT(PWR->CSR1, PWR_CSR1_MONEN);
581 }
582
583 /**
584 * @brief Check if the VBAT and Temperature monitoring is enabled
585 * @rmtoll CSR1 MONEN LL_PWR_IsEnabledMonitoring
586 * @retval State of bit (1 or 0).
587 */
LL_PWR_IsEnabledMonitoring(void)588 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
589 {
590 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MONEN) == (PWR_CSR1_MONEN)) ? 1UL : 0UL);
591 }
592
593 /**
594 * @brief Configure the PWR supply
595 * @rmtoll CSR2 SDHILEVEL LL_PWR_ConfigSupply
596 * @rmtoll CSR2 SMPSEXTHP LL_PWR_ConfigSupply
597 * @rmtoll CSR2 SDEN LL_PWR_ConfigSupply
598 * @rmtoll CSR2 LDOEN LL_PWR_ConfigSupply
599 * @rmtoll CSR2 BYPASS LL_PWR_ConfigSupply
600 * @param SupplySource This parameter can be one of the following values:
601 * @arg @ref LL_PWR_LDO_SUPPLY
602 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
603 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
604 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
605 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
606 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
607 * @retval None
608 */
LL_PWR_ConfigSupply(uint32_t SupplySource)609 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
610 {
611 /* Set the power supply configuration */
612 MODIFY_REG(PWR->CSR2, (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS),
613 SupplySource);
614 }
615
616 /**
617 * @brief Get the PWR supply
618 * @rmtoll CSR2 SDHILEVEL LL_PWR_GetSupply
619 * @rmtoll CSR2 SMPSEXTHP LL_PWR_GetSupply
620 * @rmtoll CSR2 SDEN LL_PWR_GetSupply
621 * @rmtoll CSR2 LDOEN LL_PWR_GetSupply
622 * @rmtoll CSR2 BYPASS LL_PWR_GetSupply
623 * @retval Returned value can be one of the following values:
624 * @arg @ref LL_PWR_LDO_SUPPLY
625 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
626 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
627 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
628 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
629 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
630 */
LL_PWR_GetSupply(void)631 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
632 {
633 /* Get the power supply configuration */
634 return READ_BIT(PWR->CSR2,
635 (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS));
636 }
637
638 /**
639 * @brief Enable VBAT battery charging
640 * @rmtoll CSR2 VBE LL_PWR_EnableBatteryCharging
641 * @retval None
642 */
LL_PWR_EnableBatteryCharging(void)643 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
644 {
645 SET_BIT(PWR->CSR2, PWR_CSR2_VBE);
646 }
647
648 /**
649 * @brief Disable VBAT battery charging
650 * @rmtoll CSR2 VBE LL_PWR_DisableBatteryCharging
651 * @retval None
652 */
LL_PWR_DisableBatteryCharging(void)653 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
654 {
655 CLEAR_BIT(PWR->CSR2, PWR_CSR2_VBE);
656 }
657
658 /**
659 * @brief Check if VBAT battery charging is enabled
660 * @rmtoll CSR2 VBE LL_PWR_IsEnabledBatteryCharging
661 * @retval State of bit (1 or 0).
662 */
LL_PWR_IsEnabledBatteryCharging(void)663 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
664 {
665 return ((READ_BIT(PWR->CSR2, PWR_CSR2_VBE) == (PWR_CSR2_VBE)) ? 1UL : 0UL);
666 }
667
668 /**
669 * @brief Set the Battery charge resistor impedance
670 * @rmtoll CSR2 VBRS LL_PWR_SetBattChargResistor
671 * @param Resistor This parameter can be one of the following values:
672 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
673 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
674 * @retval None
675 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)676 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
677 {
678 MODIFY_REG(PWR->CSR2, PWR_CSR2_VBRS, Resistor);
679 }
680
681 /**
682 * @brief Get the Battery charge resistor impedance
683 * @rmtoll CSR2 VBRS LL_PWR_GetBattChargResistor
684 * @retval Returned value can be one of the following values:
685 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
686 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
687 */
LL_PWR_GetBattChargResistor(void)688 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
689 {
690 return (READ_BIT(PWR->CSR2, PWR_CSR2_VBRS));
691 }
692
693 /**
694 * @brief Set the XSPI port 1 capacitor value
695 * @rmtoll CSR2 XSPICAP1 LL_PWR_SetXSPI1Capacitor
696 * @param Capacitor This parameter can be one of the following values:
697 * @arg @ref LL_PWR_XSPI1_CAPACITOR_OFF
698 * @arg @ref LL_PWR_XSPI1_CAPACITOR_1_DIV_3
699 * @arg @ref LL_PWR_XSPI1_CAPACITOR_2_DIV_3
700 * @arg @ref LL_PWR_XSPI1_CAPACITOR_FULL
701 * @retval None
702 */
LL_PWR_SetXSPI1Capacitor(uint32_t Capacitor)703 __STATIC_INLINE void LL_PWR_SetXSPI1Capacitor(uint32_t Capacitor)
704 {
705 MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP1, Capacitor);
706 }
707
708 /**
709 * @brief Get the XSPI port 1 capacitor value
710 * @rmtoll CSR2 XSPICAP1 LL_PWR_GetXSPI1Capacitor
711 * @retval Returned value can be one of the following values:
712 * @arg @ref LL_PWR_XSPI1_CAPACITOR_OFF
713 * @arg @ref LL_PWR_XSPI1_CAPACITOR_1_DIV_3
714 * @arg @ref LL_PWR_XSPI1_CAPACITOR_2_DIV_3
715 * @arg @ref LL_PWR_XSPI1_CAPACITOR_FULL
716 */
LL_PWR_GetXSPI1Capacitor(void)717 __STATIC_INLINE uint32_t LL_PWR_GetXSPI1Capacitor(void)
718 {
719 return (READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP1));
720 }
721
722 /**
723 * @brief Set the XSPI port 2 capacitor value
724 * @rmtoll CSR2 XSPICAP2 LL_PWR_SetXSPI2Capacitor
725 * @param Capacitor This parameter can be one of the following values:
726 * @arg @ref LL_PWR_XSPI2_CAPACITOR_OFF
727 * @arg @ref LL_PWR_XSPI2_CAPACITOR_1_DIV_3
728 * @arg @ref LL_PWR_XSPI2_CAPACITOR_2_DIV_3
729 * @arg @ref LL_PWR_XSPI2_CAPACITOR_FULL
730 * @retval None
731 */
LL_PWR_SetXSPI2Capacitor(uint32_t Capacitor)732 __STATIC_INLINE void LL_PWR_SetXSPI2Capacitor(uint32_t Capacitor)
733 {
734 MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP2, Capacitor);
735 }
736
737 /**
738 * @brief Get the XSPI port 2 capacitor value
739 * @rmtoll CSR2 XSPICAP2 LL_PWR_GetXSPI2Capacitor
740 * @retval Returned value can be one of the following values:
741 * @arg @ref LL_PWR_XSPI2_CAPACITOR_OFF
742 * @arg @ref LL_PWR_XSPI2_CAPACITOR_1_DIV_3
743 * @arg @ref LL_PWR_XSPI2_CAPACITOR_2_DIV_3
744 * @arg @ref LL_PWR_XSPI2_CAPACITOR_FULL
745 */
LL_PWR_GetXSPI2Capacitor(void)746 __STATIC_INLINE uint32_t LL_PWR_GetXSPI2Capacitor(void)
747 {
748 return (uint32_t)(READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP2));
749 }
750
751 /**
752 * @brief Enable the USB voltage detector
753 * @rmtoll CSR2 USB33DEN LL_PWR_EnableUSBVoltageDetector
754 * @retval None
755 */
LL_PWR_EnableUSBVoltageDetector(void)756 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
757 {
758 SET_BIT(PWR->CSR2, PWR_CSR2_USB33DEN);
759 }
760
761 /**
762 * @brief Disable the USB voltage detector
763 * @rmtoll CSR2 USB33DEN LL_PWR_DisableUSBVoltageDetector
764 * @retval None
765 */
LL_PWR_DisableUSBVoltageDetector(void)766 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
767 {
768 CLEAR_BIT(PWR->CSR2, PWR_CSR2_USB33DEN);
769 }
770
771 /**
772 * @brief Check if the USB voltage detector is enabled
773 * @rmtoll CSR2 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
774 * @retval State of bit (1 or 0).
775 */
LL_PWR_IsEnabledUSBVoltageDetector(void)776 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
777 {
778 return ((READ_BIT(PWR->CSR2, PWR_CSR2_USB33DEN) == (PWR_CSR2_USB33DEN)) ? 1UL : 0UL);
779 }
780
781 /**
782 * @brief Enable the USB regulator
783 * @rmtoll CSR2 USBREGEN LL_PWR_EnableUSBReg
784 * @retval None
785 */
LL_PWR_EnableUSBReg(void)786 __STATIC_INLINE void LL_PWR_EnableUSBReg(void)
787 {
788 SET_BIT(PWR->CSR2, PWR_CSR2_USBREGEN);
789 }
790
791 /**
792 * @brief Disable the USB regulator
793 * @rmtoll CSR2 USBREGEN LL_PWR_DisableUSBReg
794 * @retval None
795 */
LL_PWR_DisableUSBReg(void)796 __STATIC_INLINE void LL_PWR_DisableUSBReg(void)
797 {
798 CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBREGEN);
799 }
800
801 /**
802 * @brief Check if the USB regulator is enabled
803 * @rmtoll CSR2 USBREGEN LL_PWR_IsEnabledUSBReg
804 * @retval State of bit (1 or 0).
805 */
LL_PWR_IsEnabledUSBReg(void)806 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
807 {
808 return ((READ_BIT(PWR->CSR2, PWR_CSR2_USBREGEN) == (PWR_CSR2_USBREGEN)) ? 1UL : 0UL);
809 }
810
811 /**
812 * @brief Enable the USB HS PHY regulator
813 * @rmtoll CSR2 USBHSREGEN LL_PWR_EnableUSBHSPHYReg
814 * @retval None
815 */
LL_PWR_EnableUSBHSPHYReg(void)816 __STATIC_INLINE void LL_PWR_EnableUSBHSPHYReg(void)
817 {
818 SET_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN);
819 }
820
821 /**
822 * @brief Disable USB HS PHY regulator
823 * @rmtoll CSR2 USBHSREGEN LL_PWR_DisableUSBHSPHYReg
824 * @retval None
825 */
LL_PWR_DisableUSBHSPHYReg(void)826 __STATIC_INLINE void LL_PWR_DisableUSBHSPHYReg(void)
827 {
828 CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN);
829 }
830
831 /**
832 * @brief Check if the USB HS PHY regulator is enabled
833 * @rmtoll CSR2 USBHSREGEN LL_PWR_IsEnabledUSBHSPHYReg
834 * @retval State of bit (1 or 0).
835 */
LL_PWR_IsEnabledUSBHSPHYReg(void)836 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBHSPHYReg(void)
837 {
838 return ((READ_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN) == (PWR_CSR2_USBHSREGEN)) ? 1UL : 0UL);
839 }
840
841 /**
842 * @brief Enable UCPD configuration memorization in Standby.
843 * @rmtoll UCPDR UCPD_STBY LL_PWR_EnableUCPDStandbyMode
844 * @retval None
845 * @note This function must be called just before entering Standby mode when using UCPD.
846 */
LL_PWR_EnableUCPDStandbyMode(void)847 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
848 {
849 /* Memorize UCPD configuration when entering standby mode */
850 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY);
851 }
852
853 /**
854 * @brief Disable UCPD configuration memorization in Standby.
855 * @rmtoll UCPDR UCPD_STBY LL_PWR_DisableUCPDStandbyMode
856 * @retval None
857 * @note This function must be called on exiting the Standby mode and before any UCPD
858 * configuration update.
859 */
LL_PWR_DisableUCPDStandbyMode(void)860 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
861 {
862 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY);
863 }
864
865 /**
866 * @brief Check if the UCPD configuration memorization in Standby is enabled
867 * @rmtoll UCPDR UCPD_STBY LL_PWR_IsEnabledUCPDStandbyMode
868 * @retval State of bit (1 or 0).
869 */
LL_PWR_IsEnabledUCPDStandbyMode(void)870 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
871 {
872 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY) == (PWR_UCPDR_UCPD_STBY)) ? 1UL : 0UL);
873 }
874
875 /**
876 * @brief Enable the UCPD dead battery behavior
877 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
878 * @retval None
879 */
LL_PWR_EnableUCPDDeadBattery(void)880 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
881 {
882 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
883 }
884
885 /**
886 * @brief Disable the UCPD dead battery behavior
887 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
888 * @retval None
889 */
LL_PWR_DisableUCPDDeadBattery(void)890 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
891 {
892 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
893 }
894
895 /**
896 * @brief Check if the UCPD dead battery behavior is enabled
897 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
898 * @retval State of bit (1 or 0).
899 */
LL_PWR_IsEnabledUCPDDeadBattery(void)900 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
901 {
902 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 1UL : 0UL);
903 }
904
905 /**
906 * @brief Enable the XSPI_P1 interface
907 * @rmtoll CSR2 EN_XSPIM1 LL_PWR_EnableXSPIM1
908 * @retval None
909 */
LL_PWR_EnableXSPIM1(void)910 __STATIC_INLINE void LL_PWR_EnableXSPIM1(void)
911 {
912 SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1);
913 }
914
915 /**
916 * @brief Disable the XSPI_P1 interface
917 * @rmtoll CSR2 EN_XSPIM1 LL_PWR_DisableXSPIM1
918 * @retval None
919 */
LL_PWR_DisableXSPIM1(void)920 __STATIC_INLINE void LL_PWR_DisableXSPIM1(void)
921 {
922 CLEAR_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1);
923 }
924
925 /**
926 * @brief Check if the XSPI_P1 interface is enabled
927 * @rmtoll CSR2 EN_XSPIM1 LL_PWR_IsEnabledXSPIM1
928 * @retval State of bit (1 or 0).
929 */
LL_PWR_IsEnabledXSPIM1(void)930 __STATIC_INLINE uint32_t LL_PWR_IsEnabledXSPIM1(void)
931 {
932 return ((READ_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1) == (PWR_CSR2_EN_XSPIM1)) ? 1UL : 0UL);
933 }
934
935 /**
936 * @brief Enable the XSPI_P2 interface
937 * @rmtoll CSR2 EN_XSPIM2 LL_PWR_EnableXSPIM2
938 * @retval None
939 */
LL_PWR_EnableXSPIM2(void)940 __STATIC_INLINE void LL_PWR_EnableXSPIM2(void)
941 {
942 SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2);
943 }
944
945 /**
946 * @brief Disable the XSPI_P2 interface
947 * @rmtoll CSR2 EN_XSPIM2 LL_PWR_DisableXSPIM2
948 * @retval None
949 */
LL_PWR_DisableXSPIM2(void)950 __STATIC_INLINE void LL_PWR_DisableXSPIM2(void)
951 {
952 CLEAR_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2);
953 }
954
955 /**
956 * @brief Check if the XSPI_P2 interface is enabled
957 * @rmtoll CSR2 EN_XSPIM2 LL_PWR_IsEnabledXSPIM2
958 * @retval State of bit (1 or 0).
959 */
LL_PWR_IsEnabledXSPIM2(void)960 __STATIC_INLINE uint32_t LL_PWR_IsEnabledXSPIM2(void)
961 {
962 return ((READ_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2) == (PWR_CSR2_EN_XSPIM2)) ? 1UL : 0UL);
963 }
964
965 /**
966 * @brief Set the Power Down mode when device enters deepsleep mode
967 * @rmtoll CSR3 PDDS LL_PWR_SetPowerDownModeDS
968 * @param PDMode This parameter can be one of the following values:
969 * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP
970 * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY
971 * @retval None
972 */
LL_PWR_SetPowerDownModeDS(uint32_t PDMode)973 __STATIC_INLINE void LL_PWR_SetPowerDownModeDS(uint32_t PDMode)
974 {
975 MODIFY_REG(PWR->CSR3, PWR_CSR3_PDDS, PDMode);
976 }
977
978 /**
979 * @brief Get the Power Down mode when device enters deepsleep mode
980 * @rmtoll CSR3 PDDS LL_PWR_GetPowerDownModeDS
981 * @retval Returned value can be one of the following values:
982 * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP
983 * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY
984 */
LL_PWR_GetPowerDownModeDS(void)985 __STATIC_INLINE uint32_t LL_PWR_GetPowerDownModeDS(void)
986 {
987 return (uint32_t)(READ_BIT(PWR->CSR3, PWR_CSR3_PDDS));
988 }
989
990 /**
991 * @brief Set the main internal Regulator output voltage
992 * @rmtoll CSR4 VOS LL_PWR_SetRegulVoltageScaling
993 * @param VoltageScaling This parameter can be one of the following values:
994 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
995 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
996 * @retval None
997 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)998 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
999 {
1000 MODIFY_REG(PWR->CSR4, PWR_CSR4_VOS, VoltageScaling);
1001 }
1002
1003 /**
1004 * @brief Get the main internal Regulator output voltage
1005 * @rmtoll CSR4 VOS LL_PWR_GetRegulVoltageScaling
1006 * @retval Returned value can be one of the following values:
1007 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
1008 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1009 */
LL_PWR_GetRegulVoltageScaling(void)1010 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
1011 {
1012 return (uint32_t)(READ_BIT(PWR->CSR4, PWR_CSR4_VOS));
1013 }
1014
1015 /**
1016 * @brief Set the internal Regulator output voltage in STOP mode
1017 * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling
1018 * @param VoltageScaling This parameter can be one of the following values:
1019 * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3
1020 * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5
1021 * @retval None
1022 */
LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)1023 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
1024 {
1025 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
1026 }
1027
1028 /**
1029 * @brief Get the internal Regulator output voltage in STOP mode
1030 * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling
1031 * @retval Returned value can be one of the following values:
1032 * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3
1033 * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5
1034 */
LL_PWR_GetStopModeRegulVoltageScaling(void)1035 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
1036 {
1037 return READ_BIT(PWR->CR1, PWR_CR1_SVOS);
1038 }
1039
1040 /**
1041 * @brief Enable the WakeUp PINx functionality
1042 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n
1043 * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n
1044 * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n
1045 * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin
1046 * @param WakeUpPin This parameter can be one of the following values:
1047 * @arg @ref LL_PWR_WAKEUP_PIN1
1048 * @arg @ref LL_PWR_WAKEUP_PIN2
1049 * @arg @ref LL_PWR_WAKEUP_PIN3
1050 * @arg @ref LL_PWR_WAKEUP_PIN4
1051 * @retval None
1052 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)1053 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1054 {
1055 SET_BIT(PWR->WKUPEPR, WakeUpPin);
1056 }
1057
1058 /**
1059 * @brief Disable the WakeUp PINx functionality
1060 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n
1061 * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n
1062 * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n
1063 * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin
1064 * @param WakeUpPin This parameter can be one of the following values:
1065 * @arg @ref LL_PWR_WAKEUP_PIN1
1066 * @arg @ref LL_PWR_WAKEUP_PIN2
1067 * @arg @ref LL_PWR_WAKEUP_PIN3
1068 * @arg @ref LL_PWR_WAKEUP_PIN4
1069 * @retval None
1070 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1071 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1072 {
1073 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
1074 }
1075
1076 /**
1077 * @brief Check if the WakeUp PINx functionality is enabled
1078 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n
1079 * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n
1080 * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n
1081 * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin
1082 * @param WakeUpPin This parameter can be one of the following values:
1083 * @arg @ref LL_PWR_WAKEUP_PIN1
1084 * @arg @ref LL_PWR_WAKEUP_PIN2
1085 * @arg @ref LL_PWR_WAKEUP_PIN3
1086 * @arg @ref LL_PWR_WAKEUP_PIN4
1087 * @retval State of bit (1 or 0).
1088 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1089 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1090 {
1091 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1092 }
1093
1094 /**
1095 * @brief Set the Wake-Up pin polarity low for the event detection
1096 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1097 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1098 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1099 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow
1100 * @param WakeUpPin This parameter can be one of the following values:
1101 * @arg @ref LL_PWR_WAKEUP_PIN1
1102 * @arg @ref LL_PWR_WAKEUP_PIN2
1103 * @arg @ref LL_PWR_WAKEUP_PIN3
1104 * @arg @ref LL_PWR_WAKEUP_PIN4
1105 * @retval None
1106 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1107 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1108 {
1109 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1110 }
1111
1112 /**
1113 * @brief Set the Wake-Up pin polarity high for the event detection
1114 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1115 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1116 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1117 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh
1118 * @param WakeUpPin This parameter can be one of the following values:
1119 * @arg @ref LL_PWR_WAKEUP_PIN1
1120 * @arg @ref LL_PWR_WAKEUP_PIN2
1121 * @arg @ref LL_PWR_WAKEUP_PIN3
1122 * @arg @ref LL_PWR_WAKEUP_PIN4
1123 * @retval None
1124 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1125 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1126 {
1127 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1128 }
1129
1130 /**
1131 * @brief Check if the Wake-Up pin polarity is low for event detection
1132 * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
1133 * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
1134 * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
1135 * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow
1136 * @param WakeUpPin This parameter can be one of the following values:
1137 * @arg @ref LL_PWR_WAKEUP_PIN1
1138 * @arg @ref LL_PWR_WAKEUP_PIN2
1139 * @arg @ref LL_PWR_WAKEUP_PIN3
1140 * @arg @ref LL_PWR_WAKEUP_PIN4
1141 * @retval State of bit (1 or 0).
1142 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1143 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1144 {
1145 return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
1146 }
1147
1148 /**
1149 * @brief Set the Wake-Up pin Pull None
1150 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
1151 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
1152 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
1153 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone
1154 * @param WakeUpPin This parameter can be one of the following values:
1155 * @arg @ref LL_PWR_WAKEUP_PIN1
1156 * @arg @ref LL_PWR_WAKEUP_PIN2
1157 * @arg @ref LL_PWR_WAKEUP_PIN3
1158 * @arg @ref LL_PWR_WAKEUP_PIN4
1159 * @retval None
1160 */
LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)1161 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
1162 {
1163 MODIFY_REG(PWR->WKUPEPR, \
1164 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1165 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1166 }
1167
1168 /**
1169 * @brief Set the Wake-Up pin Pull Up
1170 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
1171 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
1172 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
1173 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp
1174 * @param WakeUpPin This parameter can be one of the following values:
1175 * @arg @ref LL_PWR_WAKEUP_PIN1
1176 * @arg @ref LL_PWR_WAKEUP_PIN2
1177 * @arg @ref LL_PWR_WAKEUP_PIN3
1178 * @arg @ref LL_PWR_WAKEUP_PIN4
1179 * @retval None
1180 */
LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)1181 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
1182 {
1183 MODIFY_REG(PWR->WKUPEPR, \
1184 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1185 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1186 }
1187
1188 /**
1189 * @brief Set the Wake-Up pin Pull Down
1190 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
1191 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
1192 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
1193 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown
1194 * @param WakeUpPin This parameter can be one of the following values:
1195 * @arg @ref LL_PWR_WAKEUP_PIN1
1196 * @arg @ref LL_PWR_WAKEUP_PIN2
1197 * @arg @ref LL_PWR_WAKEUP_PIN3
1198 * @arg @ref LL_PWR_WAKEUP_PIN4
1199 * @retval None
1200 */
LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)1201 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
1202 {
1203 MODIFY_REG(PWR->WKUPEPR, \
1204 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1205 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1206 }
1207
1208 /**
1209 * @brief Get the Wake-Up pin pull
1210 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n
1211 * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n
1212 * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n
1213 * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\
1214 * @param WakeUpPin This parameter can be one of the following values:
1215 * @arg @ref LL_PWR_WAKEUP_PIN1
1216 * @arg @ref LL_PWR_WAKEUP_PIN2
1217 * @arg @ref LL_PWR_WAKEUP_PIN3
1218 * @arg @ref LL_PWR_WAKEUP_PIN4
1219 * @retval Returned value can be one of the following values:
1220 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
1221 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
1222 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
1223 */
LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)1224 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
1225 {
1226 uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1227
1228 return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
1229 }
1230
1231 /**
1232 * @brief Enable the pull-up on I3C1_SCL (PB6)) in standby mode
1233 * @rmtoll APCR I3CPB6_PU LL_PWR_EnableI3CPB6PU
1234 * @retval None
1235 */
LL_PWR_EnableI3CPB6PU(void)1236 __STATIC_INLINE void LL_PWR_EnableI3CPB6PU(void)
1237 {
1238 SET_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU);
1239 }
1240
1241 /**
1242 * @brief Disable the pull-up on I3C1_SCL (PB6) in standby mode
1243 * @rmtoll APCR I3CPB6_PU LL_PWR_DisableI3CPB6PU
1244 * @retval None
1245 */
LL_PWR_DisableI3CPB6PU(void)1246 __STATIC_INLINE void LL_PWR_DisableI3CPB6PU(void)
1247 {
1248 CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU);
1249 }
1250
1251 /**
1252 * @brief Check if the pull-up on I3C1_SCL (PB6) in standby mode is enabled
1253 * @rmtoll APCR I3CPB6_PU LL_PWR_IsEnabledI3CPB6PU
1254 * @retval State of bit (1 or 0).
1255 */
LL_PWR_IsEnabledI3CPB6PU(void)1256 __STATIC_INLINE uint32_t LL_PWR_IsEnabledI3CPB6PU(void)
1257 {
1258 return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU) == (PWR_APCR_I3CPB6_PU)) ? 1UL : 0UL);
1259 }
1260
1261 /**
1262 * @brief Enable the pull-up on I3C1_SDA (PB7) in standby mode
1263 * @rmtoll APCR I3CPB7_PU LL_PWR_EnableI3CPB7PU
1264 * @retval None
1265 */
LL_PWR_EnableI3CPB7PU(void)1266 __STATIC_INLINE void LL_PWR_EnableI3CPB7PU(void)
1267 {
1268 SET_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU);
1269 }
1270
1271 /**
1272 * @brief Disable the pull-up on I3C1_SDA (PB7) in standby mode
1273 * @rmtoll APCR I3CPB7_PU LL_PWR_DisableI3CPB7PU
1274 * @retval None
1275 */
LL_PWR_DisableI3CPB7PU(void)1276 __STATIC_INLINE void LL_PWR_DisableI3CPB7PU(void)
1277 {
1278 CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU);
1279 }
1280
1281 /**
1282 * @brief Check if the pull-up on I3C1_SDA (PB7) in standby mode is enabled
1283 * @rmtoll APCR I3CPB7_PU LL_PWR_IsEnabledI3CPB7PU
1284 * @retval State of bit (1 or 0).
1285 */
LL_PWR_IsEnabledI3CPB7PU(void)1286 __STATIC_INLINE uint32_t LL_PWR_IsEnabledI3CPB7PU(void)
1287 {
1288 return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU) == (PWR_APCR_I3CPB7_PU)) ? 1UL : 0UL);
1289 }
1290
1291 /**
1292 * @brief Enable the pull-up on I3C1_SCL (PB8) in standby mode
1293 * @rmtoll APCR I3CPB8_PU LL_PWR_EnableI3CPB8PU
1294 * @retval None
1295 */
LL_PWR_EnableI3CPB8PU(void)1296 __STATIC_INLINE void LL_PWR_EnableI3CPB8PU(void)
1297 {
1298 SET_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU);
1299 }
1300
1301 /**
1302 * @brief Disable the pull-up on I3C1_SCL (PB8) in standby mode
1303 * @rmtoll APCR I3CPB8_PU LL_PWR_DisableI3CPB8PU
1304 * @retval None
1305 */
LL_PWR_DisableI3CPB8PU(void)1306 __STATIC_INLINE void LL_PWR_DisableI3CPB8PU(void)
1307 {
1308 CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU);
1309 }
1310
1311 /**
1312 * @brief Check if the pull-up on I3C1_SCL (PB8) in standby mode is enabled
1313 * @rmtoll APCR I3CPB8_PU LL_PWR_IsEnabledI3CPB8PU
1314 * @retval State of bit (1 or 0).
1315 */
LL_PWR_IsEnabledI3CPB8PU(void)1316 __STATIC_INLINE uint32_t LL_PWR_IsEnabledI3CPB8PU(void)
1317 {
1318 return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU) == (PWR_APCR_I3CPB8_PU)) ? 1UL : 0UL);
1319 }
1320
1321 /**
1322 * @brief Enable the pull-up on I3C1_SDA (PB9) in standby mode
1323 * @rmtoll APCR I3CPB9_PU LL_PWR_EnableI3CPB9PU
1324 * @retval None
1325 */
LL_PWR_EnableI3CPB9PU(void)1326 __STATIC_INLINE void LL_PWR_EnableI3CPB9PU(void)
1327 {
1328 SET_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU);
1329 }
1330
1331 /**
1332 * @brief Disable the pull-up on I3C1_SDA (PB9) in standby mode
1333 * @rmtoll APCR I3CPB9_PU LL_PWR_DisableI3CPB9PU
1334 * @retval None
1335 */
LL_PWR_DisableI3CPB9PU(void)1336 __STATIC_INLINE void LL_PWR_DisableI3CPB9PU(void)
1337 {
1338 CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU);
1339 }
1340
1341 /**
1342 * @brief Check if the pull-up on I3C1_SDA (PB9) in standby mode is enabled
1343 * @rmtoll APCR I3CPB9_PU LL_PWR_IsEnabledI3CPB9PU
1344 * @retval State of bit (1 or 0).
1345 */
LL_PWR_IsEnabledI3CPB9PU(void)1346 __STATIC_INLINE uint32_t LL_PWR_IsEnabledI3CPB9PU(void)
1347 {
1348 return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU) == (PWR_APCR_I3CPB9_PU)) ? 1UL : 0UL);
1349 }
1350
1351 /**
1352 * @brief Enable the pull-up and pull-down configuration
1353 * @rmtoll APCR APC LL_PWR_EnablePUPDConfig
1354 * @retval None
1355 */
LL_PWR_EnablePUPDConfig(void)1356 __STATIC_INLINE void LL_PWR_EnablePUPDConfig(void)
1357 {
1358 SET_BIT(PWR->APCR, PWR_APCR_APC);
1359 }
1360
1361 /**
1362 * @brief Disable the pull-up and pull-down configuration
1363 * @rmtoll APCR APC LL_PWR_DisablePUPDConfig
1364 * @retval None
1365 */
LL_PWR_DisablePUPDConfig(void)1366 __STATIC_INLINE void LL_PWR_DisablePUPDConfig(void)
1367 {
1368 CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
1369 }
1370
1371 /**
1372 * @brief Check if the pull-up and pull-down configuration is enabled.
1373 * @rmtoll APCR APC LL_PWR_IsEnabledPUPDConfig
1374 * @retval State of bit (1 or 0).
1375 */
LL_PWR_IsEnabledPUPDConfig(void)1376 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void)
1377 {
1378 return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL);
1379 }
1380
1381 /**
1382 * @brief Enable GPIO N pull-up in Standby mode
1383 * @rmtoll PUCRN PUx LL_PWR_EnableGPIONPullUp
1384 * @param GPIOPin This parameter can be a combination of the following values:
1385 * @arg @ref LL_PWR_GPIO_PIN_1
1386 * @arg @ref LL_PWR_GPIO_PIN_6
1387 * @arg @ref LL_PWR_GPIO_PIN_12
1388 * @retval None.
1389 */
LL_PWR_EnableGPIONPullUp(uint32_t GPIOPin)1390 __STATIC_INLINE void LL_PWR_EnableGPIONPullUp(uint32_t GPIOPin)
1391 {
1392 SET_BIT(PWR->PUCRN, GPIOPin);
1393 }
1394
1395 /**
1396 * @brief Disable GPIO N pull-up in Standby mode
1397 * @rmtoll PUCRN PUx LL_PWR_DisableGPIONPullUp
1398 * @param GPIOPin This parameter can be a combination of the following values:
1399 * @arg @ref LL_PWR_GPIO_PIN_1
1400 * @arg @ref LL_PWR_GPIO_PIN_6
1401 * @arg @ref LL_PWR_GPIO_PIN_12
1402 * @retval None.
1403 */
LL_PWR_DisableGPIONPullUp(uint32_t GPIOPin)1404 __STATIC_INLINE void LL_PWR_DisableGPIONPullUp(uint32_t GPIOPin)
1405 {
1406 CLEAR_BIT(PWR->PUCRN, GPIOPin);
1407 }
1408
1409 /**
1410 * @brief Check if GPIO pull-up in Standby mode is enabled
1411 * @rmtoll PUCRN PUx LL_PWR_IsEnabledGPIONPullUp
1412 * @param GPIOPin This parameter can be one of the following values:
1413 * @arg @ref LL_PWR_GPIO_PIN_1
1414 * @arg @ref LL_PWR_GPIO_PIN_6
1415 * @arg @ref LL_PWR_GPIO_PIN_12
1416 * @retval State of bit (1 or 0).
1417 */
LL_PWR_IsEnabledGPIONPullUp(uint32_t GPIOPin)1418 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIONPullUp(uint32_t GPIOPin)
1419 {
1420 return ((READ_BIT(PWR->PUCRN, GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1421 }
1422
1423 /**
1424 * @brief Enable GPIO O pull-up in Standby mode
1425 * @rmtoll PUCRO PUx LL_PWR_EnableGPIOOPullUp
1426 * @param GPIOPin This parameter can be a combination of the following values:
1427 * @arg @ref LL_PWR_GPIO_PIN_0
1428 * @arg @ref LL_PWR_GPIO_PIN_1
1429 * @arg @ref LL_PWR_GPIO_PIN_4
1430
1431 * @retval None.
1432 */
LL_PWR_EnableGPIOOPullUp(uint32_t GPIOPin)1433 __STATIC_INLINE void LL_PWR_EnableGPIOOPullUp(uint32_t GPIOPin)
1434 {
1435 SET_BIT(PWR->PUCRO, GPIOPin);
1436 }
1437
1438 /**
1439 * @brief Disable GPIO O pull-up in Standby mode
1440 * @rmtoll PUCRO PUx LL_PWR_DisableGPIOOPullUp
1441 * @param GPIOPin This parameter can be a combination of the following values:
1442 * @arg @ref LL_PWR_GPIO_PIN_0
1443 * @arg @ref LL_PWR_GPIO_PIN_1
1444 * @arg @ref LL_PWR_GPIO_PIN_4
1445 * @retval None.
1446 */
LL_PWR_DisableGPIOOPullUp(uint32_t GPIOPin)1447 __STATIC_INLINE void LL_PWR_DisableGPIOOPullUp(uint32_t GPIOPin)
1448 {
1449 CLEAR_BIT(PWR->PUCRO, GPIOPin);
1450 }
1451
1452 /**
1453 * @brief Check if GPIO O pull-up in Standby mode is enabled
1454 * @rmtoll PUCRO PUx LL_PWR_IsEnabledGPIOOPullUp
1455 * @param GPIOPin This parameter can be one of the following values:
1456 * @arg @ref LL_PWR_GPIO_PIN_0
1457 * @arg @ref LL_PWR_GPIO_PIN_1
1458 * @arg @ref LL_PWR_GPIO_PIN_4
1459 * @retval State of bit (1 or 0).
1460 */
LL_PWR_IsEnabledGPIOOPullUp(uint32_t GPIOPin)1461 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOOPullUp(uint32_t GPIOPin)
1462 {
1463 return ((READ_BIT(PWR->PUCRO, GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1464 }
1465
1466 /**
1467 * @brief Enable GPIO N pull-down in Standby mode
1468 * @rmtoll PDCRN PDx LL_PWR_EnableGPIONPullDown
1469 * @param GPIOPin This parameter can be a combination of the following values:
1470 * @arg @ref LL_PWR_GPIO_PIN_0
1471 * @arg @ref LL_PWR_GPIO_PIN_1
1472 * @arg @ref LL_PWR_GPIO_PIN_2
1473 * @arg @ref LL_PWR_GPIO_PIN_6
1474 * @arg @ref LL_PWR_GPIO_PIN_8
1475 * @arg @ref LL_PWR_GPIO_PIN_12
1476 * @retval None.
1477 */
LL_PWR_EnableGPIONPullDown(uint32_t GPIOPin)1478 __STATIC_INLINE void LL_PWR_EnableGPIONPullDown(uint32_t GPIOPin)
1479 {
1480 SET_BIT(PWR->PDCRN, GPIOPin);
1481 }
1482
1483 /**
1484 * @brief Disable GPIO N pull-down in Standby mode
1485 * @rmtoll PDCRN PDx LL_PWR_DisableGPIONPullDown
1486 * @param GPIOPin This parameter can be a combination of the following values:
1487 * @arg @ref LL_PWR_GPIO_PIN_0
1488 * @arg @ref LL_PWR_GPIO_PIN_1
1489 * @arg @ref LL_PWR_GPIO_PIN_2
1490 * @arg @ref LL_PWR_GPIO_PIN_6
1491 * @arg @ref LL_PWR_GPIO_PIN_8
1492 * @arg @ref LL_PWR_GPIO_PIN_12
1493 * @retval None.
1494 */
LL_PWR_DisableGPIONPullDown(uint32_t GPIOPin)1495 __STATIC_INLINE void LL_PWR_DisableGPIONPullDown(uint32_t GPIOPin)
1496 {
1497 CLEAR_BIT(PWR->PDCRN, GPIOPin);
1498 }
1499
1500 /**
1501 * @brief Check if GPIO N pull-down in Standby mode is enabled
1502 * @rmtoll PDCRN PDx LL_PWR_IsEnabledGPIONPullDown
1503 * @param GPIOPin This parameter can be one of the following values:
1504 * @arg @ref LL_PWR_GPIO_PIN_0
1505 * @arg @ref LL_PWR_GPIO_PIN_1
1506 * @arg @ref LL_PWR_GPIO_PIN_2
1507 * @arg @ref LL_PWR_GPIO_PIN_6
1508 * @arg @ref LL_PWR_GPIO_PIN_8
1509 * @arg @ref LL_PWR_GPIO_PIN_12
1510 * @retval State of bit (1 or 0).
1511 */
LL_PWR_IsEnabledGPIONPullDown(uint32_t GPIOPin)1512 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIONPullDown(uint32_t GPIOPin)
1513 {
1514 return ((READ_BIT(PWR->PDCRN, GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1515 }
1516 /**
1517 * @brief Enable GPIO O pull-down in Standby mode
1518 * @rmtoll PDCRO PDx LL_PWR_EnableGPIOOPullDown
1519 * @param GPIOPin This parameter can be a combination of the following values:
1520 * @arg @ref LL_PWR_GPIO_PIN_0
1521 * @arg @ref LL_PWR_GPIO_PIN_1
1522 * @arg @ref LL_PWR_GPIO_PIN_2
1523 * @arg @ref LL_PWR_GPIO_PIN_3
1524 * @arg @ref LL_PWR_GPIO_PIN_4
1525 * @retval None.
1526 */
LL_PWR_EnableGPIOOPullDown(uint32_t GPIOPin)1527 __STATIC_INLINE void LL_PWR_EnableGPIOOPullDown(uint32_t GPIOPin)
1528 {
1529 SET_BIT(PWR->PDCRO, GPIOPin);
1530 }
1531
1532 /**
1533 * @brief Disable GPIO O pull-down in Standby mode
1534 * @rmtoll PDCRO PDx LL_PWR_DisableGPIOOPullDown
1535 * @param GPIOPin This parameter can be a combination of the following values:
1536 * @arg @ref LL_PWR_GPIO_PIN_0
1537 * @arg @ref LL_PWR_GPIO_PIN_1
1538 * @arg @ref LL_PWR_GPIO_PIN_2
1539 * @arg @ref LL_PWR_GPIO_PIN_3
1540 * @arg @ref LL_PWR_GPIO_PIN_4
1541 * @retval None.
1542 */
LL_PWR_DisableGPIOOPullDown(uint32_t GPIOPin)1543 __STATIC_INLINE void LL_PWR_DisableGPIOOPullDown(uint32_t GPIOPin)
1544 {
1545 CLEAR_BIT(PWR->PDCRO, GPIOPin);
1546 }
1547
1548 /**
1549 * @brief Check if GPIO O pull-down in Standby mode is enabled
1550 * @rmtoll PDCRO PDx LL_PWR_IsEnabledGPIOOPullDown
1551 * @param GPIOPin This parameter can be one of the following values:
1552 * @arg @ref LL_PWR_GPIO_PIN_0
1553 * @arg @ref LL_PWR_GPIO_PIN_1
1554 * @arg @ref LL_PWR_GPIO_PIN_2
1555 * @arg @ref LL_PWR_GPIO_PIN_3
1556 * @arg @ref LL_PWR_GPIO_PIN_4
1557 * @retval State of bit (1 or 0).
1558 */
LL_PWR_IsEnabledGPIOOPullDown(uint32_t GPIOPin)1559 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOOPullDown(uint32_t GPIOPin)
1560 {
1561 return ((READ_BIT(PWR->PDCRO, GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1562 }
1563
1564 /**
1565 * @brief Enable GPIO P pull-down in Standby mode
1566 * @rmtoll PDCRP PDx LL_PWR_EnableGPIOPPullDown
1567 * @param GPIOPin This parameter can be a combination of the following values:
1568 * @arg @ref LL_PWR_GPIO_PIN_0
1569 * @arg @ref LL_PWR_GPIO_PIN_4
1570 * @arg @ref LL_PWR_GPIO_PIN_8
1571 * @arg @ref LL_PWR_GPIO_PIN_12
1572 * @retval None.
1573 */
LL_PWR_EnableGPIOPPullDown(uint32_t GPIOPin)1574 __STATIC_INLINE void LL_PWR_EnableGPIOPPullDown(uint32_t GPIOPin)
1575 {
1576 SET_BIT(PWR->PDCRP, GPIOPin);
1577 }
1578
1579 /**
1580 * @brief Disable GPIO P pull-down in Standby mode
1581 * @rmtoll PDCRP PDx LL_PWR_DisableGPIOPPullDown
1582 * @param GPIOPin This parameter can be a combination of the following values:
1583 * @arg @ref LL_PWR_GPIO_PIN_0
1584 * @arg @ref LL_PWR_GPIO_PIN_4
1585 * @arg @ref LL_PWR_GPIO_PIN_8
1586 * @arg @ref LL_PWR_GPIO_PIN_12
1587 * @retval None.
1588 */
LL_PWR_DisableGPIOPPullDown(uint32_t GPIOPin)1589 __STATIC_INLINE void LL_PWR_DisableGPIOPPullDown(uint32_t GPIOPin)
1590 {
1591 CLEAR_BIT(PWR->PDCRP, GPIOPin);
1592 }
1593
1594 /**
1595 * @brief Check if GPIO P pull-down in Standby mode is enabled
1596 * @rmtoll PDCRP PDx LL_PWR_IsEnabledGPIOPPullDown
1597 * @param GPIOPin This parameter can be one of the following values:
1598 * @arg @ref LL_PWR_GPIO_PIN_0
1599 * @arg @ref LL_PWR_GPIO_PIN_4
1600 * @arg @ref LL_PWR_GPIO_PIN_8
1601 * @arg @ref LL_PWR_GPIO_PIN_12
1602 * @retval State of bit (1 or 0).
1603 */
LL_PWR_IsEnabledGPIOPPullDown(uint32_t GPIOPin)1604 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPPullDown(uint32_t GPIOPin)
1605 {
1606 return ((READ_BIT(PWR->PDCRP, GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1607 }
1608 /**
1609 * @}
1610 */
1611
1612
1613 /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
1614 * @{
1615 */
1616
1617 /**
1618 * @brief Indicate whether the voltage level is ready for current actual used VOS
1619 * @rmtoll SR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOSRDY
1620 * @retval State of bit (1 or 0).
1621 */
LL_PWR_IsActiveFlag_ACTVOSRDY(void)1622 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOSRDY(void)
1623 {
1624 return ((READ_BIT(PWR->SR1, PWR_SR1_ACTVOSRDY) == (PWR_SR1_ACTVOSRDY)) ? 1UL : 0UL);
1625 }
1626
1627 /**
1628 * @brief Indicate whether VDD voltage is below the selected PVD threshold
1629 * @rmtoll SR1 PVDO LL_PWR_IsActiveFlag_PVDO
1630 * @retval State of bit (1 or 0).
1631 */
LL_PWR_IsActiveFlag_PVDO(void)1632 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1633 {
1634 return ((READ_BIT(PWR->SR1, PWR_SR1_PVDO) == (PWR_SR1_PVDO)) ? 1UL : 0UL);
1635 }
1636
1637 /**
1638 * @brief Indicate whether VDDA voltage is below the selected AVD threshold
1639 * @rmtoll SR1 AVDO LL_PWR_IsActiveFlag_AVDO
1640 * @retval State of bit (1 or 0).
1641 */
LL_PWR_IsActiveFlag_AVDO(void)1642 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
1643 {
1644 return ((READ_BIT(PWR->SR1, PWR_SR1_AVDO) == (PWR_SR1_AVDO)) ? 1UL : 0UL);
1645 }
1646
1647 /**
1648 * @brief Get Backup Regulator ready Flag
1649 * @rmtoll CSR1 BRRDY LL_PWR_IsActiveFlag_BRRDY
1650 * @retval State of bit (1 or 0).
1651 */
LL_PWR_IsActiveFlag_BRRDY(void)1652 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRRDY(void)
1653 {
1654 return ((READ_BIT(PWR->CSR1, PWR_CSR1_BRRDY) == (PWR_CSR1_BRRDY)) ? 1UL : 0UL);
1655 }
1656
1657 /**
1658 * @brief Indicate whether the VBAT level is above or below low threshold
1659 * @rmtoll CSR1 VBATL LL_PWR_IsActiveFlag_VBATL
1660 * @retval State of bit (1 or 0).
1661 */
LL_PWR_IsActiveFlag_VBATL(void)1662 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
1663 {
1664 return ((READ_BIT(PWR->CSR1, PWR_CSR1_VBATL) == (PWR_CSR1_VBATL)) ? 1UL : 0UL);
1665 }
1666
1667 /**
1668 * @brief Indicate whether the VBAT level is above or below high threshold
1669 * @rmtoll CSR1 VBATH LL_PWR_IsActiveFlag_VBATH
1670 * @retval State of bit (1 or 0).
1671 */
LL_PWR_IsActiveFlag_VBATH(void)1672 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
1673 {
1674 return ((READ_BIT(PWR->CSR1, PWR_CSR1_VBATH) == (PWR_CSR1_VBATH)) ? 1UL : 0UL);
1675 }
1676
1677 /**
1678 * @brief Indicate whether the CPU temperature level is above or below low threshold
1679 * @rmtoll CSR1 TEMPL LL_PWR_IsActiveFlag_TEMPL
1680 * @retval State of bit (1 or 0).
1681 */
LL_PWR_IsActiveFlag_TEMPL(void)1682 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
1683 {
1684 return ((READ_BIT(PWR->CSR1, PWR_CSR1_TEMPL) == (PWR_CSR1_TEMPL)) ? 1UL : 0UL);
1685 }
1686
1687 /**
1688 * @brief Indicate whether the CPU temperature level is above or below high threshold
1689 * @rmtoll CSR1 TEMPH LL_PWR_IsActiveFlag_TEMPH
1690 * @retval State of bit (1 or 0).
1691 */
LL_PWR_IsActiveFlag_TEMPH(void)1692 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
1693 {
1694 return ((READ_BIT(PWR->CSR1, PWR_CSR1_TEMPH) == (PWR_CSR1_TEMPH)) ? 1UL : 0UL);
1695 }
1696
1697 /**
1698 * @brief Indicate whether the SMPS external supply is ready or not
1699 * @rmtoll CSR2 SDEXTRDY LL_PWR_IsActiveFlag_SDEXTRDY
1700 * @retval State of bit (1 or 0).
1701 */
LL_PWR_IsActiveFlag_SDEXTRDY(void)1702 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SDEXTRDY(void)
1703 {
1704 return ((READ_BIT(PWR->CSR2, PWR_CSR2_SDEXTRDY) == (PWR_CSR2_SDEXTRDY)) ? 1UL : 0UL);
1705 }
1706
1707 /**
1708 * @brief Indicate whether the USB supply is ready or not
1709 * @rmtoll CSR2 USB33RDY LL_PWR_IsActiveFlag_USB33RDY
1710 * @retval State of bit (1 or 0).
1711 */
LL_PWR_IsActiveFlag_USB33RDY(void)1712 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB33RDY(void)
1713 {
1714 return ((READ_BIT(PWR->CSR2, PWR_CSR2_USB33RDY) == (PWR_CSR2_USB33RDY)) ? 1UL : 0UL);
1715 }
1716
1717 /**
1718 * @brief Get System Stop Flag
1719 * @rmtoll CSR3 STOPF LL_PWR_IsActiveFlag_STOP
1720 * @retval State of bit (1 or 0).
1721 */
LL_PWR_IsActiveFlag_STOP(void)1722 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
1723 {
1724 return ((READ_BIT(PWR->CSR3, PWR_CSR3_STOPF) == (PWR_CSR3_STOPF)) ? 1UL : 0UL);
1725 }
1726
1727 /**
1728 * @brief Get System Standby Flag
1729 * @rmtoll CSR3 SBF LL_PWR_IsActiveFlag_SB
1730 * @retval State of bit (1 or 0).
1731 */
LL_PWR_IsActiveFlag_SB(void)1732 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1733 {
1734 return ((READ_BIT(PWR->CSR3, PWR_CSR3_SBF) == (PWR_CSR3_SBF)) ? 1UL : 0UL);
1735 }
1736
1737 /**
1738 * @brief Indicate whether the Regulator is ready in the selected voltage range
1739 * or if its output voltage is still changing to the required voltage level
1740 * @rmtoll CSR4 VOSRDY LL_PWR_IsActiveFlag_VOSRDY
1741 * @retval State of bit (1 or 0).
1742 */
LL_PWR_IsActiveFlag_VOSRDY(void)1743 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSRDY(void)
1744 {
1745 return ((READ_BIT(PWR->CSR4, PWR_CSR4_VOSRDY) == (PWR_CSR4_VOSRDY)) ? 1UL : 0UL);
1746 }
1747
1748 /**
1749 * @brief Get Wake-up Flag 1
1750 * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1
1751 * @retval State of bit (1 or 0).
1752 */
LL_PWR_IsActiveFlag_WU1(void)1753 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1754 {
1755 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
1756 }
1757
1758 /**
1759 * @brief Get Wake-up Flag 2
1760 * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2
1761 * @retval State of bit (1 or 0).
1762 */
LL_PWR_IsActiveFlag_WU2(void)1763 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1764 {
1765 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
1766 }
1767
1768 /**
1769 * @brief Get Wake-up Flag 3
1770 * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
1771 * @retval State of bit (1 or 0).
1772 */
LL_PWR_IsActiveFlag_WU3(void)1773 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1774 {
1775 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
1776 }
1777
1778 /**
1779 * @brief Get Wake-up Flag 4
1780 * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4
1781 * @retval State of bit (1 or 0).
1782 */
LL_PWR_IsActiveFlag_WU4(void)1783 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1784 {
1785 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
1786 }
1787
1788 /**
1789 * @brief Clear STOP and STANDBY and flags
1790 * @rmtoll CSR3 CSSF LL_PWR_ClearFlag_STOP_SB
1791 * @retval None
1792 */
LL_PWR_ClearFlag_STOP_SB(void)1793 __STATIC_INLINE void LL_PWR_ClearFlag_STOP_SB(void)
1794 {
1795 SET_BIT(PWR->CSR3, PWR_CSR3_CSSF);
1796 }
1797
1798 /**
1799 * @brief Clear Wake-up Flag 1
1800 * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1
1801 * @retval None
1802 */
LL_PWR_ClearFlag_WU1(void)1803 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1804 {
1805 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
1806 }
1807
1808 /**
1809 * @brief Clear Wake-up Flag 2
1810 * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2
1811 * @retval None
1812 */
LL_PWR_ClearFlag_WU2(void)1813 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1814 {
1815 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
1816 }
1817
1818 /**
1819 * @brief Clear Wake-up Flag 3
1820 * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
1821 * @retval None
1822 */
LL_PWR_ClearFlag_WU3(void)1823 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1824 {
1825 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
1826 }
1827
1828 /**
1829 * @brief Clear Wake-up Flag 4
1830 * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4
1831 * @retval None
1832 */
LL_PWR_ClearFlag_WU4(void)1833 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1834 {
1835 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
1836 }
1837
1838 /**
1839 * @brief Clear all wake up flags.
1840 * @rmtoll WUSCR WKUPC LL_PWR_ClearFlag_WU
1841 * @retval None
1842 */
LL_PWR_ClearFlag_WU(void)1843 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1844 {
1845 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC);
1846 }
1847
1848 /**
1849 * @}
1850 */
1851
1852 #if defined (USE_FULL_LL_DRIVER)
1853 /** @defgroup PWR_LL_EF_Init De-initialization function
1854 * @{
1855 */
1856 ErrorStatus LL_PWR_DeInit(void);
1857 /**
1858 * @}
1859 */
1860 #endif /* defined (USE_FULL_LL_DRIVER) */
1861
1862
1863 /**
1864 * @}
1865 */
1866
1867 /**
1868 * @}
1869 */
1870
1871 /**
1872 * @}
1873 */
1874
1875 #endif /* defined (PWR) */
1876
1877 /**
1878 * @}
1879 */
1880
1881 #ifdef __cplusplus
1882 }
1883 #endif
1884
1885 #endif /* STM32H7RSxx_LL_PWR_H */
1886
