1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WB0x_LL_PWR_H
21 #define STM32WB0x_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wb0x.h"
29
30 /** @addtogroup STM32WB0x_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46
47 /* Exported types ------------------------------------------------------------*/
48 /* Exported constants --------------------------------------------------------*/
49 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
50 * @{
51 */
52
53 /** @defgroup PWR_LL_EC_MODE_PWR PWR Mode
54 * @{
55 */
56 #define LL_PWR_MODE_DEEPSTOP (0x000000000U)
57 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS)
58 /**
59 * @}
60 */
61
62 /** @defgroup PWR_LL_EC_RAMRET RAM Retention enable
63 * @{
64 */
65 #define LL_PWR_RAMRET_1 PWR_CR2_RAMRET1
66 #if defined(PWR_CR2_RAMRET2)
67 #define LL_PWR_RAMRET_2 PWR_CR2_RAMRET2
68 #endif /* PWR_CR2_RAMRET2 */
69 #if defined(PWR_CR2_RAMRET3)
70 #define LL_PWR_RAMRET_3 PWR_CR2_RAMRET3
71 #endif /* PWR_CR2_RAMRET3 */
72 /**
73 * @}
74 */
75
76 /** @defgroup PWR_LL_EC_PVDLEVEL PVD Level
77 * @{
78 */
79 #define LL_PWR_PVDLEVEL_0 (0x00000000U) /*!< VPVD0 around 2.0 V */
80 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PVDLS_0) /*!< VPVD1 around 2.2 V */
81 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PVDLS_1) /*!< VPVD2 around 2.4 V */
82 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PVDLS_1 | PWR_CR2_PVDLS_0) /*!< VPVD3 around 2.5 V */
83 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PVDLS_2) /*!< VPVD4 around 2.6 V */
84 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PVDLS_2 | PWR_CR2_PVDLS_0) /*!< VPVD5 around 2.8 V */
85 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PVDLS_2 | PWR_CR2_PVDLS_1) /*!< VPVD6 around 2.9 V */
86 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PVDLS) /*!< External input analog voltage (Compare internally to VBGP) */
87
88
89 /**
90 * @}
91 */
92
93 /** @defgroup PWR_LL_EW_SOURCE_PORT IO Port for wakeup source
94 * @{
95 */
96 #define LL_PWR_EWS_PORTA (0x00000000U) /*!< IO port A to get out from DEEPSTOP mode */
97 #define LL_PWR_EWS_PORTB (0x00000001U) /*!< IO port B to get out from DEEPSTOP mode */
98 /**
99 * @}
100 */
101
102 /** @defgroup PWR_LL_EW_WAKEUP_SOURCE Wakeup Source
103 * @{
104 */
105 #if !defined(PWR_CR6_EWU20)
106 #define LL_PWR_WAKEUP_CR6_ALL (0x000000FFU << 16) /*!< Enable all the wakeup source in CR6 */
107 #define LL_PWR_WAKEUP_CR3_ALL (0x0000FFFFU) /*!< Enable all the wakeup source in CR3 */
108 #define LL_PWR_WAKEUP_ALL LL_PWR_WAKEUP_CR6_ALL | LL_PWR_WAKEUP_CR3_ALL
109 #define LL_PWR_WAKEUP_RTC PWR_CR3_EIWL /*!< Enable wakeup on Internal event (RTC) */
110 #define LL_PWR_WAKEUP_LPUART PWR_CR3_EIWL2 /*!< Enable wakeup on Internal event 2 (LPUART) */
111 #define LL_PWR_WAKEUP_BLEHOST PWR_CR3_EWBLEHCPU /*!< Enable wakeup on BLE Host CPU event */
112 #define LL_PWR_WAKEUP_BLE PWR_CR3_EWBLE /*!< Enable wakeup on BLE event */
113 #define LL_PWR_WAKEUP_PA11 PWR_CR3_EWU11 /*!< Enable wakeup on PA11 I/O event */
114 #define LL_PWR_WAKEUP_PA10 PWR_CR3_EWU10 /*!< Enable wakeup on PA10 I/O event */
115 #define LL_PWR_WAKEUP_PA9 PWR_CR3_EWU9 /*!< Enable wakeup on PA9 I/O event */
116 #define LL_PWR_WAKEUP_PA8 PWR_CR3_EWU8 /*!< Enable wakeup on PA8 I/O event */
117 #define LL_PWR_WAKEUP_PA3 (PWR_CR6_EWU15 << 16) /*!< Enable wakeup on PA3 I/O event */
118 #define LL_PWR_WAKEUP_PA2 (PWR_CR6_EWU14 << 16) /*!< Enable wakeup on PA2 I/O event */
119 #define LL_PWR_WAKEUP_PA1 (PWR_CR6_EWU13 << 16) /*!< Enable wakeup on PA1 I/O event */
120 #define LL_PWR_WAKEUP_PA0 (PWR_CR6_EWU12 << 16) /*!< Enable wakeup on PA0 I/O event */
121 #define LL_PWR_WAKEUP_PB7 PWR_CR3_EWU7 /*!< Enable wakeup on PB7 I/O event */
122 #define LL_PWR_WAKEUP_PB6 PWR_CR3_EWU6 /*!< Enable wakeup on PB6 I/O event */
123 #define LL_PWR_WAKEUP_PB5 PWR_CR3_EWU5 /*!< Enable wakeup on PB5 I/O event */
124 #define LL_PWR_WAKEUP_PB4 PWR_CR3_EWU4 /*!< Enable wakeup on PB4 I/O event */
125 #define LL_PWR_WAKEUP_PB3 PWR_CR3_EWU3 /*!< Enable wakeup on PB3 I/O event */
126 #define LL_PWR_WAKEUP_PB2 PWR_CR3_EWU2 /*!< Enable wakeup on PB2 I/O event */
127 #define LL_PWR_WAKEUP_PB1 PWR_CR3_EWU1 /*!< Enable wakeup on PB1 I/O event */
128 #define LL_PWR_WAKEUP_PB0 PWR_CR3_EWU0 /*!< Enable wakeup on PB0 I/O event */
129 #define LL_PWR_WAKEUP_PB15 (PWR_CR6_EWU19 << 16) /*!< Enable wakeup on PB15 I/O event */
130 #define LL_PWR_WAKEUP_PB14 (PWR_CR6_EWU18 << 16) /*!< Enable wakeup on PB14 I/O event */
131 #define LL_PWR_WAKEUP_PB13 (PWR_CR6_EWU17 << 16) /*!< Enable wakeup on PB13 I/O event */
132 #define LL_PWR_WAKEUP_PB12 (PWR_CR6_EWU16 << 16) /*!< Enable wakeup on PB12 I/O event */
133 #else
134 #define LL_PWR_WAKEUP_CR6_ALL (0x0000FFFFU << 16) /*!< Enable all the wakeup source in CR6 */
135 #define LL_PWR_WAKEUP_CR3_ALL (0x0000BFFFU) /*!< Enable all the wakeup source in CR3 */
136 #define LL_PWR_WAKEUP_ALL LL_PWR_WAKEUP_CR6_ALL | LL_PWR_WAKEUP_CR3_ALL
137 #define LL_PWR_WAKEUP_RTC PWR_CR3_EIWL /*!< Enable wakeup on Internal event (RTC) */
138 #define LL_PWR_WAKEUP_BLEHOST PWR_CR3_EWBLEHCPU /*!< Enable wakeup on BLE Host CPU event */
139 #define LL_PWR_WAKEUP_BLE PWR_CR3_EWBLE /*!< Enable wakeup on BLE event */
140 #define LL_PWR_WAKEUP_PA15 (PWR_CR6_EWU27 << 16) /*!< Enable wakeup on PA15 I/O event */
141 #define LL_PWR_WAKEUP_PA14 (PWR_CR6_EWU26 << 16) /*!< Enable wakeup on PA14 I/O event */
142 #define LL_PWR_WAKEUP_PA13 (PWR_CR6_EWU25 << 16) /*!< Enable wakeup on PA13 I/O event */
143 #define LL_PWR_WAKEUP_PA12 (PWR_CR6_EWU24 << 16) /*!< Enable wakeup on PA12 I/O event */
144 #define LL_PWR_WAKEUP_PA11 PWR_CR3_EWU11 /*!< Enable wakeup on PA11 I/O event */
145 #define LL_PWR_WAKEUP_PA10 PWR_CR3_EWU10 /*!< Enable wakeup on PA10 I/O event */
146 #define LL_PWR_WAKEUP_PA9 PWR_CR3_EWU9 /*!< Enable wakeup on PA9 I/O event */
147 #define LL_PWR_WAKEUP_PA8 PWR_CR3_EWU8 /*!< Enable wakeup on PA8 I/O event */
148 #define LL_PWR_WAKEUP_PA7 (PWR_CR6_EWU19 << 16) /*!< Enable wakeup on LP-PA7 I/O event */
149 #define LL_PWR_WAKEUP_PA6 (PWR_CR6_EWU18 << 16) /*!< Enable wakeup on LP-PA6 I/O event */
150 #define LL_PWR_WAKEUP_PA5 (PWR_CR6_EWU17 << 16) /*!< Enable wakeup on LP-PA5 I/O event */
151 #define LL_PWR_WAKEUP_PA4 (PWR_CR6_EWU16 << 16) /*!< Enable wakeup on LP-PA4 I/O event */
152 #define LL_PWR_WAKEUP_PA3 (PWR_CR6_EWU15 << 16) /*!< Enable wakeup on PA3 I/O event */
153 #define LL_PWR_WAKEUP_PA2 (PWR_CR6_EWU14 << 16) /*!< Enable wakeup on PA2 I/O event */
154 #define LL_PWR_WAKEUP_PA1 (PWR_CR6_EWU13 << 16) /*!< Enable wakeup on PA1 I/O event */
155 #define LL_PWR_WAKEUP_PA0 (PWR_CR6_EWU12 << 16) /*!< Enable wakeup on PA0 I/O event */
156 #define LL_PWR_WAKEUP_PB11 (PWR_CR6_EWU23 << 16) /*!< Enable wakeup on PB11 I/O event */
157 #define LL_PWR_WAKEUP_PB10 (PWR_CR6_EWU22 << 16) /*!< Enable wakeup on PB10 I/O event */
158 #define LL_PWR_WAKEUP_PB9 (PWR_CR6_EWU21 << 16) /*!< Enable wakeup on PB9 I/O event */
159 #define LL_PWR_WAKEUP_PB8 (PWR_CR6_EWU20 << 16) /*!< Enable wakeup on PB8 I/O event */
160 #define LL_PWR_WAKEUP_PB7 PWR_CR3_EWU7 /*!< Enable wakeup on PB7 I/O event */
161 #define LL_PWR_WAKEUP_PB6 PWR_CR3_EWU6 /*!< Enable wakeup on PB6 I/O event */
162 #define LL_PWR_WAKEUP_PB5 PWR_CR3_EWU5 /*!< Enable wakeup on PB5 I/O event */
163 #define LL_PWR_WAKEUP_PB4 PWR_CR3_EWU4 /*!< Enable wakeup on PB4 I/O event */
164 #define LL_PWR_WAKEUP_PB3 PWR_CR3_EWU3 /*!< Enable wakeup on PB3 I/O event */
165 #define LL_PWR_WAKEUP_PB2 PWR_CR3_EWU2 /*!< Enable wakeup on PB2 I/O event */
166 #define LL_PWR_WAKEUP_PB1 PWR_CR3_EWU1 /*!< Enable wakeup on PB1 I/O event */
167 #define LL_PWR_WAKEUP_PB0 PWR_CR3_EWU0 /*!< Enable wakeup on PB0 I/O event */
168 #endif /* !defined(PWR_CR6_EWU20) */
169 /**
170 * @}
171 */
172
173 /** @defgroup PWR_LL_EC_GPIO GPIO Port
174 * @{
175 */
176 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
177 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
178
179 /**
180 * @}
181 */
182
183 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
184 * @brief Flags defines which can be used with LL_PWR_ReadReg function
185 * @{
186 */
187 #define LL_PWR_SR1_WUFI PWR_SR1_IWUF
188 #if defined(PWR_CR3_EIWL2)
189 #define LL_PWR_SR1_WUFI2 PWR_SR1_IWUF2
190 #endif /* PWR_CR3_EIWL2 */
191 #define LL_PWR_SR1_BHWF PWR_SR1_WBLEHCPUF
192 #define LL_PWR_SR1_WBLEF PWR_SR1_WBLEF
193 #define LL_PWR_SR1_WUF0 PWR_SR1_WUF0
194 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
195 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
196 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
197 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
198 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
199 #define LL_PWR_SR1_WUF6 PWR_SR1_WUF6
200 #define LL_PWR_SR1_WUF7 PWR_SR1_WUF7
201 #define LL_PWR_SR1_WUF8 PWR_SR1_WUF8
202 #define LL_PWR_SR1_WUF9 PWR_SR1_WUF9
203 #define LL_PWR_SR1_WUF10 PWR_SR1_WUF10
204 #define LL_PWR_SR1_WUF11 PWR_SR1_WUF11
205 #define LL_PWR_SR3_WUF12 (PWR_SR3_WUF12 << 16)
206 #define LL_PWR_SR3_WUF13 (PWR_SR3_WUF13 << 16)
207 #define LL_PWR_SR3_WUF14 (PWR_SR3_WUF14 << 16)
208 #define LL_PWR_SR3_WUF15 (PWR_SR3_WUF15 << 16)
209 #define LL_PWR_SR3_WUF16 (PWR_SR3_WUF16 << 16)
210 #define LL_PWR_SR3_WUF17 (PWR_SR3_WUF17 << 16)
211 #define LL_PWR_SR3_WUF18 (PWR_SR3_WUF18 << 16)
212 #define LL_PWR_SR3_WUF19 (PWR_SR3_WUF19 << 16)
213 #if defined(PWR_CR6_EWU20)
214 #define LL_PWR_SR3_WUF20 (PWR_SR3_WUF20 << 16)
215 #endif /* PWR_CR6_EWU20 */
216 #if defined(PWR_CR6_EWU21)
217 #define LL_PWR_SR3_WUF21 (PWR_SR3_WUF21 << 16)
218 #endif /* PWR_CR6_EWU21 */
219 #if defined(PWR_CR6_EWU22)
220 #define LL_PWR_SR3_WUF22 (PWR_SR3_WUF22 << 16)
221 #endif /* PWR_CR6_EWU22 */
222 #if defined(PWR_CR6_EWU23)
223 #define LL_PWR_SR3_WUF23 (PWR_SR3_WUF23 << 16)
224 #endif /* PWR_CR6_EWU23 */
225 #if defined(PWR_CR6_EWU24)
226 #define LL_PWR_SR3_WUF24 (PWR_SR3_WUF24 << 16)
227 #endif /* PWR_CR6_EWU24 */
228 #if defined(PWR_CR6_EWU25)
229 #define LL_PWR_SR3_WUF25 (PWR_SR3_WUF25 << 16)
230 #endif /* PWR_CR6_EWU25 */
231 #if defined(PWR_CR6_EWU26)
232 #define LL_PWR_SR3_WUF26 (PWR_SR3_WUF26 << 16)
233 #endif /* PWR_CR6_EWU26 */
234 #if defined(PWR_CR6_EWU27)
235 #define LL_PWR_SR3_WUF27 (PWR_SR3_WUF27 << 16)
236 #endif /* PWR_CR6_EWU27 */
237 #if defined (PWR_CR3_EIWL2)
238 #define LL_PWR_SR1_WUFALL 0x0000FFFF
239 #else
240 #define LL_PWR_SR1_WUFALL 0x0000BFFF
241 #endif /* PWR_CR3_EIWL2 */
242 #if defined (PWR_SR3_WUF20)
243 #define LL_PWR_SR3_WUFALL 0xFFFF0000
244 #else
245 #define LL_PWR_SR3_WUFALL 0x00FF0000
246 #endif /* PWR_SR3_WUF20 */
247 #define LL_PWR_WUFALL (LL_PWR_SR1_WUFALL | LL_PWR_SR3_WUFALL)
248 #define LL_PWR_EXTSRR_RFPHASEF PWR_EXTSRR_RFPHASEF
249 #define LL_PWR_EXTSRR_DEEPSTOPF PWR_EXTSRR_DEEPSTOPF
250 /**
251 * @}
252 */
253
254 /** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask
255 * @{
256 */
257 #define LL_PWR_GPIO_BIT_0 (0x0001U) /*!< GPIO port I/O pin 0 */
258 #define LL_PWR_GPIO_BIT_1 (0x0002U) /*!< GPIO port I/O pin 1 */
259 #define LL_PWR_GPIO_BIT_2 (0x0004U) /*!< GPIO port I/O pin 2 */
260 #define LL_PWR_GPIO_BIT_3 (0x0008U) /*!< GPIO port I/O pin 3 */
261 #define LL_PWR_GPIO_BIT_4 (0x0010U) /*!< GPIO port I/O pin 4 */
262 #define LL_PWR_GPIO_BIT_5 (0x0020U) /*!< GPIO port I/O pin 5 */
263 #define LL_PWR_GPIO_BIT_6 (0x0040U) /*!< GPIO port I/O pin 6 */
264 #define LL_PWR_GPIO_BIT_7 (0x0080U) /*!< GPIO port I/O pin 7 */
265 #define LL_PWR_GPIO_BIT_8 (0x0100U) /*!< GPIO port I/O pin 8 */
266 #define LL_PWR_GPIO_BIT_9 (0x0200U) /*!< GPIO port I/O pin 9 */
267 #define LL_PWR_GPIO_BIT_10 (0x0400U) /*!< GPIO port I/O pin 10 */
268 #define LL_PWR_GPIO_BIT_11 (0x0800U) /*!< GPIO port I/O pin 11 */
269 #define LL_PWR_GPIO_BIT_12 (0x1000U) /*!< GPIO port I/O pin 12 */
270 #define LL_PWR_GPIO_BIT_13 (0x2000U) /*!< GPIO port I/O pin 13 */
271 #define LL_PWR_GPIO_BIT_14 (0x4000U) /*!< GPIO port I/O pin 14 */
272 #define LL_PWR_GPIO_BIT_15 (0x8000U) /*!< GPIO port I/O pin 15 */
273 /**
274 * @}
275 */
276
277 /** @defgroup PWR_LL_EC_IO_CFG IOs PU/PD configuration
278 * @{
279 */
280 #define LL_PWR_WUP_RISIEDG (0x000000000U) /*!< Detection of wakeup event on rising edge. */
281 #define LL_PWR_WUP_FALLEDG (0x000000001U) /*!< Detection of wakeup event on falling edge. */
282 /**
283 * @}
284 */
285
286 /** @defgroup PWR_LL_EC_IO_OUT_CFG PA4-PA11 output configuration during DEEPSTOP
287 * @{
288 */
289 #define LL_PWR_IOCFG_BYP (0x000000000U) /*!< BYPASS mode. The I/O mode is controlled by the GPIO block
290 registers in active mode and switch to input mode during DEESPTOP state. */
291 #define LL_PWR_IOCFG_RTC (0x000000001U) /*!< RTC_OUT signal for PA11 and PA8 */
292 #define LL_PWR_IOCFG_LCO (0x000000001U) /*!< LCO output signal for PA10 and PA9 */
293 #define LL_PWR_IOCFG_LOW (0x000000002U) /*!< I/O drives a low level in both active and DEEPSTOP modes */
294 #define LL_PWR_IOCFG_HIGH (0x000000003U) /*!< I/O drives a high level in both active and DEEPSTOP modes */
295 /**
296 * @}
297 */
298
299 /** @defgroup PWR_LL_EC_IO_LATCH_BOOT PA8-PA11 I/Os value latched at POR.
300 * @{
301 */
302 #define LL_PWR_PA8_LATCH_POR PWR_SR2_IOBOOTVAL_0 /*!< PA8 input value latched at POR. */
303 #define LL_PWR_PA9_LATCH_POR PWR_SR2_IOBOOTVAL_1 /*!< PA9 input value latched at POR. */
304 #define LL_PWR_PA10_LATCH_POR PWR_SR2_IOBOOTVAL_2 /*!< PA10 input value latched at POR. */
305 #define LL_PWR_PA11_LATCH_POR PWR_SR2_IOBOOTVAL_3 /*!< PA11 input value latched at POR. */
306 /**
307 * @}
308 */
309
310 /** @defgroup PWR_LL_EC_IO_LATCH_BOOT_2 PB12-PB15 I/Os value latched at POR.
311 * @{
312 */
313 #if defined(PWR_SR2_IOBOOTVAL2_0)
314 #define LL_PWR_PB12_LATCH_POR PWR_SR2_IOBOOTVAL2_0 /*!< PB12 input value latched at POR. */
315 #endif /* PWR_SR2_IOBOOTVAL2_0 */
316 #if defined(PWR_SR2_IOBOOTVAL2_1)
317 #define LL_PWR_PB13_LATCH_POR PWR_SR2_IOBOOTVAL2_1 /*!< PB13 input value latched at POR. */
318 #endif /* PWR_SR2_IOBOOTVAL2_1 */
319 #if defined(PWR_SR2_IOBOOTVAL2_2)
320 #define LL_PWR_PB14_LATCH_POR PWR_SR2_IOBOOTVAL2_2 /*!< PB14 input value latched at POR. */
321 #endif /* PWR_SR2_IOBOOTVAL2_2 */
322 #if defined(PWR_SR2_IOBOOTVAL2_3)
323 #define LL_PWR_PB15_LATCH_POR PWR_SR2_IOBOOTVAL2_3 /*!< PB15 input value latched at POR. */
324 #endif /* PWR_SR2_IOBOOTVAL2_3 */
325 /**
326 * @}
327 */
328
329 /** @defgroup PWR_LL_EC_SMPS_MODE SMPS Mode
330 * @{
331 */
332 #define LL_PWR_SMPS (0x000000000U) /*!< SMPS is enabled */
333 #define LL_PWR_NO_SMPS PWR_CR5_NOSMPS /*!< SMPS is disabled */
334 /**
335 * @}
336 */
337
338 /** @defgroup PWR_LL_EC_SMPS_PRECHARGE_MODE SMPS PRECHARGE Mode
339 * @{
340 */
341 #define LL_PWR_NO_SMPS_PRECHARGE (0x000000000U) /*!< SMPS not in pecharge mode */
342 #define LL_PWR_SMPS_PRECHARGE PWR_CR5_SMPSFBYP /*!< SMPS is disabled and bypassed in precharge mode */
343 /**
344 * @}
345 */
346
347 /** @defgroup PWR_LL_EC_SMPS_OPEN_MODE SMPS OPEN Mode during DEEPSTOP
348 * @{
349 */
350 #define LL_PWR_NO_SMPS_LPOPEN (0x000000000U) /*!< In DEEPSTOP, the SMPS is in PRECHARGE mode with output connected to VDDIO */
351 #define LL_PWR_SMPS_LPOPEN PWR_CR5_SMPSLPOPEN /*!< In DEEPSTOP, the SMPS is disabled with floating output */
352 /**
353 * @}
354 */
355
356 /** @defgroup PWR_LL_EC_SMPS_BOM SMPS BOM
357 * @{
358 */
359 #define LL_PWR_SMPS_BOM1 (0x000000000U)
360 #define LL_PWR_SMPS_BOM2 PWR_CR5_SMPSBOMSEL_0
361 #define LL_PWR_SMPS_BOM3 PWR_CR5_SMPSBOMSEL_1
362 /**
363 * @}
364 */
365
366 /** @defgroup PWR_LL_EC_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level
367 * @{
368 */
369 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x000000000U) /*!< SMPS step down converter supply output voltage 1.20V */
370 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25 (PWR_CR5_SMPSLVL_0) /*!< SMPS step down converter supply output voltage 1.25V */
371 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30 (PWR_CR5_SMPSLVL_1) /*!< SMPS step down converter supply output voltage 1.30V */
372 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35 (PWR_CR5_SMPSLVL_1|PWR_CR5_SMPSLVL_0) /*!< SMPS step down converter supply output voltage 1.35V */
373 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40 (PWR_CR5_SMPSLVL_2) /*!< SMPS step down converter supply output voltage 1.40V */
374 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45 (PWR_CR5_SMPSLVL_2|PWR_CR5_SMPSLVL_0) /*!< SMPS step down converter supply output voltage 1.45V */
375 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 (PWR_CR5_SMPSLVL_2|PWR_CR5_SMPSLVL_1) /*!< SMPS step down converter supply output voltage 1.50V */
376 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55 (PWR_CR5_SMPSLVL_2|PWR_CR5_SMPSLVL_1|PWR_CR5_SMPSLVL_0) /*!< SMPS step down converter supply output voltage 1.55V */
377 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSLVL_3) /*!< SMPS step down converter supply output voltage 1.60V */
378 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSLVL_3|PWR_CR5_SMPSLVL_0) /*!< SMPS step down converter supply output voltage 1.65V */
379 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSLVL_3|PWR_CR5_SMPSLVL_1) /*!< SMPS step down converter supply output voltage 1.70V */
380 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSLVL_3|PWR_CR5_SMPSLVL_1|PWR_CR5_SMPSLVL_0) /*!< SMPS step down converter supply output voltage 1.75V */
381 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSLVL_3|PWR_CR5_SMPSLVL_2) /*!< SMPS step down converter supply output voltage 1.80V */
382 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSLVL_3|PWR_CR5_SMPSLVL_2|PWR_CR5_SMPSLVL_0) /*!< SMPS step down converter supply output voltage 1.85V */
383 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSLVL_3|PWR_CR5_SMPSLVL_2|PWR_CR5_SMPSLVL_1) /*!< SMPS step down converter supply output voltage 1.90V */
384 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V95 (PWR_CR5_SMPSLVL) /*!< SMPS step down converter supply output voltage 1.95V */
385 /**
386 * @}
387 */
388
389 #if defined(PWR_CR5_SMPS_PRECH_CUR_SEL)
390 /** @defgroup PWR_LL_EC_SMPS_PRECHARGE_LIMIT_CURRENT Select SMPS PRECHARGE limit current
391 * @{
392 */
393 #define LL_PWR_SMPS_PRECH_LIMIT_CUR_2_5 (0x000000000U)
394 #define LL_PWR_SMPS_PRECH_LIMIT_CUR_5 (PWR_CR5_SMPS_PRECH_CUR_SEL_0)
395 #define LL_PWR_SMPS_PRECH_LIMIT_CUR_10 (PWR_CR5_SMPS_PRECH_CUR_SEL_1)
396 #define LL_PWR_SMPS_PRECH_LIMIT_CUR_20 (PWR_CR5_SMPS_PRECH_CUR_SEL_0|PWR_CR5_SMPS_PRECH_CUR_SEL_1)
397 /**
398 * @}
399 */
400 #endif /* PWR_CR5_SMPS_PRECH_CUR_SEL */
401
402 /**
403 * @}
404 */
405
406 /* Exported macro ------------------------------------------------------------*/
407 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
408 * @{
409 */
410
411 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
412 * @{
413 */
414
415 /**
416 * @brief Write a value in PWR register
417 * @param __REG__ Register to be written
418 * @param __VALUE__ Value to be written in the register
419 * @retval None
420 */
421 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
422
423 /**
424 * @brief Read a value in PWR register
425 * @param __REG__ Register to be read
426 * @retval Register value
427 */
428 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
429 /**
430 * @}
431 */
432
433 /**
434 * @}
435 */
436
437
438 /* Exported functions --------------------------------------------------------*/
439 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
440 * @{
441 */
442
443 /** @defgroup PWR_LL_EF_Configuration PWR Configuration
444 * @{
445 */
446
447 /**
448 * @brief Enable the BOR reset supervising during SHUTDOWN mode.
449 * @rmtoll CR1 ENSDNBOR LL_PWR_EnableBORinSDN
450 * @retval None
451 */
LL_PWR_EnableBORinSDN(void)452 __STATIC_INLINE void LL_PWR_EnableBORinSDN(void)
453 {
454 SET_BIT(PWR->CR1, PWR_CR1_ENSDNBOR);
455 }
456
457 /**
458 * @brief Disable the BOR reset supervising during SHUTDOWN mode.
459 * @rmtoll CR1 ENSDNBOR LL_PWR_DisableBORinSDN
460 * @retval None
461 */
LL_PWR_DisableBORinSDN(void)462 __STATIC_INLINE void LL_PWR_DisableBORinSDN(void)
463 {
464 CLEAR_BIT(PWR->CR1, PWR_CR1_ENSDNBOR);
465 }
466
467 /**
468 * @brief Checks if BOR is enabled or disabled during SHUTDOWN mode.
469 * @rmtoll CR1 ENSDNBOR LL_PWR_IsEnabledBORinSDN
470 * @retval State of bit (1 or 0).
471 */
LL_PWR_IsEnabledBORinSDN(void)472 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBORinSDN(void)
473 {
474 return ((READ_BIT(PWR->CR1, PWR_CR1_ENSDNBOR) == (PWR_CR1_ENSDNBOR)) ? 1UL : 0UL);
475 }
476
477 /**
478 * @brief Set low-power mode.
479 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
480 * @param LowPowerMode Low Power Mode Selection. This parameter can be one of the following values:
481 * @arg LL_PWR_MODE_DEEPSTOP
482 * @arg LL_PWR_MODE_SHUTDOWN
483 * @retval None
484 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)485 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
486 {
487 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
488 }
489
490 /**
491 * @brief Get Low-Power mode
492 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
493 * @retval Returned value can be one of the following values:
494 * @arg @ref LL_PWR_MODE_DEEPSTOP
495 * @arg @ref LL_PWR_MODE_SHUTDOWN
496 */
497
LL_PWR_GetPowerMode(void)498 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
499 {
500 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
501 }
502
503 /**
504 * @brief Enable pull-up and pull-down configuration
505 * @rmtoll CR1 APC LL_PWR_EnablePUPDCfg
506 * @retval None
507 */
LL_PWR_EnablePUPDCfg(void)508 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
509 {
510 SET_BIT(PWR->CR1, PWR_CR1_APC);
511 }
512
513 /**
514 * @brief Disable pull-up and pull-down configuration
515 * @rmtoll CR1 APC LL_PWR_DisablePUPDCfg
516 * @retval None
517 */
LL_PWR_DisablePUPDCfg(void)518 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
519 {
520 CLEAR_BIT(PWR->CR1, PWR_CR1_APC);
521 }
522
523 /**
524 * @brief Check if pull-up and pull-down configuration is enabled
525 * @rmtoll CR1 APC LL_PWR_IsEnabledPUPDCfg
526 * @retval State of bit (1 or 0).
527 */
LL_PWR_IsEnabledPUPDCfg(void)528 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
529 {
530 return ((READ_BIT(PWR->CR1, PWR_CR1_APC) == (PWR_CR1_APC)) ? 1UL : 0UL);
531 }
532
533 #if defined(PWR_CR2_LSILPMUFEN)
534 /**
535 * @brief LSI always enabled. Instead to be enabled/disabled by hardware depending
536 * on the analog LPMU block needs.
537 * @rmtoll CR2 LSILPMUFEN LL_PWR_EnableLSILPMU
538 * @retval None
539 */
LL_PWR_EnableLSILPMU(void)540 __STATIC_INLINE void LL_PWR_EnableLSILPMU(void)
541 {
542 SET_BIT(PWR->CR2, PWR_CR2_LSILPMUFEN);
543 }
544
545 /**
546 * @brief Disable the LSI always enabled. With this setting the LSI LPMU is automatically enabled/disabled
547 * by hardware depending on the analog LPMU block needs.
548 * @rmtoll CR2 LSILPMUFEN LL_PWR_DisableLSILPMU
549 * @retval None
550 */
LL_PWR_DisableLSILPMU(void)551 __STATIC_INLINE void LL_PWR_DisableLSILPMU(void)
552 {
553 CLEAR_BIT(PWR->CR2, PWR_CR2_LSILPMUFEN);
554 }
555
556 /**
557 * @brief Checks if LSI LPMU is enabled or disabled.
558 * @rmtoll CR2 LSILPMUFEN LL_PWR_IsEnabledLSILPMU
559 * @retval State of bit (1 or 0).
560 */
LL_PWR_IsEnabledLSILPMU(void)561 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLSILPMU(void)
562 {
563 return ((READ_BIT(PWR->CR2, PWR_CR2_LSILPMUFEN) == (PWR_CR2_LSILPMUFEN)) ? 1UL : 0UL);
564 }
565 #endif /* PWR_CR2_LSILPMUFEN */
566
567 #if defined(PWR_CR2_ENTS)
568 /**
569 * @brief Enabled the temperature sensor.
570 * @rmtoll CR2 ENTS LL_PWR_EnableTempSens
571 * @retval None
572 */
LL_PWR_EnableTempSens(void)573 __STATIC_INLINE void LL_PWR_EnableTempSens(void)
574 {
575 SET_BIT(PWR->CR2, PWR_CR2_ENTS);
576 }
577
578 /**
579 * @brief Disable the temperature sensor.
580 * @rmtoll CR2 ENTS LL_PWR_DisableTempSens
581 * @retval None
582 */
LL_PWR_DisableTempSens(void)583 __STATIC_INLINE void LL_PWR_DisableTempSens(void)
584 {
585 CLEAR_BIT(PWR->CR2, PWR_CR2_ENTS);
586 }
587
588 /**
589 * @brief Checks if temperature sensor is enabled or disabled.
590 * @rmtoll CR2 ENTS LL_PWR_IsEnabledTempSens
591 * @retval State of bit (1 or 0).
592 */
LL_PWR_IsEnabledTempSens(void)593 __STATIC_INLINE uint32_t LL_PWR_IsEnabledTempSens(void)
594 {
595 return ((READ_BIT(PWR->CR2, PWR_CR2_ENTS) == (PWR_CR2_ENTS)) ? 1UL : 0UL);
596 }
597 #endif /* PWR_CR2_ENTS */
598
599 /**
600 * @brief Enable the RAM bank retention.
601 * @rmtoll CR2 RAMRET1 LL_PWR_DisableRAMBankRet
602 * CR2 RAMRET2 LL_PWR_DisableRAMBankRet
603 * CR2 RAMRET3 LL_PWR_DisableRAMBankRet
604 * @param banks RAM bank selection. This parameter can be a combination of the following values:
605 * @arg @ref LL_PWR_RAMRET_1
606 * @arg @ref LL_PWR_RAMRET_2 (*)
607 * @arg @ref LL_PWR_RAMRET_3 (*)
608 * (*) Not available on devices STM32WB05
609 * @retval None
610 */
LL_PWR_EnableRAMBankRet(uint32_t banks)611 __STATIC_INLINE void LL_PWR_EnableRAMBankRet(uint32_t banks)
612 {
613 SET_BIT(PWR->CR2, banks);
614 }
615
616 /**
617 * @brief Get the RAM banks retention selected.
618 * @rmtoll CR2 RAMRET1 LL_PWR_DisableRAMBankRet
619 * CR2 RAMRET2 LL_PWR_DisableRAMBankRet
620 * CR2 RAMRET3 LL_PWR_DisableRAMBankRet
621 * @retval Returned value can be one of the following values:
622 * @arg @ref LL_PWR_RAMRET_1
623 * @arg @ref LL_PWR_RAMRET_2 (*)
624 * @arg @ref LL_PWR_RAMRET_3 (*)
625 * (*) Not available on devices STM32WB05
626 */
LL_PWR_GetRAMBankRet(void)627 __STATIC_INLINE uint32_t LL_PWR_GetRAMBankRet(void)
628 {
629 uint32_t ram_ret;
630
631 ram_ret = READ_BIT(PWR->CR2, (PWR_CR2_RAMRET1));
632 #if defined(PWR_CR2_RAMRET2)
633 ram_ret |= READ_BIT(PWR->CR2, (PWR_CR2_RAMRET2));
634 #endif /* PWR_CR2_RAMRET2 */
635 #if defined(PWR_CR2_RAMRET3)
636 ram_ret |= READ_BIT(PWR->CR2, (PWR_CR2_RAMRET3));
637 #endif /* PWR_CR2_RAMRET3 */
638 return ram_ret;
639 }
640
641 /**
642 * @brief Disable the RAM bank retention.
643 * @rmtoll CR2 RAMRET1 LL_PWR_DisableRAMBankRet
644 * CR2 RAMRET2 LL_PWR_DisableRAMBankRet
645 * CR2 RAMRET3 LL_PWR_DisableRAMBankRet
646 * @param banks RAM bank selection. This parameter can be a combination of the following values:
647 * @arg @ref LL_PWR_RAMRET_1
648 * @arg @ref LL_PWR_RAMRET_2 (*)
649 * @arg @ref LL_PWR_RAMRET_3 (*)
650 * (*) Not available on devices STM32WB05
651 * @retval None
652 */
LL_PWR_DisableRAMBankRet(uint32_t banks)653 __STATIC_INLINE void LL_PWR_DisableRAMBankRet(uint32_t banks)
654 {
655 CLEAR_BIT(PWR->CR2, banks);
656 }
657
658 /**
659 * @brief Configure the voltage threshold detected by the Power Voltage Detector.
660 * @rmtoll CR2 PVDLS LL_PWR_SetPVDLevel
661 * @param PVDLevel PVD voltage level selection. This parameter can be one of the following values:
662 * @arg @ref LL_PWR_PVDLEVEL_0
663 * @arg @ref LL_PWR_PVDLEVEL_1
664 * @arg @ref LL_PWR_PVDLEVEL_2
665 * @arg @ref LL_PWR_PVDLEVEL_3
666 * @arg @ref LL_PWR_PVDLEVEL_4
667 * @arg @ref LL_PWR_PVDLEVEL_5
668 * @arg @ref LL_PWR_PVDLEVEL_6
669 * @arg @ref LL_PWR_PVDLEVEL_7
670 * @retval None
671 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)672 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
673 {
674 MODIFY_REG(PWR->CR2, PWR_CR2_PVDLS, PVDLevel);
675 }
676
677 /**
678 * @brief Get the voltage threshold detection.
679 * @rmtoll CR2 PVDLS LL_PWR_GetPVDLevel
680 * @retval Returned value can be one of the following values:
681 * @arg @ref LL_PWR_PVDLEVEL_0
682 * @arg @ref LL_PWR_PVDLEVEL_1
683 * @arg @ref LL_PWR_PVDLEVEL_2
684 * @arg @ref LL_PWR_PVDLEVEL_3
685 * @arg @ref LL_PWR_PVDLEVEL_4
686 * @arg @ref LL_PWR_PVDLEVEL_5
687 * @arg @ref LL_PWR_PVDLEVEL_6
688 * @arg @ref LL_PWR_PVDLEVEL_7
689 */
LL_PWR_GetPVDLevel(void)690 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
691 {
692 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDLS));
693 }
694
695 /**
696 * @brief Enable Power Voltage Detector
697 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
698 * @retval None
699 */
LL_PWR_EnablePVD(void)700 __STATIC_INLINE void LL_PWR_EnablePVD(void)
701 {
702 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
703 }
704
705 /**
706 * @brief Disable the Power Voltage Detector.
707 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
708 * @retval None
709 */
LL_PWR_DisablePVD(void)710 __STATIC_INLINE void LL_PWR_DisablePVD(void)
711 {
712 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
713 }
714
715 /**
716 * @brief Check if Power Voltage Detector is enabled or disabled.
717 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
718 * @retval State of bit (1 or 0).
719 */
LL_PWR_IsEnabledPVD(void)720 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
721 {
722 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
723 }
724
725 #if defined (PWR_CR2_GPIORET)
726 /** @defgroup PWR_LL_DEEPSTOP_GPIORET Functions to setup the GPIORET bit.
727 * GPIO retention
728 * @{
729 */
730
731 /**
732 * @brief Enable the GPIORET feature, GPIO retain their status during DEEPSTOP
733 * and exiting from DEEPSTOP.
734 * @rmtoll CR2 GPIORET LL_PWR_EnableGPIORET
735 * @retval None
736 */
LL_PWR_EnableGPIORET(void)737 __STATIC_INLINE void LL_PWR_EnableGPIORET(void)
738 {
739 SET_BIT(PWR->CR2, PWR_CR2_GPIORET);
740 }
741
742 /**
743 * @brief Disable the GPIORET feature, don't retain their status during DEEPSTOP and exiting from DEEPSTOP.
744 * @rmtoll CR2 GPIORET LL_PWR_DisableGPIORET
745 * @retval None
746 */
LL_PWR_DisableGPIORET(void)747 __STATIC_INLINE void LL_PWR_DisableGPIORET(void)
748 {
749 CLEAR_BIT(PWR->CR2, PWR_CR2_GPIORET);
750 }
751
752 /**
753 * @brief Checks if the GPIO retention in DEEPSTOP feature is enabled or disabled
754 * @rmtoll CR2 GPIORET LL_PWR_IsEnabledGPIORET
755 * @retval State of bit (1 or 0).
756 */
LL_PWR_IsEnabledGPIORET(void)757 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIORET(void)
758 {
759 return ((READ_BIT(PWR->CR2, PWR_CR2_GPIORET) == (PWR_CR2_GPIORET)) ? 1UL : 0UL);
760 }
761 /**
762 * @}
763 */
764 #endif /* PWR_CR2_GPIORET */
765
766 #if defined (PWR_CR2_DBGRET)
767 /** @defgroup PWR_LL_DEEPSTOP_DBGRET Functions to setup the DBGRET bit.
768 * GPIOA_Pin_2 and GPIOA_Pin_3 retention exiting from DEEPSTOP
769 * @{
770 */
771
772 /**
773 * @brief Enable the DBGRET feature, GPIOA_Pin_2 and GPIOA_Pin_3 retain their
774 * status during DEEPSTOP and exiting from DEEPSTOP.
775 * @rmtoll CR2 DBGRET LL_PWR_EnableDBGRET
776 * @retval None
777 */
LL_PWR_EnableDBGRET(void)778 __STATIC_INLINE void LL_PWR_EnableDBGRET(void)
779 {
780 SET_BIT(PWR->CR2, PWR_CR2_DBGRET);
781 }
782
783 /**
784 * @brief Disable the DBGRET feature, GPIOA_Pin_2 and GPIOA_Pin_3 don't retain
785 * status during DEEPSTOP and exiting from DEEPSTOP.
786 * @rmtoll CR2 DBGRET LL_PWR_DisableDBGRET
787 * @retval None
788 */
LL_PWR_DisableDBGRET(void)789 __STATIC_INLINE void LL_PWR_DisableDBGRET(void)
790 {
791 CLEAR_BIT(PWR->CR2, PWR_CR2_DBGRET);
792 }
793
794 /**
795 * @brief Checks if the GPIOA_Pin_2 and GPIOA_Pin_3 retention in DEEPSTOP
796 * feature is enabled or disabled
797 * @rmtoll CR2 DBGRET LL_PWR_IsEnabledDBGRET
798 * @retval State of bit (1 or 0).
799 */
LL_PWR_IsEnabledDBGRET(void)800 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDBGRET(void)
801 {
802 return ((READ_BIT(PWR->CR2, PWR_CR2_DBGRET) == (PWR_CR2_DBGRET)) ? 1UL : 0UL);
803 }
804 /**
805 * @}
806 */
807 #endif /* PWR_CR2_DBGRET */
808
809 /**
810 * @brief Enable Internal Wake-up line (RTC)
811 * @rmtoll CR3 EIWL LL_PWR_EnableInternWU
812 * @retval None
813 */
LL_PWR_EnableInternWU(void)814 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
815 {
816 SET_BIT(PWR->CR3, PWR_CR3_EIWL);
817 }
818
819 /**
820 * @brief Disable Internal Wake-up line (RTC)
821 * @rmtoll CR3 EIWL LL_PWR_DisableInternWU
822 * @retval None
823 */
LL_PWR_DisableInternWU(void)824 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
825 {
826 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWL);
827 }
828
829 /**
830 * @brief Check if Internal Wake-up line is enabled (RTC)
831 * @rmtoll CR3 EIWL LL_PWR_IsEnabledInternWU
832 * @retval State of bit (1 or 0).
833 */
LL_PWR_IsEnabledInternWU(void)834 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
835 {
836 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWL) == (PWR_CR3_EIWL)) ? 1UL : 0UL);
837 }
838
839 #if defined (PWR_CR3_EIWL2)
840 /**
841 * @brief Enable Internal Wake-up line (LPUART)
842 * @rmtoll CR3 EIWL2 LL_PWR_EnableInternWU2
843 * @retval None
844 */
LL_PWR_EnableInternWU2(void)845 __STATIC_INLINE void LL_PWR_EnableInternWU2(void)
846 {
847 SET_BIT(PWR->CR3, PWR_CR3_EIWL2);
848 }
849
850 /**
851 * @brief Disable Internal Wake-up line (LPUART)
852 * @rmtoll CR3 EIWL2 LL_PWR_EnableInternWU2
853 * @retval None
854 */
LL_PWR_DisableInternWU2(void)855 __STATIC_INLINE void LL_PWR_DisableInternWU2(void)
856 {
857 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWL2);
858 }
859
860 /**
861 * @brief Check if Internal Wake-up line is enabled (LPUART)
862 * @rmtoll CR3 EIWL2 LL_PWR_EnableInternWU2
863 * @retval State of bit (1 or 0).
864 */
LL_PWR_IsEnabledInternWU2(void)865 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU2(void)
866 {
867 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWL2) == (PWR_CR3_EIWL2)) ? 1UL : 0UL);
868 }
869
870 /**
871 * @brief Clear Internal Wake-up2 flag
872 * @rmtoll SR3 IWUF2 LL_PWR_ClearFlag_BORH
873 * @retval None
874 */
LL_PWR_ClearFlag_InternWU2(void)875 __STATIC_INLINE void LL_PWR_ClearFlag_InternWU2(void)
876 {
877 WRITE_REG(PWR->SR1, PWR_SR1_IWUF2);
878 }
879
880 #endif /* PWR_CR3_EIWL2 */
881
882 /**
883 * @brief Enable Wakeup PINx to get out of DEEPSTOP mode.
884 * @rmtoll CR3 EWU0 LL_PWR_EnableWakeUpPin\n
885 * CR3 EWU1 LL_PWR_EnableWakeUpPin\n
886 * CR3 EWU2 LL_PWR_EnableWakeUpPin\n
887 * CR3 EWU3 LL_PWR_EnableWakeUpPin\n
888 * CR3 EWU4 LL_PWR_EnableWakeUpPin\n
889 * CR3 EWU5 LL_PWR_EnableWakeUpPin\n
890 * CR3 EWU6 LL_PWR_EnableWakeUpPin\n
891 * CR3 EWU7 LL_PWR_EnableWakeUpPin\n
892 * CR3 EWU8 LL_PWR_EnableWakeUpPin\n
893 * CR3 EWU9 LL_PWR_EnableWakeUpPin\n
894 * CR3 EWU10 LL_PWR_EnableWakeUpPin\n
895 * CR3 EWU11 LL_PWR_EnableWakeUpPin\n
896 * CR6 EWU12 LL_PWR_EnableWakeUpPin\n
897 * CR6 EWU13 LL_PWR_EnableWakeUpPin\n
898 * CR6 EWU14 LL_PWR_EnableWakeUpPin\n
899 * CR6 EWU15 LL_PWR_EnableWakeUpPin\n
900 * CR6 EWU16 LL_PWR_EnableWakeUpPin\n
901 * CR6 EWU17 LL_PWR_EnableWakeUpPin\n
902 * CR6 EWU18 LL_PWR_EnableWakeUpPin\n
903 * CR6 EWU19 LL_PWR_EnableWakeUpPin\n
904 * CR6 EWU20 LL_PWR_EnableWakeUpPin\n
905 * CR6 EWU21 LL_PWR_EnableWakeUpPin\n
906 * CR6 EWU22 LL_PWR_EnableWakeUpPin\n
907 * CR6 EWU23 LL_PWR_EnableWakeUpPin\n
908 * CR6 EWU24 LL_PWR_EnableWakeUpPin\n
909 * CR6 EWU25 LL_PWR_EnableWakeUpPin\n
910 * CR6 EWU26 LL_PWR_EnableWakeUpPin\n
911 * CR6 EWU27 LL_PWR_EnableWakeUpPin
912 * @param WakeUpPin Enable the wakeup sources.
913 * This parameter can be a combination of the following values:
914 * @arg @ref LL_PWR_WAKEUP_PA0
915 * @arg @ref LL_PWR_WAKEUP_PA1
916 * @arg @ref LL_PWR_WAKEUP_PA2
917 * @arg @ref LL_PWR_WAKEUP_PA3
918 * @arg @ref LL_PWR_WAKEUP_PA4 (*)
919 * @arg @ref LL_PWR_WAKEUP_PA5 (*)
920 * @arg @ref LL_PWR_WAKEUP_PA6 (*)
921 * @arg @ref LL_PWR_WAKEUP_PA7 (*)
922 * @arg @ref LL_PWR_WAKEUP_PA8
923 * @arg @ref LL_PWR_WAKEUP_PA9
924 * @arg @ref LL_PWR_WAKEUP_PA10
925 * @arg @ref LL_PWR_WAKEUP_PA11
926 * @arg @ref LL_PWR_WAKEUP_PA12 (*)
927 * @arg @ref LL_PWR_WAKEUP_PA13 (*)
928 * @arg @ref LL_PWR_WAKEUP_PA14 (*)
929 * @arg @ref LL_PWR_WAKEUP_PA15 (*)
930 * @arg @ref LL_PWR_WAKEUP_PB0
931 * @arg @ref LL_PWR_WAKEUP_PB1
932 * @arg @ref LL_PWR_WAKEUP_PB2
933 * @arg @ref LL_PWR_WAKEUP_PB3
934 * @arg @ref LL_PWR_WAKEUP_PB4
935 * @arg @ref LL_PWR_WAKEUP_PB5
936 * @arg @ref LL_PWR_WAKEUP_PB6
937 * @arg @ref LL_PWR_WAKEUP_PB7
938 * @arg @ref LL_PWR_WAKEUP_PB8 (*)
939 * @arg @ref LL_PWR_WAKEUP_PB9 (*)
940 * @arg @ref LL_PWR_WAKEUP_PB10 (*)
941 * @arg @ref LL_PWR_WAKEUP_PB11 (*)
942 * @arg @ref LL_PWR_WAKEUP_PB12 (**)
943 * @arg @ref LL_PWR_WAKEUP_PB13 (**)
944 * @arg @ref LL_PWR_WAKEUP_PB14 (**)
945 * @arg @ref LL_PWR_WAKEUP_PB15 (**)
946 * (*) available only on STM32WB06 and STM32WB07 devices
947 * (**) available only on STM32WB05 and STM32WB09 devices
948 * @retval None
949 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)950 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
951 {
952 SET_BIT(PWR->CR3, (WakeUpPin & 0x0000FFFF));
953 SET_BIT(PWR->CR6, (WakeUpPin >> 16));
954 }
955
956 /**
957 * @brief Disable Wakeup PINx to get out of DEEPSTOP mode.
958 * @rmtoll CR3 EWU0 LL_PWR_DisableWakeUpPin\n
959 * CR3 EWU1 LL_PWR_DisableWakeUpPin\n
960 * CR3 EWU2 LL_PWR_DisableWakeUpPin\n
961 * CR3 EWU3 LL_PWR_DisableWakeUpPin\n
962 * CR3 EWU4 LL_PWR_DisableWakeUpPin\n
963 * CR3 EWU5 LL_PWR_DisableWakeUpPin\n
964 * CR3 EWU6 LL_PWR_DisableWakeUpPin\n
965 * CR3 EWU7 LL_PWR_DisableWakeUpPin\n
966 * CR3 EWU8 LL_PWR_DisableWakeUpPin\n
967 * CR3 EWU9 LL_PWR_DisableWakeUpPin\n
968 * CR3 EWU10 LL_PWR_DisableWakeUpPin\n
969 * CR3 EWU11 LL_PWR_DisableWakeUpPin\n
970 * CR6 EWU12 LL_PWR_DisableWakeUpPin\n
971 * CR6 EWU13 LL_PWR_DisableWakeUpPin\n
972 * CR6 EWU14 LL_PWR_DisableWakeUpPin\n
973 * CR6 EWU15 LL_PWR_DisableWakeUpPin\n
974 * CR6 EWU16 LL_PWR_DisableWakeUpPin\n
975 * CR6 EWU17 LL_PWR_DisableWakeUpPin\n
976 * CR6 EWU18 LL_PWR_DisableWakeUpPin\n
977 * CR6 EWU19 LL_PWR_DisableWakeUpPin\n
978 * CR6 EWU20 LL_PWR_DisableWakeUpPin\n
979 * CR6 EWU21 LL_PWR_DisableWakeUpPin\n
980 * CR6 EWU22 LL_PWR_DisableWakeUpPin\n
981 * CR6 EWU23 LL_PWR_DisableWakeUpPin\n
982 * CR6 EWU24 LL_PWR_DisableWakeUpPin\n
983 * CR6 EWU25 LL_PWR_DisableWakeUpPin\n
984 * CR6 EWU26 LL_PWR_DisableWakeUpPin\n
985 * CR6 EWU27 LL_PWR_DisableWakeUpPin
986 * @param WakeUpPin Enable the wakeup sources.
987 * This parameter can be a combination of the following values:
988 * @arg @ref LL_PWR_WAKEUP_PA0
989 * @arg @ref LL_PWR_WAKEUP_PA1
990 * @arg @ref LL_PWR_WAKEUP_PA2
991 * @arg @ref LL_PWR_WAKEUP_PA3
992 * @arg @ref LL_PWR_WAKEUP_PA4 (*)
993 * @arg @ref LL_PWR_WAKEUP_PA5 (*)
994 * @arg @ref LL_PWR_WAKEUP_PA6 (*)
995 * @arg @ref LL_PWR_WAKEUP_PA7 (*)
996 * @arg @ref LL_PWR_WAKEUP_PA8
997 * @arg @ref LL_PWR_WAKEUP_PA9
998 * @arg @ref LL_PWR_WAKEUP_PA10
999 * @arg @ref LL_PWR_WAKEUP_PA11
1000 * @arg @ref LL_PWR_WAKEUP_PA12 (*)
1001 * @arg @ref LL_PWR_WAKEUP_PA13 (*)
1002 * @arg @ref LL_PWR_WAKEUP_PA14 (*)
1003 * @arg @ref LL_PWR_WAKEUP_PA15 (*)
1004 * @arg @ref LL_PWR_WAKEUP_PB0
1005 * @arg @ref LL_PWR_WAKEUP_PB1
1006 * @arg @ref LL_PWR_WAKEUP_PB2
1007 * @arg @ref LL_PWR_WAKEUP_PB3
1008 * @arg @ref LL_PWR_WAKEUP_PB4
1009 * @arg @ref LL_PWR_WAKEUP_PB5
1010 * @arg @ref LL_PWR_WAKEUP_PB6
1011 * @arg @ref LL_PWR_WAKEUP_PB7
1012 * @arg @ref LL_PWR_WAKEUP_PB8 (*)
1013 * @arg @ref LL_PWR_WAKEUP_PB9 (*)
1014 * @arg @ref LL_PWR_WAKEUP_PB10 (*)
1015 * @arg @ref LL_PWR_WAKEUP_PB11 (*)
1016 * @arg @ref LL_PWR_WAKEUP_PB12 (**)
1017 * @arg @ref LL_PWR_WAKEUP_PB13 (**)
1018 * @arg @ref LL_PWR_WAKEUP_PB14 (**)
1019 * @arg @ref LL_PWR_WAKEUP_PB15 (**)
1020 * (*) available only on STM32WB06 and STM32WB07 devices
1021 * (**) available only on STM32WB05 and STM32WB09 devices
1022 * @retval None
1023 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1024 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1025 {
1026 CLEAR_BIT(PWR->CR3, (WakeUpPin & 0x0000FFFF));
1027 CLEAR_BIT(PWR->CR6, (WakeUpPin >> 16));
1028 }
1029
1030 /**
1031 * @brief Check if the WakeUp PINx functionality is enabled
1032 * @rmtoll CR3 EWU0 LL_PWR_IsEnabledWakeUpPin\n
1033 * CR3 EWU1 LL_PWR_IsEnabledWakeUpPin\n
1034 * CR3 EWU2 LL_PWR_IsEnabledWakeUpPin\n
1035 * CR3 EWU3 LL_PWR_IsEnabledWakeUpPin\n
1036 * CR3 EWU4 LL_PWR_IsEnabledWakeUpPin\n
1037 * CR3 EWU5 LL_PWR_IsEnabledWakeUpPin\n
1038 * CR3 EWU6 LL_PWR_IsEnabledWakeUpPin\n
1039 * CR3 EWU7 LL_PWR_IsEnabledWakeUpPin\n
1040 * CR3 EWU8 LL_PWR_IsEnabledWakeUpPin\n
1041 * CR3 EWU9 LL_PWR_IsEnabledWakeUpPin\n
1042 * CR3 EWU10 LL_PWR_IsEnabledWakeUpPin\n
1043 * CR3 EWU11 LL_PWR_IsEnabledWakeUpPin\n
1044 * CR6 EWU12 LL_PWR_IsEnabledWakeUpPin\n
1045 * CR6 EWU13 LL_PWR_IsEnabledWakeUpPin\n
1046 * CR6 EWU14 LL_PWR_IsEnabledWakeUpPin\n
1047 * CR6 EWU15 LL_PWR_IsEnabledWakeUpPin\n
1048 * CR6 EWU16 LL_PWR_IsEnabledWakeUpPin\n
1049 * CR6 EWU17 LL_PWR_IsEnabledWakeUpPin\n
1050 * CR6 EWU18 LL_PWR_IsEnabledWakeUpPin\n
1051 * CR6 EWU19 LL_PWR_IsEnabledWakeUpPin\n
1052 * CR6 EWU20 LL_PWR_IsEnabledWakeUpPin\n
1053 * CR6 EWU21 LL_PWR_IsEnabledWakeUpPin\n
1054 * CR6 EWU22 LL_PWR_IsEnabledWakeUpPin\n
1055 * CR6 EWU23 LL_PWR_IsEnabledWakeUpPin\n
1056 * CR6 EWU24 LL_PWR_IsEnabledWakeUpPin\n
1057 * CR6 EWU25 LL_PWR_IsEnabledWakeUpPin\n
1058 * CR6 EWU26 LL_PWR_IsEnabledWakeUpPin\n
1059 * CR6 EWU27 LL_PWR_IsEnabledWakeUpPin
1060 * @param WakeUpPin This parameter can be a combination of the following values:
1061 * @arg @ref LL_PWR_WAKEUP_PA0
1062 * @arg @ref LL_PWR_WAKEUP_PA1
1063 * @arg @ref LL_PWR_WAKEUP_PA2
1064 * @arg @ref LL_PWR_WAKEUP_PA3
1065 * @arg @ref LL_PWR_WAKEUP_PA4 (*)
1066 * @arg @ref LL_PWR_WAKEUP_PA5 (*)
1067 * @arg @ref LL_PWR_WAKEUP_PA6 (*)
1068 * @arg @ref LL_PWR_WAKEUP_PA7 (*)
1069 * @arg @ref LL_PWR_WAKEUP_PA8
1070 * @arg @ref LL_PWR_WAKEUP_PA9
1071 * @arg @ref LL_PWR_WAKEUP_PA10
1072 * @arg @ref LL_PWR_WAKEUP_PA11
1073 * @arg @ref LL_PWR_WAKEUP_PA12 (*)
1074 * @arg @ref LL_PWR_WAKEUP_PA13 (*)
1075 * @arg @ref LL_PWR_WAKEUP_PA14 (*)
1076 * @arg @ref LL_PWR_WAKEUP_PA15 (*)
1077 * @arg @ref LL_PWR_WAKEUP_PB0
1078 * @arg @ref LL_PWR_WAKEUP_PB1
1079 * @arg @ref LL_PWR_WAKEUP_PB2
1080 * @arg @ref LL_PWR_WAKEUP_PB3
1081 * @arg @ref LL_PWR_WAKEUP_PB4
1082 * @arg @ref LL_PWR_WAKEUP_PB5
1083 * @arg @ref LL_PWR_WAKEUP_PB6
1084 * @arg @ref LL_PWR_WAKEUP_PB7
1085 * @arg @ref LL_PWR_WAKEUP_PB8 (*)
1086 * @arg @ref LL_PWR_WAKEUP_PB9 (*)
1087 * @arg @ref LL_PWR_WAKEUP_PB10 (*)
1088 * @arg @ref LL_PWR_WAKEUP_PB11 (*)
1089 * @arg @ref LL_PWR_WAKEUP_PB12 (**)
1090 * @arg @ref LL_PWR_WAKEUP_PB13 (**)
1091 * @arg @ref LL_PWR_WAKEUP_PB14 (**)
1092 * @arg @ref LL_PWR_WAKEUP_PB15 (**)
1093 * (*) available only on STM32WB06 and STM32WB07 devices
1094 * (**) available only on STM32WB05 and STM32WB09 devices
1095 * @retval State of bit (1 or 0).
1096 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1097 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1098 {
1099 return ((READ_BIT(PWR->CR3, (WakeUpPin & 0x0000FFFF)) == (WakeUpPin & 0x0000FFFF)) &&
1100 (READ_BIT(PWR->CR6, (WakeUpPin >> 16)) == (WakeUpPin >> 16)) ? 1UL : 0UL);
1101 }
1102
1103 /**
1104 * @brief Set the Wake-Up pin polarity low for the event detection
1105 * @rmtoll CR4 WUP0 LL_PWR_SetWakeUpPinPolarityLow\n
1106 * CR4 WUP1 LL_PWR_SetWakeUpPinPolarityLow\n
1107 * CR4 WUP2 LL_PWR_SetWakeUpPinPolarityLow\n
1108 * CR4 WUP3 LL_PWR_SetWakeUpPinPolarityLow\n
1109 * CR4 WUP4 LL_PWR_SetWakeUpPinPolarityLow\n
1110 * CR4 WUP5 LL_PWR_SetWakeUpPinPolarityLow\n
1111 * CR4 WUP6 LL_PWR_SetWakeUpPinPolarityLow\n
1112 * CR4 WUP7 LL_PWR_SetWakeUpPinPolarityLow\n
1113 * CR4 WUP8 LL_PWR_SetWakeUpPinPolarityLow\n
1114 * CR4 WUP9 LL_PWR_SetWakeUpPinPolarityLow\n
1115 * CR4 WUP10 LL_PWR_SetWakeUpPinPolarityLow\n
1116 * CR4 WUP11 LL_PWR_SetWakeUpPinPolarityLow\n
1117 * CR7 WUP12 LL_PWR_SetWakeUpPinPolarityLow\n
1118 * CR7 WUP13 LL_PWR_SetWakeUpPinPolarityLow\n
1119 * CR7 WUP14 LL_PWR_SetWakeUpPinPolarityLow\n
1120 * CR7 WUP15 LL_PWR_SetWakeUpPinPolarityLow\n
1121 * CR7 WUP16 LL_PWR_SetWakeUpPinPolarityLow\n
1122 * CR7 WUP17 LL_PWR_SetWakeUpPinPolarityLow\n
1123 * CR7 WUP18 LL_PWR_SetWakeUpPinPolarityLow\n
1124 * CR7 WUP19 LL_PWR_SetWakeUpPinPolarityLow
1125 * @param WakeUpPin Pin to configure. This parameter can be a combination of the following values:
1126 * @arg @ref LL_PWR_WAKEUP_PA0
1127 * @arg @ref LL_PWR_WAKEUP_PA1
1128 * @arg @ref LL_PWR_WAKEUP_PA2
1129 * @arg @ref LL_PWR_WAKEUP_PA3
1130 * @arg @ref LL_PWR_WAKEUP_PA4 (*)
1131 * @arg @ref LL_PWR_WAKEUP_PA5 (*)
1132 * @arg @ref LL_PWR_WAKEUP_PA6 (*)
1133 * @arg @ref LL_PWR_WAKEUP_PA7 (*)
1134 * @arg @ref LL_PWR_WAKEUP_PA8
1135 * @arg @ref LL_PWR_WAKEUP_PA9
1136 * @arg @ref LL_PWR_WAKEUP_PA10
1137 * @arg @ref LL_PWR_WAKEUP_PA11
1138 * @arg @ref LL_PWR_WAKEUP_PA12 (*)
1139 * @arg @ref LL_PWR_WAKEUP_PA13 (*)
1140 * @arg @ref LL_PWR_WAKEUP_PA14 (*)
1141 * @arg @ref LL_PWR_WAKEUP_PA15 (*)
1142 * @arg @ref LL_PWR_WAKEUP_PB0
1143 * @arg @ref LL_PWR_WAKEUP_PB1
1144 * @arg @ref LL_PWR_WAKEUP_PB2
1145 * @arg @ref LL_PWR_WAKEUP_PB3
1146 * @arg @ref LL_PWR_WAKEUP_PB4
1147 * @arg @ref LL_PWR_WAKEUP_PB5
1148 * @arg @ref LL_PWR_WAKEUP_PB6
1149 * @arg @ref LL_PWR_WAKEUP_PB7
1150 * @arg @ref LL_PWR_WAKEUP_PB8 (*)
1151 * @arg @ref LL_PWR_WAKEUP_PB9 (*)
1152 * @arg @ref LL_PWR_WAKEUP_PB10 (*)
1153 * @arg @ref LL_PWR_WAKEUP_PB11 (*)
1154 * @arg @ref LL_PWR_WAKEUP_PB12 (**)
1155 * @arg @ref LL_PWR_WAKEUP_PB13 (**)
1156 * @arg @ref LL_PWR_WAKEUP_PB14 (**)
1157 * @arg @ref LL_PWR_WAKEUP_PB15 (**)
1158 * (*) available only on STM32WB06 and STM32WB07 devices
1159 * (**) available only on STM32WB05 and STM32WB09 devices
1160 * @retval None
1161 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1162 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1163 {
1164 SET_BIT(PWR->CR4, (WakeUpPin & 0x0000FFFF));
1165 SET_BIT(PWR->CR7, (WakeUpPin >> 16));
1166
1167 }
1168
1169 /**
1170 * @brief Set the Wake-Up pin polarity high for the event detection
1171 * @rmtoll CR4 WUP0 LL_PWR_SetWakeUpPinPolarityHigh\n
1172 * CR4 WUP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1173 * CR4 WUP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1174 * CR4 WUP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1175 * CR4 WUP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1176 * CR4 WUP5 LL_PWR_SetWakeUpPinPolarityHigh\n
1177 * CR4 WUP6 LL_PWR_SetWakeUpPinPolarityHigh\n
1178 * CR4 WUP7 LL_PWR_SetWakeUpPinPolarityHigh\n
1179 * CR4 WUP8 LL_PWR_SetWakeUpPinPolarityHigh\n
1180 * CR4 WUP9 LL_PWR_SetWakeUpPinPolarityHigh\n
1181 * CR4 WUP10 LL_PWR_SetWakeUpPinPolarityHigh\n
1182 * CR4 WUP11 LL_PWR_SetWakeUpPinPolarityHigh\n
1183 * CR7 WUP12 LL_PWR_SetWakeUpPinPolarityHigh\n
1184 * CR7 WUP13 LL_PWR_SetWakeUpPinPolarityHigh\n
1185 * CR7 WUP14 LL_PWR_SetWakeUpPinPolarityHigh\n
1186 * CR7 WUP15 LL_PWR_SetWakeUpPinPolarityHigh\n
1187 * CR7 WUP16 LL_PWR_SetWakeUpPinPolarityHigh\n
1188 * CR7 WUP17 LL_PWR_SetWakeUpPinPolarityHigh\n
1189 * CR7 WUP18 LL_PWR_SetWakeUpPinPolarityHigh\n
1190 * CR7 WUP19 LL_PWR_SetWakeUpPinPolarityHigh
1191 * @param WakeUpPin Pin to configure. This parameter can be a combination of the following values:
1192 * @arg @ref LL_PWR_WAKEUP_PA0
1193 * @arg @ref LL_PWR_WAKEUP_PA1
1194 * @arg @ref LL_PWR_WAKEUP_PA2
1195 * @arg @ref LL_PWR_WAKEUP_PA3
1196 * @arg @ref LL_PWR_WAKEUP_PA4 (*)
1197 * @arg @ref LL_PWR_WAKEUP_PA5 (*)
1198 * @arg @ref LL_PWR_WAKEUP_PA6 (*)
1199 * @arg @ref LL_PWR_WAKEUP_PA7 (*)
1200 * @arg @ref LL_PWR_WAKEUP_PA8
1201 * @arg @ref LL_PWR_WAKEUP_PA9
1202 * @arg @ref LL_PWR_WAKEUP_PA10
1203 * @arg @ref LL_PWR_WAKEUP_PA11
1204 * @arg @ref LL_PWR_WAKEUP_PA12 (*)
1205 * @arg @ref LL_PWR_WAKEUP_PA13 (*)
1206 * @arg @ref LL_PWR_WAKEUP_PA14 (*)
1207 * @arg @ref LL_PWR_WAKEUP_PA15 (*)
1208 * @arg @ref LL_PWR_WAKEUP_PB0
1209 * @arg @ref LL_PWR_WAKEUP_PB1
1210 * @arg @ref LL_PWR_WAKEUP_PB2
1211 * @arg @ref LL_PWR_WAKEUP_PB3
1212 * @arg @ref LL_PWR_WAKEUP_PB4
1213 * @arg @ref LL_PWR_WAKEUP_PB5
1214 * @arg @ref LL_PWR_WAKEUP_PB6
1215 * @arg @ref LL_PWR_WAKEUP_PB7
1216 * @arg @ref LL_PWR_WAKEUP_PB8 (*)
1217 * @arg @ref LL_PWR_WAKEUP_PB9 (*)
1218 * @arg @ref LL_PWR_WAKEUP_PB10 (*)
1219 * @arg @ref LL_PWR_WAKEUP_PB11 (*)
1220 * @arg @ref LL_PWR_WAKEUP_PB12 (**)
1221 * @arg @ref LL_PWR_WAKEUP_PB13 (**)
1222 * @arg @ref LL_PWR_WAKEUP_PB14 (**)
1223 * @arg @ref LL_PWR_WAKEUP_PB15 (**)
1224 * (*) available only on STM32WB06 and STM32WB07 devices
1225 * (**) available only on STM32WB05 and STM32WB09 devices
1226 * @retval None
1227 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1228 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1229 {
1230 CLEAR_BIT(PWR->CR4, (WakeUpPin & 0x0000FFFF));
1231 CLEAR_BIT(PWR->CR7, (WakeUpPin >> 16));
1232
1233 }
1234
1235 /**
1236 * @brief Get the polarity for the I/Os wakeup sources.
1237 * @rmtoll CR4 WUP0 LL_PWR_IsWakeUpPinPolarityLow\n
1238 * CR4 WUP1 LL_PWR_IsWakeUpPinPolarityLow\n
1239 * CR4 WUP2 LL_PWR_IsWakeUpPinPolarityLow\n
1240 * CR4 WUP3 LL_PWR_IsWakeUpPinPolarityLow\n
1241 * CR4 WUP4 LL_PWR_IsWakeUpPinPolarityLow\n
1242 * CR4 WUP5 LL_PWR_IsWakeUpPinPolarityLow\n
1243 * CR4 WUP6 LL_PWR_IsWakeUpPinPolarityLow\n
1244 * CR4 WUP7 LL_PWR_IsWakeUpPinPolarityLow\n
1245 * CR4 WUP8 LL_PWR_IsWakeUpPinPolarityLow\n
1246 * CR4 WUP9 LL_PWR_IsWakeUpPinPolarityLow\n
1247 * CR4 WUP10 LL_PWR_IsWakeUpPinPolarityLow\n
1248 * CR4 WUP11 LL_PWR_IsWakeUpPinPolarityLow\n
1249 * CR7 WUP12 LL_PWR_IsWakeUpPinPolarityLow\n
1250 * CR7 WUP13 LL_PWR_IsWakeUpPinPolarityLow\n
1251 * CR7 WUP14 LL_PWR_IsWakeUpPinPolarityLow\n
1252 * CR7 WUP15 LL_PWR_IsWakeUpPinPolarityLow\n
1253 * CR7 WUP16 LL_PWR_IsWakeUpPinPolarityLow\n
1254 * CR7 WUP17 LL_PWR_IsWakeUpPinPolarityLow\n
1255 * CR7 WUP18 LL_PWR_IsWakeUpPinPolarityLow\n
1256 * CR7 WUP19 LL_PWR_IsWakeUpPinPolarityLow
1257 * @param WakeUpPin Pin to configure. This parameter can be a combination of the following values:
1258 * @arg @ref LL_PWR_WAKEUP_PA0
1259 * @arg @ref LL_PWR_WAKEUP_PA1
1260 * @arg @ref LL_PWR_WAKEUP_PA2
1261 * @arg @ref LL_PWR_WAKEUP_PA3
1262 * @arg @ref LL_PWR_WAKEUP_PA4 (*)
1263 * @arg @ref LL_PWR_WAKEUP_PA5 (*)
1264 * @arg @ref LL_PWR_WAKEUP_PA6 (*)
1265 * @arg @ref LL_PWR_WAKEUP_PA7 (*)
1266 * @arg @ref LL_PWR_WAKEUP_PA8
1267 * @arg @ref LL_PWR_WAKEUP_PA9
1268 * @arg @ref LL_PWR_WAKEUP_PA10
1269 * @arg @ref LL_PWR_WAKEUP_PA11
1270 * @arg @ref LL_PWR_WAKEUP_PA12 (*)
1271 * @arg @ref LL_PWR_WAKEUP_PA13 (*)
1272 * @arg @ref LL_PWR_WAKEUP_PA14 (*)
1273 * @arg @ref LL_PWR_WAKEUP_PA15 (*)
1274 * @arg @ref LL_PWR_WAKEUP_PB0
1275 * @arg @ref LL_PWR_WAKEUP_PB1
1276 * @arg @ref LL_PWR_WAKEUP_PB2
1277 * @arg @ref LL_PWR_WAKEUP_PB3
1278 * @arg @ref LL_PWR_WAKEUP_PB4
1279 * @arg @ref LL_PWR_WAKEUP_PB5
1280 * @arg @ref LL_PWR_WAKEUP_PB6
1281 * @arg @ref LL_PWR_WAKEUP_PB7
1282 * @arg @ref LL_PWR_WAKEUP_PB8 (*)
1283 * @arg @ref LL_PWR_WAKEUP_PB9 (*)
1284 * @arg @ref LL_PWR_WAKEUP_PB10 (*)
1285 * @arg @ref LL_PWR_WAKEUP_PB11 (*)
1286 * @arg @ref LL_PWR_WAKEUP_PB12 (**)
1287 * @arg @ref LL_PWR_WAKEUP_PB13 (**)
1288 * @arg @ref LL_PWR_WAKEUP_PB14 (**)
1289 * @arg @ref LL_PWR_WAKEUP_PB15 (**)
1290 * (*) available only on STM32WB06 and STM32WB07 devices
1291 * (**) available only on STM32WB05 and STM32WB09 devices
1292 * @retval None
1293 * @retval State of bit (1 or 0).
1294 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1295 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1296 {
1297 if (WakeUpPin & 0x0000FFFF)
1298 {
1299 return (uint32_t)((READ_BIT(PWR->CR4, (WakeUpPin & 0x0000FFFF))) ? 1UL : 0UL);
1300 }
1301 else
1302 {
1303 return (uint32_t)((READ_BIT(PWR->CR7, (WakeUpPin >> 16))) ? 1UL : 0UL);
1304 }
1305
1306 }
1307
1308 /**
1309 * @brief Enable wakeup on BLE event.
1310 * @rmtoll CR3 EWBLE LL_PWR_EnableWU_EWBLE
1311 * @retval None
1312 */
LL_PWR_EnableWU_EWBLE(void)1313 __STATIC_INLINE void LL_PWR_EnableWU_EWBLE(void)
1314 {
1315 SET_BIT(PWR->CR3, PWR_CR3_EWBLE);
1316 }
1317
1318 /**
1319 * @brief Enable wakeup on BLE Host CPU event.
1320 * @rmtoll CR3 EWBLEHCPU LL_PWR_EnableWU_EWBLEHCPU
1321 * @retval None
1322 */
LL_PWR_EnableWU_EWBLEHCPU(void)1323 __STATIC_INLINE void LL_PWR_EnableWU_EWBLEHCPU(void)
1324 {
1325 SET_BIT(PWR->CR3, PWR_CR3_EWBLEHCPU);
1326 }
1327
1328 /**
1329 * @brief Disable wakeup on BLE Host CPU event.
1330 * @rmtoll CR3 EWBLE LL_PWR_DisableWU_EWBLE
1331 * @retval None
1332 */
LL_PWR_DisableWU_EWBLE(void)1333 __STATIC_INLINE void LL_PWR_DisableWU_EWBLE(void)
1334 {
1335 CLEAR_BIT(PWR->CR3, PWR_CR3_EWBLE);
1336 }
1337
1338 /**
1339 * @brief Disable wakeup on BLE Host CPU event.
1340 * @rmtoll CR3 EWBLEHCPU LL_PWR_DisableWU_EWBLEHCPU
1341 * @retval None
1342 */
LL_PWR_DisableWU_EWBLEHCPU(void)1343 __STATIC_INLINE void LL_PWR_DisableWU_EWBLEHCPU(void)
1344 {
1345 CLEAR_BIT(PWR->CR3, PWR_CR3_EWBLEHCPU);
1346 }
1347
1348 /**
1349 * @brief Check if the wakeup BLE is enabled
1350 * @rmtoll CR3 EWBLE LL_PWR_IsEnabledWU_EWBLE
1351 * @retval State of bit (1 or 0).
1352 */
LL_PWR_IsEnabledWU_EWBLE(void)1353 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWU_EWBLE(void)
1354 {
1355 return ((READ_BIT(PWR->CR3, PWR_CR3_EWBLE) == (PWR_CR3_EWBLE)) ? 1UL : 0UL);
1356 }
1357
1358 /**
1359 * @brief Check if the wakeup BLE Host CPU is enabled
1360 * @rmtoll CR3 EWBLEHCPU LL_PWR_IsEnabledWU_EWBLEHCPU
1361 * @retval State of bit (1 or 0).
1362 */
LL_PWR_IsEnabledWU_EWBLEHCPU(void)1363 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWU_EWBLEHCPU(void)
1364 {
1365 return ((READ_BIT(PWR->CR3, PWR_CR3_EWBLEHCPU) == (PWR_CR3_EWBLEHCPU)) ? 1UL : 0UL);
1366 }
1367
1368 /**
1369 * @}
1370 */
1371
1372 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1373 * @{
1374 */
1375
1376 /**
1377 * @brief Get Internal Wake-up line Flag (RTC)
1378 * @rmtoll SR1 IWUF LL_PWR_IsActiveFlag_InternWU
1379 * @retval State of bit (1 or 0).
1380 */
LL_PWR_IsActiveFlag_InternWU(void)1381 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1382 {
1383 return ((READ_BIT(PWR->SR1, PWR_SR1_IWUF) == (PWR_SR1_IWUF)) ? 1UL : 0UL);
1384 }
1385
1386 #if defined(PWR_CR3_EIWL2)
1387 /**
1388 * @brief Get Internal Wake-up line Flag (LPUART)
1389 * @rmtoll SR1 IWUF2 LL_PWR_IsActiveFlag_InternWU2
1390 * @retval State of bit (1 or 0).
1391 */
LL_PWR_IsActiveFlag_InternWU2(void)1392 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU2(void)
1393 {
1394 return ((READ_BIT(PWR->SR1, PWR_SR1_IWUF2) == (PWR_SR1_IWUF2)) ? 1UL : 0UL);
1395 }
1396 #endif /* PWR_CR3_EIWL2 */
1397
1398 /**
1399 * @brief Get Wake-up Flag 0
1400 * @rmtoll SR1 WUF0 LL_PWR_IsActiveFlag_WU0
1401 * @retval State of bit (1 or 0).
1402 */
LL_PWR_IsActiveFlag_WU0(void)1403 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU0(void)
1404 {
1405 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF0) == (PWR_SR1_WUF0)) ? 1UL : 0UL);
1406 }
1407
1408 /**
1409 * @brief Get Wake-up Flag 1
1410 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1411 * @retval State of bit (1 or 0).
1412 */
LL_PWR_IsActiveFlag_WU1(void)1413 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1414 {
1415 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1416 }
1417
1418 /**
1419 * @brief Get Wake-up Flag 2
1420 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1421 * @retval State of bit (1 or 0).
1422 */
LL_PWR_IsActiveFlag_WU2(void)1423 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1424 {
1425 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1426 }
1427 /**
1428 * @brief Get Wake-up Flag 3
1429 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1430 * @retval State of bit (1 or 0).
1431 */
LL_PWR_IsActiveFlag_WU3(void)1432 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1433 {
1434 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1435 }
1436
1437 /**
1438 * @brief Get Wake-up Flag 4
1439 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1440 * @retval State of bit (1 or 0).
1441 */
LL_PWR_IsActiveFlag_WU4(void)1442 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1443 {
1444 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1445 }
1446
1447 /**
1448 * @brief Get Wake-up Flag 5
1449 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1450 * @retval State of bit (1 or 0).
1451 */
LL_PWR_IsActiveFlag_WU5(void)1452 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1453 {
1454 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1455 }
1456
1457 /**
1458 * @brief Get Wake-up Flag 6
1459 * @rmtoll SR1 WUF6 LL_PWR_IsActiveFlag_WU6
1460 * @retval State of bit (1 or 0).
1461 */
LL_PWR_IsActiveFlag_WU6(void)1462 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
1463 {
1464 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL);
1465 }
1466
1467 /**
1468 * @brief Get Wake-up Flag 7
1469 * @rmtoll SR1 WUF7 LL_PWR_IsActiveFlag_WU7
1470 * @retval State of bit (1 or 0).
1471 */
LL_PWR_IsActiveFlag_WU7(void)1472 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
1473 {
1474 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF7) == (PWR_SR1_WUF7)) ? 1UL : 0UL);
1475 }
1476
1477 /**
1478 * @brief Get Wake-up Flag 8
1479 * @rmtoll SR1 WUF8 LL_PWR_IsActiveFlag_WU8
1480 * @retval State of bit (1 or 0).
1481 */
LL_PWR_IsActiveFlag_WU8(void)1482 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
1483 {
1484 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF8) == (PWR_SR1_WUF8)) ? 1UL : 0UL);
1485 }
1486
1487 /**
1488 * @brief Get Wake-up Flag 9
1489 * @rmtoll SR1 WUF9 LL_PWR_IsActiveFlag_WU9
1490 * @retval State of bit (1 or 0).
1491 */
LL_PWR_IsActiveFlag_WU9(void)1492 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU9(void)
1493 {
1494 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF9) == (PWR_SR1_WUF9)) ? 1UL : 0UL);
1495 }
1496
1497 /**
1498 * @brief Get Wake-up Flag 10
1499 * @rmtoll SR1 WUF10 LL_PWR_IsActiveFlag_WU10
1500 * @retval State of bit (1 or 0).
1501 */
LL_PWR_IsActiveFlag_WU10(void)1502 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU10(void)
1503 {
1504 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF10) == (PWR_SR1_WUF10)) ? 1UL : 0UL);
1505 }
1506
1507 /**
1508 * @brief Get Wake-up Flag 11
1509 * @rmtoll SR1 WUF11 LL_PWR_IsActiveFlag_WU11
1510 * @retval State of bit (1 or 0).
1511 */
LL_PWR_IsActiveFlag_WU11(void)1512 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU11(void)
1513 {
1514 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF11) == (PWR_SR1_WUF11)) ? 1UL : 0UL);
1515 }
1516
1517 /**
1518 * @brief Get Wake-up Flag 12
1519 * @rmtoll SR3 WUF12 LL_PWR_IsActiveFlag_WU12
1520 * @retval State of bit (1 or 0).
1521 */
LL_PWR_IsActiveFlag_WU12(void)1522 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU12(void)
1523 {
1524 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF12) == (PWR_SR3_WUF12)) ? 1UL : 0UL);
1525 }
1526
1527 /**
1528 * @brief Get Wake-up Flag 13
1529 * @rmtoll SR3 WUF13 LL_PWR_IsActiveFlag_WU13
1530 * @retval State of bit (1 or 0).
1531 */
LL_PWR_IsActiveFlag_WU13(void)1532 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU13(void)
1533 {
1534 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF13) == (PWR_SR3_WUF13)) ? 1UL : 0UL);
1535 }
1536
1537 /**
1538 * @brief Get Wake-up Flag 14
1539 * @rmtoll SR3 WUF14 LL_PWR_IsActiveFlag_WU14
1540 * @retval State of bit (1 or 0).
1541 */
LL_PWR_IsActiveFlag_WU14(void)1542 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU14(void)
1543 {
1544 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF14) == (PWR_SR3_WUF14)) ? 1UL : 0UL);
1545 }
1546
1547 /**
1548 * @brief Get Wake-up Flag 15
1549 * @rmtoll SR3 WUF15 LL_PWR_IsActiveFlag_WU15
1550 * @retval State of bit (1 or 0).
1551 */
LL_PWR_IsActiveFlag_WU15(void)1552 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU15(void)
1553 {
1554 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF15) == (PWR_SR3_WUF15)) ? 1UL : 0UL);
1555 }
1556
1557 /**
1558 * @brief Get Wake-up Flag 16
1559 * @rmtoll SR3 WUF16 LL_PWR_IsActiveFlag_WU16
1560 * @retval State of bit (1 or 0).
1561 */
LL_PWR_IsActiveFlag_WU16(void)1562 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU16(void)
1563 {
1564 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF16) == (PWR_SR3_WUF16)) ? 1UL : 0UL);
1565 }
1566
1567 /**
1568 * @brief Get Wake-up Flag 17
1569 * @rmtoll SR3 WUF17 LL_PWR_IsActiveFlag_WU17
1570 * @retval State of bit (1 or 0).
1571 */
LL_PWR_IsActiveFlag_WU17(void)1572 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU17(void)
1573 {
1574 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF17) == (PWR_SR3_WUF17)) ? 1UL : 0UL);
1575 }
1576
1577 /**
1578 * @brief Get Wake-up Flag 18
1579 * @rmtoll SR3 WUF18 LL_PWR_IsActiveFlag_WU18
1580 * @retval State of bit (1 or 0).
1581 */
LL_PWR_IsActiveFlag_WU18(void)1582 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU18(void)
1583 {
1584 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF18) == (PWR_SR3_WUF18)) ? 1UL : 0UL);
1585 }
1586
1587 /**
1588 * @brief Get Wake-up Flag 19
1589 * @rmtoll SR3 WUF19 LL_PWR_IsActiveFlag_WU19
1590 * @retval State of bit (1 or 0).
1591 */
LL_PWR_IsActiveFlag_WU19(void)1592 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU19(void)
1593 {
1594 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF19) == (PWR_SR3_WUF19)) ? 1UL : 0UL);
1595 }
1596
1597 #if defined (PWR_CR6_EWU20)
1598 /**
1599 * @brief Get Wake-up Flag 20
1600 * @rmtoll SR3 WUF20 LL_PWR_IsActiveFlag_WU20
1601 * @retval State of bit (1 or 0).
1602 */
LL_PWR_IsActiveFlag_WU20(void)1603 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU20(void)
1604 {
1605 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF20) == (PWR_SR3_WUF20)) ? 1UL : 0UL);
1606 }
1607 #endif /* PWR_CR6_EWU20 */
1608
1609 #if defined (PWR_CR6_EWU21)
1610 /**
1611 * @brief Get Wake-up Flag 21
1612 * @rmtoll SR3 WUF21 LL_PWR_IsActiveFlag_WU21
1613 * @retval State of bit (1 or 0).
1614 */
LL_PWR_IsActiveFlag_WU21(void)1615 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU21(void)
1616 {
1617 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF21) == (PWR_SR3_WUF21)) ? 1UL : 0UL);
1618 }
1619 #endif /* PWR_CR6_EWU21 */
1620
1621 #if defined (PWR_CR6_EWU22)
1622 /**
1623 * @brief Get Wake-up Flag 22
1624 * @rmtoll SR3 WUF22 LL_PWR_IsActiveFlag_WU22
1625 * @retval State of bit (1 or 0).
1626 */
LL_PWR_IsActiveFlag_WU22(void)1627 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU22(void)
1628 {
1629 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF22) == (PWR_SR3_WUF22)) ? 1UL : 0UL);
1630 }
1631 #endif /* PWR_CR6_EWU22 */
1632
1633 #if defined (PWR_CR6_EWU23)
1634 /**
1635 * @brief Get Wake-up Flag 23
1636 * @rmtoll SR3 WUF23 LL_PWR_IsActiveFlag_WU23
1637 * @retval State of bit (1 or 0).
1638 */
LL_PWR_IsActiveFlag_WU23(void)1639 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU23(void)
1640 {
1641 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF23) == (PWR_SR3_WUF23)) ? 1UL : 0UL);
1642 }
1643 #endif /* PWR_CR6_EWU23 */
1644
1645 #if defined (PWR_CR6_EWU24)
1646 /**
1647 * @brief Get Wake-up Flag 24
1648 * @rmtoll SR3 WUF24 LL_PWR_IsActiveFlag_WU23
1649 * @retval State of bit (1 or 0).
1650 */
LL_PWR_IsActiveFlag_WU24(void)1651 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU24(void)
1652 {
1653 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF24) == (PWR_SR3_WUF24)) ? 1UL : 0UL);
1654 }
1655 #endif /* PWR_CR6_EWU24 */
1656
1657 #if defined (PWR_CR6_EWU25)
1658 /**
1659 * @brief Get Wake-up Flag 23
1660 * @rmtoll SR3 WUF25 LL_PWR_IsActiveFlag_WU25
1661 * @retval State of bit (1 or 0).
1662 */
LL_PWR_IsActiveFlag_WU25(void)1663 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU25(void)
1664 {
1665 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF25) == (PWR_SR3_WUF25)) ? 1UL : 0UL);
1666 }
1667 #endif /* PWR_CR6_EWU25 */
1668
1669 #if defined (PWR_CR6_EWU26)
1670 /**
1671 * @brief Get Wake-up Flag 26
1672 * @rmtoll SR3 WUF26 LL_PWR_IsActiveFlag_WU26
1673 * @retval State of bit (1 or 0).
1674 */
LL_PWR_IsActiveFlag_WU26(void)1675 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU26(void)
1676 {
1677 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF26) == (PWR_SR3_WUF26)) ? 1UL : 0UL);
1678 }
1679 #endif /* PWR_CR6_EWU26 */
1680
1681 #if defined (PWR_CR6_EWU27)
1682 /**
1683 * @brief Get Wake-up Flag 27
1684 * @rmtoll SR3 WUF27 LL_PWR_IsActiveFlag_WU27
1685 * @retval State of bit (1 or 0).
1686 */
LL_PWR_IsActiveFlag_WU27(void)1687 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU27(void)
1688 {
1689 return ((READ_BIT(PWR->SR3, PWR_SR3_WUF27) == (PWR_SR3_WUF27)) ? 1UL : 0UL);
1690 }
1691 #endif /* PWR_CR6_EWU27 */
1692
1693 /**
1694 * @brief Get which source woken up the device after a DEEPSTOP.
1695 * @rmtoll SR1 WUFI LL_PWR_GetWakeupSource\n
1696 * SR1 WUFI2 LL_PWR_GetWakeupSource\n
1697 * SR1 BHWF LL_PWR_GetWakeupSource\n
1698 * SR1 WBLEF LL_PWR_GetWakeupSource\n
1699 * SR1 WUF0 LL_PWR_GetWakeupSource\n
1700 * SR1 WUF1 LL_PWR_GetWakeupSource\n
1701 * SR1 WUF2 LL_PWR_GetWakeupSource\n
1702 * SR1 WUF3 LL_PWR_GetWakeupSource\n
1703 * SR1 WUF4 LL_PWR_GetWakeupSource\n
1704 * SR1 WUF5 LL_PWR_GetWakeupSource\n
1705 * SR1 WUF6 LL_PWR_GetWakeupSource\n
1706 * SR1 WUF7 LL_PWR_GetWakeupSource\n
1707 * SR1 WUF8 LL_PWR_GetWakeupSource\n
1708 * SR1 WUF9 LL_PWR_GetWakeupSource\n
1709 * SR1 WUF10 LL_PWR_GetWakeupSource\n
1710 * SR1 WUF11 LL_PWR_GetWakeupSource\n
1711 * SR3 WUF12 LL_PWR_GetWakeupSource\n
1712 * SR3 WUF13 LL_PWR_GetWakeupSource\n
1713 * SR3 WUF14 LL_PWR_GetWakeupSource\n
1714 * SR3 WUF15 LL_PWR_GetWakeupSource\n
1715 * SR3 WUF16 LL_PWR_GetWakeupSource\n
1716 * SR3 WUF17 LL_PWR_GetWakeupSource\n
1717 * SR3 WUF18 LL_PWR_GetWakeupSource\n
1718 * SR3 WUF19 LL_PWR_GetWakeupSource\n
1719 * SR3 WUF20 LL_PWR_GetWakeupSource\n
1720 * SR3 WUF21 LL_PWR_GetWakeupSource\n
1721 * SR3 WUF22 LL_PWR_GetWakeupSource\n
1722 * SR3 WUF23 LL_PWR_GetWakeupSource\n
1723 * SR3 WUF24 LL_PWR_GetWakeupSource\n
1724 * SR3 WUF25 LL_PWR_GetWakeupSource\n
1725 * SR3 WUF26 LL_PWR_GetWakeupSource\n
1726 * SR3 WUF27 LL_PWR_GetWakeupSource
1727 * @retval Wakeup Source from DEEPSTOP. This parameter can be a combination of the following values:
1728 * @arg @ref LL_PWR_SR1_WUFI
1729 * @arg @ref LL_PWR_SR1_WUFI2 (**)
1730 * @arg @ref LL_PWR_SR1_BHWF
1731 * @arg @ref LL_PWR_SR1_WBLEF
1732 * @arg @ref LL_PWR_SR1_WUF0
1733 * @arg @ref LL_PWR_SR1_WUF1
1734 * @arg @ref LL_PWR_SR1_WUF2
1735 * @arg @ref LL_PWR_SR1_WUF3
1736 * @arg @ref LL_PWR_SR1_WUF4
1737 * @arg @ref LL_PWR_SR1_WUF5
1738 * @arg @ref LL_PWR_SR1_WUF6
1739 * @arg @ref LL_PWR_SR1_WUF7
1740 * @arg @ref LL_PWR_SR1_WUF8
1741 * @arg @ref LL_PWR_SR1_WUF9
1742 * @arg @ref LL_PWR_SR1_WUF10
1743 * @arg @ref LL_PWR_SR1_WUF11
1744 * @arg @ref LL_PWR_SR3_WUF12
1745 * @arg @ref LL_PWR_SR3_WUF13
1746 * @arg @ref LL_PWR_SR3_WUF14
1747 * @arg @ref LL_PWR_SR3_WUF15
1748 * @arg @ref LL_PWR_SR3_WUF16
1749 * @arg @ref LL_PWR_SR3_WUF17
1750 * @arg @ref LL_PWR_SR3_WUF18
1751 * @arg @ref LL_PWR_SR3_WUF19
1752 * @arg @ref LL_PWR_SR3_WUF20 (*)
1753 * @arg @ref LL_PWR_SR3_WUF21 (*)
1754 * @arg @ref LL_PWR_SR3_WUF22 (*)
1755 * @arg @ref LL_PWR_SR3_WUF23 (*)
1756 * @arg @ref LL_PWR_SR3_WUF24 (*)
1757 * @arg @ref LL_PWR_SR3_WUF25 (*)
1758 * @arg @ref LL_PWR_SR3_WUF26 (*)
1759 * @arg @ref LL_PWR_SR3_WUF27 (*)
1760 * (*) Not available on devices STM32WB05 and STM32WB09
1761 * (**) Not available on devices STM32WB07
1762 */
LL_PWR_GetWakeupSource(void)1763 __STATIC_INLINE uint32_t LL_PWR_GetWakeupSource(void)
1764 {
1765 uint32_t wakeup_source;
1766
1767 wakeup_source = READ_REG(PWR->SR1) & 0x0000FFFF;
1768 return (uint32_t)(wakeup_source | (READ_REG(PWR->SR3) << 16));
1769 }
1770
1771 /**
1772 * @brief Clear Wake-up Flags.
1773 * @rmtoll SR1 WUFI2 LL_PWR_ClearFlag_WU\n
1774 * SR1 BHWF LL_PWR_ClearFlag_WU\n
1775 * SR1 WBLEF LL_PWR_ClearFlag_WU\n
1776 * SR1 WUF0 LL_PWR_ClearFlag_WU\n
1777 * SR1 WUF1 LL_PWR_ClearFlag_WU\n
1778 * SR1 WUF2 LL_PWR_ClearFlag_WU\n
1779 * SR1 WUF3 LL_PWR_ClearFlag_WU\n
1780 * SR1 WUF4 LL_PWR_ClearFlag_WU\n
1781 * SR1 WUF5 LL_PWR_ClearFlag_WU\n
1782 * SR1 WUF6 LL_PWR_ClearFlag_WU\n
1783 * SR1 WUF7 LL_PWR_ClearFlag_WU\n
1784 * SR1 WUF8 LL_PWR_ClearFlag_WU\n
1785 * SR1 WUF9 LL_PWR_ClearFlag_WU\n
1786 * SR1 WUF10 LL_PWR_ClearFlag_WU\n
1787 * SR1 WUF11 LL_PWR_ClearFlag_WU\n
1788 * SR3 WUF12 LL_PWR_ClearFlag_WU\n
1789 * SR3 WUF13 LL_PWR_ClearFlag_WU\n
1790 * SR3 WUF14 LL_PWR_ClearFlag_WU\n
1791 * SR3 WUF15 LL_PWR_ClearFlag_WU\n
1792 * SR3 WUF16 LL_PWR_ClearFlag_WU\n
1793 * SR3 WUF17 LL_PWR_ClearFlag_WU\n
1794 * SR3 WUF18 LL_PWR_ClearFlag_WU\n
1795 * SR3 WUF19 LL_PWR_ClearFlag_WU\n
1796 * SR3 WUF20 LL_PWR_ClearFlag_WU\n
1797 * SR3 WUF21 LL_PWR_ClearFlag_WU\n
1798 * SR3 WUF22 LL_PWR_ClearFlag_WU\n
1799 * SR3 WUF23 LL_PWR_ClearFlag_WU\n
1800 * SR3 WUF24 LL_PWR_ClearFlag_WU\n
1801 * SR3 WUF25 LL_PWR_ClearFlag_WU\n
1802 * SR3 WUF26 LL_PWR_ClearFlag_WU\n
1803 * SR3 WUF27 LL_PWR_ClearFlag_WU
1804 * @param source Wakeup Source from DEEPSTOP. This parameter can be a combination of the following values:
1805 * @arg @ref LL_PWR_SR1_WUFI2 (**)
1806 * @arg @ref LL_PWR_SR1_BHWF
1807 * @arg @ref LL_PWR_SR1_WBLEF
1808 * @arg @ref LL_PWR_SR1_WUF0
1809 * @arg @ref LL_PWR_SR1_WUF1
1810 * @arg @ref LL_PWR_SR1_WUF2
1811 * @arg @ref LL_PWR_SR1_WUF3
1812 * @arg @ref LL_PWR_SR1_WUF4
1813 * @arg @ref LL_PWR_SR1_WUF5
1814 * @arg @ref LL_PWR_SR1_WUF6
1815 * @arg @ref LL_PWR_SR1_WUF7
1816 * @arg @ref LL_PWR_SR1_WUF8
1817 * @arg @ref LL_PWR_SR1_WUF9
1818 * @arg @ref LL_PWR_SR1_WUF10
1819 * @arg @ref LL_PWR_SR1_WUF11
1820 * @arg @ref LL_PWR_SR3_WUF12
1821 * @arg @ref LL_PWR_SR3_WUF13
1822 * @arg @ref LL_PWR_SR3_WUF14
1823 * @arg @ref LL_PWR_SR3_WUF15
1824 * @arg @ref LL_PWR_SR3_WUF16
1825 * @arg @ref LL_PWR_SR3_WUF17
1826 * @arg @ref LL_PWR_SR3_WUF18
1827 * @arg @ref LL_PWR_SR3_WUF19
1828 * @arg @ref LL_PWR_SR3_WUF20 (*)
1829 * @arg @ref LL_PWR_SR3_WUF21 (*)
1830 * @arg @ref LL_PWR_SR3_WUF22 (*)
1831 * @arg @ref LL_PWR_SR3_WUF23 (*)
1832 * @arg @ref LL_PWR_SR3_WUF24 (*)
1833 * @arg @ref LL_PWR_SR3_WUF25 (*)
1834 * @arg @ref LL_PWR_SR3_WUF26 (*)
1835 * @arg @ref LL_PWR_SR3_WUF27 (*)
1836 * (*) Not available on devices STM32WB05 and STM32WB09
1837 * (**) Not available on devices STM32WB07
1838 * @retval None
1839 */
LL_PWR_ClearWakeupSource(uint32_t source)1840 __STATIC_INLINE void LL_PWR_ClearWakeupSource(uint32_t source)
1841 {
1842 WRITE_REG(PWR->SR1, (source & 0x0000FFFF));
1843 WRITE_REG(PWR->SR3, (source >> 16));
1844 }
1845
1846 /**
1847 * @brief Clear Wake-up Flag 0.
1848 * @rmtoll SR1 WUF0 LL_PWR_ClearFlag_WU0
1849 * @retval None
1850 */
LL_PWR_ClearFlag_WU0()1851 __STATIC_INLINE void LL_PWR_ClearFlag_WU0()
1852 {
1853 WRITE_REG(PWR->SR1, PWR_SR1_WUF0);
1854 }
1855
1856 /**
1857 * @brief Clear Wake-up Flag 1.
1858 * @rmtoll SR1 WUF1 LL_PWR_ClearFlag_WU1
1859 * @retval None
1860 */
LL_PWR_ClearFlag_WU1()1861 __STATIC_INLINE void LL_PWR_ClearFlag_WU1()
1862 {
1863 WRITE_REG(PWR->SR1, PWR_SR1_WUF1);
1864 }
1865
1866
1867 /**
1868 * @brief Clear Wake-up Flag 2.
1869 * @rmtoll SR1 WUF2 LL_PWR_ClearFlag_WU2
1870 * @retval None
1871 */
LL_PWR_ClearFlag_WU2()1872 __STATIC_INLINE void LL_PWR_ClearFlag_WU2()
1873 {
1874 WRITE_REG(PWR->SR1, PWR_SR1_WUF2);
1875 }
1876
1877 /**
1878 * @brief Clear Wake-up Flag 3.
1879 * @rmtoll SR1 WUF3 LL_PWR_ClearFlag_WU3
1880 * @retval None
1881 */
LL_PWR_ClearFlag_WU3()1882 __STATIC_INLINE void LL_PWR_ClearFlag_WU3()
1883 {
1884 WRITE_REG(PWR->SR1, PWR_SR1_WUF3);
1885 }
1886
1887 /**
1888 * @brief Clear Wake-up Flag 4.
1889 * @rmtoll SR1 WUF4 LL_PWR_ClearFlag_WU4
1890 * @retval None
1891 */
LL_PWR_ClearFlag_WU4()1892 __STATIC_INLINE void LL_PWR_ClearFlag_WU4()
1893 {
1894 WRITE_REG(PWR->SR1, PWR_SR1_WUF4);
1895 }
1896
1897 /**
1898 * @brief Clear Wake-up Flag 5.
1899 * @rmtoll SR1 WUF5 LL_PWR_ClearFlag_WU5
1900 * @retval None
1901 */
LL_PWR_ClearFlag_WU5()1902 __STATIC_INLINE void LL_PWR_ClearFlag_WU5()
1903 {
1904 WRITE_REG(PWR->SR1, PWR_SR1_WUF5);
1905 }
1906
1907 /**
1908 * @brief Clear Wake-up Flag 6.
1909 * @rmtoll SR1 WUF6 LL_PWR_ClearFlag_WU6
1910 * @retval None
1911 */
LL_PWR_ClearFlag_WU6()1912 __STATIC_INLINE void LL_PWR_ClearFlag_WU6()
1913 {
1914 WRITE_REG(PWR->SR1, PWR_SR1_WUF6);
1915 }
1916
1917 /**
1918 * @brief Clear Wake-up Flag 7.
1919 * @rmtoll SR1 WUF5 LL_PWR_ClearFlag_WU7
1920 * @retval None
1921 */
LL_PWR_ClearFlag_WU7()1922 __STATIC_INLINE void LL_PWR_ClearFlag_WU7()
1923 {
1924 WRITE_REG(PWR->SR1, PWR_SR1_WUF7);
1925 }
1926
1927 /**
1928 * @brief Clear Wake-up Flag 8.
1929 * @rmtoll SR1 WUF5 LL_PWR_ClearFlag_WU8
1930 * @retval None
1931 */
LL_PWR_ClearFlag_WU8()1932 __STATIC_INLINE void LL_PWR_ClearFlag_WU8()
1933 {
1934 WRITE_REG(PWR->SR1, PWR_SR1_WUF8);
1935 }
1936
1937 /**
1938 * @brief Clear Wake-up Flag 9.
1939 * @rmtoll SR1 WUF9 LL_PWR_ClearFlag_WU9
1940 * @retval None
1941 */
LL_PWR_ClearFlag_WU9()1942 __STATIC_INLINE void LL_PWR_ClearFlag_WU9()
1943 {
1944 WRITE_REG(PWR->SR1, PWR_SR1_WUF9);
1945 }
1946
1947 /**
1948 * @brief Clear Wake-up Flag 10.
1949 * @rmtoll SR1 WUF10 LL_PWR_ClearFlag_WU10
1950 * @retval None
1951 */
LL_PWR_ClearFlag_WU10()1952 __STATIC_INLINE void LL_PWR_ClearFlag_WU10()
1953 {
1954 WRITE_REG(PWR->SR1, PWR_SR1_WUF10);
1955 }
1956
1957 /**
1958 * @brief Clear Wake-up Flag 11.
1959 * @rmtoll SR1 WUF11 LL_PWR_ClearFlag_WU11
1960 * @retval None
1961 */
LL_PWR_ClearFlag_WU11()1962 __STATIC_INLINE void LL_PWR_ClearFlag_WU11()
1963 {
1964 WRITE_REG(PWR->SR1, PWR_SR1_WUF11);
1965 }
1966
1967 /**
1968 * @brief Clear Wake-up Flag 12.
1969 * @rmtoll SR3 WUF12 LL_PWR_ClearFlag_WU12
1970 * @retval None
1971 */
LL_PWR_ClearFlag_WU12()1972 __STATIC_INLINE void LL_PWR_ClearFlag_WU12()
1973 {
1974 WRITE_REG(PWR->SR3, PWR_SR3_WUF12);
1975 }
1976
1977 /**
1978 * @brief Clear Wake-up Flag 13.
1979 * @rmtoll SR3 WUF13 LL_PWR_ClearFlag_WU13
1980 * @retval None
1981 */
LL_PWR_ClearFlag_WU13()1982 __STATIC_INLINE void LL_PWR_ClearFlag_WU13()
1983 {
1984 WRITE_REG(PWR->SR3, PWR_SR3_WUF13);
1985 }
1986
1987 /**
1988 * @brief Clear Wake-up Flag 14.
1989 * @rmtoll SR3 WUF14 LL_PWR_ClearFlag_WU14
1990 * @retval None
1991 */
LL_PWR_ClearFlag_WU14()1992 __STATIC_INLINE void LL_PWR_ClearFlag_WU14()
1993 {
1994 WRITE_REG(PWR->SR3, PWR_SR3_WUF14);
1995 }
1996
1997 /**
1998 * @brief Clear Wake-up Flag 15.
1999 * @rmtoll SR3 WUF15 LL_PWR_ClearFlag_WU15
2000 * @retval None
2001 */
LL_PWR_ClearFlag_WU15()2002 __STATIC_INLINE void LL_PWR_ClearFlag_WU15()
2003 {
2004 WRITE_REG(PWR->SR3, PWR_SR3_WUF15);
2005 }
2006
2007 /**
2008 * @brief Clear Wake-up Flag 16.
2009 * @rmtoll SR3 WUF16 LL_PWR_ClearFlag_WU16
2010 * @retval None
2011 */
LL_PWR_ClearFlag_WU16()2012 __STATIC_INLINE void LL_PWR_ClearFlag_WU16()
2013 {
2014 WRITE_REG(PWR->SR3, PWR_SR3_WUF16);
2015 }
2016
2017 /**
2018 * @brief Clear Wake-up Flag 17.
2019 * @rmtoll SR3 WUF17 LL_PWR_ClearFlag_WU17
2020 * @retval None
2021 */
LL_PWR_ClearFlag_WU17()2022 __STATIC_INLINE void LL_PWR_ClearFlag_WU17()
2023 {
2024 WRITE_REG(PWR->SR3, PWR_SR3_WUF17);
2025 }
2026
2027 /**
2028 * @brief Clear Wake-up Flag 18.
2029 * @rmtoll SR3 WUF18 LL_PWR_ClearFlag_WU18
2030 * @retval None
2031 */
LL_PWR_ClearFlag_WU18()2032 __STATIC_INLINE void LL_PWR_ClearFlag_WU18()
2033 {
2034 WRITE_REG(PWR->SR3, PWR_SR3_WUF18);
2035 }
2036
2037 /**
2038 * @brief Clear Wake-up Flag 19.
2039 * @rmtoll SR3 WUF19 LL_PWR_ClearFlag_WU19
2040 * @retval None
2041 */
LL_PWR_ClearFlag_WU19()2042 __STATIC_INLINE void LL_PWR_ClearFlag_WU19()
2043 {
2044 WRITE_REG(PWR->SR3, PWR_SR3_WUF19);
2045 }
2046
2047 #if defined(PWR_CR6_EWUP20)
2048 /**
2049 * @brief Clear Wake-up Flag 20.
2050 * @rmtoll SR3 WUF20 LL_PWR_ClearFlag_WU20
2051 * @retval None
2052 */
LL_PWR_ClearFlag_WU20()2053 __STATIC_INLINE void LL_PWR_ClearFlag_WU20()
2054 {
2055 WRITE_REG(PWR->SR3, PWR_SR3_WUF20);
2056 }
2057 #endif /* PWR_CR6_EWUP20 */
2058
2059 #if defined(PWR_CR6_EWUP21)
2060 /**
2061 * @brief Clear Wake-up Flag 21.
2062 * @rmtoll SR3 WUF21 LL_PWR_ClearFlag_WU21
2063 * @retval None
2064 */
LL_PWR_ClearFlag_WU21()2065 __STATIC_INLINE void LL_PWR_ClearFlag_WU21()
2066 {
2067 WRITE_REG(PWR->SR3, PWR_SR3_WUF21);
2068 }
2069 #endif /* PWR_CR6_EWUP21 */
2070
2071 #if defined(PWR_CR6_EWUP21)
2072 /**
2073 * @brief Clear Wake-up Flag 22.
2074 * @rmtoll SR3 WUF22 LL_PWR_ClearFlag_WU22
2075 * @retval None
2076 */
LL_PWR_ClearFlag_WU22()2077 __STATIC_INLINE void LL_PWR_ClearFlag_WU22()
2078 {
2079 WRITE_REG(PWR->SR3, PWR_SR3_WUF22);
2080 }
2081 #endif /* PWR_CR6_EWUP22 */
2082
2083 #if defined(PWR_CR6_EWUP23)
2084 /**
2085 * @brief Clear Wake-up Flag 23.
2086 * @rmtoll SR3 WUF23 LL_PWR_ClearFlag_WU23
2087 * @retval None
2088 */
LL_PWR_ClearFlag_WU23()2089 __STATIC_INLINE void LL_PWR_ClearFlag_WU23()
2090 {
2091 WRITE_REG(PWR->SR3, PWR_SR3_WUF23);
2092 }
2093 #endif /* PWR_CR6_EWUP23 */
2094
2095 #if defined(PWR_CR6_EWUP24)
2096 /**
2097 * @brief Clear Wake-up Flag 24.
2098 * @rmtoll SR3 WUF24 LL_PWR_ClearFlag_WU24
2099 * @retval None
2100 */
LL_PWR_ClearFlag_WU24()2101 __STATIC_INLINE void LL_PWR_ClearFlag_WU24()
2102 {
2103 WRITE_REG(PWR->SR3, PWR_SR3_WUF24);
2104 }
2105 #endif /* PWR_CR6_EWUP24 */
2106
2107 #if defined(PWR_CR6_EWUP25)
2108 /**
2109 * @brief Clear Wake-up Flag 25.
2110 * @rmtoll SR3 WUF25 LL_PWR_ClearFlag_WU25
2111 * @retval None
2112 */
LL_PWR_ClearFlag_WU25()2113 __STATIC_INLINE void LL_PWR_ClearFlag_WU25()
2114 {
2115 WRITE_REG(PWR->SR3, PWR_SR3_WUF25);
2116 }
2117 #endif /* PWR_CR6_EWUP25 */
2118
2119 #if defined(PWR_CR6_EWUP26)
2120 /**
2121 * @brief Clear Wake-up Flag 26.
2122 * @rmtoll SR3 WUF26 LL_PWR_ClearFlag_WU26
2123 * @retval None
2124 */
LL_PWR_ClearFlag_WU26()2125 __STATIC_INLINE void LL_PWR_ClearFlag_WU26()
2126 {
2127 WRITE_REG(PWR->SR3, PWR_SR3_WUF26);
2128 }
2129 #endif /* PWR_CR6_EWUP26 */
2130
2131 #if defined(PWR_CR6_EWUP27)
2132 /**
2133 * @brief Clear Wake-up Flag 26.
2134 * @rmtoll SR3 WUF27 LL_PWR_ClearFlag_WU27
2135 * @retval None
2136 */
LL_PWR_ClearFlag_WU27()2137 __STATIC_INLINE void LL_PWR_ClearFlag_WU27()
2138 {
2139 WRITE_REG(PWR->SR3, PWR_SR3_WUF27);
2140 }
2141 #endif /* PWR_CR6_EWUP26 */
2142
2143 /**
2144 * @}
2145 */
2146
2147 /** @defgroup PWR_LL_EF_FLAG_Management_Radio FLAG management for radio
2148 * @{
2149 */
2150
2151 /**
2152 * @brief Get BLE wakeup interrupt flag
2153 * @rmtoll SR1 WBLEHCPUF LL_PWR_IsActiveFlag_WBLEHCPUF
2154 * @retval State of bit (1 or 0).
2155 */
LL_PWR_IsActiveFlag_WBLEHCPUF(void)2156 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WBLEHCPUF(void)
2157 {
2158 return ((READ_BIT(PWR->SR1, PWR_SR1_WBLEHCPUF) == (PWR_SR1_WBLEHCPUF)) ? 1UL : 0UL);
2159 }
2160
2161 /**
2162 * @brief Get BLE wakeup interrupt flag
2163 * @rmtoll SR1 WBLEF LL_PWR_IsActiveFlag_WBLEF
2164 * @retval State of bit (1 or 0).
2165 */
LL_PWR_IsActiveFlag_WBLEF(void)2166 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WBLEF(void)
2167 {
2168 return ((READ_BIT(PWR->SR1, PWR_SR1_WBLEF) == (PWR_SR1_WBLEF)) ? 1UL : 0UL);
2169 }
2170
2171 /**
2172 * @brief Clear BLE HOST CPU wakeup interrupt flag
2173 * @rmtoll SR1 WBLEHCPUF LL_PWR_ClearFlag_WBLEHCPU
2174 * @retval None
2175 */
LL_PWR_ClearFlag_WBLEHCPUF(void)2176 __STATIC_INLINE void LL_PWR_ClearFlag_WBLEHCPUF(void)
2177 {
2178 WRITE_REG(PWR->SR1, PWR_SR1_WBLEHCPUF);
2179 }
2180
2181 /**
2182 * @brief Clear BLE wakeup interrupt flag
2183 * @rmtoll SR1 WBLEF LL_PWR_ClearFlag_WBLEF
2184 * @retval None
2185 */
LL_PWR_ClearFlag_WBLEF(void)2186 __STATIC_INLINE void LL_PWR_ClearFlag_WBLEF(void)
2187 {
2188 WRITE_REG(PWR->SR1, PWR_SR1_WBLEF);
2189 }
2190
2191 /**
2192 * @}
2193 */
2194
2195 /** @defgroup PWR_LL_RF_DEEPSTOP_FLAG flags about RF radio activity start and DEEPSTOP sequence occurred.
2196 * @{
2197 */
2198
2199 /**
2200 * @brief Check if a radio wakeup event occurs.
2201 * @rmtoll EXTSRR RFPHASEF LL_PWR_GetRFWakeupFlag
2202 * @retval State of bit (1 or 0).
2203 */
LL_PWR_GetRFWakeupFlag(void)2204 __STATIC_INLINE uint32_t LL_PWR_GetRFWakeupFlag(void)
2205 {
2206 return ((READ_BIT(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF) == (PWR_EXTSRR_RFPHASEF)) ? 1UL : 0UL);
2207 }
2208
2209 /**
2210 * @brief Clear radio wakeup event occurs flag.
2211 * @rmtoll EXTSRR RFPHASEF LL_PWR_ClearRFWakeupFlag
2212 * @retval None
2213 */
LL_PWR_ClearRFWakeupFlag(void)2214 __STATIC_INLINE void LL_PWR_ClearRFWakeupFlag(void)
2215 {
2216 WRITE_REG(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF);
2217 }
2218
2219 /**
2220 * @brief Check if a DEEPSTOP sequence occurred.
2221 * @rmtoll EXTSRR DEEPSTOPF LL_PWR_GetDeepstopSeqFlag
2222 * @retval State of bit (1 or 0).
2223 */
LL_PWR_GetDeepstopSeqFlag(void)2224 __STATIC_INLINE uint32_t LL_PWR_GetDeepstopSeqFlag(void)
2225 {
2226 return ((READ_BIT(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF) == (PWR_EXTSRR_DEEPSTOPF)) ? 1UL : 0UL);
2227 }
2228
2229 /**
2230 * @brief Clear DEEPSTOP sequence occurred flag.
2231 * @rmtoll EXTSRR DEEPSTOPF LL_PWR_ClearRFWakeupFlag
2232 * @retval None
2233 */
LL_PWR_ClearDeepstopSeqFlag(void)2234 __STATIC_INLINE void LL_PWR_ClearDeepstopSeqFlag(void)
2235 {
2236 WRITE_REG(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF);
2237 }
2238 /**
2239 * @}
2240 */
2241
2242 /**
2243 * @brief Get IO BOOT value.
2244 * @rmtoll SR2 LL_PWR_GetIOBootVal
2245 * @param IO This parameter can be one of the following values:
2246 * @arg @ref LL_PWR_PA8_LATCH_POR
2247 * @arg @ref LL_PWR_PA9_LATCH_POR
2248 * @arg @ref LL_PWR_PA10_LATCH_POR
2249 * @arg @ref LL_PWR_PA11_LATCH_POR
2250 * @arg @ref LL_PWR_PB12_LATCH_POR (*)
2251 * @arg @ref LL_PWR_PB13_LATCH_POR (*)
2252 * @arg @ref LL_PWR_PB14_LATCH_POR (*)
2253 * @arg @ref LL_PWR_PB15_LATCH_POR (*)
2254 * (*) Not available on device STM32WB05
2255 * @retval State of pin (1 or 0).
2256 */
LL_PWR_GetIOBootVal(uint32_t IO)2257 __STATIC_INLINE uint32_t LL_PWR_GetIOBootVal(uint32_t IO)
2258 {
2259 return ((READ_BIT(PWR->SR2, IO) == (IO)) ? 1UL : 0UL);
2260 }
2261
2262 /**
2263 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
2264 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
2265 * @retval State of bit (1 or 0).
2266 */
LL_PWR_IsActiveFlag_PVDO(void)2267 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
2268 {
2269 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
2270 }
2271
2272 #if defined(PWR_SR2_REGMS)
2273 /**
2274 * @brief Get the Main Regulator ready status.
2275 * @rmtoll SR2 REGMS LL_PWR_IsActiveFlag_REGMS
2276 * @retval State of bit (1 or 0).
2277 */
LL_PWR_IsActiveFlag_REGMS(void)2278 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGMS(void)
2279 {
2280 return ((READ_BIT(PWR->SR2, PWR_SR2_REGMS) == (PWR_SR2_REGMS)) ? 1UL : 0UL);
2281 }
2282 #endif /* PWR_SR2_REGMS */
2283
2284 /**
2285 * @brief Indicate whether or not the low-power regulator is ready
2286 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
2287 * @retval State of bit (1 or 0).
2288 */
LL_PWR_IsActiveFlag_REGLPS(void)2289 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
2290 {
2291 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
2292 }
2293 /** @defgroup PWR_LL_EF_Configuration_SMPS Configuration of SMPS
2294 * @{
2295 */
2296
2297 /**
2298 * @brief Get the SMPS ready status.
2299 * @rmtoll SR2 SMPSRDY LL_PWR_IsSMPSReady
2300 * @retval State of bit (1 or 0).
2301 */
LL_PWR_IsSMPSReady(void)2302 __STATIC_INLINE uint32_t LL_PWR_IsSMPSReady(void)
2303 {
2304 return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) == (PWR_SR2_SMPSRDY)) ? 1UL : 0UL);
2305 }
2306
2307 /**
2308 * @brief Get the SMPS RUN mode status.
2309 * @rmtoll SR2 SMPSENR LL_PWR_IsSMPSinRUNMode
2310 * @retval State of bit (1 or 0)
2311 */
LL_PWR_IsSMPSinRUNMode(void)2312 __STATIC_INLINE uint32_t LL_PWR_IsSMPSinRUNMode(void)
2313 {
2314 return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSENR) == (PWR_SR2_SMPSENR)) ? 1UL : 0UL);
2315 }
2316
2317 /**
2318 * @brief Get the SMPS PRECHARGE mode status.
2319 * @rmtoll SR2 SMPSBYPR LL_PWR_IsSMPSinPRECHARGEMode
2320 * @retval State of bit (1 or 0)
2321 */
LL_PWR_IsSMPSinPRECHARGEMode(void)2322 __STATIC_INLINE uint32_t LL_PWR_IsSMPSinPRECHARGEMode(void)
2323 {
2324 return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSBYPR) == (PWR_SR2_SMPSBYPR)) ? 1UL : 0UL);
2325 }
2326
2327 /**
2328 * @brief Set SMPS Mode.
2329 * @rmtoll CR5 NOSMPS LL_PWR_SetSMPSMode
2330 * @param mode SMPS Mode. This parameter can be one of the following values:
2331 * @arg @ref LL_PWR_SMPS
2332 * @arg @ref LL_PWR_NO_SMPS
2333 * @retval None
2334 */
LL_PWR_SetSMPSMode(uint32_t mode)2335 __STATIC_INLINE void LL_PWR_SetSMPSMode(uint32_t mode)
2336 {
2337 MODIFY_REG(PWR->CR5, PWR_CR5_NOSMPS, mode);
2338 }
2339
2340 /**
2341 * @brief Get SMPS Mode.
2342 * @rmtoll CR5 NOSMPS LL_PWR_GetSMPSMode
2343 * @retval SMPS Mode. This parameter can be one of the following values:
2344 * @arg @ref LL_PWR_SMPS
2345 * @arg @ref LL_PWR_NO_SMPS
2346 */
LL_PWR_GetSMPSMode(void)2347 __STATIC_INLINE uint32_t LL_PWR_GetSMPSMode(void)
2348 {
2349 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_NOSMPS));
2350 }
2351
2352 /**
2353 * @brief Set SMPS in PRECHARGE Mode.
2354 * @rmtoll CR5 SMPSFBYP LL_PWR_SetSMPSPrechargeMode
2355 * @param mode SMPS in Precharge Mode. This parameter can be one of the following values:
2356 * @arg @ref LL_PWR_NO_SMPS_PRECHARGE
2357 * @arg @ref LL_PWR_SMPS_PRECHARGE
2358 * @retval None
2359 */
LL_PWR_SetSMPSPrechargeMode(uint32_t mode)2360 __STATIC_INLINE void LL_PWR_SetSMPSPrechargeMode(uint32_t mode)
2361 {
2362 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSFBYP, mode);
2363 }
2364
2365 /**
2366 * @brief Check if SMPS is configured in PRECHARGE Mode.
2367 * @rmtoll CR5 SMPSFBYP LL_PWR_IsEnabledSMPSPrechargeMode
2368 * @retval State of bit (1 or 0).
2369 */
LL_PWR_IsEnabledSMPSPrechargeMode(void)2370 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSPrechargeMode(void)
2371 {
2372 return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSFBYP) == (PWR_CR5_SMPSFBYP)) ? 1UL : 0UL);
2373 }
2374
2375 /**
2376 * @brief Select OPEN Mode for SMPS during DEEPSTOP.
2377 * @rmtoll CR5 SMPSLPOPEN LL_PWR_SetSMPSOpenMode
2378 * @param mode SMPS Mode. This parameter can be one of the following values:
2379 * @arg @ref LL_PWR_NO_SMPS_LPOPEN
2380 * @arg @ref LL_PWR_SMPS_LPOPEN
2381 * @retval None
2382 */
LL_PWR_SetSMPSOpenMode(uint32_t mode)2383 __STATIC_INLINE void LL_PWR_SetSMPSOpenMode(uint32_t mode)
2384 {
2385 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSLPOPEN, mode);
2386 }
2387
2388 /**
2389 * @brief Set SMPS BOM
2390 * @rmtoll CR5 SMPSBOMSEL LL_PWR_SetSMPSBOM
2391 * CR5 SMPSBOMSEL LL_PWR_SetSMPSBOM
2392 * @param BOM BOM. This parameter can be one of the following values:
2393 * @arg @ref LL_PWR_SMPS_BOM1
2394 * @arg @ref LL_PWR_SMPS_BOM2
2395 * @arg @ref LL_PWR_SMPS_BOM3
2396 * @retval None
2397 */
LL_PWR_SetSMPSBOM(uint32_t BOM)2398 __STATIC_INLINE void LL_PWR_SetSMPSBOM(uint32_t BOM)
2399 {
2400 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSBOMSEL, BOM);
2401 }
2402
2403 /**
2404 * @brief Get SMPS BOM
2405 * @rmtoll CR5 SMPSBOMSEL LL_PWR_GetSMPSBOM
2406 * CR5 SMPSBOMSEL LL_PWR_GetSMPSBOM
2407 * @retval BOM. This parameter can be one of the following values:
2408 * @arg @ref LL_PWR_SMPS_BOM1
2409 * @arg @ref LL_PWR_SMPS_BOM2
2410 * @arg @ref LL_PWR_SMPS_BOM3
2411 */
LL_PWR_GetSMPSBOM(void)2412 __STATIC_INLINE uint32_t LL_PWR_GetSMPSBOM(void)
2413 {
2414 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSBOMSEL));
2415 }
2416
2417 /**
2418 * @brief Set SMPS Output Level
2419 * @rmtoll CR5 SMPSLVL LL_PWR_SMPS_SetOutputVoltageLevel
2420 * @param OutputVoltageLevel Output Level. This parameter can be one of the following values:
2421 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
2422 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
2423 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
2424 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
2425 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
2426 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
2427 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
2428 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
2429 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
2430 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
2431 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
2432 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
2433 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
2434 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
2435 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
2436 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V95
2437 * @retval None
2438 */
LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLevel)2439 __STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLevel)
2440 {
2441 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSLVL, OutputVoltageLevel);
2442 }
2443
2444 /**
2445 * @brief Get SMPS Output Level
2446 * @rmtoll CR5 SMPSLVL LL_PWR_SMPS_GetOutputVoltageLevel
2447 * @retval Output Level. This parameter can be one of the following values:
2448 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
2449 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
2450 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
2451 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
2452 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
2453 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
2454 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
2455 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
2456 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
2457 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
2458 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
2459 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
2460 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
2461 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
2462 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
2463 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V95
2464 *
2465 */
LL_PWR_SMPS_GetOutputVoltageLevel(void)2466 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel(void)
2467 {
2468 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSLVL));
2469 }
2470
2471 /**
2472 * @}
2473 */
2474
2475 /**
2476 * @brief Enable GPIO pull-up state in Shutdown mode
2477 * @note Some pins are not configurable for pulling in Shutdown modes.
2478 * Refer to reference manual for available pins.
2479 * @rmtoll PUCRA PUA0-15 LL_PWR_EnableGPIOPullUp\n
2480 * PUCRB PUB0-15 LL_PWR_EnableGPIOPullUp
2481 * @param GPIO This parameter can be one of the following values:
2482 * @arg @ref LL_PWR_GPIO_A
2483 * @arg @ref LL_PWR_GPIO_B
2484 * @param GPIONumber This parameter can be one of the following values:
2485 * @arg @ref LL_PWR_GPIO_BIT_0
2486 * @arg @ref LL_PWR_GPIO_BIT_1
2487 * @arg @ref LL_PWR_GPIO_BIT_2
2488 * @arg @ref LL_PWR_GPIO_BIT_3
2489 * @arg @ref LL_PWR_GPIO_BIT_4
2490 * @arg @ref LL_PWR_GPIO_BIT_5
2491 * @arg @ref LL_PWR_GPIO_BIT_6
2492 * @arg @ref LL_PWR_GPIO_BIT_7
2493 * @arg @ref LL_PWR_GPIO_BIT_8
2494 * @arg @ref LL_PWR_GPIO_BIT_9
2495 * @arg @ref LL_PWR_GPIO_BIT_10
2496 * @arg @ref LL_PWR_GPIO_BIT_11
2497 * @arg @ref LL_PWR_GPIO_BIT_12
2498 * @arg @ref LL_PWR_GPIO_BIT_13
2499 * @arg @ref LL_PWR_GPIO_BIT_14
2500 * @arg @ref LL_PWR_GPIO_BIT_15
2501 * @retval None
2502 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)2503 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
2504 {
2505 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
2506 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
2507 }
2508
2509 /**
2510 * @brief Disable GPIO pull-up state in Shutdown mode
2511 * @note Some pins are not configurable for pulling in Shutdown modes.
2512 * Refer to reference manual for available pins.
2513 * @rmtoll PUCRA PUA0-15 LL_PWR_DisableGPIOPullUp\n
2514 * PUCRB PUB0-15 LL_PWR_DisableGPIOPullUp
2515 * @param GPIO This parameter can be one of the following values:
2516 * @arg @ref LL_PWR_GPIO_A
2517 * @arg @ref LL_PWR_GPIO_B
2518 * @param GPIONumber This parameter can be one of the following values:
2519 * @arg @ref LL_PWR_GPIO_BIT_0
2520 * @arg @ref LL_PWR_GPIO_BIT_1
2521 * @arg @ref LL_PWR_GPIO_BIT_2
2522 * @arg @ref LL_PWR_GPIO_BIT_3
2523 * @arg @ref LL_PWR_GPIO_BIT_4
2524 * @arg @ref LL_PWR_GPIO_BIT_5
2525 * @arg @ref LL_PWR_GPIO_BIT_6
2526 * @arg @ref LL_PWR_GPIO_BIT_7
2527 * @arg @ref LL_PWR_GPIO_BIT_8
2528 * @arg @ref LL_PWR_GPIO_BIT_9
2529 * @arg @ref LL_PWR_GPIO_BIT_10
2530 * @arg @ref LL_PWR_GPIO_BIT_11
2531 * @arg @ref LL_PWR_GPIO_BIT_12
2532 * @arg @ref LL_PWR_GPIO_BIT_13
2533 * @arg @ref LL_PWR_GPIO_BIT_14
2534 * @arg @ref LL_PWR_GPIO_BIT_15
2535 * @retval None
2536 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)2537 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
2538 {
2539 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
2540 }
2541
2542 /**
2543 * @brief Check if GPIO pull-up state is enabled
2544 * @rmtoll PUCRA PUA0-15 LL_PWR_IsEnabledGPIOPullUp\n
2545 * PUCRB PUB0-15 LL_PWR_IsEnabledGPIOPullUp
2546 * @param GPIO This parameter can be one of the following values:
2547 * @arg @ref LL_PWR_GPIO_A
2548 * @arg @ref LL_PWR_GPIO_B
2549 * @param GPIONumber This parameter can be a combination of the following values:
2550 * @arg @ref LL_PWR_GPIO_BIT_0
2551 * @arg @ref LL_PWR_GPIO_BIT_1
2552 * @arg @ref LL_PWR_GPIO_BIT_2
2553 * @arg @ref LL_PWR_GPIO_BIT_3
2554 * @arg @ref LL_PWR_GPIO_BIT_4
2555 * @arg @ref LL_PWR_GPIO_BIT_5
2556 * @arg @ref LL_PWR_GPIO_BIT_6
2557 * @arg @ref LL_PWR_GPIO_BIT_7
2558 * @arg @ref LL_PWR_GPIO_BIT_8
2559 * @arg @ref LL_PWR_GPIO_BIT_9
2560 * @arg @ref LL_PWR_GPIO_BIT_10
2561 * @arg @ref LL_PWR_GPIO_BIT_11
2562 * @arg @ref LL_PWR_GPIO_BIT_12
2563 * @arg @ref LL_PWR_GPIO_BIT_13
2564 * @arg @ref LL_PWR_GPIO_BIT_14
2565 * @arg @ref LL_PWR_GPIO_BIT_15
2566 * @retval State of bit (1 or 0)
2567 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)2568 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
2569 {
2570 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
2571 }
2572
2573 /**
2574 * @brief Enable GPIO pull-down state in Shutdown mode
2575 * @note Some pins are not configurable for pulling in Shutdown
2576 * modes. Refer to reference manual for available pins
2577 * @rmtoll PDCRA PDA0-15 LL_PWR_EnableGPIOPullDown\n
2578 * PDCRB PUB0-15 LL_PWR_EnableGPIOPullDown
2579 * @param GPIO This parameter can be one of the following values:
2580 * @arg @ref LL_PWR_GPIO_A
2581 * @arg @ref LL_PWR_GPIO_B
2582 * @param GPIONumber This parameter can be a combination of the following values:
2583 * @arg @ref LL_PWR_GPIO_BIT_0
2584 * @arg @ref LL_PWR_GPIO_BIT_1
2585 * @arg @ref LL_PWR_GPIO_BIT_2
2586 * @arg @ref LL_PWR_GPIO_BIT_3
2587 * @arg @ref LL_PWR_GPIO_BIT_4
2588 * @arg @ref LL_PWR_GPIO_BIT_5
2589 * @arg @ref LL_PWR_GPIO_BIT_6
2590 * @arg @ref LL_PWR_GPIO_BIT_7
2591 * @arg @ref LL_PWR_GPIO_BIT_8
2592 * @arg @ref LL_PWR_GPIO_BIT_9
2593 * @arg @ref LL_PWR_GPIO_BIT_10
2594 * @arg @ref LL_PWR_GPIO_BIT_11
2595 * @arg @ref LL_PWR_GPIO_BIT_12
2596 * @arg @ref LL_PWR_GPIO_BIT_13
2597 * @arg @ref LL_PWR_GPIO_BIT_14
2598 * @arg @ref LL_PWR_GPIO_BIT_15
2599 * @retval None
2600 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)2601 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
2602 {
2603 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
2604 SET_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
2605 }
2606
2607 /**
2608 * @brief Disable GPIO pull-down state in Shutdown mode.
2609 * @note Some pins are not configurable for pulling in Shutdown
2610 * modes. Refer to reference manual for available pins.
2611 * @rmtoll PDCRA PDA0-15 LL_PWR_DisableGPIOPullDown\n
2612 * PDCRB PDB0-15 LL_PWR_DisableGPIOPullDown
2613 * @param GPIO This parameter can be one of the following values:
2614 * @arg @ref LL_PWR_GPIO_A
2615 * @arg @ref LL_PWR_GPIO_B
2616 * @param GPIONumber This parameter can be a combination of the following values:
2617 * @arg @ref LL_PWR_GPIO_BIT_0
2618 * @arg @ref LL_PWR_GPIO_BIT_1
2619 * @arg @ref LL_PWR_GPIO_BIT_2
2620 * @arg @ref LL_PWR_GPIO_BIT_3
2621 * @arg @ref LL_PWR_GPIO_BIT_4
2622 * @arg @ref LL_PWR_GPIO_BIT_5
2623 * @arg @ref LL_PWR_GPIO_BIT_6
2624 * @arg @ref LL_PWR_GPIO_BIT_7
2625 * @arg @ref LL_PWR_GPIO_BIT_8
2626 * @arg @ref LL_PWR_GPIO_BIT_9
2627 * @arg @ref LL_PWR_GPIO_BIT_10
2628 * @arg @ref LL_PWR_GPIO_BIT_11
2629 * @arg @ref LL_PWR_GPIO_BIT_12
2630 * @arg @ref LL_PWR_GPIO_BIT_13
2631 * @arg @ref LL_PWR_GPIO_BIT_14
2632 * @arg @ref LL_PWR_GPIO_BIT_15
2633 * @retval None
2634 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)2635 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
2636 {
2637 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
2638 }
2639
2640 /**
2641 * @brief Checks if GPIO pull-down state is enabled
2642 * @rmtoll PDCRA PDA0-15 LL_PWR_IsEnabledGPIOPullDown\n
2643 * PDCRB PDB0-15 LL_PWR_IsEnabledGPIOPullDown
2644 * @param GPIO This parameter can be one of the following values:
2645 * @arg @ref LL_PWR_GPIO_A
2646 * @arg @ref LL_PWR_GPIO_B
2647 * @param GPIONumber This parameter can be a combination of the following values:
2648 * @arg @ref LL_PWR_GPIO_BIT_0
2649 * @arg @ref LL_PWR_GPIO_BIT_1
2650 * @arg @ref LL_PWR_GPIO_BIT_2
2651 * @arg @ref LL_PWR_GPIO_BIT_3
2652 * @arg @ref LL_PWR_GPIO_BIT_4
2653 * @arg @ref LL_PWR_GPIO_BIT_5
2654 * @arg @ref LL_PWR_GPIO_BIT_6
2655 * @arg @ref LL_PWR_GPIO_BIT_7
2656 * @arg @ref LL_PWR_GPIO_BIT_8
2657 * @arg @ref LL_PWR_GPIO_BIT_9
2658 * @arg @ref LL_PWR_GPIO_BIT_10
2659 * @arg @ref LL_PWR_GPIO_BIT_11
2660 * @arg @ref LL_PWR_GPIO_BIT_12
2661 * @arg @ref LL_PWR_GPIO_BIT_13
2662 * @arg @ref LL_PWR_GPIO_BIT_14
2663 * @arg @ref LL_PWR_GPIO_BIT_15
2664 * @retval State of bit (1 or 0)
2665 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)2666 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
2667 {
2668 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
2669 }
2670
2671 /**
2672 * @brief Configure the GPIO in NO PULL configuration for port A.
2673 * @rmtoll PDCRA/PUCRA LL_PWR_SetNoPullA
2674 * @param GPIONumber Pins No Pull configuration. This parameter can be a combination of the following values:
2675 * @arg @ref LL_PWR_GPIO_BIT_0
2676 * @arg @ref LL_PWR_GPIO_BIT_1
2677 * @arg @ref LL_PWR_GPIO_BIT_2
2678 * @arg @ref LL_PWR_GPIO_BIT_3
2679 * @arg @ref LL_PWR_GPIO_BIT_4(*)
2680 * @arg @ref LL_PWR_GPIO_BIT_5(*)
2681 * @arg @ref LL_PWR_GPIO_BIT_6(*)
2682 * @arg @ref LL_PWR_GPIO_BIT_7(*)
2683 * @arg @ref LL_PWR_GPIO_BIT_8
2684 * @arg @ref LL_PWR_GPIO_BIT_9
2685 * @arg @ref LL_PWR_GPIO_BIT_10
2686 * @arg @ref LL_PWR_GPIO_BIT_11
2687 * @arg @ref LL_PWR_GPIO_BIT_12(*)
2688 * @arg @ref LL_PWR_GPIO_BIT_13(*)
2689 * @arg @ref LL_PWR_GPIO_BIT_14(*)
2690 * @arg @ref LL_PWR_GPIO_BIT_15(*)
2691 * (*) available only on STM32WB06 and STM32WB07 devices
2692 * @retval None
2693 */
LL_PWR_SetNoPullA(uint32_t GPIONumber)2694 __STATIC_INLINE void LL_PWR_SetNoPullA(uint32_t GPIONumber)
2695 {
2696 CLEAR_BIT(PWR->PUCRA, GPIONumber);
2697 CLEAR_BIT(PWR->PDCRA, GPIONumber);
2698 }
2699
2700 /**
2701 * @brief Configure the GPIO in NO PULL configuration for port B.
2702 * @rmtoll PDCRB/PUCRB LL_PWR_SetNoPullB
2703 * @param GPIONumber Pins No Pull configuration. This parameter can be a combination of the following values:
2704 * @arg @ref LL_PWR_GPIO_BIT_0
2705 * @arg @ref LL_PWR_GPIO_BIT_1
2706 * @arg @ref LL_PWR_GPIO_BIT_2
2707 * @arg @ref LL_PWR_GPIO_BIT_3
2708 * @arg @ref LL_PWR_GPIO_BIT_4
2709 * @arg @ref LL_PWR_GPIO_BIT_5
2710 * @arg @ref LL_PWR_GPIO_BIT_6
2711 * @arg @ref LL_PWR_GPIO_BIT_7
2712 * @arg @ref LL_PWR_GPIO_BIT_8(*)
2713 * @arg @ref LL_PWR_GPIO_BIT_9(*)
2714 * @arg @ref LL_PWR_GPIO_BIT_10(*)
2715 * @arg @ref LL_PWR_GPIO_BIT_11(*)
2716 * @arg @ref LL_PWR_GPIO_BIT_12
2717 * @arg @ref LL_PWR_GPIO_BIT_13
2718 * @arg @ref LL_PWR_GPIO_BIT_14
2719 * @arg @ref LL_PWR_GPIO_BIT_15
2720 * (*) available only oon STM32WB06 and STM32WB07 devices
2721 * @retval None
2722 */
LL_PWR_SetNoPullB(uint32_t GPIONumber)2723 __STATIC_INLINE void LL_PWR_SetNoPullB(uint32_t GPIONumber)
2724 {
2725 CLEAR_BIT(PWR->PUCRB, GPIONumber);
2726 CLEAR_BIT(PWR->PDCRB, GPIONumber);
2727 }
2728
2729 #if defined(PWR_IOxCFG_IOCFG4)
2730 /**
2731 * @brief Set PA4 during DEEPSTOP mode.
2732 * @rmtoll IOxCFG IOCFG4 LL_PWR_SetPA4OutputinDEEPSTOP
2733 * @param mode This parameter can be one of the following values:
2734 * @arg @ref LL_PWR_IOCFG_BYP
2735 * @arg @ref LL_PWR_IOCFG_RTC
2736 * @arg @ref LL_PWR_IOCFG_LOW
2737 * @arg @ref LL_PWR_IOCFG_HIGH
2738 * @retval None
2739 */
LL_PWR_SetPA4OutputinDEEPSTOP(uint32_t mode)2740 __STATIC_INLINE void LL_PWR_SetPA4OutputinDEEPSTOP(uint32_t mode)
2741 {
2742 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG4, mode);
2743 }
2744
2745 /**
2746 * @brief Get PA4 output during DEEPSTOP mode.
2747 * @rmtoll IOxCFG IOCFG4 LL_PWR_GetPA4OutputinDEEPSTOP
2748 * @retval This parameter can be one of the following values:
2749 * @arg @ref LL_PWR_IOCFG_BYP
2750 * @arg @ref LL_PWR_IOCFG_RTC
2751 * @arg @ref LL_PWR_IOCFG_LOW
2752 * @arg @ref LL_PWR_IOCFG_HIGH
2753 */
LL_PWR_GetPA4OutputinDEEPSTOP(void)2754 __STATIC_INLINE uint32_t LL_PWR_GetPA4OutputinDEEPSTOP(void)
2755 {
2756 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG4) >> PWR_IOxCFG_IOCFG4_Pos);
2757 }
2758 #endif /* PWR_IOxCFG_IOCFG4 */
2759
2760 #if defined(PWR_IOxCFG_IOCFG5)
2761 /**
2762 * @brief Set PA5 during DEEPSTOP mode.
2763 * @rmtoll IOxCFG IOCFG5 LL_PWR_SetPA5OutputinDEEPSTOP
2764 * @param mode This parameter can be one of the following values:
2765 * @arg @ref LL_PWR_IOCFG_BYP
2766 * @arg @ref LL_PWR_IOCFG_LCO
2767 * @arg @ref LL_PWR_IOCFG_LOW
2768 * @arg @ref LL_PWR_IOCFG_HIGH
2769 * @retval None
2770 */
LL_PWR_SetPA5OutputinDEEPSTOP(uint32_t mode)2771 __STATIC_INLINE void LL_PWR_SetPA5OutputinDEEPSTOP(uint32_t mode)
2772 {
2773 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG5, mode);
2774 }
2775
2776 /**
2777 * @brief Get PA5 output during DEEPSTOP mode.
2778 * @rmtoll IOxCFG IOCFG5 LL_PWR_GetPA5OutputinDEEPSTOP
2779 * @retval This parameter can be one of the following values:
2780 * @arg @ref LL_PWR_IOCFG_BYP
2781 * @arg @ref LL_PWR_IOCFG_LCO
2782 * @arg @ref LL_PWR_IOCFG_LOW
2783 * @arg @ref LL_PWR_IOCFG_HIGH
2784 */
LL_PWR_GetPA5OutputinDEEPSTOP(void)2785 __STATIC_INLINE uint32_t LL_PWR_GetPA5OutputinDEEPSTOP(void)
2786 {
2787 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG5) >> PWR_IOxCFG_IOCFG5_Pos);
2788 }
2789 #endif /* PWR_IOxCFG_IOCFG5 */
2790
2791 #if defined(PWR_IOxCFG_IOCFG6)
2792 /**
2793 * @brief Set PA6 during DEEPSTOP mode.
2794 * @rmtoll IOxCFG IOCFG6 LL_PWR_SetPA6OutputinDEEPSTOP
2795 * @param mode This parameter can be one of the following values:
2796 * @arg @ref LL_PWR_IOCFG_BYP
2797 * @arg @ref LL_PWR_IOCFG_LCO
2798 * @arg @ref LL_PWR_IOCFG_LOW
2799 * @arg @ref LL_PWR_IOCFG_HIGH
2800 * @retval None
2801 */
LL_PWR_SetPA6OutputinDEEPSTOP(uint32_t mode)2802 __STATIC_INLINE void LL_PWR_SetPA6OutputinDEEPSTOP(uint32_t mode)
2803 {
2804 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG6, mode);
2805 }
2806
2807 /**
2808 * @brief Get PA6 output during DEEPSTOP mode.
2809 * @rmtoll IOxCFG IOCFG6 LL_PWR_GetPA6OutputinDEEPSTOP
2810 * @retval This parameter can be one of the following values:
2811 * @arg @ref LL_PWR_IOCFG_BYP
2812 * @arg @ref LL_PWR_IOCFG_LCO
2813 * @arg @ref LL_PWR_IOCFG_LOW
2814 * @arg @ref LL_PWR_IOCFG_HIGH
2815 */
LL_PWR_GetPA6OutputinDEEPSTOP(void)2816 __STATIC_INLINE uint32_t LL_PWR_GetPA6OutputinDEEPSTOP(void)
2817 {
2818 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG6) >> PWR_IOxCFG_IOCFG6_Pos);
2819 }
2820 #endif /* PWR_IOxCFG_IOCFG6 */
2821
2822 #if defined(PWR_IOxCFG_IOCFG7)
2823 /**
2824 * @brief Set PA7 during DEEPSTOP mode.
2825 * @rmtoll IOxCFG IOCFG7 LL_PWR_SetPA7OutputinDEEPSTOP
2826 * @param mode This parameter can be one of the following values:
2827 * @arg @ref LL_PWR_IOCFG_BYP
2828 * @arg @ref LL_PWR_IOCFG_LCO
2829 * @arg @ref LL_PWR_IOCFG_LOW
2830 * @arg @ref LL_PWR_IOCFG_HIGH
2831 * @retval None
2832 */
LL_PWR_SetPA7OutputinDEEPSTOP(uint32_t mode)2833 __STATIC_INLINE void LL_PWR_SetPA7OutputinDEEPSTOP(uint32_t mode)
2834 {
2835 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG7, mode);
2836 }
2837
2838 /**
2839 * @brief Get PA7 output during DEEPSTOP mode.
2840 * @rmtoll IOxCFG IOCFG7 LL_PWR_GetPA7OutputinDEEPSTOP
2841 * @retval This parameter can be one of the following values:
2842 * @arg @ref LL_PWR_IOCFG_BYP
2843 * @arg @ref LL_PWR_IOCFG_LCO
2844 * @arg @ref LL_PWR_IOCFG_LOW
2845 * @arg @ref LL_PWR_IOCFG_HIGH
2846 */
LL_PWR_GetPA7OutputinDEEPSTOP(void)2847 __STATIC_INLINE uint32_t LL_PWR_GetPA7OutputinDEEPSTOP(void)
2848 {
2849 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG7) >> PWR_IOxCFG_IOCFG7_Pos);
2850 }
2851 #endif /* PWR_IOxCFG_IOCFG7 */
2852
2853 #if defined(PWR_IOxCFG_IOCFG0)
2854 /**
2855 * @brief Set PA8 during DEEPSTOP mode.
2856 * @rmtoll IOxCFG IOCFG0 LL_PWR_SetPA8OutputinDEEPSTOP
2857 * @param mode This parameter can be one of the following values:
2858 * @arg @ref LL_PWR_IOCFG_BYP
2859 * @arg @ref LL_PWR_IOCFG_LCO
2860 * @arg @ref LL_PWR_IOCFG_LOW
2861 * @arg @ref LL_PWR_IOCFG_HIGH
2862 * @retval None
2863 */
LL_PWR_SetPA8OutputinDEEPSTOP(uint32_t mode)2864 __STATIC_INLINE void LL_PWR_SetPA8OutputinDEEPSTOP(uint32_t mode)
2865 {
2866 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG0, mode);
2867 }
2868
2869 /**
2870 * @brief Get PA8 output during DEEPSTOP mode.
2871 * @rmtoll IOxCFG IOCFG0 LL_PWR_GetPA8OutputinDEEPSTOP
2872 * @retval This parameter can be one of the following values:
2873 * @arg @ref LL_PWR_IOCFG_BYP
2874 * @arg @ref LL_PWR_IOCFG_LCO
2875 * @arg @ref LL_PWR_IOCFG_LOW
2876 * @arg @ref LL_PWR_IOCFG_HIGH
2877 */
LL_PWR_GetPA8OutputinDEEPSTOP(void)2878 __STATIC_INLINE uint32_t LL_PWR_GetPA8OutputinDEEPSTOP(void)
2879 {
2880 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG0) >> PWR_IOxCFG_IOCFG0_Pos);
2881 }
2882 #endif /* PWR_IOxCFG_IOCFG0 */
2883
2884 #if defined(PWR_IOxCFG_IOCFG1)
2885 /**
2886 * @brief Set PA9 during DEEPSTOP mode.
2887 * @rmtoll IOxCFG IOCFG1 LL_PWR_SetPA9OutputinDEEPSTOP
2888 * @param mode This parameter can be one of the following values:
2889 * @arg @ref LL_PWR_IOCFG_BYP
2890 * @arg @ref LL_PWR_IOCFG_LCO
2891 * @arg @ref LL_PWR_IOCFG_LOW
2892 * @arg @ref LL_PWR_IOCFG_HIGH
2893 * @retval None
2894 */
LL_PWR_SetPA9OutputinDEEPSTOP(uint32_t mode)2895 __STATIC_INLINE void LL_PWR_SetPA9OutputinDEEPSTOP(uint32_t mode)
2896 {
2897 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG1, mode);
2898 }
2899
2900 /**
2901 * @brief Get PA9 output during DEEPSTOP mode.
2902 * @rmtoll IOxCFG IOCFG1 LL_PWR_GetPA9OutputinDEEPSTOP
2903 * @retval This parameter can be one of the following values:
2904 * @arg @ref LL_PWR_IOCFG_BYP
2905 * @arg @ref LL_PWR_IOCFG_LCO
2906 * @arg @ref LL_PWR_IOCFG_LOW
2907 * @arg @ref LL_PWR_IOCFG_HIGH
2908 */
LL_PWR_GetPA9OutputinDEEPSTOP(void)2909 __STATIC_INLINE uint32_t LL_PWR_GetPA9OutputinDEEPSTOP(void)
2910 {
2911 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG1) >> PWR_IOxCFG_IOCFG1_Pos);
2912 }
2913 #endif /* PWR_IOxCFG_IOCFG1 */
2914
2915 #if defined(PWR_IOxCFG_IOCFG2)
2916 /**
2917 * @brief Set PA10 during DEEPSTOP mode.
2918 * @rmtoll IOxCFG IOCFG2 LL_PWR_SetPA10OutputinDEEPSTOP
2919 * @param mode This parameter can be one of the following values:
2920 * @arg @ref LL_PWR_IOCFG_BYP
2921 * @arg @ref LL_PWR_IOCFG_LCO
2922 * @arg @ref LL_PWR_IOCFG_LOW
2923 * @arg @ref LL_PWR_IOCFG_HIGH
2924 * @retval None
2925 */
LL_PWR_SetPA10OutputinDEEPSTOP(uint32_t mode)2926 __STATIC_INLINE void LL_PWR_SetPA10OutputinDEEPSTOP(uint32_t mode)
2927 {
2928 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG2, mode);
2929 }
2930
2931 /**
2932 * @brief Get PA10 output during DEEPSTOP mode.
2933 * @rmtoll IOxCFG IOCFG2 LL_PWR_GetPA10OutputinDEEPSTOP
2934 * @retval This parameter can be one of the following values:
2935 * @arg @ref LL_PWR_IOCFG_BYP
2936 * @arg @ref LL_PWR_IOCFG_LCO
2937 * @arg @ref LL_PWR_IOCFG_LOW
2938 * @arg @ref LL_PWR_IOCFG_HIGH
2939 */
LL_PWR_GetPA10OutputinDEEPSTOP(void)2940 __STATIC_INLINE uint32_t LL_PWR_GetPA10OutputinDEEPSTOP(void)
2941 {
2942 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG2) >> PWR_IOxCFG_IOCFG2_Pos);
2943 }
2944 #endif /* PWR_IOxCFG_IOCFG2 */
2945
2946 #if defined(PWR_IOxCFG_IOCFG3)
2947 /**
2948 * @brief Set PA11 during DEEPSTOP mode.
2949 * @rmtoll IOxCFG IOCFG3 LL_PWR_SetPA11OutputinDEEPSTOP
2950 * @param mode This parameter can be one of the following values:
2951 * @arg @ref LL_PWR_IOCFG_BYP
2952 * @arg @ref LL_PWR_IOCFG_LCO
2953 * @arg @ref LL_PWR_IOCFG_LOW
2954 * @arg @ref LL_PWR_IOCFG_HIGH
2955 * @retval None
2956 */
LL_PWR_SetPA11OutputinDEEPSTOP(uint32_t mode)2957 __STATIC_INLINE void LL_PWR_SetPA11OutputinDEEPSTOP(uint32_t mode)
2958 {
2959 MODIFY_REG_FIELD(PWR->IOxCFG, PWR_IOxCFG_IOCFG3, mode);
2960 }
2961
2962 /**
2963 * @brief Get PA11 output during DEEPSTOP mode.
2964 * @rmtoll IOxCFG IOCFG3 LL_PWR_GetPA11OutputinDEEPSTOP
2965 * @retval This parameter can be one of the following values:
2966 * @arg @ref LL_PWR_IOCFG_BYP
2967 * @arg @ref LL_PWR_IOCFG_LCO
2968 * @arg @ref LL_PWR_IOCFG_LOW
2969 * @arg @ref LL_PWR_IOCFG_HIGH
2970 */
LL_PWR_GetPA11OutputinDEEPSTOP(void)2971 __STATIC_INLINE uint32_t LL_PWR_GetPA11OutputinDEEPSTOP(void)
2972 {
2973 return (uint32_t)(READ_BIT(PWR->IOxCFG, PWR_IOxCFG_IOCFG3) >> PWR_IOxCFG_IOCFG3_Pos);
2974 }
2975 #endif /* PWR_IOxCFG_IOCFG3 */
2976
2977 /**
2978 * @brief Set SMPS trimming value.
2979 * @rmtoll ENGTRIM LL_PWR_SetSMPSTrim
2980 * @param trim SMPS output voltage trimming value
2981 * @retval None
2982 */
LL_PWR_SetSMPSTrim(uint32_t trim)2983 __STATIC_INLINE void LL_PWR_SetSMPSTrim(uint32_t trim)
2984 {
2985 MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_SMPS_TRIM, ((trim << PWR_ENGTRIM_SMPS_TRIM_Pos) & PWR_ENGTRIM_SMPS_TRIM));
2986 SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_SMPSTRIMEN);
2987 }
2988
2989 /**
2990 * @brief Get SMPS trimming value.
2991 * @rmtoll TRIMR/ENGTRIM LL_PWR_GetSMPSTrim
2992 * @retval SMPS output voltage trimming value
2993 */
LL_PWR_GetSMPSTrim(void)2994 __STATIC_INLINE uint32_t LL_PWR_GetSMPSTrim(void)
2995 {
2996 if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_SMPSTRIMEN))
2997 {
2998 return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_SMPS_TRIM) >> PWR_ENGTRIM_SMPS_TRIM_Pos);
2999 }
3000 else
3001 {
3002 return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_SMPS_TRIM) >> PWR_TRIMR_SMPS_TRIM_Pos);
3003 }
3004 }
3005
3006 /**
3007 * @brief Set Main regulator voltage trimming value.
3008 * @rmtoll ENGTRIM LL_PWR_SetMRTrim
3009 * @param trim Main Regulator voltage trimming value
3010 * @retval None
3011 */
LL_PWR_SetMRTrim(uint32_t trim)3012 __STATIC_INLINE void LL_PWR_SetMRTrim(uint32_t trim)
3013 {
3014 MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_MR, ((trim << PWR_ENGTRIM_TRIM_MR_Pos) & PWR_ENGTRIM_TRIM_MR));
3015 SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMMREN);
3016 }
3017
3018 /**
3019 * @brief Get Main regulator voltage trimming value.
3020 * @rmtoll TRIMR/ENGTRIM LL_PWR_GetMRTrim
3021 * @retval Main regulator voltage trimming value
3022 */
LL_PWR_GetMRTrim(void)3023 __STATIC_INLINE uint32_t LL_PWR_GetMRTrim(void)
3024 {
3025 if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMMREN))
3026 {
3027 return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_MR) >> PWR_ENGTRIM_TRIM_MR_Pos);
3028 }
3029 else
3030 {
3031 return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_TRIM_MR) >> PWR_TRIMR_TRIM_MR_Pos);
3032 }
3033 }
3034
3035 #if defined(PWR_ENGTRIM_TRIM_LSI_LPMU)
3036 /**
3037 * @brief Set Low Speed Internal oscillator LPMU trimming value.
3038 * @rmtoll ENGTRIM LL_PWR_SetLPMULSITrim
3039 * @param trim Low Speed Internal oscillator trimming value
3040 * @retval None
3041 */
LL_PWR_SetLSILPMUTrim(uint32_t trim)3042 __STATIC_INLINE void LL_PWR_SetLSILPMUTrim(uint32_t trim)
3043 {
3044 MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_LSI_LPMU, ((trim << PWR_ENGTRIM_TRIM_LSI_LPMU_Pos) & PWR_ENGTRIM_TRIM_LSI_LPMU));
3045 SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMLSILPMUEN);
3046 }
3047
3048 /**
3049 * @brief Get Low Speed Internal oscillator LPMU trimming value.
3050 * @rmtoll TRIMR/ENGTRIM LL_PWR_GetLSITrim
3051 * @retval Low Speed Internal oscillator trimming value
3052 */
LL_PWR_GetLSILPMUTrim(void)3053 __STATIC_INLINE uint32_t LL_PWR_GetLSILPMUTrim(void)
3054 {
3055 if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMLSILPMUEN))
3056 {
3057 return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_LSI_LPMU) >> PWR_ENGTRIM_TRIM_LSI_LPMU_Pos);
3058 }
3059 else
3060 {
3061 return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_TRIM_LSI_LPMU) >> PWR_TRIMR_TRIM_LSI_LPMU_Pos);
3062 }
3063 }
3064 #endif /* PWR_ENGTRIM_TRIM_LSI_LPMU */
3065
3066 #if defined(PWR_ENGTRIM_TRIM_RFDREG)
3067 /**
3068 * @brief Set RF LDO trimming value.
3069 * @rmtoll ENGTRIM LL_PWR_SetRFDREGTrim
3070 * @param trim RF LDO trimming value
3071 * @retval None
3072 */
LL_PWR_SetRFDREGTrim(uint32_t trim)3073 __STATIC_INLINE void LL_PWR_SetRFDREGTrim(uint32_t trim)
3074 {
3075 MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_RFDREG, ((trim << PWR_ENGTRIM_TRIM_RFDREG_Pos) & PWR_ENGTRIM_TRIM_RFDREG));
3076 SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMRFDREGEN);
3077 }
3078
3079 /**
3080 * @brief Get RF LDO trimming value.
3081 * @rmtoll TRIMR/ENGTRIM LL_PWR_GetRFDREGTrim
3082 * @retval RF LDO trimming value
3083 */
LL_PWR_GetRFDREGTrim(void)3084 __STATIC_INLINE uint32_t LL_PWR_GetRFDREGTrim(void)
3085 {
3086 if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMRFDREGEN))
3087 {
3088 return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_RFDREG) >> PWR_ENGTRIM_TRIM_RFDREG_Pos);
3089 }
3090 else
3091 {
3092 return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_RFD_REG_TRIM) >> PWR_TRIMR_RFD_REG_TRIM_Pos);
3093 }
3094 }
3095 #endif /* PWR_ENGTRIM_TRIM_RFDREG */
3096
3097 /** @defgroup PWR_LL_DBG_DEEPSTOP Function to setup the DEEPSTOP2 will be applied instead
3098 * of DEEPSTOP and the debugger features not lost
3099 * @{
3100 */
3101
3102 /**
3103 * @brief Enable the DEEPSTOP2 feature, debugger feature not lost during DEEPSTOP.
3104 * @rmtoll DBGR DEEPSTOP2 LL_PWR_EnableDEEPSTOP2
3105 * @retval None
3106 */
LL_PWR_EnableDEEPSTOP2(void)3107 __STATIC_INLINE void LL_PWR_EnableDEEPSTOP2(void)
3108 {
3109 SET_BIT(PWR->DBGR, PWR_DBGR_DEEPSTOP2);
3110 }
3111
3112 /**
3113 * @brief Disable the DEEPSTOP2 feature, debugger feature lost during DEEPSTOP.
3114 * @rmtoll DBGR DEEPSTOP2 LL_PWR_DisableDEEPSTOP2
3115 * @retval None
3116 */
LL_PWR_DisableDEEPSTOP2(void)3117 __STATIC_INLINE void LL_PWR_DisableDEEPSTOP2(void)
3118 {
3119 CLEAR_BIT(PWR->DBGR, PWR_DBGR_DEEPSTOP2);
3120 }
3121
3122 /**
3123 * @brief Checks if the DEEPSTOP2 feature is enabled or disabled
3124 * @rmtoll DBGR DEEPSTOP2 LL_PWR_IsEnabledDEEPSTOP2
3125 * @retval State of bit (1 or 0).
3126 */
LL_PWR_IsEnabledDEEPSTOP2(void)3127 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDEEPSTOP2(void)
3128 {
3129 return ((READ_BIT(PWR->DBGR, PWR_DBGR_DEEPSTOP2) == (PWR_DBGR_DEEPSTOP2)) ? 1UL : 0UL);
3130 }
3131 /**
3132 * @}
3133 */
3134
3135 #if defined(PWR_CR5_SMPS_PRECH_CUR_SEL)
3136 /**
3137 * @brief Select SMPS PRECHARGE limit current.
3138 * @rmtoll CR5 SMPS_PRECH_CUR_SEL LL_PWR_SetSMPSPrechargeLimitCurrent
3139 * @param mode This parameter can be one of the following values:
3140 * @arg @ref LL_PWR_SMPS_PRECH_LIMIT_CUR_2_5
3141 * @arg @ref LL_PWR_SMPS_PRECH_LIMIT_CUR_5
3142 * @arg @ref LL_PWR_SMPS_PRECH_LIMIT_CUR_10
3143 * @arg @ref LL_PWR_SMPS_PRECH_LIMIT_CUR_20
3144 * @retval None
3145 */
LL_PWR_SetSMPSPrechargeLimitCurrent(uint32_t mode)3146 __STATIC_INLINE void LL_PWR_SetSMPSPrechargeLimitCurrent(uint32_t mode)
3147 {
3148 MODIFY_REG(PWR->CR5, PWR_CR5_SMPS_PRECH_CUR_SEL, mode);
3149 }
3150
3151 /**
3152 * @brief Get SMPS PRECHARGE limit current selected.
3153 * @rmtoll CR5 SMPS_PRECH_CUR_SEL LL_PWR_GetSMPSPrechargeLimitCurrent
3154 * @retval This parameter can be one of the following values:
3155 * @arg @ref LL_PWR_SMPS_PRECH_LIMIT_CUR_2_5
3156 * @arg @ref LL_PWR_SMPS_PRECH_LIMIT_CUR_5
3157 * @arg @ref LL_PWR_SMPS_PRECH_LIMIT_CUR_10
3158 * @arg @ref LL_PWR_SMPS_PRECH_LIMIT_CUR_20
3159 */
LL_PWR_GetSMPSPrechargeLimitCurrent(void)3160 __STATIC_INLINE uint32_t LL_PWR_GetSMPSPrechargeLimitCurrent(void)
3161 {
3162 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPS_PRECH_CUR_SEL));
3163 }
3164 #endif /* PWR_CR5_SMPS_PRECH_CUR_SEL */
3165
3166 #if defined(PWR_SDWN_WUEN_WUEN)
3167 /**
3168 * @brief Shutdown I/O Wakeup enable.
3169 * @rmtoll SDWN_WUEN WUEN LL_PWR_EnableIOWakeupSDN
3170 * @retval None
3171 */
LL_PWR_EnableIOWakeupSDN(void)3172 __STATIC_INLINE void LL_PWR_EnableIOWakeupSDN(void)
3173 {
3174 SET_BIT(PWR->SDWN_WUEN, PWR_SDWN_WUEN_WUEN);
3175 }
3176
3177 /**
3178 * @brief Shutdown I/O Wakeup disable.
3179 * @rmtoll SDWN_WUEN WUEN LL_PWR_DisableIOWakeupSDN
3180 * @retval None
3181 */
LL_PWR_DisableIOWakeupSDN(void)3182 __STATIC_INLINE void LL_PWR_DisableIOWakeupSDN(void)
3183 {
3184 CLEAR_BIT(PWR->SDWN_WUEN, PWR_SDWN_WUEN_WUEN);
3185 }
3186
3187 /**
3188 * @brief Checks if Shutdown I/O Wakeup is enabled or disabled.
3189 * @rmtoll SDWN_WUEN WUEN LL_PWR_IsEnabledIOWakeupSDN
3190 * @retval State of bit (1 or 0).
3191 */
LL_PWR_IsEnabledIOWakeupSDN(void)3192 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIOWakeupSDN(void)
3193 {
3194 return ((READ_BIT(PWR->SDWN_WUEN, PWR_SDWN_WUEN_WUEN) == (PWR_SDWN_WUEN_WUEN)) ? 1UL : 0UL);
3195 }
3196
3197 /**
3198 * @brief Shutdown I/O Wakeup Polarity configuration.
3199 * @rmtoll SDWN_WUPOL WUPOL LL_PWR_IOWakeupPolaritySDN
3200 * @param pol:
3201 * - 0 : PB0 pin wakeup from shutdown on high pulse or high level detection
3202 * - 1 : PB0 pin wakeup from shutdown on low pulse or low level detection
3203 * @retval None
3204 */
LL_PWR_IOWakeupPolaritySDN(uint8_t pol)3205 __STATIC_INLINE void LL_PWR_IOWakeupPolaritySDN(uint8_t pol)
3206 {
3207 if (pol == 0)
3208 {
3209 CLEAR_BIT(PWR->SDWN_WUPOL, PWR_SDWN_WUPOL_WUPOL);
3210 }
3211 else
3212 {
3213 SET_BIT(PWR->SDWN_WUPOL, PWR_SDWN_WUPOL_WUPOL);
3214 }
3215 }
3216
3217 /**
3218 * @brief Checks if Shutdown I/O Wakeup from PB0 pin occurred.
3219 * @rmtoll SDWN_WUF WUF LL_PWR_IsIOWakeupSDN
3220 * @retval State of bit (1 or 0).
3221 */
LL_PWR_IsIOWakeupSDN(void)3222 __STATIC_INLINE uint32_t LL_PWR_IsIOWakeupSDN(void)
3223 {
3224 return ((READ_BIT(PWR->SDWN_WUF, PWR_SDWN_WUF_WUF) == (PWR_SDWN_WUF_WUF)) ? 1UL : 0UL);
3225 }
3226
3227 /**
3228 * @brief Clear I/O Wakeup from PB0 pin occurred flag
3229 * @rmtoll SDWN_WUF WUF LL_PWR_ClearIOWakeupFlagSDN
3230 * @retval None
3231 */
LL_PWR_ClearIOWakeupFlagSDN(void)3232 __STATIC_INLINE void LL_PWR_ClearIOWakeupFlagSDN(void)
3233 {
3234 CLEAR_BIT(PWR->SDWN_WUF, PWR_SDWN_WUF_WUF);
3235 }
3236 #endif /* PWR_SDWN_WUEN_WUEN */
3237
3238 #if defined(USE_FULL_LL_DRIVER)
3239 /** @defgroup PWR_LL_EF_Init De-initialization function
3240 * @{
3241 */
3242 ErrorStatus LL_PWR_DeInit(void);
3243 /**
3244 * @}
3245 */
3246 #endif /* USE_FULL_LL_DRIVER */
3247
3248 /**
3249 * @}
3250 */
3251
3252 /**
3253 * @}
3254 */
3255
3256 #endif /* PWR */
3257
3258 /**
3259 * @}
3260 */
3261
3262 #ifdef __cplusplus
3263 }
3264 #endif
3265
3266 #endif /* STM32WB0x_LL_PWR_H */
3267
