1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U0xx_LL_PWR_H
21 #define STM32U0xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46
47 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
48 * @{
49 */
50
51 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
52 * @brief Flags defines which can be used with LL_PWR_WriteReg function
53 * @{
54 */
55 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
56 #define LL_PWR_SCR_CWUF7 PWR_SCR_CWUF7
57 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
58 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
59 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
60 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
61 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
62 /**
63 * @}
64 */
65
66 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
67 * @brief Flags defines which can be used with LL_PWR_ReadReg function
68 * @{
69 */
70 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
71 #define LL_PWR_SR1_STOP2 (PWR_SR1_STOPF_2 | PWR_SR1_STOPF_1)
72 #define LL_PWR_SR1_STOP1 (PWR_SR1_STOPF_2 | PWR_SR1_STOPF_0)
73 #define LL_PWR_SR1_STOP0 PWR_SR1_STOPF_2
74 #define LL_PWR_SR1_SBF PWR_SR1_SBF
75 #define LL_PWR_SR1_WUF7 PWR_SR1_WUF7
76 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
77 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
78 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
79 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
80 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
81 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
82 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
83 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
84 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
85 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
86 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
87 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
88 #define LL_PWR_SR2_FLASHRDY PWR_SR2_FLASH_RDY
89 /**
90 * @}
91 */
92
93 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
94 * @{
95 */
96 #define LL_PWR_CR1_LPR PWR_CR1_LPR
97 /**
98 * @}
99 */
100
101 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
102 * @{
103 */
104 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_CR1_VOS_0
105 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1
106 /**
107 * @}
108 */
109
110 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
111 * @{
112 */
113 #define LL_PWR_MODE_STOP0 0x00000000U
114 #define LL_PWR_MODE_STOP1 PWR_CR1_LPMS_0
115 #define LL_PWR_MODE_STOP2 PWR_CR1_LPMS_1
116 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
117 #define LL_PWR_MODE_SHUTDOWN PWR_CR1_LPMS_2
118 /**
119 * @}
120 */
121
122 #define LL_PWR_CR1_DBP PWR_CR1_DBP
123 #define LL_PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP
124 #define LL_PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN
125 #define LL_PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP
126
127 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
128 * @{
129 */
130 #if defined(USB_DRD_FS)
131 #define LL_PWR_PVM_VDDUSB_1_2V PWR_CR2_PVME1 /* Monitoring VDDUSB vs. 1.2V */
132 #endif /* USB_DRD_FS */
133 #define LL_PWR_PVM_VDDA_1_62V PWR_CR2_PVME3 /* Monitoring VDDA_P vs. 1.62V */
134 #define LL_PWR_PVM_VDDA_2_2V PWR_CR2_PVME4 /* Monitoring VDDA_P vs. 2.2V */
135 /**
136 * @}
137 */
138
139 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
140 * @{
141 */
142 #define LL_PWR_PVDLEVEL_0 0x00000000U /* VPVD0 around 2.0 V */
143 #define LL_PWR_PVDLEVEL_1 PWR_CR2_PLS_0 /* VPVD1 around 2.2 V */
144 #define LL_PWR_PVDLEVEL_2 PWR_CR2_PLS_1 /* VPVD2 around 2.4 V */
145 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* VPVD3 around 2.5 V */
146 #define LL_PWR_PVDLEVEL_4 PWR_CR2_PLS_2 /* VPVD4 around 2.6 V */
147 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /* VPVD5 around 2.8 V */
148 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /* VPVD6 around 2.9 V */
149 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage
150 (Compare internally to VREFINT) */
151 /**
152 * @}
153 */
154
155 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
156 * @{
157 */
158 #define LL_PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
159 #define LL_PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
160 #define LL_PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
161 #define LL_PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
162 #define LL_PWR_WAKEUP_PIN5 PWR_CR3_EWUP5
163 #define LL_PWR_WAKEUP_PIN7 PWR_CR3_EWUP7
164 /**
165 * @}
166 */
167
168 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
169 * @{
170 */
171 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0U
172 #define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR4_VBRS
173 /**
174 * @}
175 */
176
177 /** @defgroup PWR_LL_EC_SRAM_CONTENT_RETENTION SRAM CONTENT RETENTION
178 * @{
179 */
180 #define LL_PWR_NO_SRAM_RETENTION 0U
181 #define LL_PWR_FULL_SRAM_RETENTION PWR_CR3_RRS
182
183 /**
184 * @}
185 */
186 /** @defgroup PWR_LL_EC_GPIO GPIO
187 * @{
188 */
189 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
190 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
191 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
192 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
193 #if defined (GPIOE)
194 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
195 #endif /* GPIOE */
196 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
197 /**
198 * @}
199 */
200
201 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
202 * @{
203 */
204 #define LL_PWR_GPIO_BIT_0 0x00000001U
205 #define LL_PWR_GPIO_BIT_1 0x00000002U
206 #define LL_PWR_GPIO_BIT_2 0x00000004U
207 #define LL_PWR_GPIO_BIT_3 0x00000008U
208 #define LL_PWR_GPIO_BIT_4 0x00000010U
209 #define LL_PWR_GPIO_BIT_5 0x00000020U
210 #define LL_PWR_GPIO_BIT_6 0x00000040U
211 #define LL_PWR_GPIO_BIT_7 0x00000080U
212 #define LL_PWR_GPIO_BIT_8 0x00000100U
213 #define LL_PWR_GPIO_BIT_9 0x00000200U
214 #define LL_PWR_GPIO_BIT_10 0x00000400U
215 #define LL_PWR_GPIO_BIT_11 0x00000800U
216 #define LL_PWR_GPIO_BIT_12 0x00001000U
217 #define LL_PWR_GPIO_BIT_13 0x00002000U
218 #define LL_PWR_GPIO_BIT_14 0x00004000U
219 #define LL_PWR_GPIO_BIT_15 0x00008000U
220 /**
221 * @}
222 */
223
224 /**
225 * @}
226 */
227
228 /* Exported macro ------------------------------------------------------------*/
229 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
230 * @{
231 */
232
233 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
234 * @{
235 */
236
237 /**
238 * @brief Write a value in PWR register
239 * @param __REG__ Register to be written
240 * @param __VALUE__ Value to be written in the register
241 * @retval None
242 */
243 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
244
245 /**
246 * @brief Read a value in PWR register
247 * @param __REG__ Register to be read
248 * @retval Register value
249 */
250 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
251 /**
252 * @}
253 */
254
255 /**
256 * @}
257 */
258
259 /* Exported functions --------------------------------------------------------*/
260 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
261 * @{
262 */
263
264 /** @defgroup PWR_LL_EF_Configuration Configuration
265 * @{
266 */
267
268 /**
269 * @brief Set Low-Power mode
270 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
271 * @param LowPowerMode This parameter can be one of the following values:
272 * @arg @ref LL_PWR_MODE_STOP0
273 * @arg @ref LL_PWR_MODE_STOP1
274 * @arg @ref LL_PWR_MODE_STOP2
275 * @arg @ref LL_PWR_MODE_STANDBY
276 * @arg @ref LL_PWR_MODE_SHUTDOWN
277 * @retval None
278 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)279 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
280 {
281 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
282 }
283
284 /**
285 * @brief Get Low-Power mode
286 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
287 * @retval Returned value can be one of the following values:
288 * @arg @ref LL_PWR_MODE_STOP0
289 * @arg @ref LL_PWR_MODE_STOP1
290 * @arg @ref LL_PWR_MODE_STOP2
291 * @arg @ref LL_PWR_MODE_STANDBY
292 * @arg @ref LL_PWR_MODE_SHUTDOWN
293 */
LL_PWR_GetPowerMode(void)294 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
295 {
296 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
297 }
298
299 /**
300 * @brief Enable Flash Pwr Down Mode during Stop
301 * @rmtoll CR1 FPD_STOP LL_PWR_EnableFlashPWRDownModeDuringStop
302 * @retval None
303 */
LL_PWR_EnableFlashPWRDownModeDuringStop(void)304 __STATIC_INLINE void LL_PWR_EnableFlashPWRDownModeDuringStop(void)
305 {
306 SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
307 }
308
309 /**
310 * @brief Disable Flash Pwr Down Mode during Stop
311 * @rmtoll CR1 FPD_STOP LL_PWR_DisableFlashPWRDownModeDuringStop
312 * @retval None
313 */
LL_PWR_DisableFlashPWRDownModeDuringStop(void)314 __STATIC_INLINE void LL_PWR_DisableFlashPWRDownModeDuringStop(void)
315 {
316 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
317 }
318
319 /**
320 * @brief Check if Flash Pwr Down Mode during Stop is enabled
321 * @rmtoll CR1 FPD_STOP LL_PWR_IsEnabledFlashPWRDownModeDuringSTOP
322 * @retval State of bit (1 or 0).
323 */
LL_PWR_IsEnabledFlashPWRDownModeDuringSTOP(void)324 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPWRDownModeDuringSTOP(void)
325 {
326 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL);
327 }
328
329 /**
330 * @brief Enable Flash Pwr Down Mode during LP run
331 * @rmtoll CR1 FPD_LPRUN LL_PWR_EnableFlashPWRDownModeDuringLPRun
332 * @retval None
333 */
LL_PWR_EnableFlashPWRDownModeDuringLPRun(void)334 __STATIC_INLINE void LL_PWR_EnableFlashPWRDownModeDuringLPRun(void)
335 {
336 SET_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
337 }
338
339 /**
340 * @brief Disable Flash Pwr Down Mode during LP run
341 * @rmtoll CR1 FPD_LPRUN LL_PWR_DisableFlashPWRDownModeDuringLPRun
342 * @retval None
343 */
LL_PWR_DisableFlashPWRDownModeDuringLPRun(void)344 __STATIC_INLINE void LL_PWR_DisableFlashPWRDownModeDuringLPRun(void)
345 {
346 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
347 }
348
349 /**
350 * @brief Check if Flash Pwr Down Mode during LP run is enabled
351 * @rmtoll CR1 FPD_LPRUN LL_PWR_IsEnabledFlashPWRDownModeDuringLPRun
352 * @retval State of bit (1 or 0).
353 */
LL_PWR_IsEnabledFlashPWRDownModeDuringLPRun(void)354 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPWRDownModeDuringLPRun(void)
355 {
356 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN) == (PWR_CR1_FPD_LPRUN)) ? 1UL : 0UL);
357 }
358
359 /**
360 * @brief Enable Flash Pwr Down Mode during LP Sleep
361 * @rmtoll CR1 FPD_LPSLP LL_PWR_EnableFlashPWRDownModeDuringSleeep
362 * @retval None
363 */
LL_PWR_EnableFlashPWRDownModeDuringSleeep(void)364 __STATIC_INLINE void LL_PWR_EnableFlashPWRDownModeDuringSleeep(void)
365 {
366 SET_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
367 }
368
369 /**
370 * @brief Disable Flash Pwr Down Mode during LP Sleep
371 * @rmtoll CR1 FPD_LPSLP LL_PWR_DisableFlashPWRDownModeDuringSleeep
372 * @retval None
373 */
LL_PWR_DisableFlashPWRDownModeDuringSleeep(void)374 __STATIC_INLINE void LL_PWR_DisableFlashPWRDownModeDuringSleeep(void)
375 {
376 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
377 }
378
379 /**
380 * @brief Check if Flash Pwr Down Mode is enabled during Sleep
381 * @rmtoll CR1 FPD_LPSLP LL_PWR_IsEnabledFlashPWRDownModeDuringSleeep
382 * @retval State of bit (1 or 0).
383 */
LL_PWR_IsEnabledFlashPWRDownModeDuringSleeep(void)384 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPWRDownModeDuringSleeep(void)
385 {
386 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP) == (PWR_CR1_FPD_LPSLP)) ? 1UL : 0UL);
387 }
388
389 /**
390 * @brief Enable access to the backup domain
391 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
392 * @retval None
393 */
LL_PWR_EnableBkUpAccess(void)394 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
395 {
396 SET_BIT(PWR->CR1, PWR_CR1_DBP);
397 }
398
399 /**
400 * @brief Disable access to the backup domain
401 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
402 * @retval None
403 */
LL_PWR_DisableBkUpAccess(void)404 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
405 {
406 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
407 }
408
409 /**
410 * @brief Check if the backup domain is enabled
411 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
412 * @retval State of bit (1 or 0).
413 */
LL_PWR_IsEnabledBkUpAccess(void)414 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
415 {
416 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
417 }
418
419 /**
420 * @brief Set the main internal regulator output voltage
421 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
422 * @param VoltageScaling This parameter can be one of the following values:
423 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
424 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
425 * @retval None
426 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)427 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
428 {
429 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
430 }
431
432 /**
433 * @brief Get the main internal regulator output voltage
434 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
435 * @retval Returned value can be one of the following values:
436 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
437 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
438 */
LL_PWR_GetRegulVoltageScaling(void)439 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
440 {
441 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
442 }
443 /**
444 * @brief Switch the regulator from main mode to low-power mode
445 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
446 * @retval None
447 */
LL_PWR_EnableLowPowerRunMode(void)448 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
449 {
450 SET_BIT(PWR->CR1, PWR_CR1_LPR);
451 }
452
453 /**
454 * @brief Switch the regulator from low-power mode to main mode
455 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
456 * @retval None
457 */
LL_PWR_DisableLowPowerRunMode(void)458 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
459 {
460 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
461 }
462
463 /** * @brief Switch from run main mode to run low-power mode.
464 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
465 * @retval None
466 */
LL_PWR_EnterLowPowerRunMode(void)467 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
468 {
469 LL_PWR_EnableLowPowerRunMode();
470 }
471
472 /**
473 * @brief Switch from run main mode to low-power mode.
474 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
475 * @retval None
476 */
LL_PWR_ExitLowPowerRunMode(void)477 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
478 {
479 LL_PWR_DisableLowPowerRunMode();
480 }
481
482 /**
483 * @brief Check if the regulator is in low-power mode
484 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
485 * @retval State of bit (1 or 0).
486 */
LL_PWR_IsEnabledLowPowerRunMode(void)487 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
488 {
489 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
490 }
491
492 /**
493 * @brief Enable Power Voltage Detector
494 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
495 * @retval None
496 */
LL_PWR_EnablePVD(void)497 __STATIC_INLINE void LL_PWR_EnablePVD(void)
498 {
499 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
500 }
501
502 /**
503 * @brief Disable Power Voltage Detector
504 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
505 * @retval None
506 */
LL_PWR_DisablePVD(void)507 __STATIC_INLINE void LL_PWR_DisablePVD(void)
508 {
509 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
510 }
511
512 /**
513 * @brief Check if Power Voltage Detector is enabled
514 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
515 * @retval State of bit (1 or 0).
516 */
LL_PWR_IsEnabledPVD(void)517 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
518 {
519 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
520 }
521
522 /**
523 * @brief Configure the voltage threshold detected by the Power Voltage Detector
524 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
525 * @param PVDLevel This parameter can be one of the following values:
526 * @arg @ref LL_PWR_PVDLEVEL_0
527 * @arg @ref LL_PWR_PVDLEVEL_1
528 * @arg @ref LL_PWR_PVDLEVEL_2
529 * @arg @ref LL_PWR_PVDLEVEL_3
530 * @arg @ref LL_PWR_PVDLEVEL_4
531 * @arg @ref LL_PWR_PVDLEVEL_5
532 * @arg @ref LL_PWR_PVDLEVEL_6
533 * @arg @ref LL_PWR_PVDLEVEL_7
534 * @retval None
535 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)536 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
537 {
538 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
539 }
540
541 /**
542 * @brief Get the voltage threshold detection
543 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
544 * @retval Returned value can be one of the following values:
545 * @arg @ref LL_PWR_PVDLEVEL_0
546 * @arg @ref LL_PWR_PVDLEVEL_1
547 * @arg @ref LL_PWR_PVDLEVEL_2
548 * @arg @ref LL_PWR_PVDLEVEL_3
549 * @arg @ref LL_PWR_PVDLEVEL_4
550 * @arg @ref LL_PWR_PVDLEVEL_5
551 * @arg @ref LL_PWR_PVDLEVEL_6
552 * @arg @ref LL_PWR_PVDLEVEL_7
553 */
LL_PWR_GetPVDLevel(void)554 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
555 {
556 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
557 }
558
559 /**
560 * @brief Enable the Power Voltage Monitoring on a peripheral
561 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
562 * CR2 PVME2 LL_PWR_EnablePVM\n
563 * CR2 PVME3 LL_PWR_EnablePVM\n
564 * @param PeriphVoltage This parameter can be one of the following values:
565 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
566 * @arg @ref LL_PWR_PVM_VDDA_1_62V
567 * @arg @ref LL_PWR_PVM_VDDA_2_2V
568 *
569 * (*) value not defined in all devices
570 * @retval None
571 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)572 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
573 {
574 SET_BIT(PWR->CR2, PeriphVoltage);
575 }
576
577 /**
578 * @brief Disable the Power Voltage Monitoring on a peripheral
579 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
580 * CR2 PVME2 LL_PWR_DisablePVM\n
581 * CR2 PVME3 LL_PWR_DisablePVM\n
582 * @param PeriphVoltage This parameter can be one of the following values:
583 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
584 * @arg @ref LL_PWR_PVM_VDDA_1_62V
585 * @arg @ref LL_PWR_PVM_VDDA_2_2V
586 *
587 * (*) value not defined in all devices
588 * @retval None
589 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)590 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
591 {
592 CLEAR_BIT(PWR->CR2, PeriphVoltage);
593 }
594
595 /**
596 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
597 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
598 * CR2 PVME2 LL_PWR_IsEnabledPVM\n
599 * CR2 PVME3 LL_PWR_IsEnabledPVM\n
600 * @param PeriphVoltage This parameter can be one of the following values:
601 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
602 * @arg @ref LL_PWR_PVM_VDDA_1_62V
603 * @arg @ref LL_PWR_PVM_VDDA_2_2V
604 *
605 * (*) value not defined in all devices
606 * @retval State of bit (1 or 0).
607 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)608 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
609 {
610 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
611 }
612
613 #if defined(USB_DRD_FS)
614 /**
615 * @brief Enable VDDUSB supply
616 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
617 * @retval None
618 */
LL_PWR_EnableVddUSB(void)619 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
620 {
621 SET_BIT(PWR->CR2, PWR_CR2_USV);
622 }
623
624 /**
625 * @brief Disable VDDUSB supply
626 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
627 * @retval None
628 */
LL_PWR_DisableVddUSB(void)629 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
630 {
631 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
632 }
633
634 /**
635 * @brief Check if VDDUSB supply is enabled
636 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
637 * @retval State of bit (1 or 0).
638 */
LL_PWR_IsEnabledVddUSB(void)639 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
640 {
641 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
642 }
643 #endif /* USB_DRD_FS */
644
645 /**
646 * @brief Enable the WakeUp PINx functionality
647 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
648 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
649 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
650 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
651 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
652 * CR3 EWUP7 LL_PWR_EnableWakeUpPin\n
653 * @param WakeUpPin This parameter can be one of the following values:
654 * @arg @ref LL_PWR_WAKEUP_PIN1
655 * @arg @ref LL_PWR_WAKEUP_PIN2
656 * @arg @ref LL_PWR_WAKEUP_PIN3
657 * @arg @ref LL_PWR_WAKEUP_PIN4
658 * @arg @ref LL_PWR_WAKEUP_PIN5
659 * @arg @ref LL_PWR_WAKEUP_PIN7
660 * @retval None
661 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)662 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
663 {
664 SET_BIT(PWR->CR3, WakeUpPin);
665 }
666
667 /**
668 * @brief Disable the WakeUp PINx functionality
669 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
670 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
671 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
672 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
673 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
674 * CR3 EWUP7 LL_PWR_DisableWakeUpPin\n
675 * @param WakeUpPin This parameter can be one of the following values:
676 * @arg @ref LL_PWR_WAKEUP_PIN1
677 * @arg @ref LL_PWR_WAKEUP_PIN2
678 * @arg @ref LL_PWR_WAKEUP_PIN3
679 * @arg @ref LL_PWR_WAKEUP_PIN4
680 * @arg @ref LL_PWR_WAKEUP_PIN5
681 * @arg @ref LL_PWR_WAKEUP_PIN7
682 * @retval None
683 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)684 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
685 {
686 CLEAR_BIT(PWR->CR3, WakeUpPin);
687 }
688
689 /**
690 * @brief Check if the WakeUp PINx functionality is enabled
691 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
692 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
693 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
694 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
695 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
696 * CR3 EWUP7 LL_PWR_IsEnabledWakeUpPin\n
697 * @param WakeUpPin This parameter can be one of the following values:
698 * @arg @ref LL_PWR_WAKEUP_PIN1
699 * @arg @ref LL_PWR_WAKEUP_PIN2
700 * @arg @ref LL_PWR_WAKEUP_PIN3
701 * @arg @ref LL_PWR_WAKEUP_PIN4
702 * @arg @ref LL_PWR_WAKEUP_PIN5
703 * @arg @ref LL_PWR_WAKEUP_PIN7
704 * @retval State of bit (1 or 0).
705 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)706 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
707 {
708 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
709 }
710
711 /**
712 * @brief Enable SRAM full content retention in Standby mode
713 * @rmtoll CR3 RRS LL_PWR_EnableSRAMRetention
714 * @retval None
715 */
LL_PWR_EnableSRAMRetention(void)716 __STATIC_INLINE void LL_PWR_EnableSRAMRetention(void)
717 {
718 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM_RETENTION);
719 }
720
721 /**
722 * @brief Disable SRAM content retention in Standby mode
723 * @rmtoll CR3 RRS LL_PWR_DisableSRAMRetention
724 * @retval None
725 */
LL_PWR_DisableSRAMRetention(void)726 __STATIC_INLINE void LL_PWR_DisableSRAMRetention(void)
727 {
728 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
729 }
730
731 /**
732 * @brief Check if SRAM full content retention in Standby mode is enabled
733 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAMRetention
734 * @retval State of bit (1 or 0).
735 */
LL_PWR_IsEnabledSRAMRetention(void)736 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAMRetention(void)
737 {
738 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM_RETENTION)) ? 1UL : 0UL);
739 }
740
741 /**
742 * @brief Set SRAM content retention in Standby mode
743 * @rmtoll CR3 RRS LL_PWR_SetSRAMContentRetention
744 * @param SRAMSize This parameter can be one of the following values:
745 * @arg @ref LL_PWR_NO_SRAM_RETENTION
746 * @arg @ref LL_PWR_FULL_SRAM_RETENTION
747 * @note Setting LL_PWR_NO_SRAM_RETENTION is same as calling LL_PWR_DisableSRAMRetention()
748 * @note Setting LL_PWR_FULL_SRAM_RETENTION is same as calling LL_PWR_EnableSRAMRetention()
749 * @retval None
750 */
LL_PWR_SetSRAMContentRetention(uint32_t SRAMSize)751 __STATIC_INLINE void LL_PWR_SetSRAMContentRetention(uint32_t SRAMSize)
752 {
753 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAMSize);
754 }
755
756 /**
757 * @brief Get SRAM content retention in Standby mode
758 * @rmtoll CR3 RRS LL_PWR_GetSRAMContentRetention
759 * @retval Returned value can be one of the following values:
760 * @arg @ref LL_PWR_NO_SRAM_RETENTION
761 * @arg @ref LL_PWR_FULL_SRAM_RETENTION
762 */
LL_PWR_GetSRAMContentRetention(void)763 __STATIC_INLINE uint32_t LL_PWR_GetSRAMContentRetention(void)
764 {
765 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS));
766 }
767
768 /**
769 * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes
770 * @rmtoll CR3 ENULP LL_PWR_EnableBORPVD_ULP
771 * @retval None
772 */
LL_PWR_EnableBORPVD_ULP(void)773 __STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void)
774 {
775 SET_BIT(PWR->CR3, PWR_CR3_ENULP);
776 }
777
778 /**
779 * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes
780 * @rmtoll CR3 ENULP LL_PWR_DisableBORPVD_ULP
781 * @retval None
782 */
LL_PWR_DisableBORPVD_ULP(void)783 __STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void)
784 {
785 CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);
786 }
787
788 /**
789 * @brief Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled
790 * @rmtoll CR3 ENULP LL_PWR_IsEnabledBORPVD_ULP
791 * @retval State of bit (1 or 0).
792 */
LL_PWR_IsEnabledBORPVD_ULP(void)793 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void)
794 {
795 return ((READ_BIT(PWR->CR3, PWR_CR3_ENULP) == (PWR_CR3_ENULP)) ? 1UL : 0UL);
796 }
797
798 /**
799 * @brief Enable pull-up and pull-down configuration
800 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
801 * @retval None
802 */
LL_PWR_EnablePUPDCfg(void)803 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
804 {
805 SET_BIT(PWR->CR3, PWR_CR3_APC);
806 }
807
808 /**
809 * @brief Disable pull-up and pull-down configuration
810 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
811 * @retval None
812 */
LL_PWR_DisablePUPDCfg(void)813 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
814 {
815 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
816 }
817
818 /**
819 * @brief Check if pull-up and pull-down configuration is enabled
820 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
821 * @retval State of bit (1 or 0).
822 */
LL_PWR_IsEnabledPUPDCfg(void)823 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
824 {
825 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
826 }
827
828 /**
829 * @brief Enable Internal Wake-up line
830 * @rmtoll CR3 EIWUL LL_PWR_EnableInternWU
831 * @retval None
832 */
LL_PWR_EnableInternWU(void)833 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
834 {
835 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
836 }
837
838 /**
839 * @brief Disable Internal Wake-up line
840 * @rmtoll CR3 EIWUL LL_PWR_DisableInternWU
841 * @retval None
842 */
LL_PWR_DisableInternWU(void)843 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
844 {
845 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
846 }
847
848 /**
849 * @brief Check if Internal Wake-up line is enabled
850 * @rmtoll CR3 EIWUL LL_PWR_IsEnabledInternWU
851 * @retval State of bit (1 or 0).
852 */
LL_PWR_IsEnabledInternWU(void)853 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
854 {
855 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
856 }
857
858 /**
859 * @brief Set the Wake-Up pin polarity low for the event detection
860 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
861 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
862 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
863 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
864 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow\n
865 * CR4 WP7 LL_PWR_SetWakeUpPinPolarityLow
866 * @param WakeUpPin This parameter can be one of the following values:
867 * @arg @ref LL_PWR_WAKEUP_PIN1
868 * @arg @ref LL_PWR_WAKEUP_PIN2
869 * @arg @ref LL_PWR_WAKEUP_PIN3
870 * @arg @ref LL_PWR_WAKEUP_PIN4
871 * @arg @ref LL_PWR_WAKEUP_PIN5
872 * @arg @ref LL_PWR_WAKEUP_PIN7
873 * @retval None
874 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)875 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
876 {
877 SET_BIT(PWR->CR4, WakeUpPin);
878 }
879
880 /**
881 * @brief Set the Wake-Up pin polarity high for the event detection
882 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
883 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
884 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
885 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
886 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh\n
887 * CR4 WP7 LL_PWR_SetWakeUpPinPolarityHigh\n
888 * @param WakeUpPin This parameter can be one of the following values:
889 * @arg @ref LL_PWR_WAKEUP_PIN1
890 * @arg @ref LL_PWR_WAKEUP_PIN2
891 * @arg @ref LL_PWR_WAKEUP_PIN3
892 * @arg @ref LL_PWR_WAKEUP_PIN4
893 * @arg @ref LL_PWR_WAKEUP_PIN5
894 * @arg @ref LL_PWR_WAKEUP_PIN7
895 * @retval None
896 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)897 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
898 {
899 CLEAR_BIT(PWR->CR4, WakeUpPin);
900 }
901
902 /**
903 * @brief Get the Wake-Up pin polarity for the event detection
904 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
905 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
906 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
907 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
908 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow\n
909 * CR4 WP7 LL_PWR_IsWakeUpPinPolarityLow\n
910 * @param WakeUpPin This parameter can be one of the following values:
911 * @arg @ref LL_PWR_WAKEUP_PIN1
912 * @arg @ref LL_PWR_WAKEUP_PIN2
913 * @arg @ref LL_PWR_WAKEUP_PIN3
914 * @arg @ref LL_PWR_WAKEUP_PIN4
915 * @arg @ref LL_PWR_WAKEUP_PIN5
916 * @arg @ref LL_PWR_WAKEUP_PIN7
917 * @retval State of bit (1 or 0).
918 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)919 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
920 {
921 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
922 }
923
924 /**
925 * @brief Enable battery charging
926 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
927 * @retval None
928 */
LL_PWR_EnableBatteryCharging(void)929 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
930 {
931 SET_BIT(PWR->CR4, PWR_CR4_VBE);
932 }
933
934 /**
935 * @brief Disable battery charging
936 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
937 * @retval None
938 */
LL_PWR_DisableBatteryCharging(void)939 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
940 {
941 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
942 }
943
944 /**
945 * @brief Check if battery charging is enabled
946 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
947 * @retval State of bit (1 or 0).
948 */
LL_PWR_IsEnabledBatteryCharging(void)949 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
950 {
951 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
952 }
953
954 /**
955 * @brief Set the resistor impedance
956 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
957 * @param Resistor This parameter can be one of the following values:
958 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
959 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
960 * @retval None
961 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)962 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
963 {
964 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
965 }
966
967 /**
968 * @brief Get the resistor impedance
969 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
970 * @retval Returned value can be one of the following values:
971 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
972 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
973 */
LL_PWR_GetBattChargResistor(void)974 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
975 {
976 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
977 }
978
979 /**
980 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
981 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
982 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
983 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
984 * PUCRD PU0-13 LL_PWR_EnableGPIOPullUp\n
985 * PUCRE PU3,PU7-9 LL_PWR_EnableGPIOPullUp\n
986 * PUCRF PU0-3 LL_PWR_EnableGPIOPullUp\n
987 * @param GPIO This parameter can be one of the following values:
988 * @arg @ref LL_PWR_GPIO_A
989 * @arg @ref LL_PWR_GPIO_B
990 * @arg @ref LL_PWR_GPIO_C
991 * @arg @ref LL_PWR_GPIO_D
992 * @arg @ref LL_PWR_GPIO_E
993 * @arg @ref LL_PWR_GPIO_F
994 * @param GPIONumber This parameter can be one of the following values:
995 * @arg @ref LL_PWR_GPIO_BIT_0
996 * @arg @ref LL_PWR_GPIO_BIT_1
997 * @arg @ref LL_PWR_GPIO_BIT_2
998 * @arg @ref LL_PWR_GPIO_BIT_3
999 * @arg @ref LL_PWR_GPIO_BIT_4
1000 * @arg @ref LL_PWR_GPIO_BIT_5
1001 * @arg @ref LL_PWR_GPIO_BIT_6
1002 * @arg @ref LL_PWR_GPIO_BIT_7
1003 * @arg @ref LL_PWR_GPIO_BIT_8
1004 * @arg @ref LL_PWR_GPIO_BIT_9
1005 * @arg @ref LL_PWR_GPIO_BIT_10
1006 * @arg @ref LL_PWR_GPIO_BIT_11
1007 * @arg @ref LL_PWR_GPIO_BIT_12
1008 * @arg @ref LL_PWR_GPIO_BIT_13
1009 * @arg @ref LL_PWR_GPIO_BIT_14
1010 * @arg @ref LL_PWR_GPIO_BIT_15
1011 * @retval None
1012 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1013 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1014 {
1015 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1016 }
1017
1018 /**
1019 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1020 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1021 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1022 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1023 * PUCRD PU0-13 LL_PWR_EnableGPIOPullUp\n
1024 * PUCRE PU3,PU7-9 LL_PWR_EnableGPIOPullUp\n
1025 * PUCRF PU0-3 LL_PWR_EnableGPIOPullUp\n
1026 * @param GPIO This parameter can be one of the following values:
1027 * @arg @ref LL_PWR_GPIO_A
1028 * @arg @ref LL_PWR_GPIO_B
1029 * @arg @ref LL_PWR_GPIO_C
1030 * @arg @ref LL_PWR_GPIO_D
1031 * @arg @ref LL_PWR_GPIO_E
1032 * @arg @ref LL_PWR_GPIO_F
1033 * @param GPIONumber This parameter can be one of the following values:
1034 * @arg @ref LL_PWR_GPIO_BIT_0
1035 * @arg @ref LL_PWR_GPIO_BIT_1
1036 * @arg @ref LL_PWR_GPIO_BIT_2
1037 * @arg @ref LL_PWR_GPIO_BIT_3
1038 * @arg @ref LL_PWR_GPIO_BIT_4
1039 * @arg @ref LL_PWR_GPIO_BIT_5
1040 * @arg @ref LL_PWR_GPIO_BIT_6
1041 * @arg @ref LL_PWR_GPIO_BIT_7
1042 * @arg @ref LL_PWR_GPIO_BIT_8
1043 * @arg @ref LL_PWR_GPIO_BIT_9
1044 * @arg @ref LL_PWR_GPIO_BIT_10
1045 * @arg @ref LL_PWR_GPIO_BIT_11
1046 * @arg @ref LL_PWR_GPIO_BIT_12
1047 * @arg @ref LL_PWR_GPIO_BIT_13
1048 * @arg @ref LL_PWR_GPIO_BIT_14
1049 * @arg @ref LL_PWR_GPIO_BIT_15
1050 * @retval None
1051 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1052 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1053 {
1054 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1055 }
1056
1057 /**
1058 * @brief Check if GPIO pull-up state is enabled
1059 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1060 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1061 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1062 * PUCRD PU0-13 LL_PWR_EnableGPIOPullUp\n
1063 * PUCRE PU3,PU7-9 LL_PWR_EnableGPIOPullUp\n
1064 * PUCRF PU0-3 LL_PWR_EnableGPIOPullUp\n
1065 * @param GPIO This parameter can be one of the following values:
1066 * @arg @ref LL_PWR_GPIO_A
1067 * @arg @ref LL_PWR_GPIO_B
1068 * @arg @ref LL_PWR_GPIO_C
1069 * @arg @ref LL_PWR_GPIO_D
1070 * @arg @ref LL_PWR_GPIO_E
1071 * @arg @ref LL_PWR_GPIO_F
1072 * @param GPIONumber This parameter can be one of the following values:
1073 * @arg @ref LL_PWR_GPIO_BIT_0
1074 * @arg @ref LL_PWR_GPIO_BIT_1
1075 * @arg @ref LL_PWR_GPIO_BIT_2
1076 * @arg @ref LL_PWR_GPIO_BIT_3
1077 * @arg @ref LL_PWR_GPIO_BIT_4
1078 * @arg @ref LL_PWR_GPIO_BIT_5
1079 * @arg @ref LL_PWR_GPIO_BIT_6
1080 * @arg @ref LL_PWR_GPIO_BIT_7
1081 * @arg @ref LL_PWR_GPIO_BIT_8
1082 * @arg @ref LL_PWR_GPIO_BIT_9
1083 * @arg @ref LL_PWR_GPIO_BIT_10
1084 * @arg @ref LL_PWR_GPIO_BIT_11
1085 * @arg @ref LL_PWR_GPIO_BIT_12
1086 * @arg @ref LL_PWR_GPIO_BIT_13
1087 * @arg @ref LL_PWR_GPIO_BIT_14
1088 * @arg @ref LL_PWR_GPIO_BIT_15
1089 * @retval State of bit (1 or 0).
1090 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1091 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1092 {
1093 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1094 }
1095
1096 /**
1097 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1098 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1099 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1100 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1101 * PUCRD PU0-13 LL_PWR_EnableGPIOPullUp\n
1102 * PUCRE PU3,PU7-9 LL_PWR_EnableGPIOPullUp\n
1103 * PUCRF PU0-3 LL_PWR_EnableGPIOPullUp\n
1104 * @param GPIO This parameter can be one of the following values:
1105 * @arg @ref LL_PWR_GPIO_A
1106 * @arg @ref LL_PWR_GPIO_B
1107 * @arg @ref LL_PWR_GPIO_C
1108 * @arg @ref LL_PWR_GPIO_D
1109 * @arg @ref LL_PWR_GPIO_E
1110 * @arg @ref LL_PWR_GPIO_F
1111 * @param GPIONumber This parameter can be one of the following values:
1112 * @arg @ref LL_PWR_GPIO_BIT_0
1113 * @arg @ref LL_PWR_GPIO_BIT_1
1114 * @arg @ref LL_PWR_GPIO_BIT_2
1115 * @arg @ref LL_PWR_GPIO_BIT_3
1116 * @arg @ref LL_PWR_GPIO_BIT_4
1117 * @arg @ref LL_PWR_GPIO_BIT_5
1118 * @arg @ref LL_PWR_GPIO_BIT_6
1119 * @arg @ref LL_PWR_GPIO_BIT_7
1120 * @arg @ref LL_PWR_GPIO_BIT_8
1121 * @arg @ref LL_PWR_GPIO_BIT_9
1122 * @arg @ref LL_PWR_GPIO_BIT_10
1123 * @arg @ref LL_PWR_GPIO_BIT_11
1124 * @arg @ref LL_PWR_GPIO_BIT_12
1125 * @arg @ref LL_PWR_GPIO_BIT_13
1126 * @arg @ref LL_PWR_GPIO_BIT_14
1127 * @arg @ref LL_PWR_GPIO_BIT_15
1128 * @retval None
1129 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1130 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1131 {
1132 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1133 }
1134
1135 /**
1136 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1137 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1138 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1139 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1140 * PUCRD PU0-13 LL_PWR_EnableGPIOPullUp\n
1141 * PUCRE PU3,PU7-9 LL_PWR_EnableGPIOPullUp\n
1142 * PUCRF PU0-3 LL_PWR_EnableGPIOPullUp\n
1143 * @param GPIO This parameter can be one of the following values:
1144 * @arg @ref LL_PWR_GPIO_A
1145 * @arg @ref LL_PWR_GPIO_B
1146 * @arg @ref LL_PWR_GPIO_C
1147 * @arg @ref LL_PWR_GPIO_D
1148 * @arg @ref LL_PWR_GPIO_E
1149 * @arg @ref LL_PWR_GPIO_F
1150 * @param GPIONumber This parameter can be one of the following values:
1151 * @arg @ref LL_PWR_GPIO_BIT_0
1152 * @arg @ref LL_PWR_GPIO_BIT_1
1153 * @arg @ref LL_PWR_GPIO_BIT_2
1154 * @arg @ref LL_PWR_GPIO_BIT_3
1155 * @arg @ref LL_PWR_GPIO_BIT_4
1156 * @arg @ref LL_PWR_GPIO_BIT_5
1157 * @arg @ref LL_PWR_GPIO_BIT_6
1158 * @arg @ref LL_PWR_GPIO_BIT_7
1159 * @arg @ref LL_PWR_GPIO_BIT_8
1160 * @arg @ref LL_PWR_GPIO_BIT_9
1161 * @arg @ref LL_PWR_GPIO_BIT_10
1162 * @arg @ref LL_PWR_GPIO_BIT_11
1163 * @arg @ref LL_PWR_GPIO_BIT_12
1164 * @arg @ref LL_PWR_GPIO_BIT_13
1165 * @arg @ref LL_PWR_GPIO_BIT_14
1166 * @arg @ref LL_PWR_GPIO_BIT_15
1167 * @retval None
1168 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1169 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1170 {
1171 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1172 }
1173
1174 /**
1175 * @brief Check if GPIO pull-down state is enabled
1176 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1177 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1178 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1179 * PUCRD PU0-13 LL_PWR_EnableGPIOPullUp\n
1180 * PUCRE PU3,PU7-9 LL_PWR_EnableGPIOPullUp\n
1181 * PUCRF PU0-3 LL_PWR_EnableGPIOPullUp\n
1182 * @param GPIO This parameter can be one of the following values:
1183 * @arg @ref LL_PWR_GPIO_A
1184 * @arg @ref LL_PWR_GPIO_B
1185 * @arg @ref LL_PWR_GPIO_C
1186 * @arg @ref LL_PWR_GPIO_D
1187 * @arg @ref LL_PWR_GPIO_E
1188 * @arg @ref LL_PWR_GPIO_F
1189 * @param GPIONumber This parameter can be one of the following values:
1190 * @arg @ref LL_PWR_GPIO_BIT_0
1191 * @arg @ref LL_PWR_GPIO_BIT_1
1192 * @arg @ref LL_PWR_GPIO_BIT_2
1193 * @arg @ref LL_PWR_GPIO_BIT_3
1194 * @arg @ref LL_PWR_GPIO_BIT_4
1195 * @arg @ref LL_PWR_GPIO_BIT_5
1196 * @arg @ref LL_PWR_GPIO_BIT_6
1197 * @arg @ref LL_PWR_GPIO_BIT_7
1198 * @arg @ref LL_PWR_GPIO_BIT_8
1199 * @arg @ref LL_PWR_GPIO_BIT_9
1200 * @arg @ref LL_PWR_GPIO_BIT_10
1201 * @arg @ref LL_PWR_GPIO_BIT_11
1202 * @arg @ref LL_PWR_GPIO_BIT_12
1203 * @arg @ref LL_PWR_GPIO_BIT_13
1204 * @arg @ref LL_PWR_GPIO_BIT_14
1205 * @arg @ref LL_PWR_GPIO_BIT_15
1206 * @retval State of bit (1 or 0).
1207 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1208 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1209 {
1210 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1211 }
1212 /**
1213 * @}
1214 */
1215
1216 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1217 * @{
1218 */
1219
1220 /**
1221 * @brief Get Wake-up Flag 1
1222 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1223 * @retval State of bit (1 or 0).
1224 */
LL_PWR_IsActiveFlag_WU1(void)1225 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1226 {
1227 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1228 }
1229
1230 /**
1231 * @brief Get Wake-up Flag 2
1232 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1233 * @retval State of bit (1 or 0).
1234 */
LL_PWR_IsActiveFlag_WU2(void)1235 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1236 {
1237 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1238 }
1239
1240 /**
1241 * @brief Get Wake-up Flag 3
1242 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1243 * @retval State of bit (1 or 0).
1244 */
LL_PWR_IsActiveFlag_WU3(void)1245 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1246 {
1247 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1248 }
1249
1250 /**
1251 * @brief Get Wake-up Flag 4
1252 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1253 * @retval State of bit (1 or 0).
1254 */
LL_PWR_IsActiveFlag_WU4(void)1255 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1256 {
1257 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1258 }
1259
1260 /**
1261 * @brief Get Wake-up Flag 5
1262 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1263 * @retval State of bit (1 or 0).
1264 */
LL_PWR_IsActiveFlag_WU5(void)1265 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1266 {
1267 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1268 }
1269
1270 /**
1271 * @brief Get Wake-up Flag 7
1272 * @rmtoll SR1 WUF7 LL_PWR_IsActiveFlag_WU7
1273 * @retval State of bit (1 or 0).
1274 */
LL_PWR_IsActiveFlag_WU7(void)1275 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
1276 {
1277 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF7) == (PWR_SR1_WUF7)) ? 1UL : 0UL);
1278 }
1279
1280 /**
1281 * @brief Get Stand-By Flag
1282 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1283 * @retval State of bit (1 or 0).
1284 */
LL_PWR_IsActiveFlag_SB(void)1285 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1286 {
1287 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
1288 }
1289
1290 /**
1291 * @brief Get Stop Flag
1292 * @rmtoll SR1 STOPF 0 LL_PWR_IsActiveFlag_Stop
1293 * @retval State of bit (1 or 0).
1294 */
LL_PWR_IsActiveFlag_Stop0(void)1295 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_Stop0(void)
1296 {
1297 return ((READ_BIT(PWR->SR1, LL_PWR_SR1_STOP0) == (LL_PWR_SR1_STOP0)) ? 1UL : 0UL);
1298 }
1299
1300 /**
1301 * @brief Get Stop Flag
1302 * @rmtoll SR1 STOPF 1 LL_PWR_IsActiveFlag_Stop
1303 * @retval State of bit (1 or 0).
1304 */
LL_PWR_IsActiveFlag_Stop1(void)1305 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_Stop1(void)
1306 {
1307 return ((READ_BIT(PWR->SR1, LL_PWR_SR1_STOP1) == (LL_PWR_SR1_STOP1)) ? 1UL : 0UL);
1308 }
1309 /**
1310 * @brief Get Stop Flag
1311 * @rmtoll SR1 STOPF 2 LL_PWR_IsActiveFlag_Stop
1312 * @retval State of bit (1 or 0).
1313 */
LL_PWR_IsActiveFlag_Stop2(void)1314 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_Stop2(void)
1315 {
1316 return ((READ_BIT(PWR->SR1, LL_PWR_SR1_STOP2) == (LL_PWR_SR1_STOP2)) ? 1UL : 0UL);
1317 }
1318
1319 /**
1320 * @brief Get Internal Wake-up line Flag
1321 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1322 * @retval State of bit (1 or 0).
1323 */
LL_PWR_IsActiveFlag_InternWU(void)1324 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1325 {
1326 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
1327 }
1328
1329 /**
1330 * @brief Indicate whether or not the flash is ready
1331 * @rmtoll SR2 FLASH_RDY LL_PWR_IsActiveFlag_FLASH_RDY
1332 * @retval State of bit (1 or 0).
1333 */
LL_PWR_IsActiveFlag_FLASH_RDY(void)1334 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void)
1335 {
1336 return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL);
1337 }
1338
1339 /**
1340 * @brief Indicate whether or not the low-power regulator is ready
1341 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1342 * @retval State of bit (1 or 0).
1343 */
LL_PWR_IsActiveFlag_REGLPS(void)1344 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1345 {
1346 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
1347 }
1348
1349 /**
1350 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1351 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range
1352 * is still changing.
1353 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1354 * @retval State of bit (1 or 0).
1355 */
LL_PWR_IsActiveFlag_REGLPF(void)1356 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1357 {
1358 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
1359 }
1360
1361 /**
1362 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is
1363 * still changing to the required voltage level
1364 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1365 * @retval State of bit (1 or 0).
1366 */
LL_PWR_IsActiveFlag_VOS(void)1367 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1368 {
1369 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
1370 }
1371
1372 /**
1373 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1374 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1375 * @retval State of bit (1 or 0).
1376 */
LL_PWR_IsActiveFlag_PVDO(void)1377 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1378 {
1379 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
1380 }
1381
1382 #if defined(USB_DRD_FS)
1383 /**
1384 * @brief Indicate whether VDDUSB voltage is below or above PVMO1 threshold
1385 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO_1
1386 * @retval State of bit (1 or 0).
1387 */
LL_PWR_IsActiveFlag_PVMO_1(void)1388 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO_1(void)
1389 {
1390 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
1391 }
1392 #endif /* USB_DRD_FS */
1393
1394 /**
1395 * @brief Indicate whether VDDA ADC voltage is below or above PVMO3 threshold
1396 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO_3
1397 * @retval State of bit (1 or 0).
1398 */
LL_PWR_IsActiveFlag_PVMO_3(void)1399 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO_3(void)
1400 {
1401 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
1402 }
1403
1404 /**
1405 * @brief Indicate whether VDDA voltage is below or above PVMO4 threshold
1406 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO_4
1407 * @retval State of bit (1 or 0).
1408 */
LL_PWR_IsActiveFlag_PVMO_4(void)1409 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO_4(void)
1410 {
1411 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL);
1412 }
1413
1414 /**
1415 * @brief Clear Wake-up Flag 1
1416 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1417 * @retval None
1418 */
LL_PWR_ClearFlag_WU1(void)1419 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1420 {
1421 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1422 }
1423
1424 /**
1425 * @brief Clear Wake-up Flag 2
1426 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1427 * @retval None
1428 */
LL_PWR_ClearFlag_WU2(void)1429 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1430 {
1431 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1432 }
1433
1434 /**
1435 * @brief Clear Wake-up Flag 3
1436 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1437 * @retval None
1438 */
LL_PWR_ClearFlag_WU3(void)1439 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1440 {
1441 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1442 }
1443
1444 /**
1445 * @brief Clear Wake-up Flag 4
1446 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1447 * @retval None
1448 */
LL_PWR_ClearFlag_WU4(void)1449 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1450 {
1451 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1452 }
1453
1454 /**
1455 * @brief Clear Wake-up Flag 5
1456 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1457 * @retval None
1458 */
LL_PWR_ClearFlag_WU5(void)1459 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1460 {
1461 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1462 }
1463
1464 /**
1465 * @brief Clear Wake-up Flag 7
1466 * @rmtoll SCR CWUF7 LL_PWR_ClearFlag_WU7
1467 * @retval None
1468 */
LL_PWR_ClearFlag_WU7(void)1469 __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
1470 {
1471 WRITE_REG(PWR->SCR, PWR_SCR_CWUF7);
1472 }
1473
1474 /**
1475 * @brief Clear standby and stop Flags
1476 * @rmtoll SCR CSBF LL_PWR_ClearFlag_CSB
1477 * @retval None
1478 */
LL_PWR_ClearFlag_CSB(void)1479 __STATIC_INLINE void LL_PWR_ClearFlag_CSB(void)
1480 {
1481 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1482 }
1483 /**
1484 * @}
1485 */
1486
1487 /**
1488 * @}
1489 */
1490 #if defined(USE_FULL_LL_DRIVER)
1491 /** @defgroup PWR_LL_EF_Init De-initialization function
1492 * @{
1493 */
1494 ErrorStatus LL_PWR_DeInit(void);
1495 /**
1496 * @}
1497 */
1498 #endif /* USE_FULL_LL_DRIVER */
1499
1500 /**
1501 * @}
1502 */
1503
1504 /**
1505 * @}
1506 */
1507
1508 #endif /* defined(PWR) */
1509
1510 /**
1511 * @}
1512 */
1513
1514 #ifdef __cplusplus
1515 }
1516 #endif
1517
1518 #endif /* STM32U0xx_LL_PWR_H */
1519
