1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_PWR_H
21 #define STM32G4xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46
47 /* Exported types ------------------------------------------------------------*/
48 /* Exported constants --------------------------------------------------------*/
49 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
50 * @{
51 */
52
53 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
54 * @brief Flags defines which can be used with LL_PWR_WriteReg function
55 * @{
56 */
57 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
58 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
59 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
60 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
61 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
62 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
63 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
64 /**
65 * @}
66 */
67
68 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
69 * @brief Flags defines which can be used with LL_PWR_ReadReg function
70 * @{
71 */
72 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
73 #define LL_PWR_SR1_SBF PWR_SR1_SBF
74 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
75 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
76 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
77 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
78 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
79 #if defined(PWR_SR2_PVMO4)
80 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
81 #endif /* PWR_SR2_PVMO4 */
82 #if defined(PWR_SR2_PVMO3)
83 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
84 #endif /* PWR_SR2_PVMO3 */
85 #if defined(PWR_SR2_PVMO2)
86 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
87 #endif /* PWR_SR2_PVMO2 */
88 #if defined(PWR_SR2_PVMO1)
89 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
90 #endif /* PWR_SR2_PVMO1 */
91 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
92 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
93 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
94 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
95 /**
96 * @}
97 */
98
99 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
100 * @{
101 */
102 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
103 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
104 /**
105 * @}
106 */
107
108 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
109 * @{
110 */
111 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
112 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
113 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
114 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
115 /**
116 * @}
117 */
118
119 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
120 * @{
121 */
122 #if defined(PWR_CR2_PVME1)
123 #define LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
124 #endif
125 #if defined(PWR_CR2_PVME2)
126 #define LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
127 #endif
128 #if defined(PWR_CR2_PVME3)
129 #define LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
130 #endif
131 #if defined(PWR_CR2_PVME4)
132 #define LL_PWR_PVM_VDDA_OPAMP_DAC (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */
133 #endif
134 /**
135 * @}
136 */
137
138 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
139 * @{
140 */
141 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
142 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
143 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
144 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
145 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
146 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
147 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
148 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
149 /**
150 * @}
151 */
152
153 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
154 * @{
155 */
156 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
157 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
158 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
159 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
160 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
161 /**
162 * @}
163 */
164
165 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
166 * @{
167 */
168 #define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
169 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
170 /**
171 * @}
172 */
173
174 /** @defgroup PWR_LL_EC_GPIO GPIO
175 * @{
176 */
177 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
178 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
179 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
180 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
181 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
182 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
183 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
184 /**
185 * @}
186 */
187
188 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
189 * @{
190 */
191 #define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
192 #define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
193 #define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
194 #define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
195 #define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
196 #define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
197 #define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
198 #define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
199 #define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
200 #define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
201 #define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
202 #define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
203 #define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
204 #define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
205 #define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
206 #define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
207 /**
208 * @}
209 */
210
211 /**
212 * @}
213 */
214
215 /* Exported macro ------------------------------------------------------------*/
216 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
217 * @{
218 */
219
220 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
221 * @{
222 */
223
224 /**
225 * @brief Write a value in PWR register
226 * @param __REG__ Register to be written
227 * @param __VALUE__ Value to be written in the register
228 * @retval None
229 */
230 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
231
232 /**
233 * @brief Read a value in PWR register
234 * @param __REG__ Register to be read
235 * @retval Register value
236 */
237 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
238 /**
239 * @}
240 */
241
242 /**
243 * @}
244 */
245
246
247 /* Exported functions --------------------------------------------------------*/
248 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
249 * @{
250 */
251
252 /** @defgroup PWR_LL_EF_Configuration Configuration
253 * @{
254 */
255
256 /**
257 * @brief Switch the regulator from main mode to low-power mode
258 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
259 * @retval None
260 */
LL_PWR_EnableLowPowerRunMode(void)261 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
262 {
263 SET_BIT(PWR->CR1, PWR_CR1_LPR);
264 }
265
266 /**
267 * @brief Switch the regulator from low-power mode to main mode
268 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
269 * @retval None
270 */
LL_PWR_DisableLowPowerRunMode(void)271 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
272 {
273 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
274 }
275
276 /**
277 * @brief Check if the regulator is in low-power mode
278 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
279 * @retval State of bit (1 or 0).
280 */
LL_PWR_IsEnabledLowPowerRunMode(void)281 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
282 {
283 uint32_t temp;
284 temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
285
286 return ((temp == (PWR_CR1_LPR))?1U:0U);
287
288 }
289
290 /**
291 * @brief Switch from run main mode to run low-power mode.
292 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
293 * @retval None
294 */
LL_PWR_EnterLowPowerRunMode(void)295 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
296 {
297 LL_PWR_EnableLowPowerRunMode();
298 }
299
300 /**
301 * @brief Switch from run main mode to low-power mode.
302 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
303 * @retval None
304 */
LL_PWR_ExitLowPowerRunMode(void)305 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
306 {
307 LL_PWR_DisableLowPowerRunMode();
308 }
309
310 /**
311 * @brief Set the main internal regulator output voltage
312 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
313 * @param VoltageScaling This parameter can be one of the following values:
314 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
315 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
316 * @retval None
317 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)318 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
319 {
320 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
321 }
322
323 /**
324 * @brief Get the main internal regulator output voltage
325 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
326 * @retval Returned value can be one of the following values:
327 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
328 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
329 */
LL_PWR_GetRegulVoltageScaling(void)330 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
331 {
332 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
333 }
334
335 #if defined(PWR_CR5_R1MODE)
336 /**
337 * @brief Enable main regulator voltage range 1 boost mode
338 * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
339 * @retval None
340 */
LL_PWR_EnableRange1BoostMode(void)341 __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
342 {
343 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
344 }
345
346 /**
347 * @brief Disable main regulator voltage range 1 boost mode
348 * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
349 * @retval None
350 */
LL_PWR_DisableRange1BoostMode(void)351 __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
352 {
353 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
354 }
355
356 /**
357 * @brief Check if the main regulator voltage range 1 boost mode is enabled
358 * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
359 * @retval Inverted state of bit (0 or 1).
360 */
LL_PWR_IsEnabledRange1BoostMode(void)361 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
362 {
363 uint32_t temp;
364 temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
365
366 return ((temp == (0U))?1U:0U);
367 }
368 #endif /* PWR_CR5_R1MODE */
369
370 /**
371 * @brief Enable access to the backup domain
372 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
373 * @retval None
374 */
LL_PWR_EnableBkUpAccess(void)375 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
376 {
377 SET_BIT(PWR->CR1, PWR_CR1_DBP);
378 }
379
380 /**
381 * @brief Disable access to the backup domain
382 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
383 * @retval None
384 */
LL_PWR_DisableBkUpAccess(void)385 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
386 {
387 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
388 }
389
390 /**
391 * @brief Check if the backup domain is enabled
392 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
393 * @retval State of bit (1 or 0).
394 */
LL_PWR_IsEnabledBkUpAccess(void)395 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
396 {
397 uint32_t temp;
398 temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
399
400 return ((temp == (PWR_CR1_DBP))?1U:0U);
401
402 }
403
404 /**
405 * @brief Set Low-Power mode
406 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
407 * @param LowPowerMode This parameter can be one of the following values:
408 * @arg @ref LL_PWR_MODE_STOP0
409 * @arg @ref LL_PWR_MODE_STOP1
410 * @arg @ref LL_PWR_MODE_STANDBY
411 * @arg @ref LL_PWR_MODE_SHUTDOWN
412 * @retval None
413 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)414 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
415 {
416 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
417 }
418
419 /**
420 * @brief Get Low-Power mode
421 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
422 * @retval Returned value can be one of the following values:
423 * @arg @ref LL_PWR_MODE_STOP0
424 * @arg @ref LL_PWR_MODE_STOP1
425 * @arg @ref LL_PWR_MODE_STANDBY
426 * @arg @ref LL_PWR_MODE_SHUTDOWN
427 */
LL_PWR_GetPowerMode(void)428 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
429 {
430 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
431 }
432
433 #if defined(PWR_CR3_UCPD_STDBY)
434 /**
435 * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
436 * @note This function must be called just before entering Standby mode.
437 * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
438 * @retval None
439 */
LL_PWR_EnableUCPDStandbyMode(void)440 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
441 {
442 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
443 }
444
445 /**
446 * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
447 * @note This function must be called after exiting Standby mode and before any
448 * UCPD configuration update.
449 * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
450 * @retval None
451 */
LL_PWR_DisableUCPDStandbyMode(void)452 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
453 {
454 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
455 }
456
457 /**
458 * @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
459 * @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
460 * @retval State of bit (1 or 0).
461 */
LL_PWR_IsEnabledUCPDStandbyMode(void)462 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
463 {
464
465 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL);
466
467 }
468 #endif /* PWR_CR3_UCPD_STDBY */
469
470 #if defined(PWR_CR3_UCPD_DBDIS)
471 /**
472 * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
473 * on UCPD CC1 and CC2 pins.
474 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
475 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
476 * to disable it in all cases, either to stop this pull-down or to hand over
477 * control to the UCPD (which should therefore be initialized before doing the disable).
478 * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
479 * @retval None
480 */
LL_PWR_EnableUCPDDeadBattery(void)481 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
482 {
483 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
484 }
485
486 /**
487 * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
488 * on UCPD CC1 and CC2 pins.
489 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
490 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
491 * to disable it in all cases, either to stop this pull-down or to hand over
492 * control to the UCPD (which should therefore be initialized before doing the disable).
493 * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
494 * @retval None
495 */
LL_PWR_DisableUCPDDeadBattery(void)496 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
497 {
498 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
499 }
500
501 /**
502 * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
503 * on UCPD CC1 and CC2 pins.
504 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
505 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
506 * to disable it in all cases, either to stop this pull-down or to hand over
507 * control to the UCPD (which should therefore be initialized before doing the disable).
508 * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
509 * @retval State of feature (1 : enabled; 0 : disabled).
510 */
LL_PWR_IsEnabledUCPDDeadBattery(void)511 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
512 {
513 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
514 }
515 #endif /* PWR_CR3_UCPD_DBDIS */
516
517 #if defined(PWR_CR2_USV)
518 /**
519 * @brief Enable VDDUSB supply
520 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
521 * @retval None
522 */
LL_PWR_EnableVddUSB(void)523 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
524 {
525 SET_BIT(PWR->CR2, PWR_CR2_USV);
526 }
527
528 /**
529 * @brief Disable VDDUSB supply
530 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
531 * @retval None
532 */
LL_PWR_DisableVddUSB(void)533 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
534 {
535 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
536 }
537
538 /**
539 * @brief Check if VDDUSB supply is enabled
540 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
541 * @retval State of bit (1 or 0).
542 */
LL_PWR_IsEnabledVddUSB(void)543 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
544 {
545 uint32_t temp;
546 temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
547
548 return ((temp == (PWR_CR2_USV))?1U:0U);
549
550 }
551 #endif
552
553 #if defined(PWR_CR2_IOSV)
554 /**
555 * @brief Enable VDDIO2 supply
556 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
557 * @retval None
558 */
LL_PWR_EnableVddIO2(void)559 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
560 {
561 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
562 }
563
564 /**
565 * @brief Disable VDDIO2 supply
566 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
567 * @retval None
568 */
LL_PWR_DisableVddIO2(void)569 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
570 {
571 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
572 }
573
574 /**
575 * @brief Check if VDDIO2 supply is enabled
576 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
577 * @retval State of bit (1 or 0).
578 */
LL_PWR_IsEnabledVddIO2(void)579 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
580 {
581 uint32_t temp;
582 temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
583
584 return ((temp == (PWR_CR2_IOSV))?1U:0U);
585
586 }
587 #endif
588
589 /**
590 * @brief Enable the Power Voltage Monitoring on a peripheral
591 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
592 * CR2 PVME2 LL_PWR_EnablePVM\n
593 * CR2 PVME3 LL_PWR_EnablePVM\n
594 * CR2 PVME4 LL_PWR_EnablePVM
595 * @param PeriphVoltage This parameter can be one of the following values:
596 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
597 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
598 * @arg @ref LL_PWR_PVM_VDDA_ADC
599 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
600 *
601 * (*) value not defined in all devices
602 * @retval None
603 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)604 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
605 {
606 SET_BIT(PWR->CR2, PeriphVoltage);
607 }
608
609 /**
610 * @brief Disable the Power Voltage Monitoring on a peripheral
611 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
612 * CR2 PVME2 LL_PWR_DisablePVM\n
613 * CR2 PVME3 LL_PWR_DisablePVM\n
614 * CR2 PVME4 LL_PWR_DisablePVM
615 * @param PeriphVoltage This parameter can be one of the following values:
616 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
617 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
618 * @arg @ref LL_PWR_PVM_VDDA_ADC
619 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
620 *
621 * (*) value not defined in all devices
622 * @retval None
623 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)624 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
625 {
626 CLEAR_BIT(PWR->CR2, PeriphVoltage);
627 }
628
629 /**
630 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
631 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
632 * CR2 PVME2 LL_PWR_IsEnabledPVM\n
633 * CR2 PVME3 LL_PWR_IsEnabledPVM\n
634 * CR2 PVME4 LL_PWR_IsEnabledPVM
635 * @param PeriphVoltage This parameter can be one of the following values:
636 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
637 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
638 * @arg @ref LL_PWR_PVM_VDDA_ADC
639 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
640 *
641 * (*) value not defined in all devices
642 * @retval State of bit (1 or 0).
643 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)644 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
645 {
646 uint32_t temp;
647 temp = READ_BIT(PWR->CR2, PeriphVoltage);
648
649 return ((temp == (PeriphVoltage))?1U:0U);
650
651 }
652
653 /**
654 * @brief Configure the voltage threshold detected by the Power Voltage Detector
655 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
656 * @param PVDLevel This parameter can be one of the following values:
657 * @arg @ref LL_PWR_PVDLEVEL_0
658 * @arg @ref LL_PWR_PVDLEVEL_1
659 * @arg @ref LL_PWR_PVDLEVEL_2
660 * @arg @ref LL_PWR_PVDLEVEL_3
661 * @arg @ref LL_PWR_PVDLEVEL_4
662 * @arg @ref LL_PWR_PVDLEVEL_5
663 * @arg @ref LL_PWR_PVDLEVEL_6
664 * @arg @ref LL_PWR_PVDLEVEL_7
665 * @retval None
666 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)667 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
668 {
669 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
670 }
671
672 /**
673 * @brief Get the voltage threshold detection
674 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
675 * @retval Returned value can be one of the following values:
676 * @arg @ref LL_PWR_PVDLEVEL_0
677 * @arg @ref LL_PWR_PVDLEVEL_1
678 * @arg @ref LL_PWR_PVDLEVEL_2
679 * @arg @ref LL_PWR_PVDLEVEL_3
680 * @arg @ref LL_PWR_PVDLEVEL_4
681 * @arg @ref LL_PWR_PVDLEVEL_5
682 * @arg @ref LL_PWR_PVDLEVEL_6
683 * @arg @ref LL_PWR_PVDLEVEL_7
684 */
LL_PWR_GetPVDLevel(void)685 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
686 {
687 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
688 }
689
690 /**
691 * @brief Enable Power Voltage Detector
692 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
693 * @retval None
694 */
LL_PWR_EnablePVD(void)695 __STATIC_INLINE void LL_PWR_EnablePVD(void)
696 {
697 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
698 }
699
700 /**
701 * @brief Disable Power Voltage Detector
702 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
703 * @retval None
704 */
LL_PWR_DisablePVD(void)705 __STATIC_INLINE void LL_PWR_DisablePVD(void)
706 {
707 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
708 }
709
710 /**
711 * @brief Check if Power Voltage Detector is enabled
712 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
713 * @retval State of bit (1 or 0).
714 */
LL_PWR_IsEnabledPVD(void)715 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
716 {
717 uint32_t temp;
718 temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
719
720 return ((temp == (PWR_CR2_PVDE))?1U:0U);
721 }
722
723 /**
724 * @brief Enable Internal Wake-up line
725 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
726 * @retval None
727 */
LL_PWR_EnableInternWU(void)728 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
729 {
730 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
731 }
732
733 /**
734 * @brief Disable Internal Wake-up line
735 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
736 * @retval None
737 */
LL_PWR_DisableInternWU(void)738 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
739 {
740 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
741 }
742
743 /**
744 * @brief Check if Internal Wake-up line is enabled
745 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
746 * @retval State of bit (1 or 0).
747 */
LL_PWR_IsEnabledInternWU(void)748 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
749 {
750 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
751 }
752
753 /**
754 * @brief Enable pull-up and pull-down configuration
755 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
756 * @retval None
757 */
LL_PWR_EnablePUPDCfg(void)758 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
759 {
760 SET_BIT(PWR->CR3, PWR_CR3_APC);
761 }
762
763 /**
764 * @brief Disable pull-up and pull-down configuration
765 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
766 * @retval None
767 */
LL_PWR_DisablePUPDCfg(void)768 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
769 {
770 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
771 }
772
773 /**
774 * @brief Check if pull-up and pull-down configuration is enabled
775 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
776 * @retval State of bit (1 or 0).
777 */
LL_PWR_IsEnabledPUPDCfg(void)778 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
779 {
780 uint32_t temp;
781 temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
782
783 return ((temp == (PWR_CR3_APC))?1U:0U);
784 }
785
786 #if defined(SRAM2_BASE)
787 /**
788 * @brief Enable SRAM2 content retention in Standby mode
789 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
790 * @retval None
791 */
LL_PWR_EnableSRAM2Retention(void)792 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
793 {
794 SET_BIT(PWR->CR3, PWR_CR3_RRS);
795 }
796
797 /**
798 * @brief Disable SRAM2 content retention in Standby mode
799 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
800 * @retval None
801 */
LL_PWR_DisableSRAM2Retention(void)802 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
803 {
804 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
805 }
806
807 /**
808 * @brief Check if SRAM2 content retention in Standby mode is enabled
809 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
810 * @retval State of bit (1 or 0).
811 */
LL_PWR_IsEnabledSRAM2Retention(void)812 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
813 {
814 uint32_t temp;
815 temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
816
817 return ((temp == (PWR_CR3_RRS))?1U:0U);
818 }
819
820 #endif /* SRAM2_BASE */
821 /**
822 * @brief Enable the WakeUp PINx functionality
823 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
824 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
825 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
826 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
827 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
828 * @param WakeUpPin This parameter can be one of the following values:
829 * @arg @ref LL_PWR_WAKEUP_PIN1
830 * @arg @ref LL_PWR_WAKEUP_PIN2
831 * @arg @ref LL_PWR_WAKEUP_PIN3
832 * @arg @ref LL_PWR_WAKEUP_PIN4
833 * @arg @ref LL_PWR_WAKEUP_PIN5
834 * @retval None
835 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)836 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
837 {
838 SET_BIT(PWR->CR3, WakeUpPin);
839 }
840
841 /**
842 * @brief Disable the WakeUp PINx functionality
843 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
844 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
845 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
846 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
847 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
848 * @param WakeUpPin This parameter can be one of the following values:
849 * @arg @ref LL_PWR_WAKEUP_PIN1
850 * @arg @ref LL_PWR_WAKEUP_PIN2
851 * @arg @ref LL_PWR_WAKEUP_PIN3
852 * @arg @ref LL_PWR_WAKEUP_PIN4
853 * @arg @ref LL_PWR_WAKEUP_PIN5
854 * @retval None
855 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)856 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
857 {
858 CLEAR_BIT(PWR->CR3, WakeUpPin);
859 }
860
861 /**
862 * @brief Check if the WakeUp PINx functionality is enabled
863 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
864 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
865 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
866 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
867 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
868 * @param WakeUpPin This parameter can be one of the following values:
869 * @arg @ref LL_PWR_WAKEUP_PIN1
870 * @arg @ref LL_PWR_WAKEUP_PIN2
871 * @arg @ref LL_PWR_WAKEUP_PIN3
872 * @arg @ref LL_PWR_WAKEUP_PIN4
873 * @arg @ref LL_PWR_WAKEUP_PIN5
874 * @retval State of bit (1 or 0).
875 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)876 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
877 {
878 uint32_t temp;
879 temp = READ_BIT(PWR->CR3, WakeUpPin);
880
881 return ((temp == (WakeUpPin))?1U:0U);
882 }
883
884 /**
885 * @brief Set the resistor impedance
886 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
887 * @param Resistor This parameter can be one of the following values:
888 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
889 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
890 * @retval None
891 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)892 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
893 {
894 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
895 }
896
897 /**
898 * @brief Get the resistor impedance
899 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
900 * @retval Returned value can be one of the following values:
901 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
902 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
903 */
LL_PWR_GetBattChargResistor(void)904 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
905 {
906 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
907 }
908
909 /**
910 * @brief Enable battery charging
911 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
912 * @retval None
913 */
LL_PWR_EnableBatteryCharging(void)914 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
915 {
916 SET_BIT(PWR->CR4, PWR_CR4_VBE);
917 }
918
919 /**
920 * @brief Disable battery charging
921 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
922 * @retval None
923 */
LL_PWR_DisableBatteryCharging(void)924 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
925 {
926 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
927 }
928
929 /**
930 * @brief Check if battery charging is enabled
931 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
932 * @retval State of bit (1 or 0).
933 */
LL_PWR_IsEnabledBatteryCharging(void)934 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
935 {
936 uint32_t temp;
937 temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
938
939 return ((temp == (PWR_CR4_VBE))?1U:0U);
940 }
941
942 /**
943 * @brief Set the Wake-Up pin polarity low for the event detection
944 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
945 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
946 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
947 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
948 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
949 * @param WakeUpPin This parameter can be one of the following values:
950 * @arg @ref LL_PWR_WAKEUP_PIN1
951 * @arg @ref LL_PWR_WAKEUP_PIN2
952 * @arg @ref LL_PWR_WAKEUP_PIN3
953 * @arg @ref LL_PWR_WAKEUP_PIN4
954 * @arg @ref LL_PWR_WAKEUP_PIN5
955 * @retval None
956 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)957 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
958 {
959 SET_BIT(PWR->CR4, WakeUpPin);
960 }
961
962 /**
963 * @brief Set the Wake-Up pin polarity high for the event detection
964 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
965 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
966 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
967 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
968 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
969 * @param WakeUpPin This parameter can be one of the following values:
970 * @arg @ref LL_PWR_WAKEUP_PIN1
971 * @arg @ref LL_PWR_WAKEUP_PIN2
972 * @arg @ref LL_PWR_WAKEUP_PIN3
973 * @arg @ref LL_PWR_WAKEUP_PIN4
974 * @arg @ref LL_PWR_WAKEUP_PIN5
975 * @retval None
976 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)977 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
978 {
979 CLEAR_BIT(PWR->CR4, WakeUpPin);
980 }
981
982 /**
983 * @brief Get the Wake-Up pin polarity for the event detection
984 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
985 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
986 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
987 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
988 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
989 * @param WakeUpPin This parameter can be one of the following values:
990 * @arg @ref LL_PWR_WAKEUP_PIN1
991 * @arg @ref LL_PWR_WAKEUP_PIN2
992 * @arg @ref LL_PWR_WAKEUP_PIN3
993 * @arg @ref LL_PWR_WAKEUP_PIN4
994 * @arg @ref LL_PWR_WAKEUP_PIN5
995 * @retval State of bit (1 or 0).
996 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)997 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
998 {
999 uint32_t temp;
1000 temp = READ_BIT(PWR->CR4, WakeUpPin);
1001
1002 return ((temp == (WakeUpPin))?1U:0U);
1003 }
1004
1005 /**
1006 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1007 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1008 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1009 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1010 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1011 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1012 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
1013 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
1014 * @param GPIO This parameter can be one of the following values:
1015 * @arg @ref LL_PWR_GPIO_A
1016 * @arg @ref LL_PWR_GPIO_B
1017 * @arg @ref LL_PWR_GPIO_C
1018 * @arg @ref LL_PWR_GPIO_D
1019 * @arg @ref LL_PWR_GPIO_E
1020 * @arg @ref LL_PWR_GPIO_F
1021 * @arg @ref LL_PWR_GPIO_G
1022 *
1023 * (*) value not defined in all devices
1024 * @param GPIONumber This parameter can be one of the following values:
1025 * @arg @ref LL_PWR_GPIO_BIT_0
1026 * @arg @ref LL_PWR_GPIO_BIT_1
1027 * @arg @ref LL_PWR_GPIO_BIT_2
1028 * @arg @ref LL_PWR_GPIO_BIT_3
1029 * @arg @ref LL_PWR_GPIO_BIT_4
1030 * @arg @ref LL_PWR_GPIO_BIT_5
1031 * @arg @ref LL_PWR_GPIO_BIT_6
1032 * @arg @ref LL_PWR_GPIO_BIT_7
1033 * @arg @ref LL_PWR_GPIO_BIT_8
1034 * @arg @ref LL_PWR_GPIO_BIT_9
1035 * @arg @ref LL_PWR_GPIO_BIT_10
1036 * @arg @ref LL_PWR_GPIO_BIT_11
1037 * @arg @ref LL_PWR_GPIO_BIT_12
1038 * @arg @ref LL_PWR_GPIO_BIT_13
1039 * @arg @ref LL_PWR_GPIO_BIT_14
1040 * @arg @ref LL_PWR_GPIO_BIT_15
1041 * @retval None
1042 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1043 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1044 {
1045 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1046 }
1047
1048 /**
1049 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1050 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1051 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1052 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1053 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1054 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1055 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
1056 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
1057 * @param GPIO This parameter can be one of the following values:
1058 * @arg @ref LL_PWR_GPIO_A
1059 * @arg @ref LL_PWR_GPIO_B
1060 * @arg @ref LL_PWR_GPIO_C
1061 * @arg @ref LL_PWR_GPIO_D
1062 * @arg @ref LL_PWR_GPIO_E
1063 * @arg @ref LL_PWR_GPIO_F
1064 * @arg @ref LL_PWR_GPIO_G
1065 *
1066 * (*) value not defined in all devices
1067 * @param GPIONumber This parameter can be one of the following values:
1068 * @arg @ref LL_PWR_GPIO_BIT_0
1069 * @arg @ref LL_PWR_GPIO_BIT_1
1070 * @arg @ref LL_PWR_GPIO_BIT_2
1071 * @arg @ref LL_PWR_GPIO_BIT_3
1072 * @arg @ref LL_PWR_GPIO_BIT_4
1073 * @arg @ref LL_PWR_GPIO_BIT_5
1074 * @arg @ref LL_PWR_GPIO_BIT_6
1075 * @arg @ref LL_PWR_GPIO_BIT_7
1076 * @arg @ref LL_PWR_GPIO_BIT_8
1077 * @arg @ref LL_PWR_GPIO_BIT_9
1078 * @arg @ref LL_PWR_GPIO_BIT_10
1079 * @arg @ref LL_PWR_GPIO_BIT_11
1080 * @arg @ref LL_PWR_GPIO_BIT_12
1081 * @arg @ref LL_PWR_GPIO_BIT_13
1082 * @arg @ref LL_PWR_GPIO_BIT_14
1083 * @arg @ref LL_PWR_GPIO_BIT_15
1084 * @retval None
1085 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1086 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1087 {
1088 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1089 }
1090
1091 /**
1092 * @brief Check if GPIO pull-up state is enabled
1093 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1094 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1095 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1096 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1097 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1098 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1099 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1100 * @param GPIO This parameter can be one of the following values:
1101 * @arg @ref LL_PWR_GPIO_A
1102 * @arg @ref LL_PWR_GPIO_B
1103 * @arg @ref LL_PWR_GPIO_C
1104 * @arg @ref LL_PWR_GPIO_D
1105 * @arg @ref LL_PWR_GPIO_E
1106 * @arg @ref LL_PWR_GPIO_F
1107 * @arg @ref LL_PWR_GPIO_G
1108 *
1109 * (*) value not defined in all devices
1110 * @param GPIONumber This parameter can be one of the following values:
1111 * @arg @ref LL_PWR_GPIO_BIT_0
1112 * @arg @ref LL_PWR_GPIO_BIT_1
1113 * @arg @ref LL_PWR_GPIO_BIT_2
1114 * @arg @ref LL_PWR_GPIO_BIT_3
1115 * @arg @ref LL_PWR_GPIO_BIT_4
1116 * @arg @ref LL_PWR_GPIO_BIT_5
1117 * @arg @ref LL_PWR_GPIO_BIT_6
1118 * @arg @ref LL_PWR_GPIO_BIT_7
1119 * @arg @ref LL_PWR_GPIO_BIT_8
1120 * @arg @ref LL_PWR_GPIO_BIT_9
1121 * @arg @ref LL_PWR_GPIO_BIT_10
1122 * @arg @ref LL_PWR_GPIO_BIT_11
1123 * @arg @ref LL_PWR_GPIO_BIT_12
1124 * @arg @ref LL_PWR_GPIO_BIT_13
1125 * @arg @ref LL_PWR_GPIO_BIT_14
1126 * @arg @ref LL_PWR_GPIO_BIT_15
1127 * @retval State of bit (1 or 0).
1128 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1129 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1130 {
1131 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1132 }
1133
1134 /**
1135 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1136 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1137 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1138 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1139 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1140 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1141 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
1142 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
1143 * @param GPIO This parameter can be one of the following values:
1144 * @arg @ref LL_PWR_GPIO_A
1145 * @arg @ref LL_PWR_GPIO_B
1146 * @arg @ref LL_PWR_GPIO_C
1147 * @arg @ref LL_PWR_GPIO_D
1148 * @arg @ref LL_PWR_GPIO_E
1149 * @arg @ref LL_PWR_GPIO_F
1150 * @arg @ref LL_PWR_GPIO_G
1151 *
1152 * (*) value not defined in all devices
1153 * @param GPIONumber This parameter can be one of the following values:
1154 * @arg @ref LL_PWR_GPIO_BIT_0
1155 * @arg @ref LL_PWR_GPIO_BIT_1
1156 * @arg @ref LL_PWR_GPIO_BIT_2
1157 * @arg @ref LL_PWR_GPIO_BIT_3
1158 * @arg @ref LL_PWR_GPIO_BIT_4
1159 * @arg @ref LL_PWR_GPIO_BIT_5
1160 * @arg @ref LL_PWR_GPIO_BIT_6
1161 * @arg @ref LL_PWR_GPIO_BIT_7
1162 * @arg @ref LL_PWR_GPIO_BIT_8
1163 * @arg @ref LL_PWR_GPIO_BIT_9
1164 * @arg @ref LL_PWR_GPIO_BIT_10
1165 * @arg @ref LL_PWR_GPIO_BIT_11
1166 * @arg @ref LL_PWR_GPIO_BIT_12
1167 * @arg @ref LL_PWR_GPIO_BIT_13
1168 * @arg @ref LL_PWR_GPIO_BIT_14
1169 * @arg @ref LL_PWR_GPIO_BIT_15
1170 * @retval None
1171 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1172 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1173 {
1174 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1175 }
1176
1177 /**
1178 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1179 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1180 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1181 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1182 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1183 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1184 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
1185 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
1186 * @param GPIO This parameter can be one of the following values:
1187 * @arg @ref LL_PWR_GPIO_A
1188 * @arg @ref LL_PWR_GPIO_B
1189 * @arg @ref LL_PWR_GPIO_C
1190 * @arg @ref LL_PWR_GPIO_D
1191 * @arg @ref LL_PWR_GPIO_E
1192 * @arg @ref LL_PWR_GPIO_F
1193 * @arg @ref LL_PWR_GPIO_G
1194 *
1195 * (*) value not defined in all devices
1196 * @param GPIONumber This parameter can be one of the following values:
1197 * @arg @ref LL_PWR_GPIO_BIT_0
1198 * @arg @ref LL_PWR_GPIO_BIT_1
1199 * @arg @ref LL_PWR_GPIO_BIT_2
1200 * @arg @ref LL_PWR_GPIO_BIT_3
1201 * @arg @ref LL_PWR_GPIO_BIT_4
1202 * @arg @ref LL_PWR_GPIO_BIT_5
1203 * @arg @ref LL_PWR_GPIO_BIT_6
1204 * @arg @ref LL_PWR_GPIO_BIT_7
1205 * @arg @ref LL_PWR_GPIO_BIT_8
1206 * @arg @ref LL_PWR_GPIO_BIT_9
1207 * @arg @ref LL_PWR_GPIO_BIT_10
1208 * @arg @ref LL_PWR_GPIO_BIT_11
1209 * @arg @ref LL_PWR_GPIO_BIT_12
1210 * @arg @ref LL_PWR_GPIO_BIT_13
1211 * @arg @ref LL_PWR_GPIO_BIT_14
1212 * @arg @ref LL_PWR_GPIO_BIT_15
1213 * @retval None
1214 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1215 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1216 {
1217 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1218 }
1219
1220 /**
1221 * @brief Check if GPIO pull-down state is enabled
1222 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1223 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1224 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1225 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1226 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1227 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1228 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1229 * @param GPIO This parameter can be one of the following values:
1230 * @arg @ref LL_PWR_GPIO_A
1231 * @arg @ref LL_PWR_GPIO_B
1232 * @arg @ref LL_PWR_GPIO_C
1233 * @arg @ref LL_PWR_GPIO_D
1234 * @arg @ref LL_PWR_GPIO_E
1235 * @arg @ref LL_PWR_GPIO_F
1236 * @arg @ref LL_PWR_GPIO_G
1237 *
1238 * (*) value not defined in all devices
1239 * @param GPIONumber This parameter can be one of the following values:
1240 * @arg @ref LL_PWR_GPIO_BIT_0
1241 * @arg @ref LL_PWR_GPIO_BIT_1
1242 * @arg @ref LL_PWR_GPIO_BIT_2
1243 * @arg @ref LL_PWR_GPIO_BIT_3
1244 * @arg @ref LL_PWR_GPIO_BIT_4
1245 * @arg @ref LL_PWR_GPIO_BIT_5
1246 * @arg @ref LL_PWR_GPIO_BIT_6
1247 * @arg @ref LL_PWR_GPIO_BIT_7
1248 * @arg @ref LL_PWR_GPIO_BIT_8
1249 * @arg @ref LL_PWR_GPIO_BIT_9
1250 * @arg @ref LL_PWR_GPIO_BIT_10
1251 * @arg @ref LL_PWR_GPIO_BIT_11
1252 * @arg @ref LL_PWR_GPIO_BIT_12
1253 * @arg @ref LL_PWR_GPIO_BIT_13
1254 * @arg @ref LL_PWR_GPIO_BIT_14
1255 * @arg @ref LL_PWR_GPIO_BIT_15
1256 * @retval State of bit (1 or 0).
1257 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1258 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1259 {
1260 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1261 }
1262
1263 /**
1264 * @}
1265 */
1266
1267 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1268 * @{
1269 */
1270
1271 /**
1272 * @brief Get Internal Wake-up line Flag
1273 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1274 * @retval State of bit (1 or 0).
1275 */
LL_PWR_IsActiveFlag_InternWU(void)1276 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1277 {
1278 uint32_t temp;
1279 temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
1280
1281 return ((temp == (PWR_SR1_WUFI))?1U:0U);
1282
1283 }
1284
1285 /**
1286 * @brief Get Stand-By Flag
1287 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1288 * @retval State of bit (1 or 0).
1289 */
LL_PWR_IsActiveFlag_SB(void)1290 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1291 {
1292 uint32_t temp;
1293 temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
1294
1295 return ((temp == (PWR_SR1_SBF))?1U:0U);
1296
1297 }
1298
1299 /**
1300 * @brief Get Wake-up Flag 5
1301 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1302 * @retval State of bit (1 or 0).
1303 */
LL_PWR_IsActiveFlag_WU5(void)1304 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1305 {
1306 uint32_t temp;
1307 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
1308
1309 return ((temp == (PWR_SR1_WUF5))?1U:0U);
1310 }
1311
1312 /**
1313 * @brief Get Wake-up Flag 4
1314 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1315 * @retval State of bit (1 or 0).
1316 */
LL_PWR_IsActiveFlag_WU4(void)1317 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1318 {
1319 uint32_t temp;
1320 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
1321
1322 return ((temp == (PWR_SR1_WUF4))?1U:0U);
1323 }
1324
1325 /**
1326 * @brief Get Wake-up Flag 3
1327 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1328 * @retval State of bit (1 or 0).
1329 */
LL_PWR_IsActiveFlag_WU3(void)1330 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1331 {
1332 uint32_t temp;
1333 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
1334
1335 return ((temp == (PWR_SR1_WUF3))?1U:0U);
1336 }
1337
1338 /**
1339 * @brief Get Wake-up Flag 2
1340 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1341 * @retval State of bit (1 or 0).
1342 */
LL_PWR_IsActiveFlag_WU2(void)1343 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1344 {
1345 uint32_t temp;
1346 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
1347
1348 return ((temp == (PWR_SR1_WUF2))?1U:0U);
1349 }
1350
1351 /**
1352 * @brief Get Wake-up Flag 1
1353 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1354 * @retval State of bit (1 or 0).
1355 */
LL_PWR_IsActiveFlag_WU1(void)1356 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1357 {
1358 uint32_t temp;
1359 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
1360
1361 return ((temp == (PWR_SR1_WUF1))?1U:0U);
1362 }
1363
1364 /**
1365 * @brief Clear Stand-By Flag
1366 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
1367 * @retval None
1368 */
LL_PWR_ClearFlag_SB(void)1369 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1370 {
1371 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1372 }
1373
1374 /**
1375 * @brief Clear Wake-up Flags
1376 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1377 * @retval None
1378 */
LL_PWR_ClearFlag_WU(void)1379 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1380 {
1381 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1382 }
1383
1384 /**
1385 * @brief Clear Wake-up Flag 5
1386 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1387 * @retval None
1388 */
LL_PWR_ClearFlag_WU5(void)1389 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1390 {
1391 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1392 }
1393
1394 /**
1395 * @brief Clear Wake-up Flag 4
1396 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1397 * @retval None
1398 */
LL_PWR_ClearFlag_WU4(void)1399 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1400 {
1401 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1402 }
1403
1404 /**
1405 * @brief Clear Wake-up Flag 3
1406 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1407 * @retval None
1408 */
LL_PWR_ClearFlag_WU3(void)1409 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1410 {
1411 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1412 }
1413
1414 /**
1415 * @brief Clear Wake-up Flag 2
1416 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1417 * @retval None
1418 */
LL_PWR_ClearFlag_WU2(void)1419 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1420 {
1421 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1422 }
1423
1424 /**
1425 * @brief Clear Wake-up Flag 1
1426 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1427 * @retval None
1428 */
LL_PWR_ClearFlag_WU1(void)1429 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1430 {
1431 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1432 }
1433
1434 /**
1435 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
1436 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
1437 * @retval State of bit (1 or 0).
1438 */
LL_PWR_IsActiveFlag_PVMO4(void)1439 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
1440 {
1441 uint32_t temp;
1442 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
1443
1444 return ((temp == (PWR_SR2_PVMO4))?1U:0U);
1445
1446 }
1447
1448 /**
1449 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
1450 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
1451 * @retval State of bit (1 or 0).
1452 */
LL_PWR_IsActiveFlag_PVMO3(void)1453 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
1454 {
1455 uint32_t temp;
1456 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
1457
1458 return ((temp == (PWR_SR2_PVMO3))?1U:0U);
1459
1460 }
1461
1462 #if defined(PWR_SR2_PVMO2)
1463 /**
1464 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
1465 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
1466 * @retval State of bit (1 or 0).
1467 */
LL_PWR_IsActiveFlag_PVMO2(void)1468 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
1469 {
1470 uint32_t temp;
1471 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
1472
1473 return ((temp == (PWR_SR2_PVMO2))?1U:0U);
1474
1475 }
1476 #endif /* PWR_SR2_PVMO2 */
1477
1478 #if defined(PWR_SR2_PVMO1)
1479 /**
1480 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
1481 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
1482 * @retval State of bit (1 or 0).
1483 */
LL_PWR_IsActiveFlag_PVMO1(void)1484 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
1485 {
1486 uint32_t temp;
1487 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
1488
1489 return ((temp == (PWR_SR2_PVMO1))?1U:0U);
1490
1491 }
1492 #endif /* PWR_SR2_PVMO1 */
1493
1494 /**
1495 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1496 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1497 * @retval State of bit (1 or 0).
1498 */
LL_PWR_IsActiveFlag_PVDO(void)1499 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1500 {
1501 uint32_t temp;
1502 temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
1503
1504 return ((temp == (PWR_SR2_PVDO))?1U:0U);
1505
1506 }
1507
1508 /**
1509 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
1510 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1511 * @retval State of bit (1 or 0).
1512 */
LL_PWR_IsActiveFlag_VOS(void)1513 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1514 {
1515 uint32_t temp;
1516 temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
1517
1518 return ((temp == (PWR_SR2_VOSF))?1U:0U);
1519
1520 }
1521
1522 /**
1523 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1524 * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
1525 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1526 * @retval State of bit (1 or 0).
1527 */
LL_PWR_IsActiveFlag_REGLPF(void)1528 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1529 {
1530 uint32_t temp;
1531 temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
1532
1533 return ((temp == (PWR_SR2_REGLPF))?1U:0U);
1534
1535 }
1536
1537 /**
1538 * @brief Indicate whether or not the low-power regulator is ready
1539 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1540 * @retval State of bit (1 or 0).
1541 */
LL_PWR_IsActiveFlag_REGLPS(void)1542 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1543 {
1544 uint32_t temp;
1545 temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
1546
1547 return ((temp == (PWR_SR2_REGLPS))?1U:0U);
1548
1549 }
1550
1551 /**
1552 * @}
1553 */
1554
1555 #if defined(USE_FULL_LL_DRIVER)
1556 /** @defgroup PWR_LL_EF_Init De-initialization function
1557 * @{
1558 */
1559 ErrorStatus LL_PWR_DeInit(void);
1560 /**
1561 * @}
1562 */
1563 #endif /* USE_FULL_LL_DRIVER */
1564
1565 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
1566 * @{
1567 */
1568 /* Old functions name kept for legacy purpose, to be replaced by the */
1569 /* current functions name. */
1570 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
1571 #define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
1572 #define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
1573 #define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
1574 #define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
1575 #define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
1576 #define LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode
1577 #define LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode
1578 #define LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode
1579 #define LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode
1580 #define LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode
1581 /**
1582 * @}
1583 */
1584
1585 /**
1586 * @}
1587 */
1588
1589 /**
1590 * @}
1591 */
1592
1593 #endif /* defined(PWR) */
1594
1595 /**
1596 * @}
1597 */
1598
1599 #ifdef __cplusplus
1600 }
1601 #endif
1602
1603 #endif /* STM32G4xx_LL_PWR_H */
1604
1605
