1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F3xx_LL_PWR_H
21 #define __STM32F3xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f3xx.h"
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
47 * @{
48 */
49
50 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
51 * @brief Flags defines which can be used with LL_PWR_WriteReg function
52 * @{
53 */
54 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
55 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
56 /**
57 * @}
58 */
59
60 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
61 * @brief Flags defines which can be used with LL_PWR_ReadReg function
62 * @{
63 */
64 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
65 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
66 #if defined(PWR_PVD_SUPPORT)
67 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
68 #endif /* PWR_PVD_SUPPORT */
69 #if defined(PWR_CSR_VREFINTRDYF)
70 #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
71 #endif /* PWR_CSR_VREFINTRDYF */
72 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
73 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
74 #if defined(PWR_CSR_EWUP3)
75 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
76 #endif /* PWR_CSR_EWUP3 */
77 /**
78 * @}
79 */
80
81
82 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
83 * @{
84 */
85 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
86 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
87 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
88 /**
89 * @}
90 */
91
92 #if defined(PWR_CR_LPDS)
93 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
94 * @{
95 */
96 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
97 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
98 /**
99 * @}
100 */
101 #endif /* PWR_CR_LPDS */
102
103 #if defined(PWR_PVD_SUPPORT)
104 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
105 * @{
106 */
107 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
108 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
109 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
110 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
111 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
112 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
113 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
114 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
115 /**
116 * @}
117 */
118 #endif /* PWR_PVD_SUPPORT */
119 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
120 * @{
121 */
122 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
123 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
124 #if defined(PWR_CSR_EWUP3)
125 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
126 #endif /* PWR_CSR_EWUP3 */
127 /**
128 * @}
129 */
130
131 /** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx
132 * @{
133 */
134 #if defined(SDADC1)
135 #define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */
136 #endif /* SDADC1 */
137 #if defined(SDADC2)
138 #define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */
139 #endif /* SDADC2 */
140 #if defined(SDADC3)
141 #define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */
142 #endif /* SDADC3 */
143 /**
144 * @}
145 */
146 /**
147 * @}
148 */
149
150
151 /* Exported macro ------------------------------------------------------------*/
152 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
153 * @{
154 */
155
156 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
157 * @{
158 */
159
160 /**
161 * @brief Write a value in PWR register
162 * @param __REG__ Register to be written
163 * @param __VALUE__ Value to be written in the register
164 * @retval None
165 */
166 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
167
168 /**
169 * @brief Read a value in PWR register
170 * @param __REG__ Register to be read
171 * @retval Register value
172 */
173 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
174 /**
175 * @}
176 */
177
178 /**
179 * @}
180 */
181
182 /* Exported functions --------------------------------------------------------*/
183 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
184 * @{
185 */
186
187 /** @defgroup PWR_LL_EF_Configuration Configuration
188 * @{
189 */
190 /**
191 * @brief Enables the SDADC peripheral functionality
192 * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
193 * CR ENSD2 LL_PWR_EnableSDADC\n
194 * CR ENSD3 LL_PWR_EnableSDADC
195 * @param Analogx This parameter can be a combination of the following values:
196 * @arg @ref LL_PWR_SDADC_ANALOG1
197 * @arg @ref LL_PWR_SDADC_ANALOG2
198 * @arg @ref LL_PWR_SDADC_ANALOG3
199 * @retval None
200 */
LL_PWR_EnableSDADC(uint32_t Analogx)201 __STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
202 {
203 SET_BIT(PWR->CR, Analogx);
204 }
205
206 /**
207 * @brief Disables the SDADC peripheral functionality
208 * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
209 * CR ENSD2 LL_PWR_EnableSDADC\n
210 * CR ENSD3 LL_PWR_EnableSDADC
211 * @param Analogx This parameter can be a combination of the following values:
212 * @arg @ref LL_PWR_SDADC_ANALOG1
213 * @arg @ref LL_PWR_SDADC_ANALOG2
214 * @arg @ref LL_PWR_SDADC_ANALOG3
215 * @retval None
216 */
LL_PWR_DisableSDADC(uint32_t Analogx)217 __STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx)
218 {
219 CLEAR_BIT(PWR->CR, Analogx);
220 }
221
222 /**
223 * @brief Check if SDADCx has been enabled or not
224 * @rmtoll CR ENSD1 LL_PWR_IsEnabledSDADC\n
225 * CR ENSD2 LL_PWR_IsEnabledSDADC\n
226 * CR ENSD3 LL_PWR_IsEnabledSDADC
227 * @param Analogx This parameter can be a combination of the following values:
228 * @arg @ref LL_PWR_SDADC_ANALOG1
229 * @arg @ref LL_PWR_SDADC_ANALOG2
230 * @arg @ref LL_PWR_SDADC_ANALOG3
231 * @retval None
232 */
LL_PWR_IsEnabledSDADC(uint32_t Analogx)233 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx)
234 {
235 return (READ_BIT(PWR->CR, Analogx) == (Analogx));
236 }
237
238 /**
239 * @brief Enable access to the backup domain
240 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
241 * @retval None
242 */
LL_PWR_EnableBkUpAccess(void)243 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
244 {
245 SET_BIT(PWR->CR, PWR_CR_DBP);
246 }
247
248 /**
249 * @brief Disable access to the backup domain
250 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
251 * @retval None
252 */
LL_PWR_DisableBkUpAccess(void)253 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
254 {
255 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
256 }
257
258 /**
259 * @brief Check if the backup domain is enabled
260 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
261 * @retval State of bit (1 or 0).
262 */
LL_PWR_IsEnabledBkUpAccess(void)263 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
264 {
265 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
266 }
267
268 #if defined(PWR_CR_LPDS)
269 /**
270 * @brief Set voltage Regulator mode during deep sleep mode
271 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
272 * @param RegulMode This parameter can be one of the following values:
273 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
274 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
275 * @retval None
276 */
LL_PWR_SetRegulModeDS(uint32_t RegulMode)277 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
278 {
279 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
280 }
281
282 /**
283 * @brief Get voltage Regulator mode during deep sleep mode
284 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
285 * @retval Returned value can be one of the following values:
286 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
287 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
288 */
LL_PWR_GetRegulModeDS(void)289 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
290 {
291 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
292 }
293 #endif /* PWR_CR_LPDS */
294
295 /**
296 * @brief Set Power Down mode when CPU enters deepsleep
297 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
298 * @rmtoll CR LPDS LL_PWR_SetPowerMode
299 * @param PDMode This parameter can be one of the following values:
300 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
301 * @arg @ref LL_PWR_MODE_STOP_LPREGU
302 * @arg @ref LL_PWR_MODE_STANDBY
303 * @retval None
304 */
LL_PWR_SetPowerMode(uint32_t PDMode)305 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
306 {
307 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
308 }
309
310 /**
311 * @brief Get Power Down mode when CPU enters deepsleep
312 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
313 * @rmtoll CR LPDS LL_PWR_GetPowerMode
314 * @retval Returned value can be one of the following values:
315 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
316 * @arg @ref LL_PWR_MODE_STOP_LPREGU
317 * @arg @ref LL_PWR_MODE_STANDBY
318 */
LL_PWR_GetPowerMode(void)319 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
320 {
321 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
322 }
323
324 #if defined(PWR_PVD_SUPPORT)
325 /**
326 * @brief Configure the voltage threshold detected by the Power Voltage Detector
327 * @rmtoll CR PLS LL_PWR_SetPVDLevel
328 * @param PVDLevel This parameter can be one of the following values:
329 * @arg @ref LL_PWR_PVDLEVEL_0
330 * @arg @ref LL_PWR_PVDLEVEL_1
331 * @arg @ref LL_PWR_PVDLEVEL_2
332 * @arg @ref LL_PWR_PVDLEVEL_3
333 * @arg @ref LL_PWR_PVDLEVEL_4
334 * @arg @ref LL_PWR_PVDLEVEL_5
335 * @arg @ref LL_PWR_PVDLEVEL_6
336 * @arg @ref LL_PWR_PVDLEVEL_7
337 * @retval None
338 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)339 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
340 {
341 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
342 }
343
344 /**
345 * @brief Get the voltage threshold detection
346 * @rmtoll CR PLS LL_PWR_GetPVDLevel
347 * @retval Returned value can be one of the following values:
348 * @arg @ref LL_PWR_PVDLEVEL_0
349 * @arg @ref LL_PWR_PVDLEVEL_1
350 * @arg @ref LL_PWR_PVDLEVEL_2
351 * @arg @ref LL_PWR_PVDLEVEL_3
352 * @arg @ref LL_PWR_PVDLEVEL_4
353 * @arg @ref LL_PWR_PVDLEVEL_5
354 * @arg @ref LL_PWR_PVDLEVEL_6
355 * @arg @ref LL_PWR_PVDLEVEL_7
356 */
LL_PWR_GetPVDLevel(void)357 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
358 {
359 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
360 }
361
362 /**
363 * @brief Enable Power Voltage Detector
364 * @rmtoll CR PVDE LL_PWR_EnablePVD
365 * @retval None
366 */
LL_PWR_EnablePVD(void)367 __STATIC_INLINE void LL_PWR_EnablePVD(void)
368 {
369 SET_BIT(PWR->CR, PWR_CR_PVDE);
370 }
371
372 /**
373 * @brief Disable Power Voltage Detector
374 * @rmtoll CR PVDE LL_PWR_DisablePVD
375 * @retval None
376 */
LL_PWR_DisablePVD(void)377 __STATIC_INLINE void LL_PWR_DisablePVD(void)
378 {
379 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
380 }
381
382 /**
383 * @brief Check if Power Voltage Detector is enabled
384 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
385 * @retval State of bit (1 or 0).
386 */
LL_PWR_IsEnabledPVD(void)387 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
388 {
389 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
390 }
391 #endif /* PWR_PVD_SUPPORT */
392
393 /**
394 * @brief Enable the WakeUp PINx functionality
395 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
396 * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
397 * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
398 * @param WakeUpPin This parameter can be one of the following values:
399 * @arg @ref LL_PWR_WAKEUP_PIN1
400 * @arg @ref LL_PWR_WAKEUP_PIN2
401 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
402 *
403 * (*) not available on all devices
404 * @retval None
405 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)406 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
407 {
408 SET_BIT(PWR->CSR, WakeUpPin);
409 }
410
411 /**
412 * @brief Disable the WakeUp PINx functionality
413 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
414 * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
415 * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
416 * @param WakeUpPin This parameter can be one of the following values:
417 * @arg @ref LL_PWR_WAKEUP_PIN1
418 * @arg @ref LL_PWR_WAKEUP_PIN2
419 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
420 *
421 * (*) not available on all devices
422 * @retval None
423 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)424 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
425 {
426 CLEAR_BIT(PWR->CSR, WakeUpPin);
427 }
428
429 /**
430 * @brief Check if the WakeUp PINx functionality is enabled
431 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
432 * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
433 * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
434 * @param WakeUpPin This parameter can be one of the following values:
435 * @arg @ref LL_PWR_WAKEUP_PIN1
436 * @arg @ref LL_PWR_WAKEUP_PIN2
437 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
438 *
439 * (*) not available on all devices
440 * @retval State of bit (1 or 0).
441 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)442 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
443 {
444 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
445 }
446
447
448 /**
449 * @}
450 */
451
452 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
453 * @{
454 */
455
456 /**
457 * @brief Get Wake-up Flag
458 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
459 * @retval State of bit (1 or 0).
460 */
LL_PWR_IsActiveFlag_WU(void)461 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
462 {
463 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
464 }
465
466 /**
467 * @brief Get Standby Flag
468 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
469 * @retval State of bit (1 or 0).
470 */
LL_PWR_IsActiveFlag_SB(void)471 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
472 {
473 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
474 }
475
476 #if defined(PWR_PVD_SUPPORT)
477 /**
478 * @brief Indicate whether VDD voltage is below the selected PVD threshold
479 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
480 * @retval State of bit (1 or 0).
481 */
LL_PWR_IsActiveFlag_PVDO(void)482 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
483 {
484 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
485 }
486 #endif /* PWR_PVD_SUPPORT */
487
488 #if defined(PWR_CSR_VREFINTRDYF)
489 /**
490 * @brief Get Internal Reference VrefInt Flag
491 * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
492 * @retval State of bit (1 or 0).
493 */
LL_PWR_IsActiveFlag_VREFINTRDY(void)494 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
495 {
496 return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
497 }
498 #endif /* PWR_CSR_VREFINTRDYF */
499 /**
500 * @brief Clear Standby Flag
501 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
502 * @retval None
503 */
LL_PWR_ClearFlag_SB(void)504 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
505 {
506 SET_BIT(PWR->CR, PWR_CR_CSBF);
507 }
508
509 /**
510 * @brief Clear Wake-up Flags
511 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
512 * @retval None
513 */
LL_PWR_ClearFlag_WU(void)514 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
515 {
516 SET_BIT(PWR->CR, PWR_CR_CWUF);
517 }
518
519 /**
520 * @}
521 */
522
523 #if defined(USE_FULL_LL_DRIVER)
524 /** @defgroup PWR_LL_EF_Init De-initialization function
525 * @{
526 */
527 ErrorStatus LL_PWR_DeInit(void);
528 /**
529 * @}
530 */
531 #endif /* USE_FULL_LL_DRIVER */
532
533 /**
534 * @}
535 */
536
537 /**
538 * @}
539 */
540
541 #endif /* defined(PWR) */
542
543 /**
544 * @}
545 */
546
547 #ifdef __cplusplus
548 }
549 #endif
550
551 #endif /* __STM32F3xx_LL_PWR_H */
552
