1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL UTILS driver contains a set of generic APIs that can be
23 used by user:
24 (+) Device electronic signature
25 (+) Timing functions
26 (+) PLL configuration functions
27
28 @endverbatim
29 */
30 /* Define to prevent recursive inclusion -------------------------------------*/
31 #ifndef __STM32U5xx_LL_UTILS_H
32 #define __STM32U5xx_LL_UTILS_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 /* Includes ------------------------------------------------------------------*/
39 #include "stm32u5xx.h"
40
41 /** @addtogroup STM32U5xx_LL_Driver
42 * @{
43 */
44
45 /** @defgroup UTILS_LL UTILS
46 * @{
47 */
48
49 /* Private types -------------------------------------------------------------*/
50 /* Private variables ---------------------------------------------------------*/
51
52 /* Private constants ---------------------------------------------------------*/
53 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
54 * @{
55 */
56
57 /* Max delay can be used in LL_mDelay */
58 #define LL_MAX_DELAY 0xFFFFFFFFU
59
60 /**
61 * @brief Unique device ID register base address
62 */
63 #define UID_BASE_ADDRESS UID_BASE
64
65 /**
66 * @brief Flash size data register base address
67 */
68 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
69
70 /**
71 * @brief Package data register base address
72 */
73 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
74
75 /**
76 * @}
77 */
78
79 /* Private macros ------------------------------------------------------------*/
80 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
81 * @{
82 */
83 /**
84 * @}
85 */
86 /* Exported types ------------------------------------------------------------*/
87 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
88 * @{
89 */
90
91 /**
92 * @brief UTILS PLL structure definition
93 */
94 typedef struct
95 {
96 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
97 This parameter can be a value of @ref RCC_LL_EC_PLL1MBOOST_DIV
98
99 This feature can be modified afterwards using unitary function
100 @ref LL_RCC_PLL1_ConfigDomain_SYS(). */
101
102 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
103 This parameter must be a number between Min_Data = 8 and Max_Data = 86
104
105 This feature can be modified afterwards using unitary function
106 @ref LL_RCC_PLL1_ConfigDomain_SYS(). */
107
108 uint32_t PLLR; /*!< Division for the main system clock.
109 This parameter must be a number between Min_Data = 1 and Max_Data = 128
110
111 This feature can be modified afterwards using unitary function
112 @ref LL_RCC_PLL1_ConfigDomain_SYS(). */
113 } LL_UTILS_PLLInitTypeDef;
114
115 /**
116 * @brief UTILS System, AHB and APB buses clock configuration structure definition
117 */
118 typedef struct
119 {
120 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
121 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
122
123 This feature can be modified afterwards using unitary function
124 @ref LL_RCC_SetAHBPrescaler(). */
125
126 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
127 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
128
129 This feature can be modified afterwards using unitary function
130 @ref LL_RCC_SetAPB1Prescaler(). */
131
132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
133 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
134
135 This feature can be modified afterwards using unitary function
136 @ref LL_RCC_SetAPB2Prescaler(). */
137
138 uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
139 This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
140
141 This feature can be modified afterwards using unitary function
142 @ref LL_RCC_SetAPB3Prescaler(). */
143
144 } LL_UTILS_ClkInitTypeDef;
145
146 /**
147 * @}
148 */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
152 * @{
153 */
154
155 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
156 * @{
157 */
158 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
159 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
160 /**
161 * @}
162 */
163
164 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
165 * @{
166 */
167 #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
168 #define LL_UTILS_PACKAGETYPE_WLCSP72_SMPS 0x00000001U /*!< WLCSP72 with internal SMPS package type */
169 #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
170 #define LL_UTILS_PACKAGETYPE_UFBGA132 0x00000003U /*!< UFBGA132 package type */
171 #define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */
172 #define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */
173 #define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007U /*!< UFBGA169 package type */
174 #define LL_UTILS_PACKAGETYPE_LQFP64_SMPS 0x00000008U /*!< LQFP64 with internal SMPS package type */
175 #define LL_UTILS_PACKAGETYPE_WLSCP90_SMPS 0x00000009U /*!< WLSCP90 with internal SMPS package type */
176 #define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */
177 #define LL_UTILS_PACKAGETYPE_UFBGA132_SMPS 0x0000000BU /*!< UFBGA132 with internal SMPS package type */
178 #define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */
179 #define LL_UTILS_PACKAGETYPE_LQFP48_SMPS 0x0000000DU /*!< LQFP48 with internal SMPS package type */
180 #define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000FU /*!< UFBGA169 with internal SMPS package type */
181 #define LL_UTILS_PACKAGETYPE_UFBGA64 0x00000012U /*!< UFBGA64 package type */
182 #define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000013U /*!< UFBGA100 package type */
183 #define LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS 0x00000014U /*!< LQFP100 DSI with internal SMPS package type */
184 #define LL_UTILS_PACKAGETYPE_LQFP144_DSI_SMPS 0x00000015U /*!< LQFP144 DSI with internal SMPS package type */
185 #define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS 0x00000019U /*!< UFBGA144 with internal SMPS package type */
186 #define LL_UTILS_PACKAGETYPE_WLCSP208_SMPS 0x0000001BU /*!< WLCSP208 with internal SMPS package type */
187 #define LL_UTILS_PACKAGETYPE_TFBGA216_SMPS 0x0000001CU /*!< TFBGA216 with internal SMPS package type */
188 #define LL_UTILS_PACKAGETYPE_UFBGA100_SMPS 0x0000001DU /*!< UFBGA100 with internal SMPS package type */
189 #define LL_UTILS_PACKAGETYPE_WLCSP56_SMPS 0x0000001EU /*!< WLCSP56 with internal SMPS package type */
190 #define LL_UTILS_PACKAGETYPE_WLCSP150_SMPS 0x0000001FU /*!< WLCSP150 or WLCSP150 DSI with internal package type */
191
192 /**
193 * @}
194 */
195
196 /**
197 * @}
198 */
199
200 /* Exported macro ------------------------------------------------------------*/
201
202 /* Exported functions --------------------------------------------------------*/
203 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
204 * @{
205 */
206
207 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
208 * @{
209 */
210
211 /**
212 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
213 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
214 */
LL_GetUID_Word0(void)215 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
216 {
217 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
218 }
219
220 /**
221 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
222 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
223 */
LL_GetUID_Word1(void)224 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
225 {
226 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
227 }
228
229 /**
230 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
231 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
232 */
LL_GetUID_Word2(void)233 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
234 {
235 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
236 }
237
238 /**
239 * @brief Get Flash memory size
240 * @note This bitfield indicates the size of the device Flash memory expressed in
241 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
242 * @retval FLASH_SIZE[15:0]: Flash memory size
243 */
LL_GetFlashSize(void)244 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
245 {
246 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
247 }
248
249 /**
250 * @brief Get Package type
251 * @retval Returned value can be one of the following values:
252 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
253 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
254 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132
255 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144
256 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
257 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169
258 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64_SMPS
259 * @arg @ref LL_UTILS_PACKAGETYPE_WLSCP90_SMPS
260 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS
261 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132_SMPS
262 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS
263 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_SMPS
264 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS
265 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144
266 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144
267 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_SMPS
268 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS
269 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP208_SMPS
270 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216_SMPS
271 */
LL_GetPackageType(void)272 __STATIC_INLINE uint32_t LL_GetPackageType(void)
273 {
274 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
275 }
276
277 /**
278 * @}
279 */
280
281 /** @defgroup UTILS_LL_EF_DELAY DELAY
282 * @{
283 */
284
285 /**
286 * @brief This function configures the Cortex-M SysTick source of the time base.
287 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
288 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
289 * configuration by calling this function, for a delay use rather osDelay RTOS service.
290 * @param Ticks Number of ticks
291 * @retval None
292 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)293 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
294 {
295 /* Configure the SysTick to have interrupt in 1ms time base */
296 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
297 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
298 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
299 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
300 }
301
302 void LL_Init1msTick(uint32_t HCLKFrequency);
303 void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency);
304 void LL_Init1msTick_LSE(void);
305 void LL_Init1msTick_LSI(void);
306 void LL_mDelay(uint32_t Delay);
307
308 /**
309 * @}
310 */
311
312 /** @defgroup LL_UTILS_Aliased_Functions LL UTILS Aliased Functions maintained for legacy purpose
313 * @{
314 */
315 #define LL_PLL1_ConfigSystemClock_MSI LL_PLL_ConfigSystemClock_MSI /* for legacy purpose */
316 #define LL_PLL1_ConfigSystemClock_HSI LL_PLL_ConfigSystemClock_HSI /* for legacy purpose */
317 #define LL_PLL1_ConfigSystemClock_HSE LL_PLL_ConfigSystemClock_HSE /* for legacy purpose */
318 /**
319 * @}
320 */
321
322 /** @defgroup UTILS_EF_SYSTEM SYSTEM
323 * @{
324 */
325
326 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
327 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
328 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
329 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
330 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
331 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
332 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
333 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
334 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
335 /**
336 * @}
337 */
338
339 /**
340 * @}
341 */
342
343 /**
344 * @}
345 */
346
347 /**
348 * @}
349 */
350
351 #ifdef __cplusplus
352 }
353 #endif
354
355 #endif /* __STM32U5xx_LL_UTILS_H */
356
357
