1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_LPTIM_H
21 #define STM32H5xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5) || defined (LPTIM6)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45
46 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
47 {
48 0U, /* CC1P */
49 16U /* CC2P */
50 };
51
52 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
53 {
54 0U, /* IC1F */
55 16U /* IC2F */
56 };
57
58 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
59 {
60 0U, /* IC1PSC */
61 16U /* IC2PSC */
62 };
63
64 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
65 {
66 0U, /* CC1SEL */
67 16U /* CC2SEL */
68 };
69
70 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
71 {
72 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
73 LPTIM_CCMR1_CC2E_Pos /* CC2E */
74 };
75
76 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
77 {
78 {2, 7, 9, 13},
79 {3, 5, 6, 8},
80 {2, 3, 4, 5},
81 {2, 2, 3, 3},
82 {2, 2, 2, 2},
83 {2, 2, 2, 2},
84 {2, 2, 2, 2},
85 {2, 2, 2, 2}
86
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94 /** Legacy definitions for compatibility purpose
95 @cond 0
96 */
97 #define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1
98 #define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2
99 #define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1
100 #define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2
101 /**
102 @endcond
103 */
104
105 /* Private macros ------------------------------------------------------------*/
106 #if defined(USE_FULL_LL_DRIVER)
107 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
108 * @{
109 */
110 /**
111 * @}
112 */
113 #endif /*USE_FULL_LL_DRIVER*/
114
115 /* Exported types ------------------------------------------------------------*/
116 #if defined(USE_FULL_LL_DRIVER)
117 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
118 * @{
119 */
120
121 /**
122 * @brief LPTIM Init structure definition
123 */
124 typedef struct
125 {
126 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
127 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
128
129 This feature can be modified afterwards using unitary
130 function @ref LL_LPTIM_SetClockSource().*/
131
132 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
133 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
134
135 This feature can be modified afterwards using using unitary
136 function @ref LL_LPTIM_SetPrescaler().*/
137
138 uint32_t Waveform; /*!< Specifies the waveform shape.
139 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
140
141 This feature can be modified afterwards using unitary
142 function @ref LL_LPTIM_SetWaveform().*/
143 } LL_LPTIM_InitTypeDef;
144
145 /**
146 * @}
147 */
148 #endif /* USE_FULL_LL_DRIVER */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
152 * @{
153 */
154
155 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
156 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
157 * @{
158 */
159 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
160 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
161 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
162 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
163 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
164 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
165 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
166 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
167 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
168 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
169 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
170 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
171 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
172 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
173 /**
174 * @}
175 */
176
177 /** @defgroup LPTIM_LL_EC_IT IT Defines
178 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
179 * @{
180 */
181 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
182 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
183 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
184 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
185 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
186 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
187 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
188 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
189 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
190 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
191 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
192 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
193 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
194 /**
195 * @}
196 */
197
198 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
199 * @{
200 */
201 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
202 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
203 /**
204 * @}
205 */
206
207 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
208 * @{
209 */
210 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
211 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
212 /**
213 * @}
214 */
215
216 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
217 * @{
218 */
219 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
220 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
226 * @{
227 */
228 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
229 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
230 /**
231 * @}
232 */
233
234 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
235 * @{
236 */
237 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
238 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
239 /**
240 * @}
241 */
242
243 /** @defgroup TIM_LL_EC_CHANNEL Channel
244 * @{
245 */
246 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
247 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
248 /**
249 * @}
250 */
251
252 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
253 * @{
254 */
255 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
256 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
257 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
258 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
259 /**
260 * @}
261 */
262
263 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
264 * @{
265 */
266 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
267 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
268 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
269 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
270 /**
271 * @}
272 */
273
274 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
275 * @{
276 */
277 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
278 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
279 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
280 /**
281 * @}
282 */
283 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
284 * @{
285 */
286 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
287 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
288 /**
289 * @}
290 */
291
292 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
293 * @{
294 */
295 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
296 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
297 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
298 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
299 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
300 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
301 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
302 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
303 /**
304 * @}
305 */
306
307 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
308 * @{
309 */
310 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
311 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
312 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
313 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
314 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
315 #if defined(COMP1)
316 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
317 #endif /* COMP1 */
318 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to GPDMA CH0 transfer complete */
319 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH1_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to GPDMA CH1 transfer complete */
320 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to GPDMA CH4 transfer complete */
321 #define LL_LPTIM_TRIG_SOURCE_EVENTOUT (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to EVENTOUT */
322 /**
323 * @}
324 */
325
326 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
327 * @{
328 */
329 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
330 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
331 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
332 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
333 /**
334 * @}
335 */
336
337 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
338 * @{
339 */
340 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
341 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
342 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
343 /**
344 * @}
345 */
346
347 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
348 * @{
349 */
350 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
351 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
352 /**
353 * @}
354 */
355
356 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
357 * @{
358 */
359 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
360 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
361 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
362 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
363 /**
364 * @}
365 */
366
367 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
368 * @{
369 */
370 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
371 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
372 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
373 /**
374 * @}
375 */
376
377 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
378 * @{
379 */
380 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
381 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
382 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
383 /**
384 * @}
385 */
386
387 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
388 * @{
389 */
390 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 and LPTIM6 */
391 #if defined(STM32H503xx)
392 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */
393 #define LL_LPTIM_INPUT1_SRC_LPTIM2_CH1 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM1 */
394 #define LL_LPTIM_INPUT1_SRC_LPTIM1_CH2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM2 */
395 #endif /* STM32H503xx */
396 /**
397 * @}
398 */
399
400 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
401 * @{
402 */
403 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2, LPTIM3, LPTIM4 , LPTIM5 and LPTIM6 */
404 /**
405 * @}
406 */
407
408 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
409 * @{
410 */
411 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
412 #if defined(STM32H503xx)
413 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
414 #define LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to EVENTOUT */
415 #define LL_LPTIM_LPTIM1_IC1_RMP_MCO1 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1) /*!< IC1 connected to MCO1 */
416 #endif /* STM32H503xx */
417 /**
418 * @}
419 */
420
421 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
422 * @{
423 */
424 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
425 #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
426 #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
427 #if defined(STM32H503xx)
428 #define LL_LPTIM_LPTIM1_IC2_RMP_HSE_1M (LPTIM_CFGR2_IC2SEL_0 | LPTIM_CFGR2_IC2SEL_1) /*!< IC2 connected to HSE_1M */
429 #endif /* STM32H503xx */
430 /**
431 * @}
432 */
433
434 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
435 * @{
436 */
437 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
438 #if defined(STM32H503xx)
439 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
440 #define LL_LPTIM_LPTIM2_IC1_RMP_EVENTOUT LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to EVENTOUT */
441 #define LL_LPTIM_LPTIM2_IC1_RMP_MCO2 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1) /*!< IC1 connected to MCO2 */
442 #endif /* STM32H503xx */
443 /**
444 * @}
445 */
446
447 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
448 * @{
449 */
450 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
451 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI/1024 */
452 #define LL_LPTIM_LPTIM2_IC2_RMP_CSI_128 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to CSI/128 */
453 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI_8 (LPTIM_CFGR2_IC2SEL_0 | LPTIM_CFGR2_IC2SEL_1) /*!< IC2 connected to HSI/8 */
454 /**
455 * @}
456 */
457
458 /** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
459 * @{
460 */
461 #define LL_LPTIM_LPTIM3_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
462 /**
463 * @}
464 */
465
466 /** @defgroup LPTIM_EC_LPTIM3_IC2_RMP LPTIM3 Input Ch2 Remap
467 * @{
468 */
469 #define LL_LPTIM_LPTIM3_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
470 /**
471 * @}
472 */
473
474 #if defined(LPTIM5) && defined(LPTIM6)
475 /** @defgroup LPTIM_EC_LPTIM5_IC1_RMP LPTIM5 Input Ch1 Remap
476 * @{
477 */
478 #define LL_LPTIM_LPTIM5_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
479 /**
480 * @}
481 */
482
483 /** @defgroup LPTIM_EC_LPTIM5_IC2_RMP LPTIM5 Input Ch2 Remap
484 * @{
485 */
486 #define LL_LPTIM_LPTIM5_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
487 /**
488 * @}
489 */
490
491 /** @defgroup LPTIM_EC_LPTIM6_IC1_RMP LPTIM6 Input Ch1 Remap
492 * @{
493 */
494 #define LL_LPTIM_LPTIM6_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
495 /**
496 * @}
497 */
498
499 /** @defgroup LPTIM_EC_LPTIM6_IC2_RMP LPTIM6 Input Ch2 Remap
500 * @{
501 */
502 #define LL_LPTIM_LPTIM6_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
503 /**
504 * @}
505 */
506
507 #endif /* LPTIM5 && LPTIM6 */
508
509 /**
510 * @}
511 */
512
513 /* Exported macro ------------------------------------------------------------*/
514 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
515 * @{
516 */
517
518 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
519 * @{
520 */
521
522 /**
523 * @brief Write a value in LPTIM register
524 * @param __INSTANCE__ LPTIM Instance
525 * @param __REG__ Register to be written
526 * @param __VALUE__ Value to be written in the register
527 * @retval None
528 */
529 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
530
531 /**
532 * @brief Read a value in LPTIM register
533 * @param __INSTANCE__ LPTIM Instance
534 * @param __REG__ Register to be read
535 * @retval Register value
536 */
537 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
538
539 /**
540 * @brief LPTimer Input Capture Get Offset(in counter step unit)
541 * @note The real capture value corresponding to the input capture trigger can be calculated using
542 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
543 * The Offset value is depending on the glitch filter value for the channel
544 * and the value of the prescaler for the kernel clock.
545 * Please check Errata Sheet V1_8 for more details under "variable latency
546 * on input capture channel" section.
547 * @param __PSC__ This parameter can be one of the following values:
548 * @arg @ref LL_LPTIM_PRESCALER_DIV1
549 * @arg @ref LL_LPTIM_PRESCALER_DIV2
550 * @arg @ref LL_LPTIM_PRESCALER_DIV4
551 * @arg @ref LL_LPTIM_PRESCALER_DIV8
552 * @arg @ref LL_LPTIM_PRESCALER_DIV16
553 * @arg @ref LL_LPTIM_PRESCALER_DIV32
554 * @arg @ref LL_LPTIM_PRESCALER_DIV64
555 * @arg @ref LL_LPTIM_PRESCALER_DIV128
556 * @param __FLT__ This parameter can be one of the following values:
557 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
558 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
559 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
560 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
561 * @retval offset value
562 */
563 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
564 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
565 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
566 /**
567 * @}
568 */
569
570 /**
571 * @}
572 */
573
574 /* Exported functions --------------------------------------------------------*/
575 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
576 * @{
577 */
578
579 /** Legacy definitions for compatibility purpose
580 @cond 0
581 */
582 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
583 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
584 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
585 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
586 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
587 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
588 /**
589 @endcond
590 */
591
592 #if defined(USE_FULL_LL_DRIVER)
593 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
594 * @{
595 */
596
597 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
598 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
599 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
600 /**
601 * @}
602 */
603 #endif /* USE_FULL_LL_DRIVER */
604
605 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
606 * @{
607 */
608
609 /**
610 * @brief Enable the LPTIM instance
611 * @note After setting the ENABLE bit, a delay of two counter clock is needed
612 * before the LPTIM instance is actually enabled.
613 * @rmtoll CR ENABLE LL_LPTIM_Enable
614 * @param LPTIMx Low-Power Timer instance
615 * @retval None
616 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)617 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
618 {
619 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
620 }
621
622 /**
623 * @brief Disable the LPTIM instance
624 * @rmtoll CR ENABLE LL_LPTIM_Disable
625 * @param LPTIMx Low-Power Timer instance
626 * @retval None
627 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)628 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
629 {
630 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
631 }
632
633 /**
634 * @brief Indicates whether the LPTIM instance is enabled.
635 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
636 * @param LPTIMx Low-Power Timer instance
637 * @retval State of bit (1 or 0).
638 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)639 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
640 {
641 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
642 }
643
644 /**
645 * @brief Starts the LPTIM counter in the desired mode.
646 * @note LPTIM instance must be enabled before starting the counter.
647 * @note It is possible to change on the fly from One Shot mode to
648 * Continuous mode.
649 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
650 * CR SNGSTRT LL_LPTIM_StartCounter
651 * @param LPTIMx Low-Power Timer instance
652 * @param OperatingMode This parameter can be one of the following values:
653 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
654 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
655 * @retval None
656 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)657 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
658 {
659 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
660 }
661
662 /**
663 * @brief Enable reset after read.
664 * @note After calling this function any read access to LPTIM_CNT
665 * register will asynchronously reset the LPTIM_CNT register content.
666 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
667 * @param LPTIMx Low-Power Timer instance
668 * @retval None
669 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)670 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
671 {
672 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
673 }
674
675 /**
676 * @brief Disable reset after read.
677 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
678 * @param LPTIMx Low-Power Timer instance
679 * @retval None
680 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)681 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
682 {
683 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
684 }
685
686 /**
687 * @brief Indicate whether the reset after read feature is enabled.
688 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
689 * @param LPTIMx Low-Power Timer instance
690 * @retval State of bit (1 or 0).
691 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)692 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
693 {
694 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
695 }
696
697 /**
698 * @brief Reset of the LPTIM_CNT counter register (synchronous).
699 * @note Due to the synchronous nature of this reset, it only takes
700 * place after a synchronization delay of 3 LPTIM core clock cycles
701 * (LPTIM core clock may be different from APB clock).
702 * @note COUNTRST is automatically cleared by hardware
703 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
704 * @param LPTIMx Low-Power Timer instance
705 * @retval None
706 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)707 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
708 {
709 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
710 }
711
712 /**
713 * @brief Set the LPTIM registers update mode (enable/disable register preload)
714 * @note This function must be called when the LPTIM instance is disabled.
715 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
716 * @param LPTIMx Low-Power Timer instance
717 * @param UpdateMode This parameter can be one of the following values:
718 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
719 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
720 * @retval None
721 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)722 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
723 {
724 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
725 }
726
727 /**
728 * @brief Get the LPTIM registers update mode
729 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
730 * @param LPTIMx Low-Power Timer instance
731 * @retval Returned value can be one of the following values:
732 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
733 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
734 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)735 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
736 {
737 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
738 }
739
740 /**
741 * @brief Set the auto reload value
742 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
743 * @note After a write to the LPTIMx_ARR register a new write operation to the
744 * same register can only be performed when the previous write operation
745 * is completed. Any successive write before the ARROK flag is set, will
746 * lead to unpredictable results.
747 * @note autoreload value be strictly greater than the compare value.
748 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
749 * @param LPTIMx Low-Power Timer instance
750 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
751 * @retval None
752 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)753 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
754 {
755 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
756 }
757
758 /**
759 * @brief Get actual auto reload value
760 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
761 * @param LPTIMx Low-Power Timer instance
762 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
763 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)764 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
765 {
766 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
767 }
768
769 /**
770 * @brief Set the repetition value
771 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
772 * @rmtoll RCR REP LL_LPTIM_SetRepetition
773 * @param LPTIMx Low-Power Timer instance
774 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
775 * @retval None
776 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)777 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
778 {
779 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
780 }
781
782 /**
783 * @brief Get the repetition value
784 * @rmtoll RCR REP LL_LPTIM_GetRepetition
785 * @param LPTIMx Low-Power Timer instance
786 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
787 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)788 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
789 {
790 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
791 }
792
793 /**
794 * @brief Enable capture/compare channel.
795 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
796 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
797 * @param LPTIMx LPTimer instance
798 * @param Channel This parameter can be one of the following values:
799 * @arg @ref LL_LPTIM_CHANNEL_CH1
800 * @arg @ref LL_LPTIM_CHANNEL_CH2
801 * @retval None
802 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)803 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
804 {
805 SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
806 }
807
808 /**
809 * @brief Disable capture/compare channel.
810 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
811 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
812 * @param LPTIMx LPTimer instance
813 * @param Channel This parameter can be one of the following values:
814 * @arg @ref LL_LPTIM_CHANNEL_CH1
815 * @arg @ref LL_LPTIM_CHANNEL_CH2
816 * @retval None
817 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)818 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
819 {
820 CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
821 }
822
823 /**
824 * @brief Indicate whether channel is enabled.
825 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
826 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
827 * @param LPTIMx LPTimer instance
828 * @param Channel This parameter can be one of the following values:
829 * @arg @ref LL_LPTIM_CHANNEL_CH1
830 * @arg @ref LL_LPTIM_CHANNEL_CH2
831 * @retval State of bit (1 or 0).
832 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)833 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
834 {
835 return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
836 (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
837
838 }
839
840 /**
841 * @brief Set the compare value
842 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
843 * same register can only be performed when the previous write operation
844 * is completed. Any successive write before the CMP1OK flag is set, will
845 * lead to unpredictable results.
846 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
847 * @param LPTIMx Low-Power Timer instance
848 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
849 * @retval None
850 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)851 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
852 {
853 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
854 }
855
856 /**
857 * @brief Get actual compare value
858 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
859 * @param LPTIMx Low-Power Timer instance
860 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
861 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)862 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
863 {
864 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
865 }
866
867 /**
868 * @brief Set the compare value
869 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
870 * same register can only be performed when the previous write operation
871 * is completed. Any successive write before the CMP2OK flag is set, will
872 * lead to unpredictable results.
873 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
874 * @param LPTIMx Low-Power Timer instance
875 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
876 * @retval None
877 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)878 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
879 {
880 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
881 }
882
883 /**
884 * @brief Get actual compare value
885 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
886 * @param LPTIMx Low-Power Timer instance
887 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
888 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)889 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
890 {
891 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
892 }
893
894 /**
895 * @brief Get actual counter value
896 * @note When the LPTIM instance is running with an asynchronous clock, reading
897 * the LPTIMx_CNT register may return unreliable values. So in this case
898 * it is necessary to perform two consecutive read accesses and verify
899 * that the two returned values are identical.
900 * @rmtoll CNT CNT LL_LPTIM_GetCounter
901 * @param LPTIMx Low-Power Timer instance
902 * @retval Counter value
903 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)904 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
905 {
906 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
907 }
908
909 /**
910 * @brief Set the counter mode (selection of the LPTIM counter clock source).
911 * @note The counter mode can be set only when the LPTIM instance is disabled.
912 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
913 * @param LPTIMx Low-Power Timer instance
914 * @param CounterMode This parameter can be one of the following values:
915 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
916 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
917 * @retval None
918 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)919 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
920 {
921 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
922 }
923
924 /**
925 * @brief Get the counter mode
926 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
927 * @param LPTIMx Low-Power Timer instance
928 * @retval Returned value can be one of the following values:
929 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
930 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
931 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)932 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
933 {
934 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
935 }
936
937 /**
938 * @brief Set waveform shape
939 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
940 * @param LPTIMx Low-Power Timer instance
941 * @param Waveform This parameter can be one of the following values:
942 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
943 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
944 * @retval None
945 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)946 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
947 {
948 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
949 }
950
951 /**
952 * @brief Get actual waveform shape
953 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
954 * @param LPTIMx Low-Power Timer instance
955 * @retval Returned value can be one of the following values:
956 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
957 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
958 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)959 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
960 {
961 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
962 }
963
964 /**
965 * @brief Set the polarity of an output channel.
966 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
967 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
968 * @param LPTIMx Low-Power Timer instance
969 * @param Channel This parameter can be one of the following values:
970 * @arg @ref LL_LPTIM_CHANNEL_CH1
971 * @arg @ref LL_LPTIM_CHANNEL_CH2
972 * @param Polarity This parameter can be one of the following values:
973 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
974 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
975 * @retval None
976 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)977 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
978 {
979 #if defined(LPTIM4)
980 if (LPTIMx == LPTIM4)
981 {
982 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
983 }
984 else
985 #endif /* LPTIM4 */
986 {
987 MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
988 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
989 }
990 }
991
992 /**
993 * @brief Get the polarity of an output channel.
994 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
995 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
996 * @param LPTIMx Low-Power Timer instance
997 * @param Channel This parameter can be one of the following values:
998 * @arg @ref LL_LPTIM_CHANNEL_CH1
999 * @arg @ref LL_LPTIM_CHANNEL_CH2
1000 * @retval Returned value can be one of the following values:
1001 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
1002 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
1003 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1004 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1005 {
1006 #if defined(LPTIM4)
1007 if (LPTIMx == LPTIM4)
1008 {
1009 return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
1010 }
1011 else
1012 #endif /* LPTIM4 */
1013 {
1014 return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \
1015 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1016 }
1017 }
1018
1019 /**
1020 * @brief Set actual prescaler division ratio.
1021 * @note This function must be called when the LPTIM instance is disabled.
1022 * @note When the LPTIM is configured to be clocked by an internal clock source
1023 * and the LPTIM counter is configured to be updated by active edges
1024 * detected on the LPTIM external Input1, the internal clock provided to
1025 * the LPTIM must be not be prescaled.
1026 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
1027 * @param LPTIMx Low-Power Timer instance
1028 * @param Prescaler This parameter can be one of the following values:
1029 * @arg @ref LL_LPTIM_PRESCALER_DIV1
1030 * @arg @ref LL_LPTIM_PRESCALER_DIV2
1031 * @arg @ref LL_LPTIM_PRESCALER_DIV4
1032 * @arg @ref LL_LPTIM_PRESCALER_DIV8
1033 * @arg @ref LL_LPTIM_PRESCALER_DIV16
1034 * @arg @ref LL_LPTIM_PRESCALER_DIV32
1035 * @arg @ref LL_LPTIM_PRESCALER_DIV64
1036 * @arg @ref LL_LPTIM_PRESCALER_DIV128
1037 * @retval None
1038 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)1039 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
1040 {
1041 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
1042 }
1043
1044 /**
1045 * @brief Get actual prescaler division ratio.
1046 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
1047 * @param LPTIMx Low-Power Timer instance
1048 * @retval Returned value can be one of the following values:
1049 * @arg @ref LL_LPTIM_PRESCALER_DIV1
1050 * @arg @ref LL_LPTIM_PRESCALER_DIV2
1051 * @arg @ref LL_LPTIM_PRESCALER_DIV4
1052 * @arg @ref LL_LPTIM_PRESCALER_DIV8
1053 * @arg @ref LL_LPTIM_PRESCALER_DIV16
1054 * @arg @ref LL_LPTIM_PRESCALER_DIV32
1055 * @arg @ref LL_LPTIM_PRESCALER_DIV64
1056 * @arg @ref LL_LPTIM_PRESCALER_DIV128
1057 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)1058 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
1059 {
1060 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
1061 }
1062
1063 /**
1064 * @brief Set LPTIM input 1 source (default GPIO).
1065 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
1066 * @param LPTIMx Low-Power Timer instance
1067 * @param Src This parameter can be one of the following values:
1068 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
1069 @if STM32H503xx
1070 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1 (*)
1071 * @arg @ref LL_LPTIM_INPUT1SOURCE_LPTIM2_CH1 (*)
1072 * @arg @ref LL_LPTIM_INPUT1SOURCE_LPTIM1_CH2 (*)
1073 @endif
1074 * (*) Value not defined for all devices
1075 * @retval None
1076 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1077 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1078 {
1079 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
1080 }
1081
1082 /**
1083 * @brief Set LPTIM input 2 source (default GPIO).
1084 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
1085 * @param LPTIMx Low-Power Timer instance
1086 * @param Src This parameter can be one of the following values:
1087 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1088 * @retval None
1089 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1090 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1091 {
1092 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1093 }
1094
1095 /**
1096 * @brief Set LPTIM input source (default GPIO).
1097 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
1098 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
1099 * @param LPTIMx Low-Power Timer instance
1100 * @param Src This parameter can be one of the following values:
1101 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1102 @if STM32H503xx
1103 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1 (*)
1104 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT (*)
1105 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_MCO1 (*)
1106 @endif
1107 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1108 @if STM32H503xx
1109 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI (*)
1110 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE (*)
1111 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_HSE_1M (*)
1112 @endif
1113 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1114 @if STM32H503xx
1115 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1 (*)
1116 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_EVENTOUT (*)
1117 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_MCO2 (*)
1118 @endif
1119 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1120 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024
1121 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_CSI_128
1122 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_8
1123 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO (*)
1124 * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_GPIO (*)
1125 * @arg @ref LL_LPTIM_LPTIM5_IC1_RMP_GPIO (*)
1126 * @arg @ref LL_LPTIM_LPTIM5_IC2_RMP_GPIO (*)
1127 * @arg @ref LL_LPTIM_LPTIM6_IC1_RMP_GPIO (*)
1128 * @arg @ref LL_LPTIM_LPTIM6_IC2_RMP_GPIO (*)
1129 *
1130 * (*) Value not defined in all devices. \n
1131 *
1132 * @retval None
1133 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1134 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1135 {
1136 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
1137 }
1138
1139 /**
1140 * @brief Set the polarity of IC channel 1.
1141 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1142 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1143 * @param LPTIMx Low-Power Timer instance
1144 * @param Channel This parameter can be one of the following values:
1145 * @arg @ref LL_LPTIM_CHANNEL_CH1
1146 * @arg @ref LL_LPTIM_CHANNEL_CH2
1147 * @param Polarity This parameter can be one of the following values:
1148 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1149 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1150 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1151 * @retval None
1152 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1153 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1154 {
1155 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
1156 Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1157 }
1158
1159 /**
1160 * @brief Get the polarity of IC channels.
1161 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1162 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1163 * @param LPTIMx Low-Power Timer instance
1164 * @param Channel This parameter can be one of the following values:
1165 * @arg @ref LL_LPTIM_CHANNEL_CH1
1166 * @arg @ref LL_LPTIM_CHANNEL_CH2
1167 * @retval Returned value can be one of the following values:
1168 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1169 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1170 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1171 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1172 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1173 {
1174 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1175 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1176
1177 }
1178
1179 /**
1180 * @brief Set the filter of IC channels.
1181 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1182 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1183 * @param LPTIMx Low-Power Timer instance
1184 * @param Channel This parameter can be one of the following values:
1185 * @arg @ref LL_LPTIM_CHANNEL_CH1
1186 * @arg @ref LL_LPTIM_CHANNEL_CH2
1187 * @param Filter This parameter can be one of the following values:
1188 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1189 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1190 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1191 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1192 * @retval None
1193 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1194 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1195 {
1196 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
1197 Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1198 }
1199
1200 /**
1201 * @brief Get the filter of IC channels.
1202 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1203 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1204 * @param LPTIMx Low-Power Timer instance
1205 * @param Channel This parameter can be one of the following values:
1206 * @arg @ref LL_LPTIM_CHANNEL_CH1
1207 * @arg @ref LL_LPTIM_CHANNEL_CH2
1208 * @retval Returned value can be one of the following values:
1209 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1210 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1211 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1212 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1213 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1214 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1215 {
1216 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1217 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1218 }
1219
1220 /**
1221 * @brief Set the prescaler of IC channels.
1222 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1223 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1224 * @param LPTIMx Low-Power Timer instance
1225 * @param Channel This parameter can be one of the following values:
1226 * @arg @ref LL_LPTIM_CHANNEL_CH1
1227 * @arg @ref LL_LPTIM_CHANNEL_CH2
1228 * @param Prescaler This parameter can be one of the following values:
1229 * @arg @ref LL_LPTIM_ICPSC_DIV1
1230 * @arg @ref LL_LPTIM_ICPSC_DIV2
1231 * @arg @ref LL_LPTIM_ICPSC_DIV4
1232 * @arg @ref LL_LPTIM_ICPSC_DIV8
1233 * @retval None
1234 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1235 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1236 {
1237 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1238 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1239 }
1240
1241 /**
1242 * @brief Get the prescaler of IC channels.
1243 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1244 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1245 * @param LPTIMx Low-Power Timer instance
1246 * @param Channel This parameter can be one of the following values:
1247 * @arg @ref LL_LPTIM_CHANNEL_CH1
1248 * @arg @ref LL_LPTIM_CHANNEL_CH2
1249 * @retval Returned value can be one of the following values:
1250 * @arg @ref LL_LPTIM_ICPSC_DIV1
1251 * @arg @ref LL_LPTIM_ICPSC_DIV2
1252 * @arg @ref LL_LPTIM_ICPSC_DIV4
1253 * @arg @ref LL_LPTIM_ICPSC_DIV8
1254 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1255 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1256 {
1257 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1258 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1259 }
1260
1261 /**
1262 * @brief Set the Channel Mode.
1263 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1264 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
1265 * @param LPTIMx Low-Power Timer instance
1266 * @param Channel This parameter can be one of the following values:
1267 * @arg @ref LL_LPTIM_CHANNEL_CH1
1268 * @arg @ref LL_LPTIM_CHANNEL_CH2
1269 * @param CCMode This parameter can be one of the following values:
1270 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1271 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1272 * @retval None
1273 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1274 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1275 {
1276 SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1277 }
1278
1279 /**
1280 * @brief Get the Channel Mode.
1281 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1282 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
1283 * @param LPTIMx Low-Power Timer instance
1284 * @param Channel This parameter can be one of the following values:
1285 * @arg @ref LL_LPTIM_CHANNEL_CH1
1286 * @arg @ref LL_LPTIM_CHANNEL_CH2
1287 * @retval Returned value can be one of the following values:
1288 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1289 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1290 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1291 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1292 {
1293 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1294 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1295 }
1296
1297 /**
1298 * @brief Get captured value for input channel 1.
1299 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1300 * @note The real capture value corresponding to the input capture trigger can be calculated using
1301 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1302 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1303 * @param LPTIMx Low-Power Timer instance
1304 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1305 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1306 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1307 {
1308 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1309 }
1310
1311 /**
1312 * @brief Get captured value for input channel 2.
1313 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1314 * @note The real capture value corresponding to the input capture trigger can be calculated using
1315 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1316 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1317 * @param LPTIMx Low-Power Timer instance
1318 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1319 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1320 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1321 {
1322 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1323 }
1324
1325 /**
1326 * @}
1327 */
1328
1329 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1330 * @{
1331 */
1332
1333 /**
1334 * @brief Enable the timeout function
1335 * @note This function must be called when the LPTIM instance is disabled.
1336 * @note The first trigger event will start the timer, any successive trigger
1337 * event will reset the counter and the timer will restart.
1338 * @note The timeout value corresponds to the compare value; if no trigger
1339 * occurs within the expected time frame, the MCU is waked-up by the
1340 * compare match event.
1341 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1342 * @param LPTIMx Low-Power Timer instance
1343 * @retval None
1344 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1345 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1346 {
1347 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1348 }
1349
1350 /**
1351 * @brief Disable the timeout function
1352 * @note This function must be called when the LPTIM instance is disabled.
1353 * @note A trigger event arriving when the timer is already started will be
1354 * ignored.
1355 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1356 * @param LPTIMx Low-Power Timer instance
1357 * @retval None
1358 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1359 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1360 {
1361 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1362 }
1363
1364 /**
1365 * @brief Indicate whether the timeout function is enabled.
1366 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1367 * @param LPTIMx Low-Power Timer instance
1368 * @retval State of bit (1 or 0).
1369 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1370 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1371 {
1372 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1373 }
1374
1375 /**
1376 * @brief Start the LPTIM counter
1377 * @note This function must be called when the LPTIM instance is disabled.
1378 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1379 * @param LPTIMx Low-Power Timer instance
1380 * @retval None
1381 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1382 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1383 {
1384 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1385 }
1386
1387 /**
1388 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1389 * @note This function must be called when the LPTIM instance is disabled.
1390 * @note An internal clock source must be present when a digital filter is
1391 * required for the trigger.
1392 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1393 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1394 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1395 * @param LPTIMx Low-Power Timer instance
1396 * @param Source This parameter can be one of the following values:
1397 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1398 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1399 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1400 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1401 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1402 @if STM32H503xx
1403 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
1404 @endif
1405 *
1406 * (*) Value not defined in all devices. \n
1407 *
1408 * @param Filter This parameter can be one of the following values:
1409 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1410 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1411 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1412 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1413 * @param Polarity This parameter can be one of the following values:
1414 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1415 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1416 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1417 * @retval None
1418 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1419 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1420 {
1421 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1422 }
1423
1424 /**
1425 * @brief Get actual external trigger source.
1426 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1427 * @param LPTIMx Low-Power Timer instance
1428 * @retval Returned value can be one of the following values:
1429 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1430 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1431 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1432 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1433 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1434 @if STM32H503xx
1435 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
1436 @endif
1437 *
1438 * (*) Value not defined in all devices. \n
1439 *
1440 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1441 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1442 {
1443 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1444 }
1445
1446 /**
1447 * @brief Get actual external trigger filter.
1448 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1449 * @param LPTIMx Low-Power Timer instance
1450 * @retval Returned value can be one of the following values:
1451 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1452 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1453 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1454 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1455 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1456 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1457 {
1458 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1459 }
1460
1461 /**
1462 * @brief Get actual external trigger polarity.
1463 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1464 * @param LPTIMx Low-Power Timer instance
1465 * @retval Returned value can be one of the following values:
1466 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1467 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1468 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1469 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1470 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1471 {
1472 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1473 }
1474
1475 /**
1476 * @}
1477 */
1478
1479 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1480 * @{
1481 */
1482
1483 /**
1484 * @brief Set the source of the clock used by the LPTIM instance.
1485 * @note This function must be called when the LPTIM instance is disabled.
1486 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1487 * @param LPTIMx Low-Power Timer instance
1488 * @param ClockSource This parameter can be one of the following values:
1489 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1490 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1491 * @retval None
1492 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1493 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1494 {
1495 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1496 }
1497
1498 /**
1499 * @brief Get actual LPTIM instance clock source.
1500 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1501 * @param LPTIMx Low-Power Timer instance
1502 * @retval Returned value can be one of the following values:
1503 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1504 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1505 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1506 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1507 {
1508 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1509 }
1510
1511 /**
1512 * @brief Configure the active edge or edges used by the counter when
1513 the LPTIM is clocked by an external clock source.
1514 * @note This function must be called when the LPTIM instance is disabled.
1515 * @note When both external clock signal edges are considered active ones,
1516 * the LPTIM must also be clocked by an internal clock source with a
1517 * frequency equal to at least four times the external clock frequency.
1518 * @note An internal clock source must be present when a digital filter is
1519 * required for external clock.
1520 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1521 * CFGR CKPOL LL_LPTIM_ConfigClock
1522 * @param LPTIMx Low-Power Timer instance
1523 * @param ClockFilter This parameter can be one of the following values:
1524 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1525 * @arg @ref LL_LPTIM_CLK_FILTER_2
1526 * @arg @ref LL_LPTIM_CLK_FILTER_4
1527 * @arg @ref LL_LPTIM_CLK_FILTER_8
1528 * @param ClockPolarity This parameter can be one of the following values:
1529 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1530 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1531 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1532 * @retval None
1533 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1534 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1535 {
1536 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1537 }
1538
1539 /**
1540 * @brief Get actual clock polarity
1541 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1542 * @param LPTIMx Low-Power Timer instance
1543 * @retval Returned value can be one of the following values:
1544 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1545 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1546 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1547 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1548 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1549 {
1550 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1551 }
1552
1553 /**
1554 * @brief Get actual clock digital filter
1555 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1556 * @param LPTIMx Low-Power Timer instance
1557 * @retval Returned value can be one of the following values:
1558 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1559 * @arg @ref LL_LPTIM_CLK_FILTER_2
1560 * @arg @ref LL_LPTIM_CLK_FILTER_4
1561 * @arg @ref LL_LPTIM_CLK_FILTER_8
1562 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1563 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1564 {
1565 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1566 }
1567
1568 /**
1569 * @}
1570 */
1571
1572 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1573 * @{
1574 */
1575
1576 /**
1577 * @brief Configure the encoder mode.
1578 * @note This function must be called when the LPTIM instance is disabled.
1579 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1580 * @param LPTIMx Low-Power Timer instance
1581 * @param EncoderMode This parameter can be one of the following values:
1582 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1583 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1584 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1585 * @retval None
1586 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1587 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1588 {
1589 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1590 }
1591
1592 /**
1593 * @brief Get actual encoder mode.
1594 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1595 * @param LPTIMx Low-Power Timer instance
1596 * @retval Returned value can be one of the following values:
1597 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1598 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1599 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1600 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1601 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1602 {
1603 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1604 }
1605
1606 /**
1607 * @brief Enable the encoder mode
1608 * @note This function must be called when the LPTIM instance is disabled.
1609 * @note In this mode the LPTIM instance must be clocked by an internal clock
1610 * source. Also, the prescaler division ratio must be equal to 1.
1611 * @note LPTIM instance must be configured in continuous mode prior enabling
1612 * the encoder mode.
1613 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1614 * @param LPTIMx Low-Power Timer instance
1615 * @retval None
1616 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1617 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1618 {
1619 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1620 }
1621
1622 /**
1623 * @brief Disable the encoder mode
1624 * @note This function must be called when the LPTIM instance is disabled.
1625 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1626 * @param LPTIMx Low-Power Timer instance
1627 * @retval None
1628 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1629 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1630 {
1631 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1632 }
1633
1634 /**
1635 * @brief Indicates whether the LPTIM operates in encoder mode.
1636 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1637 * @param LPTIMx Low-Power Timer instance
1638 * @retval State of bit (1 or 0).
1639 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1640 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1641 {
1642 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1643 }
1644
1645 /**
1646 * @}
1647 */
1648
1649 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1650 * @{
1651 */
1652
1653 /**
1654 * @brief Clear the compare match flag for channel 1 (CC1CF)
1655 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1656 * @param LPTIMx Low-Power Timer instance
1657 * @retval None
1658 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1659 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1660 {
1661 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1662 }
1663
1664 /**
1665 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1666 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1667 * @param LPTIMx Low-Power Timer instance
1668 * @retval State of bit (1 or 0).
1669 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1670 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1671 {
1672 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1673 }
1674
1675 /**
1676 * @brief Clear the compare match flag for channel 2 (CC2CF)
1677 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1678 * @param LPTIMx Low-Power Timer instance
1679 * @retval None
1680 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1681 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1682 {
1683 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1684 }
1685
1686 /**
1687 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1688 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1689 * @param LPTIMx Low-Power Timer instance
1690 * @retval State of bit (1 or 0).
1691 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1692 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1693 {
1694 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1695 }
1696
1697 /**
1698 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1699 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1700 * @param LPTIMx Low-Power Timer instance
1701 * @retval None
1702 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1703 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1704 {
1705 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1706 }
1707
1708 /**
1709 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1710 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1711 * @param LPTIMx Low-Power Timer instance
1712 * @retval State of bit (1 or 0).
1713 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1714 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1715 {
1716 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1717 }
1718
1719 /**
1720 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1721 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1722 * @param LPTIMx Low-Power Timer instance
1723 * @retval None
1724 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1725 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1726 {
1727 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1728 }
1729
1730 /**
1731 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1732 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1733 * @param LPTIMx Low-Power Timer instance
1734 * @retval State of bit (1 or 0).
1735 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1736 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1737 {
1738 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1739 }
1740 /**
1741 * @brief Clear the autoreload match flag (ARRMCF)
1742 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1743 * @param LPTIMx Low-Power Timer instance
1744 * @retval None
1745 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1746 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1747 {
1748 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1749 }
1750
1751 /**
1752 * @brief Inform application whether a autoreload match interrupt has occurred.
1753 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1754 * @param LPTIMx Low-Power Timer instance
1755 * @retval State of bit (1 or 0).
1756 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1757 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1758 {
1759 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1760 }
1761
1762 /**
1763 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1764 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1765 * @param LPTIMx Low-Power Timer instance
1766 * @retval None
1767 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1768 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1769 {
1770 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1771 }
1772
1773 /**
1774 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1775 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1776 * @param LPTIMx Low-Power Timer instance
1777 * @retval State of bit (1 or 0).
1778 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1779 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1780 {
1781 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1782 }
1783
1784 /**
1785 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
1786 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
1787 * @param LPTIMx Low-Power Timer instance
1788 * @retval None
1789 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)1790 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
1791 {
1792 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
1793 }
1794
1795 /**
1796 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
1797 completed. If so, a new one can be initiated.
1798 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
1799 * @param LPTIMx Low-Power Timer instance
1800 * @retval State of bit (1 or 0).
1801 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)1802 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
1803 {
1804 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
1805 }
1806
1807 /**
1808 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
1809 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
1810 * @param LPTIMx Low-Power Timer instance
1811 * @retval None
1812 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)1813 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
1814 {
1815 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
1816 }
1817
1818 /**
1819 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
1820 completed. If so, a new one can be initiated.
1821 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
1822 * @param LPTIMx Low-Power Timer instance
1823 * @retval State of bit (1 or 0).
1824 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)1825 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
1826 {
1827 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
1828 }
1829
1830 /**
1831 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
1832 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
1833 * @param LPTIMx Low-Power Timer instance
1834 * @retval None
1835 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)1836 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
1837 {
1838 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
1839 }
1840
1841 /**
1842 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
1843 completed. If so, a new one can be initiated.
1844 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
1845 * @param LPTIMx Low-Power Timer instance
1846 * @retval State of bit (1 or 0).
1847 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)1848 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
1849 {
1850 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
1851 }
1852
1853 /**
1854 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1855 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1856 * @param LPTIMx Low-Power Timer instance
1857 * @retval None
1858 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1859 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1860 {
1861 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1862 }
1863
1864 /**
1865 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1866 completed. If so, a new one can be initiated.
1867 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1868 * @param LPTIMx Low-Power Timer instance
1869 * @retval State of bit (1 or 0).
1870 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1871 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1872 {
1873 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1874 }
1875
1876 /**
1877 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1878 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1879 * @param LPTIMx Low-Power Timer instance
1880 * @retval None
1881 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1882 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1883 {
1884 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1885 }
1886
1887 /**
1888 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1889 operates in encoder mode).
1890 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1891 * @param LPTIMx Low-Power Timer instance
1892 * @retval State of bit (1 or 0).
1893 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1894 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1895 {
1896 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1897 }
1898
1899 /**
1900 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1901 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1902 * @param LPTIMx Low-Power Timer instance
1903 * @retval None
1904 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1905 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1906 {
1907 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1908 }
1909
1910 /**
1911 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1912 operates in encoder mode).
1913 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1914 * @param LPTIMx Low-Power Timer instance
1915 * @retval State of bit (1 or 0).
1916 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1917 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1918 {
1919 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1920 }
1921
1922 /**
1923 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1924 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1925 * @param LPTIMx Low-Power Timer instance
1926 * @retval None
1927 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1928 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1929 {
1930 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1931 }
1932
1933 /**
1934 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1935 completed; If so, a new one can be initiated.
1936 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1937 * @param LPTIMx Low-Power Timer instance
1938 * @retval State of bit (1 or 0).
1939 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1940 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1941 {
1942 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1943 }
1944
1945 /**
1946 * @brief Clear the update event flag (UECF).
1947 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1948 * @param LPTIMx Low-Power Timer instance
1949 * @retval None
1950 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1951 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1952 {
1953 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1954 }
1955
1956 /**
1957 * @brief Informs application whether the LPTIMx update event has occurred.
1958 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1959 * @param LPTIMx Low-Power Timer instance
1960 * @retval State of bit (1 or 0).
1961 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1962 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1963 {
1964 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1965 }
1966
1967 /**
1968 * @}
1969 */
1970
1971 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1972 * @{
1973 */
1974 /**
1975 * @brief Enable capture/compare 1 interrupt (CC1IE).
1976 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
1977 * @param LPTIMx Low-Power Timer instance
1978 * @retval None
1979 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)1980 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
1981 {
1982 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1983 }
1984
1985 /**
1986 * @brief Disable capture/compare 1 interrupt (CC1IE).
1987 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
1988 * @param LPTIMx Low-Power Timer instance
1989 * @retval None
1990 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)1991 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
1992 {
1993 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1994 }
1995
1996 /**
1997 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
1998 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
1999 * @param LPTIMx Low-Power Timer instance
2000 * @retval State of bit (1 or 0).
2001 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)2002 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
2003 {
2004 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
2005 }
2006
2007 /**
2008 * @brief Enable capture/compare 1 interrupt (CC2IE).
2009 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
2010 * @param LPTIMx Low-Power Timer instance
2011 * @retval None
2012 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)2013 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
2014 {
2015 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
2016 }
2017
2018 /**
2019 * @brief Disable capture/compare 2 interrupt (CC2IE).
2020 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
2021 * @param LPTIMx Low-Power Timer instance
2022 * @retval None
2023 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)2024 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
2025 {
2026 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
2027 }
2028
2029 /**
2030 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
2031 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
2032 * @param LPTIMx Low-Power Timer instance
2033 * @retval State of bit (1 or 0).
2034 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)2035 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
2036 {
2037 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
2038 }
2039
2040 /**
2041 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
2042 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
2043 * @param LPTIMx Low-Power Timer instance
2044 * @retval None
2045 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)2046 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
2047 {
2048 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
2049 }
2050
2051 /**
2052 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
2053 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
2054 * @param LPTIMx Low-Power Timer instance
2055 * @retval None
2056 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)2057 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
2058 {
2059 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
2060 }
2061
2062 /**
2063 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
2064 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
2065 * @param LPTIMx Low-Power Timer instance
2066 * @retval State of bit (1 or 0).
2067 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)2068 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
2069 {
2070 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
2071 }
2072
2073 /**
2074 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
2075 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
2076 * @param LPTIMx Low-Power Timer instance
2077 * @retval None
2078 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)2079 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2080 {
2081 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2082 }
2083
2084 /**
2085 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
2086 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
2087 * @param LPTIMx Low-Power Timer instance
2088 * @retval None
2089 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)2090 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2091 {
2092 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2093 }
2094
2095 /**
2096 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
2097 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
2098 * @param LPTIMx Low-Power Timer instance
2099 * @retval State of bit (1 or 0).
2100 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)2101 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
2102 {
2103 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2104 }
2105
2106 /**
2107 * @brief Enable autoreload match interrupt (ARRMIE).
2108 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2109 * @param LPTIMx Low-Power Timer instance
2110 * @retval None
2111 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2112 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2113 {
2114 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2115 }
2116
2117 /**
2118 * @brief Disable autoreload match interrupt (ARRMIE).
2119 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2120 * @param LPTIMx Low-Power Timer instance
2121 * @retval None
2122 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2123 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2124 {
2125 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2126 }
2127
2128 /**
2129 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2130 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2131 * @param LPTIMx Low-Power Timer instance
2132 * @retval State of bit (1 or 0).
2133 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2134 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2135 {
2136 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2137 }
2138
2139 /**
2140 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2141 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2142 * @param LPTIMx Low-Power Timer instance
2143 * @retval None
2144 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2145 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2146 {
2147 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2148 }
2149
2150 /**
2151 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2152 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2153 * @param LPTIMx Low-Power Timer instance
2154 * @retval None
2155 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2156 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2157 {
2158 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2159 }
2160
2161 /**
2162 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2163 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2164 * @param LPTIMx Low-Power Timer instance
2165 * @retval State of bit (1 or 0).
2166 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2167 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2168 {
2169 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2170 }
2171
2172 /**
2173 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2174 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2175 * @param LPTIMx Low-Power Timer instance
2176 * @retval None
2177 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2178 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2179 {
2180 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2181 }
2182
2183 /**
2184 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2185 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2186 * @param LPTIMx Low-Power Timer instance
2187 * @retval None
2188 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2189 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2190 {
2191 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2192 }
2193
2194 /**
2195 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2196 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2197 * @param LPTIMx Low-Power Timer instance
2198 * @retval State of bit (1 or 0).
2199 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2200 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2201 {
2202 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2203 }
2204
2205 /**
2206 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2207 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2208 * @param LPTIMx Low-Power Timer instance
2209 * @retval None
2210 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2211 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2212 {
2213 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2214 }
2215
2216 /**
2217 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2218 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2219 * @param LPTIMx Low-Power Timer instance
2220 * @retval None
2221 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2222 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2223 {
2224 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2225 }
2226
2227 /**
2228 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2229 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2230 * @param LPTIMx Low-Power Timer instance
2231 * @retval State of bit (1 or 0).
2232 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2233 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2234 {
2235 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2236 }
2237
2238 /**
2239 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2240 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2241 * @param LPTIMx Low-Power Timer instance
2242 * @retval None
2243 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2244 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2245 {
2246 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2247 }
2248
2249 /**
2250 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2251 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2252 * @param LPTIMx Low-Power Timer instance
2253 * @retval None
2254 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2255 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2256 {
2257 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2258 }
2259
2260 /**
2261 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2262 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2263 * @param LPTIMx Low-Power Timer instance
2264 * @retval State of bit(1 or 0).
2265 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2266 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2267 {
2268 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2269 }
2270
2271 /**
2272 * @brief Enable direction change to up interrupt (UPIE).
2273 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2274 * @param LPTIMx Low-Power Timer instance
2275 * @retval None
2276 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2277 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2278 {
2279 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2280 }
2281
2282 /**
2283 * @brief Disable direction change to up interrupt (UPIE).
2284 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2285 * @param LPTIMx Low-Power Timer instance
2286 * @retval None
2287 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2288 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2289 {
2290 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2291 }
2292
2293 /**
2294 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2295 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2296 * @param LPTIMx Low-Power Timer instance
2297 * @retval State of bit(1 or 0).
2298 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2299 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2300 {
2301 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2302 }
2303
2304 /**
2305 * @brief Enable direction change to down interrupt (DOWNIE).
2306 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2307 * @param LPTIMx Low-Power Timer instance
2308 * @retval None
2309 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2310 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2311 {
2312 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2313 }
2314
2315 /**
2316 * @brief Disable direction change to down interrupt (DOWNIE).
2317 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2318 * @param LPTIMx Low-Power Timer instance
2319 * @retval None
2320 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2321 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2322 {
2323 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2324 }
2325
2326 /**
2327 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2328 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2329 * @param LPTIMx Low-Power Timer instance
2330 * @retval State of bit(1 or 0).
2331 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2332 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2333 {
2334 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2335 }
2336
2337 /**
2338 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2339 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2340 * @param LPTIMx Low-Power Timer instance
2341 * @retval None
2342 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2343 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2344 {
2345 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2346 }
2347
2348 /**
2349 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2350 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2351 * @param LPTIMx Low-Power Timer instance
2352 * @retval None
2353 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2354 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2355 {
2356 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2357 }
2358
2359 /**
2360 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2361 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2362 * @param LPTIMx Low-Power Timer instance
2363 * @retval State of bit(1 or 0).
2364 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2365 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2366 {
2367 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2368 }
2369
2370 /**
2371 * @brief Enable update event interrupt (UEIE).
2372 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2373 * @param LPTIMx Low-Power Timer instance
2374 * @retval None
2375 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2376 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2377 {
2378 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2379 }
2380
2381 /**
2382 * @brief Disable update event interrupt (UEIE).
2383 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2384 * @param LPTIMx Low-Power Timer instance
2385 * @retval None
2386 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2387 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2388 {
2389 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2390 }
2391
2392 /**
2393 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2394 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2395 * @param LPTIMx Low-Power Timer instance
2396 *@ retval State of bit(1 or 0).
2397 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2398 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2399 {
2400 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2401 }
2402 /**
2403 * @}
2404 */
2405
2406
2407 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2408 * @{
2409 */
2410 /**
2411 * @brief Enable update DMA request.
2412 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2413 * @param LPTIMx Low-Power Timer instance
2414 * @retval None
2415 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2416 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2417 {
2418 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2419 }
2420
2421 /**
2422 * @brief Disable update DMA request.
2423 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2424 * @param LPTIMx Low-Power Timer instance
2425 * @retval None
2426 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2427 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2428 {
2429 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2430 }
2431
2432 /**
2433 * @brief Indicates whether the update DMA request is enabled.
2434 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2435 * @param LPTIMx Low-Power Timer instance
2436 * @retval State of bit (1 or 0).
2437 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2438 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2439 {
2440 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2441 }
2442
2443 /**
2444 * @brief Enable capture/compare 1 DMA request (CC1DE).
2445 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2446 * @param LPTIMx Low-Power Timer instance
2447 * @retval None
2448 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2449 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2450 {
2451 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2452 }
2453
2454 /**
2455 * @brief Disable capture/compare 1 DMA request (CC1DE).
2456 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2457 * @param LPTIMx Low-Power Timer instance
2458 * @retval None
2459 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2460 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2461 {
2462 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2463 }
2464
2465 /**
2466 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2467 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2468 * @param LPTIMx Low-Power Timer instance
2469 * @retval State of bit (1 or 0).
2470 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2471 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2472 {
2473 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2474 }
2475
2476 /**
2477 * @brief Enable capture/compare 2 DMA request (CC2DE).
2478 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2479 * @param LPTIMx Low-Power Timer instance
2480 * @retval None
2481 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2482 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2483 {
2484 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2485 }
2486
2487 /**
2488 * @brief Disable capture/compare 2 DMA request (CC2DE).
2489 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2490 * @param LPTIMx Low-Power Timer instance
2491 * @retval None
2492 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2493 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2494 {
2495 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2496 }
2497
2498 /**
2499 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2500 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2501 * @param LPTIMx Low-Power Timer instance
2502 * @retval State of bit (1 or 0).
2503 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)2504 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
2505 {
2506 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
2507 }
2508
2509 /**
2510 * @}
2511 */
2512 /**
2513 * @}
2514 */
2515
2516 /**
2517 * @}
2518 */
2519
2520 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 || LPTIM6 */
2521
2522 /**
2523 * @}
2524 */
2525
2526 #ifdef __cplusplus
2527 }
2528 #endif
2529
2530 #endif /* STM32H5xx_LL_LPTIM_H */
2531
