1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U0xx_LL_LPTIM_H
21 #define STM32U0xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45 static const uint8_t LL_LPTIM_OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* CCMR1: LPTIM_CH1 */
48 0x00U, /* CCMR1: LPTIM_CH2 */
49 0x04U, /* CCMR2: LPTIM_CH3 */
50 0x04U /* CCMR2: LPTIM_CH4 */
51 };
52
53 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
54 {
55 0U, /* CC1P */
56 16U, /* CC2P */
57 0U, /* CC3P */
58 16U /* CC4P */
59 };
60
61 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
62 {
63 0U, /* IC1F */
64 16U, /* IC2F */
65 0U, /* IC3F */
66 16U /* IC4F */
67 };
68
69 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
70 {
71 0U, /* IC1PSC */
72 16U, /* IC2PSC */
73 0U, /* IC3PSC */
74 16U /* IC4PSC */
75 };
76
77 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
78 {
79 0U, /* CC1SEL */
80 16U, /* CC2SEL */
81 0U, /* CC3SEL */
82 16U /* CC4SEL */
83 };
84
85 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
86 {
87 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
88 LPTIM_CCMR1_CC2E_Pos, /* CC2E */
89 LPTIM_CCMR2_CC3E_Pos, /* CC3E */
90 LPTIM_CCMR2_CC4E_Pos, /* CC4E */
91 };
92
93 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
94 {
95 {2, 7, 9, 13},
96 {3, 5, 6, 8},
97 {2, 3, 4, 5},
98 {2, 2, 3, 3},
99 {2, 2, 2, 2},
100 {2, 2, 2, 2},
101 {2, 2, 2, 2},
102 {2, 2, 2, 2}
103
104 };
105
106 /**
107 * @}
108 */
109
110 /* Private constants ---------------------------------------------------------*/
111
112 /* Private macros ------------------------------------------------------------*/
113 #if defined(USE_FULL_LL_DRIVER)
114 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
115 * @{
116 */
117 /**
118 * @}
119 */
120 #endif /*USE_FULL_LL_DRIVER*/
121
122 /* Exported types ------------------------------------------------------------*/
123 #if defined(USE_FULL_LL_DRIVER)
124 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
125 * @{
126 */
127
128 /**
129 * @brief LPTIM Init structure definition
130 */
131 typedef struct
132 {
133 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
134 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
135
136 This feature can be modified afterwards using unitary
137 function @ref LL_LPTIM_SetClockSource().*/
138
139 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
140 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
141
142 This feature can be modified afterwards using using unitary
143 function @ref LL_LPTIM_SetPrescaler().*/
144
145 uint32_t Waveform; /*!< Specifies the waveform shape.
146 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
147
148 This feature can be modified afterwards using unitary
149 function @ref LL_LPTIM_SetWaveform().*/
150 } LL_LPTIM_InitTypeDef;
151
152 /**
153 * @}
154 */
155 #endif /* USE_FULL_LL_DRIVER */
156
157 /* Exported constants --------------------------------------------------------*/
158 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
159 * @{
160 */
161
162 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
163 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
164 * @{
165 */
166 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
167 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
168 #define LL_LPTIM_ISR_CMP3OK LPTIM_ISR_CMP3OK /*!< Compare register 3 update OK */
169 #define LL_LPTIM_ISR_CMP4OK LPTIM_ISR_CMP4OK /*!< Compare register 4 update OK */
170 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
171 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
172 #define LL_LPTIM_ISR_CC3IF LPTIM_ISR_CC3IF /*!< Capture/Compare 3 interrupt flag */
173 #define LL_LPTIM_ISR_CC4IF LPTIM_ISR_CC4IF /*!< Capture/Compare 4 interrupt flag */
174 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
175 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
176 #define LL_LPTIM_ISR_CC3OF LPTIM_ISR_CC3OF /*!< Capture/Compare 3 over-capture flag */
177 #define LL_LPTIM_ISR_CC4OF LPTIM_ISR_CC4OF /*!< Capture/Compare 4 over-capture flag */
178 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
179 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
180 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
181 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
182 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
183 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
184 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
185 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
186 /**
187 * @}
188 */
189
190 /** @defgroup LPTIM_LL_EC_IT IT Defines
191 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
192 * @{
193 */
194 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
195 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
196 #define LL_LPTIM_DIER_CMP3OKIE LPTIM_DIER_CMP3OKIE /*!< Compare register 3 update OK */
197 #define LL_LPTIM_DIER_CMP4OKIE LPTIM_DIER_CMP4OKIE /*!< Compare register 4 update OK */
198 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
199 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
200 #define LL_LPTIM_DIER_CC3IFIE LPTIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt flag */
201 #define LL_LPTIM_DIER_CC4IFIE LPTIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt flag */
202 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
203 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
204 #define LL_LPTIM_DIER_CC3OFIE LPTIM_DIER_CC3OIE /*!< Capture/Compare 3 over-capture flag */
205 #define LL_LPTIM_DIER_CC4OFIE LPTIM_DIER_CC4OIE /*!< Capture/Compare 4 over-capture flag */
206 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
207 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
208 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
209 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
210 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
211 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
212 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
213 /**
214 * @}
215 */
216
217 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
218 * @{
219 */
220 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
221 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
222 /**
223 * @}
224 */
225
226 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
227 * @{
228 */
229 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
230 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
231 /**
232 * @}
233 */
234
235 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
236 * @{
237 */
238 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
239 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
240 /**
241 * @}
242 */
243
244 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
245 * @{
246 */
247 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
248 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
249 /**
250 * @}
251 */
252
253 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
254 * @{
255 */
256 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
257 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
258 /**
259 * @}
260 */
261
262 /** @defgroup TIM_LL_EC_CHANNEL Channel
263 * @{
264 */
265 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
266 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
267 #define LL_LPTIM_CHANNEL_CH3 0x00000002U /*!< LPTIM input/output channel 3 */
268 #define LL_LPTIM_CHANNEL_CH4 0x00000003U /*!< LPTIM input/output channel 4 */
269 /**
270 * @}
271 */
272
273 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
274 * @{
275 */
276 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
277 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
278 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
279 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
280 /**
281 * @}
282 */
283
284 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
285 * @{
286 */
287 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
288 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
289 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
290 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
291 /**
292 * @}
293 */
294
295 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
296 * @{
297 */
298 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
299 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
300 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
301 /**
302 * @}
303 */
304 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
305 * @{
306 */
307 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
308 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
309 /**
310 * @}
311 */
312
313 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
314 * @{
315 */
316 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
317 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
318 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
319 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
320 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
321 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
322 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
323 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
324 /**
325 * @}
326 */
327
328 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
329 * @{
330 */
331 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
332 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
333 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
334 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
335 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
336 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
337 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
338 #if defined(COMP2)
339 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
340 #endif /* COMP2 */
341 /**
342 * @}
343 */
344
345 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
346 * @{
347 */
348 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
349 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
350 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
351 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
352 /**
353 * @}
354 */
355
356 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
357 * @{
358 */
359 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
360 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
361 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
362 /**
363 * @}
364 */
365
366 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
367 * @{
368 */
369 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
370 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
371 /**
372 * @}
373 */
374
375 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
376 * @{
377 */
378 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
379 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
380 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
381 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
382 /**
383 * @}
384 */
385
386 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
387 * @{
388 */
389 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
390 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
391 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
392 /**
393 * @}
394 */
395
396 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
397 * @{
398 */
399 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
400 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
401 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
402 /**
403 * @}
404 */
405
406 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
407 * @{
408 */
409 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */
410 #define LL_LPTIM_INPUT1_SRC_COMP1 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */
411 #if defined(COMP2)
412 #define LL_LPTIM_INPUT1_SRC_COMP2 0x00000000UL /*!< For LPTIM2 */
413 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */
414 #endif /* COMP2 */
415 /**
416 * @}
417 */
418
419 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
420 * @{
421 */
422 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM3 */
423 #if defined(COMP2)
424 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM3 */
425 #endif /* COMP2 */
426 /**
427 * @}
428 */
429
430 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
431 * @{
432 */
433 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
434 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
435 #if defined(COMP2)
436 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
437 #endif /* COMP2 */
438 /**
439 * @}
440 */
441
442 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
443 * @{
444 */
445 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
446 #define LL_LPTIM_LPTIM1_IC2_RMP_MCO1 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to MCO1 */
447 #define LL_LPTIM_LPTIM1_IC2_RMP_MCO2 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to MCO2 */
448 /**
449 * @}
450 */
451
452 /** @defgroup LPTIM_EC_LPTIM1_IC3_RMP LPTIM1 Input Ch3 Remap
453 * @{
454 */
455 #define LL_LPTIM_LPTIM1_IC3_RMP_GPIO 0x00000000UL /*!< IC3 connected to GPIO */
456 #define LL_LPTIM_LPTIM1_IC3_RMP_COMP1 LPTIM_CFGR2_IC3SEL_0 /*!< IC3 connected to COMP1 */
457 #if defined(COMP2)
458 #define LL_LPTIM_LPTIM1_IC3_RMP_COMP2 LPTIM_CFGR2_IC3SEL_1 /*!< IC3 connected to COMP2 */
459 #endif /* COMP2 */
460 /**
461 * @}
462 */
463
464 /** @defgroup LPTIM_EC_LPTIM1_IC4_RMP LPTIM1 Input Ch4 Remap
465 * @{
466 */
467 #define LL_LPTIM_LPTIM1_IC4_RMP_GPIO 0x00000000UL /*!< IC4 connected to GPIO */
468 #define LL_LPTIM_LPTIM1_IC4_RMP_COMP1 LPTIM_CFGR2_IC4SEL_0 /*!< IC4 connected to COMP1 */
469 #if defined(COMP2)
470 #define LL_LPTIM_LPTIM1_IC4_RMP_COMP2 LPTIM_CFGR2_IC4SEL_1 /*!< IC4 connected to COMP2 */
471 #endif /* COMP2 */
472 /**
473 * @}
474 */
475
476 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
477 * @{
478 */
479 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
480 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
481 #if defined(COMP2)
482 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
483 #endif /* COMP2 */
484 /**
485 * @}
486 */
487
488 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
489 * @{
490 */
491 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
492 #define LL_LPTIM_LPTIM2_IC2_RMP_MCO1 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to MCO1 */
493 #define LL_LPTIM_LPTIM2_IC2_RMP_MCO2 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to MCO2 */
494 /**
495 * @}
496 */
497
498 #if defined(LPTIM3)
499 /** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
500 * @{
501 */
502 #define LL_LPTIM_LPTIM3_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
503 #define LL_LPTIM_LPTIM3_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
504 #define LL_LPTIM_LPTIM3_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
505 /**
506 * @}
507 */
508
509 /** @defgroup LPTIM_EC_LPTIM3_IC2_RMP LPTIM3 Input Ch2 Remap
510 * @{
511 */
512 #define LL_LPTIM_LPTIM3_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
513 #define LL_LPTIM_LPTIM3_IC2_RMP_MCO1 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to MCO1 */
514 #define LL_LPTIM_LPTIM3_IC2_RMP_MCO2 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to MCO2 */
515 /**
516 * @}
517 */
518
519 /** @defgroup LPTIM_EC_LPTIM3_IC3_RMP LPTIM3 Input Ch3 Remap
520 * @{
521 */
522 #define LL_LPTIM_LPTIM3_IC3_RMP_GPIO 0x00000000UL /*!< IC3 connected to GPIO */
523 #define LL_LPTIM_LPTIM3_IC3_RMP_COMP1 LPTIM_CFGR2_IC3SEL_0 /*!< IC3 connected to COMP1 */
524 #define LL_LPTIM_LPTIM3_IC3_RMP_COMP2 LPTIM_CFGR2_IC3SEL_1 /*!< IC3 connected to COMP2 */
525 /**
526 * @}
527 */
528
529 /** @defgroup LPTIM_EC_LPTIM3_IC4_RMP LPTIM3 Input Ch4 Remap
530 * @{
531 */
532 #define LL_LPTIM_LPTIM3_IC4_RMP_GPIO 0x00000000UL /*!< IC4 connected to GPIO */
533 #define LL_LPTIM_LPTIM3_IC4_RMP_COMP1 LPTIM_CFGR2_IC4SEL_0 /*!< IC4 connected to COMP1 */
534 #define LL_LPTIM_LPTIM3_IC4_RMP_COMP2 LPTIM_CFGR2_IC4SEL_1 /*!< IC4 connected to COMP2 */
535 /**
536 * @}
537 */
538 #endif /*LPTIM3 */
539
540 /**
541 * @}
542 */
543
544 /* Exported macro ------------------------------------------------------------*/
545 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
546 * @{
547 */
548
549 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
550 * @{
551 */
552
553 /**
554 * @brief Write a value in LPTIM register
555 * @param __INSTANCE__ LPTIM Instance
556 * @param __REG__ Register to be written
557 * @param __VALUE__ Value to be written in the register
558 * @retval None
559 */
560 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
561
562 /**
563 * @brief Read a value in LPTIM register
564 * @param __INSTANCE__ LPTIM Instance
565 * @param __REG__ Register to be read
566 * @retval Register value
567 */
568 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
569
570 /**
571 * @brief LPTimer Input Capture Get Offset(in counter step unit)
572 * @note The real capture value corresponding to the input capture trigger can be calculated using
573 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
574 * The Offset value is depending on the glitch filter value for the channel
575 * and the value of the prescaler for the kernel clock.
576 * Please check Errata Sheet V1_8 for more details under "variable latency
577 * on input capture channel" section.
578 * @param __PSC__ This parameter can be one of the following values:
579 * @arg @ref LL_LPTIM_PRESCALER_DIV1
580 * @arg @ref LL_LPTIM_PRESCALER_DIV2
581 * @arg @ref LL_LPTIM_PRESCALER_DIV4
582 * @arg @ref LL_LPTIM_PRESCALER_DIV8
583 * @arg @ref LL_LPTIM_PRESCALER_DIV16
584 * @arg @ref LL_LPTIM_PRESCALER_DIV32
585 * @arg @ref LL_LPTIM_PRESCALER_DIV64
586 * @arg @ref LL_LPTIM_PRESCALER_DIV128
587 * @param __FLT__ This parameter can be one of the following values:
588 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
589 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
590 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
591 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
592 * @retval offset value
593 */
594 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
595 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
596 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
597 /**
598 * @}
599 */
600
601 /**
602 * @}
603 */
604
605 /* Exported functions --------------------------------------------------------*/
606 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
607 * @{
608 */
609
610 /** Legacy definitions for compatibility purpose
611 @cond 0
612 */
613 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
614 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
615 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
616 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
617 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
618 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
619 /**
620 @endcond
621 */
622
623 #if defined(USE_FULL_LL_DRIVER)
624 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
625 * @{
626 */
627
628 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
629 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
630 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
631 /**
632 * @}
633 */
634 #endif /* USE_FULL_LL_DRIVER */
635
636 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
637 * @{
638 */
639
640 /**
641 * @brief Enable the LPTIM instance
642 * @note After setting the ENABLE bit, a delay of two counter clock is needed
643 * before the LPTIM instance is actually enabled.
644 * @rmtoll CR ENABLE LL_LPTIM_Enable
645 * @param LPTIMx Low-Power Timer instance
646 * @retval None
647 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)648 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
649 {
650 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
651 }
652
653 /**
654 * @brief Disable the LPTIM instance
655 * @rmtoll CR ENABLE LL_LPTIM_Disable
656 * @param LPTIMx Low-Power Timer instance
657 * @retval None
658 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)659 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
660 {
661 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
662 }
663
664 /**
665 * @brief Indicates whether the LPTIM instance is enabled.
666 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
667 * @param LPTIMx Low-Power Timer instance
668 * @retval State of bit (1 or 0).
669 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)670 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
671 {
672 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
673 }
674
675 /**
676 * @brief Starts the LPTIM counter in the desired mode.
677 * @note LPTIM instance must be enabled before starting the counter.
678 * @note It is possible to change on the fly from One Shot mode to
679 * Continuous mode.
680 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
681 * CR SNGSTRT LL_LPTIM_StartCounter
682 * @param LPTIMx Low-Power Timer instance
683 * @param OperatingMode This parameter can be one of the following values:
684 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
685 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
686 * @retval None
687 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)688 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
689 {
690 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
691 }
692
693 /**
694 * @brief Enable reset after read.
695 * @note After calling this function any read access to LPTIM_CNT
696 * register will asynchronously reset the LPTIM_CNT register content.
697 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
698 * @param LPTIMx Low-Power Timer instance
699 * @retval None
700 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)701 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
702 {
703 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
704 }
705
706 /**
707 * @brief Disable reset after read.
708 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
709 * @param LPTIMx Low-Power Timer instance
710 * @retval None
711 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)712 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
713 {
714 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
715 }
716
717 /**
718 * @brief Indicate whether the reset after read feature is enabled.
719 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
720 * @param LPTIMx Low-Power Timer instance
721 * @retval State of bit (1 or 0).
722 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)723 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
724 {
725 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
726 }
727
728 /**
729 * @brief Reset of the LPTIM_CNT counter register (synchronous).
730 * @note Due to the synchronous nature of this reset, it only takes
731 * place after a synchronization delay of 3 LPTIM core clock cycles
732 * (LPTIM core clock may be different from APB clock).
733 * @note COUNTRST is automatically cleared by hardware
734 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
735 * @param LPTIMx Low-Power Timer instance
736 * @retval None
737 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)738 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
739 {
740 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
741 }
742
743 /**
744 * @brief Set the LPTIM registers update mode (enable/disable register preload)
745 * @note This function must be called when the LPTIM instance is disabled.
746 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
747 * @param LPTIMx Low-Power Timer instance
748 * @param UpdateMode This parameter can be one of the following values:
749 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
750 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
751 * @retval None
752 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)753 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
754 {
755 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
756 }
757
758 /**
759 * @brief Get the LPTIM registers update mode
760 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
761 * @param LPTIMx Low-Power Timer instance
762 * @retval Returned value can be one of the following values:
763 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
764 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
765 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)766 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
767 {
768 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
769 }
770
771 /**
772 * @brief Set the auto reload value
773 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
774 * @note After a write to the LPTIMx_ARR register a new write operation to the
775 * same register can only be performed when the previous write operation
776 * is completed. Any successive write before the ARROK flag is set, will
777 * lead to unpredictable results.
778 * @note autoreload value be strictly greater than the compare value.
779 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
780 * @param LPTIMx Low-Power Timer instance
781 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
782 * @retval None
783 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)784 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
785 {
786 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
787 }
788
789 /**
790 * @brief Get actual auto reload value
791 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
792 * @param LPTIMx Low-Power Timer instance
793 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
794 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)795 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
796 {
797 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
798 }
799
800 /**
801 * @brief Set the repetition value
802 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
803 * @rmtoll RCR REP LL_LPTIM_SetRepetition
804 * @param LPTIMx Low-Power Timer instance
805 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
806 * @retval None
807 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)808 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
809 {
810 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
811 }
812
813 /**
814 * @brief Get the repetition value
815 * @rmtoll RCR REP LL_LPTIM_GetRepetition
816 * @param LPTIMx Low-Power Timer instance
817 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
818 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)819 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
820 {
821 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
822 }
823
824 /**
825 * @brief Enable capture/compare channel.
826 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
827 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel\n
828 * CCMR2 CC3E LL_LPTIM_CC_EnableChannel\n
829 * CCMR2 CC4E LL_LPTIM_CC_EnableChannel
830 * @param LPTIMx LPTimer instance
831 * @param Channel This parameter can be one of the following values:
832 * @arg @ref LL_LPTIM_CHANNEL_CH1
833 * @arg @ref LL_LPTIM_CHANNEL_CH2
834 * @arg @ref LL_LPTIM_CHANNEL_CH3
835 * @arg @ref LL_LPTIM_CHANNEL_CH4
836 * @retval None
837 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)838 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
839 {
840 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
841 SET_BIT(*pReg, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
842 }
843
844 /**
845 * @brief Disable capture/compare channel.
846 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
847 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel\n
848 * CCMR2 CC3E LL_LPTIM_CC_DisableChannel\n
849 * CCMR2 CC4E LL_LPTIM_CC_DisableChannel
850 * @param LPTIMx LPTimer instance
851 * @param Channel This parameter can be one of the following values:
852 * @arg @ref LL_LPTIM_CHANNEL_CH1
853 * @arg @ref LL_LPTIM_CHANNEL_CH2
854 * @arg @ref LL_LPTIM_CHANNEL_CH3
855 * @arg @ref LL_LPTIM_CHANNEL_CH4
856 * @retval None
857 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)858 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
859 {
860 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
861 CLEAR_BIT(*pReg, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
862 }
863
864 /**
865 * @brief Indicate whether channel is enabled.
866 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
867 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel\n
868 * @rmtoll CCMR2 CC3E LL_LPTIM_CC_IsEnabledChannel\n
869 * CCMR2 CC4E LL_LPTIM_CC_IsEnabledChannel
870 * @param LPTIMx LPTimer instance
871 * @param Channel This parameter can be one of the following values:
872 * @arg @ref LL_LPTIM_CHANNEL_CH1
873 * @arg @ref LL_LPTIM_CHANNEL_CH2
874 * @arg @ref LL_LPTIM_CHANNEL_CH3
875 * @arg @ref LL_LPTIM_CHANNEL_CH4
876 * @retval State of bit (1 or 0).
877 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)878 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
879 {
880 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
881 return ((READ_BIT(*pReg, (uint32_t)LPTIM_CCMR1_CC1E_Pos << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
882 ((uint32_t)LPTIM_CCMR1_CC1E_Pos << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
883
884 }
885
886 /**
887 * @brief Set the compare value
888 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
889 * same register can only be performed when the previous write operation
890 * is completed. Any successive write before the CMP1OK flag is set, will
891 * lead to unpredictable results.
892 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
893 * @param LPTIMx Low-Power Timer instance
894 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
895 * @retval None
896 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)897 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
898 {
899 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
900 }
901
902 /**
903 * @brief Get actual compare value
904 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
905 * @param LPTIMx Low-Power Timer instance
906 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
907 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)908 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
909 {
910 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
911 }
912
913 /**
914 * @brief Set the compare value
915 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
916 * same register can only be performed when the previous write operation
917 * is completed. Any successive write before the CMP2OK flag is set, will
918 * lead to unpredictable results.
919 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
920 * @param LPTIMx Low-Power Timer instance
921 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
922 * @retval None
923 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)924 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
925 {
926 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
927 }
928
929 /**
930 * @brief Get actual compare value
931 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
932 * @param LPTIMx Low-Power Timer instance
933 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
934 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)935 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
936 {
937 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
938 }
939
940 /**
941 * @brief Set the compare value
942 * @note After a write to the LPTIMx_CCR3 register a new write operation to the
943 * same register can only be performed when the previous write operation
944 * is completed. Any successive write before the CMP3OK flag is set, will
945 * lead to unpredictable results.
946 * @rmtoll CCR3 CCR3 LL_LPTIM_OC_SetCompareCH3
947 * @param LPTIMx Low-Power Timer instance
948 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
949 * @retval None
950 */
LL_LPTIM_OC_SetCompareCH3(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)951 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH3(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
952 {
953 MODIFY_REG(LPTIMx->CCR3, LPTIM_CCR3_CCR3, CompareValue);
954 }
955
956 /**
957 * @brief Get actual compare value
958 * @rmtoll CCR3 CCR3 LL_LPTIM_OC_GetCompareCH3
959 * @param LPTIMx Low-Power Timer instance
960 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
961 */
LL_LPTIM_OC_GetCompareCH3(const LPTIM_TypeDef * LPTIMx)962 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH3(const LPTIM_TypeDef *LPTIMx)
963 {
964 return (uint32_t)(READ_BIT(LPTIMx->CCR3, LPTIM_CCR3_CCR3));
965 }
966
967 /**
968 * @brief Set the compare value
969 * @note After a write to the LPTIMx_CCR4 register a new write operation to the
970 * same register can only be performed when the previous write operation
971 * is completed. Any successive write before the CMP4OK flag is set, will
972 * lead to unpredictable results.
973 * @rmtoll CCR4 CCR4 LL_LPTIM_OC_SetCompareCH4
974 * @param LPTIMx Low-Power Timer instance
975 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
976 * @retval None
977 */
LL_LPTIM_OC_SetCompareCH4(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)978 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH4(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
979 {
980 MODIFY_REG(LPTIMx->CCR4, LPTIM_CCR4_CCR4, CompareValue);
981 }
982
983 /**
984 * @brief Get actual compare value
985 * @rmtoll CCR4 CCR4 LL_LPTIM_OC_GetCompareCH4
986 * @param LPTIMx Low-Power Timer instance
987 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
988 */
LL_LPTIM_OC_GetCompareCH4(const LPTIM_TypeDef * LPTIMx)989 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH4(const LPTIM_TypeDef *LPTIMx)
990 {
991 return (uint32_t)(READ_BIT(LPTIMx->CCR4, LPTIM_CCR4_CCR4));
992 }
993
994 /**
995 * @brief Get actual counter value
996 * @note When the LPTIM instance is running with an asynchronous clock, reading
997 * the LPTIMx_CNT register may return unreliable values. So in this case
998 * it is necessary to perform two consecutive read accesses and verify
999 * that the two returned values are identical.
1000 * @rmtoll CNT CNT LL_LPTIM_GetCounter
1001 * @param LPTIMx Low-Power Timer instance
1002 * @retval Counter value
1003 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)1004 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
1005 {
1006 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
1007 }
1008
1009 /**
1010 * @brief Set the counter mode (selection of the LPTIM counter clock source).
1011 * @note The counter mode can be set only when the LPTIM instance is disabled.
1012 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
1013 * @param LPTIMx Low-Power Timer instance
1014 * @param CounterMode This parameter can be one of the following values:
1015 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
1016 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
1017 * @retval None
1018 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)1019 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
1020 {
1021 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
1022 }
1023
1024 /**
1025 * @brief Get the counter mode
1026 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
1027 * @param LPTIMx Low-Power Timer instance
1028 * @retval Returned value can be one of the following values:
1029 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
1030 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
1031 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)1032 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
1033 {
1034 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
1035 }
1036
1037 /**
1038 * @brief Set waveform shape
1039 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
1040 * @param LPTIMx Low-Power Timer instance
1041 * @param Waveform This parameter can be one of the following values:
1042 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
1043 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
1044 * @retval None
1045 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)1046 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
1047 {
1048 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
1049 }
1050
1051 /**
1052 * @brief Get actual waveform shape
1053 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
1054 * @param LPTIMx Low-Power Timer instance
1055 * @retval Returned value can be one of the following values:
1056 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
1057 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
1058 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)1059 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
1060 {
1061 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
1062 }
1063
1064 /**
1065 * @brief Set the polarity of an output channel.
1066 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
1067 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
1068 * @rmtoll CCMR2 CC3P LL_LPTIM_OC_SetPolarity\n
1069 * @rmtoll CCMR2 CC4P LL_LPTIM_OC_SetPolarity
1070 * @param LPTIMx Low-Power Timer instance
1071 * @param Channel This parameter can be one of the following values:
1072 * @arg @ref LL_LPTIM_CHANNEL_CH1
1073 * @arg @ref LL_LPTIM_CHANNEL_CH2
1074 * @arg @ref LL_LPTIM_CHANNEL_CH3
1075 * @arg @ref LL_LPTIM_CHANNEL_CH4
1076 * @param Polarity This parameter can be one of the following values:
1077 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
1078 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
1079 * @retval None
1080 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1081 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1082 {
1083 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1084 MODIFY_REG(*pReg, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
1085 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
1086 }
1087
1088 /**
1089 * @brief Get the polarity of an output channel.
1090 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
1091 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
1092 * @rmtoll CCMR2 CC3P LL_LPTIM_OC_GetPolarity\n
1093 * @rmtoll CCMR2 CC4P LL_LPTIM_OC_GetPolarity
1094 * @param LPTIMx Low-Power Timer instance
1095 * @param Channel This parameter can be one of the following values:
1096 * @arg @ref LL_LPTIM_CHANNEL_CH1
1097 * @arg @ref LL_LPTIM_CHANNEL_CH2
1098 * @arg @ref LL_LPTIM_CHANNEL_CH3
1099 * @arg @ref LL_LPTIM_CHANNEL_CH4
1100 * @retval Returned value can be one of the following values:
1101 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
1102 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
1103 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1104 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1105 {
1106 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1107 return (READ_BIT(*pReg, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1108 }
1109
1110 /**
1111 * @brief Set actual prescaler division ratio.
1112 * @note This function must be called when the LPTIM instance is disabled.
1113 * @note When the LPTIM is configured to be clocked by an internal clock source
1114 * and the LPTIM counter is configured to be updated by active edges
1115 * detected on the LPTIM external Input1, the internal clock provided to
1116 * the LPTIM must be not be prescaled.
1117 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
1118 * @param LPTIMx Low-Power Timer instance
1119 * @param Prescaler This parameter can be one of the following values:
1120 * @arg @ref LL_LPTIM_PRESCALER_DIV1
1121 * @arg @ref LL_LPTIM_PRESCALER_DIV2
1122 * @arg @ref LL_LPTIM_PRESCALER_DIV4
1123 * @arg @ref LL_LPTIM_PRESCALER_DIV8
1124 * @arg @ref LL_LPTIM_PRESCALER_DIV16
1125 * @arg @ref LL_LPTIM_PRESCALER_DIV32
1126 * @arg @ref LL_LPTIM_PRESCALER_DIV64
1127 * @arg @ref LL_LPTIM_PRESCALER_DIV128
1128 * @retval None
1129 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)1130 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
1131 {
1132 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
1133 }
1134
1135 /**
1136 * @brief Get actual prescaler division ratio.
1137 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
1138 * @param LPTIMx Low-Power Timer instance
1139 * @retval Returned value can be one of the following values:
1140 * @arg @ref LL_LPTIM_PRESCALER_DIV1
1141 * @arg @ref LL_LPTIM_PRESCALER_DIV2
1142 * @arg @ref LL_LPTIM_PRESCALER_DIV4
1143 * @arg @ref LL_LPTIM_PRESCALER_DIV8
1144 * @arg @ref LL_LPTIM_PRESCALER_DIV16
1145 * @arg @ref LL_LPTIM_PRESCALER_DIV32
1146 * @arg @ref LL_LPTIM_PRESCALER_DIV64
1147 * @arg @ref LL_LPTIM_PRESCALER_DIV128
1148 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)1149 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
1150 {
1151 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
1152 }
1153
1154 /**
1155 * @brief Set LPTIM input 1 source (default GPIO).
1156 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
1157 * @param LPTIMx Low-Power Timer instance
1158 * @param Src This parameter can be one of the following values:
1159 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
1160 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
1161 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2 (*)
1162 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (*)
1163 * (*) Value not defined for all devices
1164 * @retval None
1165 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1166 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1167 {
1168 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
1169 }
1170
1171 /**
1172 * @brief Set LPTIM input 2 source (default GPIO).
1173 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
1174 * @param LPTIMx Low-Power Timer instance
1175 * @param Src This parameter can be one of the following values:
1176 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1177 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2 (*)
1178 * (*) Value not defined for all devices
1179 * @retval None
1180 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1181 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1182 {
1183 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1184 }
1185
1186 /**
1187 * @brief Set LPTIM input source (default GPIO).
1188 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap\n
1189 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap\n
1190 * @rmtoll CFGR2 IC3SEL LL_LPTIM_SetRemap\n
1191 * @rmtoll CFGR2 IC4SEL LL_LPTIM_SetRemap
1192 * @param LPTIMx Low-Power Timer instance
1193 * @param Src This parameter can be one of the following values:
1194 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1195 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1
1196 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP2 (*)
1197 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1198 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_MCO1
1199 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_MCO2
1200 * @arg @ref LL_LPTIM_LPTIM1_IC3_RMP_GPIO
1201 * @arg @ref LL_LPTIM_LPTIM1_IC3_RMP_COMP1
1202 * @arg @ref LL_LPTIM_LPTIM1_IC3_RMP_COMP2 (*)
1203 * @arg @ref LL_LPTIM_LPTIM1_IC4_RMP_GPIO
1204 * @arg @ref LL_LPTIM_LPTIM1_IC4_RMP_COMP1
1205 * @arg @ref LL_LPTIM_LPTIM1_IC4_RMP_COMP2 (*)
1206 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1207 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1
1208 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2 (*)
1209 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1210 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MCO1
1211 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MCO2
1212 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO (*)
1213 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP1 (*)
1214 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP2 (*)
1215 * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_GPIO (*)
1216 * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_MCO1 (*)
1217 * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_MCO2 (*)
1218 * @arg @ref LL_LPTIM_LPTIM3_IC3_RMP_GPIO (*)
1219 * @arg @ref LL_LPTIM_LPTIM3_IC3_RMP_COMP1 (*)
1220 * @arg @ref LL_LPTIM_LPTIM3_IC3_RMP_COMP2 (*)
1221 * @arg @ref LL_LPTIM_LPTIM3_IC4_RMP_GPIO (*)
1222 * @arg @ref LL_LPTIM_LPTIM3_IC4_RMP_COMP1 (*)
1223 * @arg @ref LL_LPTIM_LPTIM3_IC4_RMP_COMP2 (*)
1224 *
1225 * (*) Value not defined in all devices. \n
1226 *
1227 * @retval None
1228 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1229 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1230 {
1231 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL | LPTIM_CFGR2_IC3SEL | LPTIM_CFGR2_IC4SEL, Src);
1232 }
1233
1234 /**
1235 * @brief Set the polarity of IC channel 1.
1236 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1237 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1238 * @rmtoll CCMR2 CC3P LL_LPTIM_IC_SetPolarity\n
1239 * @rmtoll CCMR2 CC4P LL_LPTIM_IC_SetPolarity
1240 * @param LPTIMx Low-Power Timer instance
1241 * @param Channel This parameter can be one of the following values:
1242 * @arg @ref LL_LPTIM_CHANNEL_CH1
1243 * @arg @ref LL_LPTIM_CHANNEL_CH2
1244 * @arg @ref LL_LPTIM_CHANNEL_CH3
1245 * @arg @ref LL_LPTIM_CHANNEL_CH4
1246 * @param Polarity This parameter can be one of the following values:
1247 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1248 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1249 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1250 * @retval None
1251 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1252 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1253 {
1254 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1255 MODIFY_REG(*pReg, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel], Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1256 }
1257
1258 /**
1259 * @brief Get the polarity of IC channels.
1260 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1261 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1262 * @rmtoll CCMR2 CC3P LL_LPTIM_IC_GetPolarity\n
1263 * @rmtoll CCMR2 CC4P LL_LPTIM_IC_GetPolarity
1264 * @param LPTIMx Low-Power Timer instance
1265 * @param Channel This parameter can be one of the following values:
1266 * @arg @ref LL_LPTIM_CHANNEL_CH1
1267 * @arg @ref LL_LPTIM_CHANNEL_CH2
1268 * @arg @ref LL_LPTIM_CHANNEL_CH3
1269 * @arg @ref LL_LPTIM_CHANNEL_CH4
1270 * @retval Returned value can be one of the following values:
1271 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1272 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1273 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1274 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1275 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1276 {
1277 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1278 return (uint32_t)((READ_BIT(*pReg, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1279 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1280
1281 }
1282
1283 /**
1284 * @brief Set the filter of IC channels.
1285 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1286 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1287 * @rmtoll CCMR2 IC3F LL_LPTIM_IC_SetFilter\n
1288 * @rmtoll CCMR2 IC4F LL_LPTIM_IC_SetFilter
1289 * @param LPTIMx Low-Power Timer instance
1290 * @param Channel This parameter can be one of the following values:
1291 * @arg @ref LL_LPTIM_CHANNEL_CH1
1292 * @arg @ref LL_LPTIM_CHANNEL_CH2
1293 * @arg @ref LL_LPTIM_CHANNEL_CH3
1294 * @arg @ref LL_LPTIM_CHANNEL_CH4
1295 * @param Filter This parameter can be one of the following values:
1296 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1297 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1298 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1299 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1300 * @retval None
1301 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1302 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1303 {
1304 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1305 MODIFY_REG(*pReg, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel], Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1306 }
1307
1308 /**
1309 * @brief Get the filter of IC channels.
1310 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1311 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1312 * @rmtoll CCMR2 IC3F LL_LPTIM_IC_GetFilter\n
1313 * @rmtoll CCMR2 IC4F LL_LPTIM_IC_GetFilter
1314 * @param LPTIMx Low-Power Timer instance
1315 * @param Channel This parameter can be one of the following values:
1316 * @arg @ref LL_LPTIM_CHANNEL_CH1
1317 * @arg @ref LL_LPTIM_CHANNEL_CH2
1318 * @arg @ref LL_LPTIM_CHANNEL_CH3
1319 * @arg @ref LL_LPTIM_CHANNEL_CH4
1320 * @retval Returned value can be one of the following values:
1321 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1322 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1323 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1324 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1325 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1326 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1327 {
1328 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1329 return (uint32_t)((READ_BIT(*pReg, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1330 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1331 }
1332
1333 /**
1334 * @brief Set the prescaler of IC channels.
1335 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1336 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1337 * @rmtoll CCMR2 IC3PSC LL_LPTIM_IC_SetPrescaler\n
1338 * @rmtoll CCMR2 IC4PSC LL_LPTIM_IC_SetPrescaler
1339 * @param LPTIMx Low-Power Timer instance
1340 * @param Channel This parameter can be one of the following values:
1341 * @arg @ref LL_LPTIM_CHANNEL_CH1
1342 * @arg @ref LL_LPTIM_CHANNEL_CH2
1343 * @arg @ref LL_LPTIM_CHANNEL_CH3
1344 * @arg @ref LL_LPTIM_CHANNEL_CH4
1345 * @param Prescaler This parameter can be one of the following values:
1346 * @arg @ref LL_LPTIM_ICPSC_DIV1
1347 * @arg @ref LL_LPTIM_ICPSC_DIV2
1348 * @arg @ref LL_LPTIM_ICPSC_DIV4
1349 * @arg @ref LL_LPTIM_ICPSC_DIV8
1350 * @retval None
1351 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1352 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1353 {
1354 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1355 MODIFY_REG(*pReg, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1356 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1357 }
1358
1359 /**
1360 * @brief Get the prescaler of IC channels.
1361 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1362 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1363 * @rmtoll CCMR2 IC3PSC LL_LPTIM_IC_GetPrescaler\n
1364 * @rmtoll CCMR2 IC4PSC LL_LPTIM_IC_GetPrescaler
1365 * @param LPTIMx Low-Power Timer instance
1366 * @param Channel This parameter can be one of the following values:
1367 * @arg @ref LL_LPTIM_CHANNEL_CH1
1368 * @arg @ref LL_LPTIM_CHANNEL_CH2
1369 * @arg @ref LL_LPTIM_CHANNEL_CH3
1370 * @arg @ref LL_LPTIM_CHANNEL_CH4
1371 * @retval Returned value can be one of the following values:
1372 * @arg @ref LL_LPTIM_ICPSC_DIV1
1373 * @arg @ref LL_LPTIM_ICPSC_DIV2
1374 * @arg @ref LL_LPTIM_ICPSC_DIV4
1375 * @arg @ref LL_LPTIM_ICPSC_DIV8
1376 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1377 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1378 {
1379 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1380 return (uint32_t)((READ_BIT(*pReg, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1381 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1382 }
1383
1384 /**
1385 * @brief Set the Channel Mode.
1386 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1387 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode\n
1388 * CCMR2 CC3SEL LL_LPTIM_CC_SetChannelMode\n
1389 * CCMR2 CC4SEL LL_LPTIM_CC_SetChannelMode
1390 * @param LPTIMx Low-Power Timer instance
1391 * @param Channel This parameter can be one of the following values:
1392 * @arg @ref LL_LPTIM_CHANNEL_CH1
1393 * @arg @ref LL_LPTIM_CHANNEL_CH2
1394 * @arg @ref LL_LPTIM_CHANNEL_CH3
1395 * @arg @ref LL_LPTIM_CHANNEL_CH4
1396 * @param CCMode This parameter can be one of the following values:
1397 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1398 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1399 * @retval None
1400 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1401 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1402 {
1403 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1404 MODIFY_REG(*pReg, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel],
1405 CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1406 }
1407
1408 /**
1409 * @brief Get the Channel Mode.
1410 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1411 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode\n
1412 * CCMR2 CC3SEL LL_LPTIM_CC_GetChannelMode\n
1413 * CCMR2 CC4SEL LL_LPTIM_CC_GetChannelMode
1414 * @param LPTIMx Low-Power Timer instance
1415 * @param Channel This parameter can be one of the following values:
1416 * @arg @ref LL_LPTIM_CHANNEL_CH1
1417 * @arg @ref LL_LPTIM_CHANNEL_CH2
1418 * @arg @ref LL_LPTIM_CHANNEL_CH3
1419 * @arg @ref LL_LPTIM_CHANNEL_CH4
1420 * @retval Returned value can be one of the following values:
1421 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1422 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1423 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1424 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1425 {
1426 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&LPTIMx->CCMR1) + LL_LPTIM_OFFSET_TAB_CCMRx[Channel]));
1427 return (uint32_t)((READ_BIT(*pReg, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1428 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1429 }
1430
1431 /**
1432 * @brief Get captured value for input channel 1.
1433 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1434 * @note The real capture value corresponding to the input capture trigger can be calculated using
1435 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1436 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1437 * @param LPTIMx Low-Power Timer instance
1438 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1439 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1440 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1441 {
1442 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1443 }
1444
1445 /**
1446 * @brief Get captured value for input channel 2.
1447 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1448 * @note The real capture value corresponding to the input capture trigger can be calculated using
1449 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1450 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1451 * @param LPTIMx Low-Power Timer instance
1452 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1453 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1454 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1455 {
1456 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1457 }
1458
1459 /**
1460 * @brief Get captured value for input channel 3.
1461 * @rmtoll CCR3 CCR3 LL_LPTIM_IC_GetCaptureCH3
1462 * @note The real capture value corresponding to the input capture trigger can be calculated using
1463 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1464 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1465 * @param LPTIMx Low-Power Timer instance
1466 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1467 */
LL_LPTIM_IC_GetCaptureCH3(const LPTIM_TypeDef * LPTIMx)1468 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH3(const LPTIM_TypeDef *LPTIMx)
1469 {
1470 return (uint32_t)(READ_BIT(LPTIMx->CCR3, LPTIM_CCR3_CCR3));
1471 }
1472
1473 /**
1474 * @brief Get captured value for input channel 4.
1475 * @rmtoll CCR4 CCR4 LL_LPTIM_IC_GetCaptureCH4
1476 * @note The real capture value corresponding to the input capture trigger can be calculated using
1477 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1478 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1479 * @param LPTIMx Low-Power Timer instance
1480 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1481 */
LL_LPTIM_IC_GetCaptureCH4(const LPTIM_TypeDef * LPTIMx)1482 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH4(const LPTIM_TypeDef *LPTIMx)
1483 {
1484 return (uint32_t)(READ_BIT(LPTIMx->CCR4, LPTIM_CCR4_CCR4));
1485 }
1486
1487
1488 /**
1489 * @}
1490 */
1491
1492 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1493 * @{
1494 */
1495
1496 /**
1497 * @brief Enable the timeout function
1498 * @note This function must be called when the LPTIM instance is disabled.
1499 * @note The first trigger event will start the timer, any successive trigger
1500 * event will reset the counter and the timer will restart.
1501 * @note The timeout value corresponds to the compare value; if no trigger
1502 * occurs within the expected time frame, the MCU is waked-up by the
1503 * compare match event.
1504 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1505 * @param LPTIMx Low-Power Timer instance
1506 * @retval None
1507 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1508 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1509 {
1510 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1511 }
1512
1513 /**
1514 * @brief Disable the timeout function
1515 * @note This function must be called when the LPTIM instance is disabled.
1516 * @note A trigger event arriving when the timer is already started will be
1517 * ignored.
1518 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1519 * @param LPTIMx Low-Power Timer instance
1520 * @retval None
1521 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1522 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1523 {
1524 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1525 }
1526
1527 /**
1528 * @brief Indicate whether the timeout function is enabled.
1529 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1530 * @param LPTIMx Low-Power Timer instance
1531 * @retval State of bit (1 or 0).
1532 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1533 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1534 {
1535 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1536 }
1537
1538 /**
1539 * @brief Start the LPTIM counter
1540 * @note This function must be called when the LPTIM instance is disabled.
1541 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1542 * @param LPTIMx Low-Power Timer instance
1543 * @retval None
1544 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1545 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1546 {
1547 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1548 }
1549
1550 /**
1551 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1552 * @note This function must be called when the LPTIM instance is disabled.
1553 * @note An internal clock source must be present when a digital filter is
1554 * required for the trigger.
1555 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1556 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1557 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1558 * @param LPTIMx Low-Power Timer instance
1559 * @param Source This parameter can be one of the following values:
1560 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1561 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1562 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1563 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1564 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1565 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1566 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
1567 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
1568 *
1569 * (*) Value not defined in all devices. \n
1570 *
1571 * @param Filter This parameter can be one of the following values:
1572 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1573 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1574 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1575 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1576 * @param Polarity This parameter can be one of the following values:
1577 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1578 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1579 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1580 * @retval None
1581 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1582 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1583 {
1584 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1585 }
1586
1587 /**
1588 * @brief Get actual external trigger source.
1589 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1590 * @param LPTIMx Low-Power Timer instance
1591 * @retval Returned value can be one of the following values:
1592 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1593 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1594 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1595 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1596 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1597 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1598 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
1599 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
1600 *
1601 * (*) Value not defined in all devices. \n
1602 *
1603 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1604 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1605 {
1606 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1607 }
1608
1609 /**
1610 * @brief Get actual external trigger filter.
1611 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1612 * @param LPTIMx Low-Power Timer instance
1613 * @retval Returned value can be one of the following values:
1614 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1615 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1616 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1617 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1618 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1619 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1620 {
1621 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1622 }
1623
1624 /**
1625 * @brief Get actual external trigger polarity.
1626 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1627 * @param LPTIMx Low-Power Timer instance
1628 * @retval Returned value can be one of the following values:
1629 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1630 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1631 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1632 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1633 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1634 {
1635 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1636 }
1637
1638 /**
1639 * @}
1640 */
1641
1642 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1643 * @{
1644 */
1645
1646 /**
1647 * @brief Set the source of the clock used by the LPTIM instance.
1648 * @note This function must be called when the LPTIM instance is disabled.
1649 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1650 * @param LPTIMx Low-Power Timer instance
1651 * @param ClockSource This parameter can be one of the following values:
1652 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1653 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1654 * @retval None
1655 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1656 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1657 {
1658 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1659 }
1660
1661 /**
1662 * @brief Get actual LPTIM instance clock source.
1663 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1664 * @param LPTIMx Low-Power Timer instance
1665 * @retval Returned value can be one of the following values:
1666 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1667 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1668 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1669 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1670 {
1671 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1672 }
1673
1674 /**
1675 * @brief Configure the active edge or edges used by the counter when
1676 the LPTIM is clocked by an external clock source.
1677 * @note This function must be called when the LPTIM instance is disabled.
1678 * @note When both external clock signal edges are considered active ones,
1679 * the LPTIM must also be clocked by an internal clock source with a
1680 * frequency equal to at least four times the external clock frequency.
1681 * @note An internal clock source must be present when a digital filter is
1682 * required for external clock.
1683 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1684 * CFGR CKPOL LL_LPTIM_ConfigClock
1685 * @param LPTIMx Low-Power Timer instance
1686 * @param ClockFilter This parameter can be one of the following values:
1687 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1688 * @arg @ref LL_LPTIM_CLK_FILTER_2
1689 * @arg @ref LL_LPTIM_CLK_FILTER_4
1690 * @arg @ref LL_LPTIM_CLK_FILTER_8
1691 * @param ClockPolarity This parameter can be one of the following values:
1692 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1693 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1694 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1695 * @retval None
1696 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1697 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1698 {
1699 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1700 }
1701
1702 /**
1703 * @brief Get actual clock polarity
1704 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1705 * @param LPTIMx Low-Power Timer instance
1706 * @retval Returned value can be one of the following values:
1707 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1708 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1709 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1710 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1711 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1712 {
1713 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1714 }
1715
1716 /**
1717 * @brief Get actual clock digital filter
1718 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1719 * @param LPTIMx Low-Power Timer instance
1720 * @retval Returned value can be one of the following values:
1721 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1722 * @arg @ref LL_LPTIM_CLK_FILTER_2
1723 * @arg @ref LL_LPTIM_CLK_FILTER_4
1724 * @arg @ref LL_LPTIM_CLK_FILTER_8
1725 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1726 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1727 {
1728 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1729 }
1730
1731 /**
1732 * @}
1733 */
1734
1735 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1736 * @{
1737 */
1738
1739 /**
1740 * @brief Configure the encoder mode.
1741 * @note This function must be called when the LPTIM instance is disabled.
1742 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1743 * @param LPTIMx Low-Power Timer instance
1744 * @param EncoderMode This parameter can be one of the following values:
1745 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1746 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1747 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1748 * @retval None
1749 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1750 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1751 {
1752 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1753 }
1754
1755 /**
1756 * @brief Get actual encoder mode.
1757 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1758 * @param LPTIMx Low-Power Timer instance
1759 * @retval Returned value can be one of the following values:
1760 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1761 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1762 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1763 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1764 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1765 {
1766 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1767 }
1768
1769 /**
1770 * @brief Enable the encoder mode
1771 * @note This function must be called when the LPTIM instance is disabled.
1772 * @note In this mode the LPTIM instance must be clocked by an internal clock
1773 * source. Also, the prescaler division ratio must be equal to 1.
1774 * @note LPTIM instance must be configured in continuous mode prior enabling
1775 * the encoder mode.
1776 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1777 * @param LPTIMx Low-Power Timer instance
1778 * @retval None
1779 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1780 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1781 {
1782 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1783 }
1784
1785 /**
1786 * @brief Disable the encoder mode
1787 * @note This function must be called when the LPTIM instance is disabled.
1788 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1789 * @param LPTIMx Low-Power Timer instance
1790 * @retval None
1791 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1792 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1793 {
1794 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1795 }
1796
1797 /**
1798 * @brief Indicates whether the LPTIM operates in encoder mode.
1799 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1800 * @param LPTIMx Low-Power Timer instance
1801 * @retval State of bit (1 or 0).
1802 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1803 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1804 {
1805 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1806 }
1807
1808 /**
1809 * @}
1810 */
1811
1812 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1813 * @{
1814 */
1815
1816 /**
1817 * @brief Clear the compare match flag for channel 1 (CC1CF)
1818 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1819 * @param LPTIMx Low-Power Timer instance
1820 * @retval None
1821 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1822 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1823 {
1824 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1825 }
1826
1827 /**
1828 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1829 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1830 * @param LPTIMx Low-Power Timer instance
1831 * @retval State of bit (1 or 0).
1832 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1833 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1834 {
1835 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1836 }
1837
1838 /**
1839 * @brief Clear the compare match flag for channel 2 (CC2CF)
1840 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1841 * @param LPTIMx Low-Power Timer instance
1842 * @retval None
1843 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1844 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1845 {
1846 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1847 }
1848
1849 /**
1850 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1851 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1852 * @param LPTIMx Low-Power Timer instance
1853 * @retval State of bit (1 or 0).
1854 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1855 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1856 {
1857 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1858 }
1859
1860 /**
1861 * @brief Clear the capture/compare flag for channel 3 (CC3F)
1862 * @rmtoll ICR CC3 LL_LPTIM_ClearFlag_CC3
1863 * @param LPTIMx Low-Power Timer instance
1864 * @retval None
1865 */
LL_LPTIM_ClearFlag_CC3(LPTIM_TypeDef * LPTIMx)1866 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC3(LPTIM_TypeDef *LPTIMx)
1867 {
1868 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC3CF);
1869 }
1870
1871 /**
1872 * @brief Inform application whether a capture/compare interrupt has occurred for channel 3.
1873 * @rmtoll ISR CC3 LL_LPTIM_IsActiveFlag_CC3
1874 * @param LPTIMx Low-Power Timer instance
1875 * @retval State of bit (1 or 0).
1876 */
LL_LPTIM_IsActiveFlag_CC3(const LPTIM_TypeDef * LPTIMx)1877 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC3(const LPTIM_TypeDef *LPTIMx)
1878 {
1879 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC3IF) == LPTIM_ISR_CC3IF) ? 1UL : 0UL));
1880 }
1881
1882 /**
1883 * @brief Clear the capture/compare flag for channel 4 (CC4F)
1884 * @rmtoll ICR CC4 LL_LPTIM_ClearFlag_CC4
1885 * @param LPTIMx Low-Power Timer instance
1886 * @retval None
1887 */
LL_LPTIM_ClearFlag_CC4(LPTIM_TypeDef * LPTIMx)1888 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC4(LPTIM_TypeDef *LPTIMx)
1889 {
1890 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC4CF);
1891 }
1892
1893 /**
1894 * @brief Inform application whether a capture/compare interrupt has occurred for channel 4.
1895 * @rmtoll ISR CC4 LL_LPTIM_IsActiveFlag_CC4
1896 * @param LPTIMx Low-Power Timer instance
1897 * @retval State of bit (1 or 0).
1898 */
LL_LPTIM_IsActiveFlag_CC4(const LPTIM_TypeDef * LPTIMx)1899 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC4(const LPTIM_TypeDef *LPTIMx)
1900 {
1901 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC4IF) == LPTIM_ISR_CC4IF) ? 1UL : 0UL));
1902 }
1903
1904 /**
1905 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1906 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1907 * @param LPTIMx Low-Power Timer instance
1908 * @retval None
1909 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1910 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1911 {
1912 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1913 }
1914
1915 /**
1916 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1917 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1918 * @param LPTIMx Low-Power Timer instance
1919 * @retval State of bit (1 or 0).
1920 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1921 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1922 {
1923 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1924 }
1925
1926 /**
1927 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1928 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1929 * @param LPTIMx Low-Power Timer instance
1930 * @retval None
1931 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1932 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1933 {
1934 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1935 }
1936
1937 /**
1938 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1939 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1940 * @param LPTIMx Low-Power Timer instance
1941 * @retval State of bit (1 or 0).
1942 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1943 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1944 {
1945 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1946 }
1947
1948 /**
1949 * @brief Clear the Capture/Compare 3 over-capture flag for channel 3 (CC3OCF)
1950 * @rmtoll ICR CC3OCF LL_LPTIM_ClearFlag_CC3O
1951 * @param LPTIMx Low-Power Timer instance
1952 * @retval None
1953 */
LL_LPTIM_ClearFlag_CC3O(LPTIM_TypeDef * LPTIMx)1954 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC3O(LPTIM_TypeDef *LPTIMx)
1955 {
1956 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC3OCF);
1957 }
1958
1959 /**
1960 * @brief Inform application whether a Capture/Compare 3 over-capture has occurred for channel 3.
1961 * @rmtoll ISR CC3OF LL_LPTIM_IsActiveFlag_CC3O
1962 * @param LPTIMx Low-Power Timer instance
1963 * @retval State of bit (1 or 0).
1964 */
LL_LPTIM_IsActiveFlag_CC3O(const LPTIM_TypeDef * LPTIMx)1965 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC3O(const LPTIM_TypeDef *LPTIMx)
1966 {
1967 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC3OF) == LPTIM_ISR_CC3OF) ? 1UL : 0UL));
1968 }
1969
1970 /**
1971 * @brief Clear the Capture/Compare 4 over-capture flag for channel 4 (CC4OCF)
1972 * @rmtoll ICR CC4OCF LL_LPTIM_ClearFlag_CC4O
1973 * @param LPTIMx Low-Power Timer instance
1974 * @retval None
1975 */
LL_LPTIM_ClearFlag_CC4O(LPTIM_TypeDef * LPTIMx)1976 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC4O(LPTIM_TypeDef *LPTIMx)
1977 {
1978 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC4OCF);
1979 }
1980
1981 /**
1982 * @brief Inform application whether a Capture/Compare 4 over-capture has occurred for channel 4.
1983 * @rmtoll ISR CC4OF LL_LPTIM_IsActiveFlag_CC4O
1984 * @param LPTIMx Low-Power Timer instance
1985 * @retval State of bit (1 or 0).
1986 */
LL_LPTIM_IsActiveFlag_CC4O(const LPTIM_TypeDef * LPTIMx)1987 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC4O(const LPTIM_TypeDef *LPTIMx)
1988 {
1989 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC4OF) == LPTIM_ISR_CC4OF) ? 1UL : 0UL));
1990 }
1991
1992 /**
1993 * @brief Clear the autoreload match flag (ARRMCF)
1994 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1995 * @param LPTIMx Low-Power Timer instance
1996 * @retval None
1997 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1998 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1999 {
2000 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
2001 }
2002
2003 /**
2004 * @brief Inform application whether a autoreload match interrupt has occurred.
2005 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
2006 * @param LPTIMx Low-Power Timer instance
2007 * @retval State of bit (1 or 0).
2008 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)2009 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
2010 {
2011 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
2012 }
2013
2014 /**
2015 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
2016 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
2017 * @param LPTIMx Low-Power Timer instance
2018 * @retval None
2019 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)2020 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2021 {
2022 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
2023 }
2024
2025 /**
2026 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
2027 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
2028 * @param LPTIMx Low-Power Timer instance
2029 * @retval State of bit (1 or 0).
2030 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2031 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2032 {
2033 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
2034 }
2035
2036 /**
2037 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
2038 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
2039 * @param LPTIMx Low-Power Timer instance
2040 * @retval None
2041 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)2042 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
2043 {
2044 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
2045 }
2046
2047 /**
2048 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
2049 completed. If so, a new one can be initiated.
2050 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
2051 * @param LPTIMx Low-Power Timer instance
2052 * @retval State of bit (1 or 0).
2053 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)2054 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2055 {
2056 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
2057 }
2058
2059 /**
2060 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
2061 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
2062 * @param LPTIMx Low-Power Timer instance
2063 * @retval None
2064 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)2065 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
2066 {
2067 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
2068 }
2069
2070 /**
2071 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
2072 completed. If so, a new one can be initiated.
2073 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
2074 * @param LPTIMx Low-Power Timer instance
2075 * @retval State of bit (1 or 0).
2076 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)2077 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2078 {
2079 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
2080 }
2081
2082 /**
2083 * @brief Clear the compare register update interrupt flag (CMP3OKCF).
2084 * @rmtoll ICR CMP3OKCF LL_LPTIM_ClearFlag_CMP3OK
2085 * @param LPTIMx Low-Power Timer instance
2086 * @retval None
2087 */
LL_LPTIM_ClearFlag_CMP3OK(LPTIM_TypeDef * LPTIMx)2088 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP3OK(LPTIM_TypeDef *LPTIMx)
2089 {
2090 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP3OKCF);
2091 }
2092
2093 /**
2094 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR3 register has been successfully
2095 completed. If so, a new one can be initiated.
2096 * @rmtoll ISR CMP3OK LL_LPTIM_IsActiveFlag_CMP3OK
2097 * @param LPTIMx Low-Power Timer instance
2098 * @retval State of bit (1 or 0).
2099 */
LL_LPTIM_IsActiveFlag_CMP3OK(const LPTIM_TypeDef * LPTIMx)2100 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP3OK(const LPTIM_TypeDef *LPTIMx)
2101 {
2102 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP3OK) == LPTIM_ISR_CMP3OK) ? 1UL : 0UL));
2103 }
2104
2105 /**
2106 * @brief Clear the compare register update interrupt flag (CMP4OKCF).
2107 * @rmtoll ICR CMP4OKCF LL_LPTIM_ClearFlag_CMP4OK
2108 * @param LPTIMx Low-Power Timer instance
2109 * @retval None
2110 */
LL_LPTIM_ClearFlag_CMP4OK(LPTIM_TypeDef * LPTIMx)2111 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP4OK(LPTIM_TypeDef *LPTIMx)
2112 {
2113 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP4OKCF);
2114 }
2115
2116 /**
2117 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR4 register has been successfully
2118 completed. If so, a new one can be initiated.
2119 * @rmtoll ISR CMP4OK LL_LPTIM_IsActiveFlag_CMP4OK
2120 * @param LPTIMx Low-Power Timer instance
2121 * @retval State of bit (1 or 0).
2122 */
LL_LPTIM_IsActiveFlag_CMP4OK(const LPTIM_TypeDef * LPTIMx)2123 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP4OK(const LPTIM_TypeDef *LPTIMx)
2124 {
2125 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP4OK) == LPTIM_ISR_CMP4OK) ? 1UL : 0UL));
2126 }
2127
2128 /**
2129 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
2130 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
2131 * @param LPTIMx Low-Power Timer instance
2132 * @retval None
2133 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)2134 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
2135 {
2136 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
2137 }
2138
2139 /**
2140 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
2141 completed. If so, a new one can be initiated.
2142 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
2143 * @param LPTIMx Low-Power Timer instance
2144 * @retval State of bit (1 or 0).
2145 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)2146 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
2147 {
2148 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
2149 }
2150
2151 /**
2152 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
2153 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
2154 * @param LPTIMx Low-Power Timer instance
2155 * @retval None
2156 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)2157 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
2158 {
2159 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
2160 }
2161
2162 /**
2163 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
2164 completed. If so, a new one can be initiated.
2165 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
2166 * @param LPTIMx Low-Power Timer instance
2167 * @retval State of bit (1 or 0).
2168 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)2169 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
2170 {
2171 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
2172 }
2173
2174 /**
2175 * @brief Clear the counter direction change to up interrupt flag (UPCF).
2176 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
2177 * @param LPTIMx Low-Power Timer instance
2178 * @retval None
2179 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)2180 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
2181 {
2182 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
2183 }
2184
2185 /**
2186 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
2187 operates in encoder mode).
2188 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
2189 * @param LPTIMx Low-Power Timer instance
2190 * @retval State of bit (1 or 0).
2191 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)2192 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
2193 {
2194 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
2195 }
2196
2197 /**
2198 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
2199 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
2200 * @param LPTIMx Low-Power Timer instance
2201 * @retval None
2202 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)2203 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
2204 {
2205 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
2206 }
2207
2208 /**
2209 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
2210 operates in encoder mode).
2211 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
2212 * @param LPTIMx Low-Power Timer instance
2213 * @retval State of bit (1 or 0).
2214 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)2215 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
2216 {
2217 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
2218 }
2219
2220 /**
2221 * @brief Clear the repetition register update interrupt flag (REPOKCF).
2222 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
2223 * @param LPTIMx Low-Power Timer instance
2224 * @retval None
2225 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)2226 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
2227 {
2228 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
2229 }
2230
2231 /**
2232 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
2233 completed; If so, a new one can be initiated.
2234 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
2235 * @param LPTIMx Low-Power Timer instance
2236 * @retval State of bit (1 or 0).
2237 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)2238 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
2239 {
2240 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
2241 }
2242
2243 /**
2244 * @brief Clear the update event flag (UECF).
2245 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
2246 * @param LPTIMx Low-Power Timer instance
2247 * @retval None
2248 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)2249 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
2250 {
2251 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
2252 }
2253
2254 /**
2255 * @brief Informs application whether the LPTIMx update event has occurred.
2256 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
2257 * @param LPTIMx Low-Power Timer instance
2258 * @retval State of bit (1 or 0).
2259 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)2260 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
2261 {
2262 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
2263 }
2264
2265 /**
2266 * @}
2267 */
2268
2269 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
2270 * @{
2271 */
2272 /**
2273 * @brief Enable capture/compare 1 interrupt (CC1IE).
2274 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
2275 * @param LPTIMx Low-Power Timer instance
2276 * @retval None
2277 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)2278 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
2279 {
2280 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
2281 }
2282
2283 /**
2284 * @brief Disable capture/compare 1 interrupt (CC1IE).
2285 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
2286 * @param LPTIMx Low-Power Timer instance
2287 * @retval None
2288 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)2289 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
2290 {
2291 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
2292 }
2293
2294 /**
2295 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
2296 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
2297 * @param LPTIMx Low-Power Timer instance
2298 * @retval State of bit (1 or 0).
2299 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)2300 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
2301 {
2302 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
2303 }
2304
2305 /**
2306 * @brief Enable capture/compare 1 interrupt (CC2IE).
2307 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
2308 * @param LPTIMx Low-Power Timer instance
2309 * @retval None
2310 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)2311 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
2312 {
2313 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
2314 }
2315
2316 /**
2317 * @brief Disable capture/compare 2 interrupt (CC2IE).
2318 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
2319 * @param LPTIMx Low-Power Timer instance
2320 * @retval None
2321 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)2322 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
2323 {
2324 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
2325 }
2326
2327 /**
2328 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
2329 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
2330 * @param LPTIMx Low-Power Timer instance
2331 * @retval State of bit (1 or 0).
2332 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)2333 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
2334 {
2335 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
2336 }
2337
2338 /**
2339 * @brief Enable capture/compare 3 interrupt (CC3IE).
2340 * @rmtoll DIER CC3IE LL_LPTIM_EnableIT_CC3
2341 * @param LPTIMx Low-Power Timer instance
2342 * @retval None
2343 */
LL_LPTIM_EnableIT_CC3(LPTIM_TypeDef * LPTIMx)2344 __STATIC_INLINE void LL_LPTIM_EnableIT_CC3(LPTIM_TypeDef *LPTIMx)
2345 {
2346 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC3IE);
2347 }
2348
2349 /**
2350 * @brief Disable capture/compare 3 interrupt (CC3IE).
2351 * @rmtoll DIER CC3IE LL_LPTIM_DisableIT_CC3
2352 * @param LPTIMx Low-Power Timer instance
2353 * @retval None
2354 */
LL_LPTIM_DisableIT_CC3(LPTIM_TypeDef * LPTIMx)2355 __STATIC_INLINE void LL_LPTIM_DisableIT_CC3(LPTIM_TypeDef *LPTIMx)
2356 {
2357 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC3IE);
2358 }
2359
2360 /**
2361 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
2362 * @rmtoll DIER CC3IE LL_LPTIM_IsEnabledIT_CC3
2363 * @param LPTIMx Low-Power Timer instance
2364 * @retval State of bit (1 or 0).
2365 */
LL_LPTIM_IsEnabledIT_CC3(const LPTIM_TypeDef * LPTIMx)2366 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC3(const LPTIM_TypeDef *LPTIMx)
2367 {
2368 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC3IE) == LPTIM_DIER_CC3IE) ? 1UL : 0UL));
2369 }
2370
2371 /**
2372 * @brief Enable capture/compare 4 interrupt (CC4IE).
2373 * @rmtoll DIER CC4IE LL_LPTIM_EnableIT_CC4
2374 * @param LPTIMx Low-Power Timer instance
2375 * @retval None
2376 */
LL_LPTIM_EnableIT_CC4(LPTIM_TypeDef * LPTIMx)2377 __STATIC_INLINE void LL_LPTIM_EnableIT_CC4(LPTIM_TypeDef *LPTIMx)
2378 {
2379 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC4IE);
2380 }
2381
2382 /**
2383 * @brief Disable capture/compare 4 interrupt (CC4IE).
2384 * @rmtoll DIER CC4IE LL_LPTIM_DisableIT_CC4
2385 * @param LPTIMx Low-Power Timer instance
2386 * @retval None
2387 */
LL_LPTIM_DisableIT_CC4(LPTIM_TypeDef * LPTIMx)2388 __STATIC_INLINE void LL_LPTIM_DisableIT_CC4(LPTIM_TypeDef *LPTIMx)
2389 {
2390 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC4IE);
2391 }
2392
2393 /**
2394 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
2395 * @rmtoll DIER CC4IE LL_LPTIM_IsEnabledIT_CC4
2396 * @param LPTIMx Low-Power Timer instance
2397 * @retval State of bit (1 or 0).
2398 */
LL_LPTIM_IsEnabledIT_CC4(const LPTIM_TypeDef * LPTIMx)2399 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC4(const LPTIM_TypeDef *LPTIMx)
2400 {
2401 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC4IE) == LPTIM_DIER_CC4IE) ? 1UL : 0UL));
2402 }
2403
2404 /**
2405 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
2406 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
2407 * @param LPTIMx Low-Power Timer instance
2408 * @retval None
2409 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)2410 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
2411 {
2412 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
2413 }
2414
2415 /**
2416 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
2417 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
2418 * @param LPTIMx Low-Power Timer instance
2419 * @retval None
2420 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)2421 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
2422 {
2423 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
2424 }
2425
2426 /**
2427 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
2428 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
2429 * @param LPTIMx Low-Power Timer instance
2430 * @retval State of bit (1 or 0).
2431 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)2432 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
2433 {
2434 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
2435 }
2436
2437 /**
2438 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
2439 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
2440 * @param LPTIMx Low-Power Timer instance
2441 * @retval None
2442 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)2443 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2444 {
2445 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2446 }
2447
2448 /**
2449 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
2450 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
2451 * @param LPTIMx Low-Power Timer instance
2452 * @retval None
2453 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)2454 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2455 {
2456 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2457 }
2458
2459 /**
2460 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
2461 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
2462 * @param LPTIMx Low-Power Timer instance
2463 * @retval State of bit (1 or 0).
2464 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)2465 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
2466 {
2467 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2468 }
2469
2470 /**
2471 * @brief Enable capture/compare 3 over-capture interrupt (CC3OIE).
2472 * @rmtoll DIER CC3OIE LL_LPTIM_EnableIT_CC3O
2473 * @param LPTIMx Low-Power Timer instance
2474 * @retval None
2475 */
LL_LPTIM_EnableIT_CC3O(LPTIM_TypeDef * LPTIMx)2476 __STATIC_INLINE void LL_LPTIM_EnableIT_CC3O(LPTIM_TypeDef *LPTIMx)
2477 {
2478 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC3OIE);
2479 }
2480
2481 /**
2482 * @brief Disable capture/compare 3 over-capture interrupt (CC3OIE).
2483 * @rmtoll DIER CC3OIE LL_LPTIM_DisableIT_CC3O
2484 * @param LPTIMx Low-Power Timer instance
2485 * @retval None
2486 */
LL_LPTIM_DisableIT_CC3O(LPTIM_TypeDef * LPTIMx)2487 __STATIC_INLINE void LL_LPTIM_DisableIT_CC3O(LPTIM_TypeDef *LPTIMx)
2488 {
2489 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC3OIE);
2490 }
2491
2492 /**
2493 * @brief Indicates whether the capture/compare 3 over-capture interrupt (CC3OIE) is enabled.
2494 * @rmtoll DIER CC3OIE LL_LPTIM_IsEnabledIT_CC3O
2495 * @param LPTIMx Low-Power Timer instance
2496 * @retval State of bit (1 or 0).
2497 */
LL_LPTIM_IsEnabledIT_CC3O(const LPTIM_TypeDef * LPTIMx)2498 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC3O(const LPTIM_TypeDef *LPTIMx)
2499 {
2500 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC3OIE) == LPTIM_DIER_CC3OIE) ? 1UL : 0UL));
2501 }
2502
2503 /**
2504 * @brief Enable capture/compare 4 over-capture interrupt (CC4OIE).
2505 * @rmtoll DIER CC4OIE LL_LPTIM_EnableIT_CC4O
2506 * @param LPTIMx Low-Power Timer instance
2507 * @retval None
2508 */
LL_LPTIM_EnableIT_CC4O(LPTIM_TypeDef * LPTIMx)2509 __STATIC_INLINE void LL_LPTIM_EnableIT_CC4O(LPTIM_TypeDef *LPTIMx)
2510 {
2511 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC4OIE);
2512 }
2513
2514 /**
2515 * @brief Disable capture/compare 4 over-capture interrupt (CC4OIE).
2516 * @rmtoll DIER CC4OIE LL_LPTIM_DisableIT_CC4O
2517 * @param LPTIMx Low-Power Timer instance
2518 * @retval None
2519 */
LL_LPTIM_DisableIT_CC4O(LPTIM_TypeDef * LPTIMx)2520 __STATIC_INLINE void LL_LPTIM_DisableIT_CC4O(LPTIM_TypeDef *LPTIMx)
2521 {
2522 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC4OIE);
2523 }
2524
2525 /**
2526 * @brief Indicates whether the capture/compare 4 over-capture interrupt (CC4OIE) is enabled.
2527 * @rmtoll DIER CC4OIE LL_LPTIM_IsEnabledIT_CC4O
2528 * @param LPTIMx Low-Power Timer instance
2529 * @retval State of bit (1 or 0).
2530 */
LL_LPTIM_IsEnabledIT_CC4O(const LPTIM_TypeDef * LPTIMx)2531 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC4O(const LPTIM_TypeDef *LPTIMx)
2532 {
2533 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC4OIE) == LPTIM_DIER_CC4OIE) ? 1UL : 0UL));
2534 }
2535
2536 /**
2537 * @brief Enable autoreload match interrupt (ARRMIE).
2538 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2539 * @param LPTIMx Low-Power Timer instance
2540 * @retval None
2541 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2542 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2543 {
2544 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2545 }
2546
2547 /**
2548 * @brief Disable autoreload match interrupt (ARRMIE).
2549 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2550 * @param LPTIMx Low-Power Timer instance
2551 * @retval None
2552 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2553 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2554 {
2555 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2556 }
2557
2558 /**
2559 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2560 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2561 * @param LPTIMx Low-Power Timer instance
2562 * @retval State of bit (1 or 0).
2563 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2564 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2565 {
2566 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2567 }
2568
2569 /**
2570 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2571 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2572 * @param LPTIMx Low-Power Timer instance
2573 * @retval None
2574 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2575 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2576 {
2577 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2578 }
2579
2580 /**
2581 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2582 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2583 * @param LPTIMx Low-Power Timer instance
2584 * @retval None
2585 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2586 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2587 {
2588 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2589 }
2590
2591 /**
2592 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2593 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2594 * @param LPTIMx Low-Power Timer instance
2595 * @retval State of bit (1 or 0).
2596 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2597 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2598 {
2599 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2600 }
2601
2602 /**
2603 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2604 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2605 * @param LPTIMx Low-Power Timer instance
2606 * @retval None
2607 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2608 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2609 {
2610 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2611 }
2612
2613 /**
2614 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2615 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2616 * @param LPTIMx Low-Power Timer instance
2617 * @retval None
2618 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2619 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2620 {
2621 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2622 }
2623
2624 /**
2625 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2626 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2627 * @param LPTIMx Low-Power Timer instance
2628 * @retval State of bit (1 or 0).
2629 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2630 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2631 {
2632 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2633 }
2634
2635 /**
2636 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2637 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2638 * @param LPTIMx Low-Power Timer instance
2639 * @retval None
2640 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2641 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2642 {
2643 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2644 }
2645
2646 /**
2647 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2648 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2649 * @param LPTIMx Low-Power Timer instance
2650 * @retval None
2651 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2652 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2653 {
2654 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2655 }
2656
2657 /**
2658 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2659 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2660 * @param LPTIMx Low-Power Timer instance
2661 * @retval State of bit (1 or 0).
2662 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2663 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2664 {
2665 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2666 }
2667
2668 /**
2669 * @brief Enable compare register write completed interrupt (CMP3OKIE).
2670 * @rmtoll IER CMP3OKIE LL_LPTIM_EnableIT_CMP3OK
2671 * @param LPTIMx Low-Power Timer instance
2672 * @retval None
2673 */
LL_LPTIM_EnableIT_CMP3OK(LPTIM_TypeDef * LPTIMx)2674 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP3OK(LPTIM_TypeDef *LPTIMx)
2675 {
2676 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP3OKIE);
2677 }
2678
2679 /**
2680 * @brief Disable compare register write completed interrupt (CMP3OKIE).
2681 * @rmtoll IER CMP3OKIE LL_LPTIM_DisableIT_CMP3OK
2682 * @param LPTIMx Low-Power Timer instance
2683 * @retval None
2684 */
LL_LPTIM_DisableIT_CMP3OK(LPTIM_TypeDef * LPTIMx)2685 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP3OK(LPTIM_TypeDef *LPTIMx)
2686 {
2687 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP3OKIE);
2688 }
2689
2690 /**
2691 * @brief Indicates whether the compare register write completed interrupt (CMP3OKIE) is enabled.
2692 * @rmtoll IER CMP3OKIE LL_LPTIM_IsEnabledIT_CMP3OK
2693 * @param LPTIMx Low-Power Timer instance
2694 * @retval State of bit (1 or 0).
2695 */
LL_LPTIM_IsEnabledIT_CMP3OK(const LPTIM_TypeDef * LPTIMx)2696 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP3OK(const LPTIM_TypeDef *LPTIMx)
2697 {
2698 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP3OKIE) == LPTIM_DIER_CMP3OKIE) ? 1UL : 0UL));
2699 }
2700
2701 /**
2702 * @brief Enable compare register write completed interrupt (CMP4OKIE).
2703 * @rmtoll IER CMP4OKIE LL_LPTIM_EnableIT_CMP4OK
2704 * @param LPTIMx Low-Power Timer instance
2705 * @retval None
2706 */
LL_LPTIM_EnableIT_CMP4OK(LPTIM_TypeDef * LPTIMx)2707 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP4OK(LPTIM_TypeDef *LPTIMx)
2708 {
2709 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP4OKIE);
2710 }
2711
2712 /**
2713 * @brief Disable compare register write completed interrupt (CMP4OKIE).
2714 * @rmtoll IER CMP4OKIE LL_LPTIM_DisableIT_CMP4OK
2715 * @param LPTIMx Low-Power Timer instance
2716 * @retval None
2717 */
LL_LPTIM_DisableIT_CMP4OK(LPTIM_TypeDef * LPTIMx)2718 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP4OK(LPTIM_TypeDef *LPTIMx)
2719 {
2720 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP4OKIE);
2721 }
2722
2723 /**
2724 * @brief Indicates whether the compare register write completed interrupt (CMP4OKIE) is enabled.
2725 * @rmtoll IER CMP4OKIE LL_LPTIM_IsEnabledIT_CMP4OK
2726 * @param LPTIMx Low-Power Timer instance
2727 * @retval State of bit (1 or 0).
2728 */
LL_LPTIM_IsEnabledIT_CMP4OK(const LPTIM_TypeDef * LPTIMx)2729 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP4OK(const LPTIM_TypeDef *LPTIMx)
2730 {
2731 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP4OKIE) == LPTIM_DIER_CMP4OKIE) ? 1UL : 0UL));
2732 }
2733
2734 /**
2735 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2736 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2737 * @param LPTIMx Low-Power Timer instance
2738 * @retval None
2739 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2740 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2741 {
2742 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2743 }
2744
2745 /**
2746 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2747 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2748 * @param LPTIMx Low-Power Timer instance
2749 * @retval None
2750 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2751 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2752 {
2753 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2754 }
2755
2756 /**
2757 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2758 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2759 * @param LPTIMx Low-Power Timer instance
2760 * @retval State of bit(1 or 0).
2761 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2762 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2763 {
2764 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2765 }
2766
2767 /**
2768 * @brief Enable direction change to up interrupt (UPIE).
2769 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2770 * @param LPTIMx Low-Power Timer instance
2771 * @retval None
2772 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2773 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2774 {
2775 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2776 }
2777
2778 /**
2779 * @brief Disable direction change to up interrupt (UPIE).
2780 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2781 * @param LPTIMx Low-Power Timer instance
2782 * @retval None
2783 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2784 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2785 {
2786 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2787 }
2788
2789 /**
2790 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2791 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2792 * @param LPTIMx Low-Power Timer instance
2793 * @retval State of bit(1 or 0).
2794 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2795 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2796 {
2797 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2798 }
2799
2800 /**
2801 * @brief Enable direction change to down interrupt (DOWNIE).
2802 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2803 * @param LPTIMx Low-Power Timer instance
2804 * @retval None
2805 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2806 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2807 {
2808 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2809 }
2810
2811 /**
2812 * @brief Disable direction change to down interrupt (DOWNIE).
2813 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2814 * @param LPTIMx Low-Power Timer instance
2815 * @retval None
2816 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2817 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2818 {
2819 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2820 }
2821
2822 /**
2823 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2824 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2825 * @param LPTIMx Low-Power Timer instance
2826 * @retval State of bit(1 or 0).
2827 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2828 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2829 {
2830 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2831 }
2832
2833 /**
2834 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2835 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2836 * @param LPTIMx Low-Power Timer instance
2837 * @retval None
2838 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2839 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2840 {
2841 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2842 }
2843
2844 /**
2845 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2846 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2847 * @param LPTIMx Low-Power Timer instance
2848 * @retval None
2849 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2850 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2851 {
2852 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2853 }
2854
2855 /**
2856 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2857 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2858 * @param LPTIMx Low-Power Timer instance
2859 * @retval State of bit(1 or 0).
2860 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2861 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2862 {
2863 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2864 }
2865
2866 /**
2867 * @brief Enable update event interrupt (UEIE).
2868 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2869 * @param LPTIMx Low-Power Timer instance
2870 * @retval None
2871 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2872 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2873 {
2874 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2875 }
2876
2877 /**
2878 * @brief Disable update event interrupt (UEIE).
2879 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2880 * @param LPTIMx Low-Power Timer instance
2881 * @retval None
2882 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2883 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2884 {
2885 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2886 }
2887
2888 /**
2889 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2890 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2891 * @param LPTIMx Low-Power Timer instance
2892 *@ retval State of bit(1 or 0).
2893 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2894 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2895 {
2896 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2897 }
2898 /**
2899 * @}
2900 */
2901
2902
2903 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2904 * @{
2905 */
2906 /**
2907 * @brief Enable update DMA request.
2908 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2909 * @param LPTIMx Low-Power Timer instance
2910 * @retval None
2911 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2912 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2913 {
2914 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2915 }
2916
2917 /**
2918 * @brief Disable update DMA request.
2919 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2920 * @param LPTIMx Low-Power Timer instance
2921 * @retval None
2922 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2923 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2924 {
2925 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2926 }
2927
2928 /**
2929 * @brief Indicates whether the update DMA request is enabled.
2930 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2931 * @param LPTIMx Low-Power Timer instance
2932 * @retval State of bit (1 or 0).
2933 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2934 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2935 {
2936 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2937 }
2938
2939 /**
2940 * @brief Enable capture/compare 1 DMA request (CC1DE).
2941 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2942 * @param LPTIMx Low-Power Timer instance
2943 * @retval None
2944 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2945 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2946 {
2947 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2948 }
2949
2950 /**
2951 * @brief Disable capture/compare 1 DMA request (CC1DE).
2952 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2953 * @param LPTIMx Low-Power Timer instance
2954 * @retval None
2955 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2956 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2957 {
2958 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2959 }
2960
2961 /**
2962 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2963 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2964 * @param LPTIMx Low-Power Timer instance
2965 * @retval State of bit (1 or 0).
2966 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2967 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2968 {
2969 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2970 }
2971
2972 /**
2973 * @brief Enable capture/compare 2 DMA request (CC2DE).
2974 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2975 * @param LPTIMx Low-Power Timer instance
2976 * @retval None
2977 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2978 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2979 {
2980 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2981 }
2982
2983 /**
2984 * @brief Disable capture/compare 2 DMA request (CC2DE).
2985 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2986 * @param LPTIMx Low-Power Timer instance
2987 * @retval None
2988 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2989 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2990 {
2991 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2992 }
2993
2994 /**
2995 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2996 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2997 * @param LPTIMx Low-Power Timer instance
2998 * @retval State of bit (1 or 0).
2999 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)3000 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
3001 {
3002 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
3003 }
3004
3005 /**
3006 * @brief Enable capture/compare 3 DMA request (CC3DE).
3007 * @rmtoll DIER CC3DE LL_LPTIM_EnableDMAReq_CC3
3008 * @param LPTIMx Low-Power Timer instance
3009 * @retval None
3010 */
LL_LPTIM_EnableDMAReq_CC3(LPTIM_TypeDef * LPTIMx)3011 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC3(LPTIM_TypeDef *LPTIMx)
3012 {
3013 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC3DE);
3014 }
3015
3016 /**
3017 * @brief Disable capture/compare 3 DMA request (CC3DE).
3018 * @rmtoll DIER CC3DE LL_LPTIM_DisableDMAReq_CC3
3019 * @param LPTIMx Low-Power Timer instance
3020 * @retval None
3021 */
LL_LPTIM_DisableDMAReq_CC3(LPTIM_TypeDef * LPTIMx)3022 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC3(LPTIM_TypeDef *LPTIMx)
3023 {
3024 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC3DE);
3025 }
3026
3027 /**
3028 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3029 * @rmtoll DIER CC3DE LL_LPTIM_IsEnabledDMAReq_CC3
3030 * @param LPTIMx Low-Power Timer instance
3031 * @retval State of bit (1 or 0).
3032 */
LL_LPTIM_IsEnabledDMAReq_CC3(const LPTIM_TypeDef * LPTIMx)3033 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC3(const LPTIM_TypeDef *LPTIMx)
3034 {
3035 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC3DE) == (LPTIM_DIER_CC3DE)) ? 1UL : 0UL);
3036 }
3037
3038 /**
3039 * @brief Enable capture/compare 4 DMA request (CC4DE).
3040 * @rmtoll DIER CC4DE LL_LPTIM_EnableDMAReq_CC4
3041 * @param LPTIMx Low-Power Timer instance
3042 * @retval None
3043 */
LL_LPTIM_EnableDMAReq_CC4(LPTIM_TypeDef * LPTIMx)3044 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC4(LPTIM_TypeDef *LPTIMx)
3045 {
3046 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC4DE);
3047 }
3048
3049 /**
3050 * @brief Disable capture/compare 4 DMA request (CC4DE).
3051 * @rmtoll DIER CC4DE LL_LPTIM_DisableDMAReq_CC4
3052 * @param LPTIMx Low-Power Timer instance
3053 * @retval None
3054 */
LL_LPTIM_DisableDMAReq_CC4(LPTIM_TypeDef * LPTIMx)3055 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC4(LPTIM_TypeDef *LPTIMx)
3056 {
3057 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC4DE);
3058 }
3059
3060 /**
3061 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3062 * @rmtoll DIER CC4DE LL_LPTIM_IsEnabledDMAReq_CC4
3063 * @param LPTIMx Low-Power Timer instance
3064 * @retval State of bit (1 or 0).
3065 */
LL_LPTIM_IsEnabledDMAReq_CC4(const LPTIM_TypeDef * LPTIMx)3066 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC4(const LPTIM_TypeDef *LPTIMx)
3067 {
3068 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC4DE) == (LPTIM_DIER_CC4DE)) ? 1UL : 0UL);
3069 }
3070
3071 /**
3072 * @}
3073 */
3074 /**
3075 * @}
3076 */
3077
3078 /**
3079 * @}
3080 */
3081
3082 #endif /* LPTIM1 || LPTIM2 || LPTIM3 */
3083
3084 /**
3085 * @}
3086 */
3087
3088 #ifdef __cplusplus
3089 }
3090 #endif
3091
3092 #endif /* STM32U0xx_LL_LPTIM_H */
3093
