1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_LL_LPTIM_H
21 #define STM32H7RSxx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx.h"
29
30 /** @addtogroup STM32H7RSxx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45
46 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
47 {
48 0U, /* CC1P */
49 16U /* CC2P */
50 };
51
52 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
53 {
54 0U, /* IC1F */
55 16U /* IC2F */
56 };
57
58 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
59 {
60 0U, /* IC1PSC */
61 16U /* IC2PSC */
62 };
63
64 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
65 {
66 0U, /* CC1SEL */
67 16U /* CC2SEL */
68 };
69
70 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
71 {
72 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
73 LPTIM_CCMR1_CC2E_Pos /* CC2E */
74 };
75
76 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
77 {
78 {2, 7, 9, 13},
79 {3, 5, 6, 8},
80 {2, 3, 4, 5},
81 {2, 2, 3, 3},
82 {2, 2, 2, 2},
83 {2, 2, 2, 2},
84 {2, 2, 2, 2},
85 {2, 2, 2, 2}
86
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94
95 /* Private macros ------------------------------------------------------------*/
96 #if defined(USE_FULL_LL_DRIVER)
97 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
98 * @{
99 */
100 /**
101 * @}
102 */
103 #endif /*USE_FULL_LL_DRIVER*/
104
105 /* Exported types ------------------------------------------------------------*/
106 #if defined(USE_FULL_LL_DRIVER)
107 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
108 * @{
109 */
110
111 /**
112 * @brief LPTIM Init structure definition
113 */
114 typedef struct
115 {
116 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
117 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPTIM_SetClockSource().*/
121
122 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
123 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
124
125 This feature can be modified afterwards using using unitary
126 function @ref LL_LPTIM_SetPrescaler().*/
127
128 uint32_t Waveform; /*!< Specifies the waveform shape.
129 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPTIM_SetWaveform().*/
133 } LL_LPTIM_InitTypeDef;
134
135 /**
136 * @}
137 */
138 #endif /* USE_FULL_LL_DRIVER */
139
140 /* Exported constants --------------------------------------------------------*/
141 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
142 * @{
143 */
144
145 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
146 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
147 * @{
148 */
149 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
150 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
151 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
152 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
153 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
154 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
155 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
156 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
157 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
158 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
159 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
160 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
161 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
162 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_IT IT Defines
168 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
169 * @{
170 */
171 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
172 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
173 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
174 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
175 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
176 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
177 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
178 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
179 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
180 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
181 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
182 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
183 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
184 /**
185 * @}
186 */
187
188 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
189 * @{
190 */
191 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
192 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
193 /**
194 * @}
195 */
196
197 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
198 * @{
199 */
200 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
201 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
202 /**
203 * @}
204 */
205
206 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
207 * @{
208 */
209 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
210 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
211 /**
212 * @}
213 */
214
215 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
216 * @{
217 */
218 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
219 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
220 /**
221 * @}
222 */
223
224 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
225 * @{
226 */
227 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
228 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
229 /**
230 * @}
231 */
232
233 /** @defgroup TIM_LL_EC_CHANNEL Channel
234 * @{
235 */
236 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
237 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
238 /**
239 * @}
240 */
241
242 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
243 * @{
244 */
245 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
246 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
247 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
248 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
249 /**
250 * @}
251 */
252
253 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
254 * @{
255 */
256 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
257 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
258 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
259 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
260 /**
261 * @}
262 */
263
264 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
265 * @{
266 */
267 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
268 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
269 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
270 /**
271 * @}
272 */
273 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
274 * @{
275 */
276 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
277 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
278 /**
279 * @}
280 */
281
282 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
283 * @{
284 */
285 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
286 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
287 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
288 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
289 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
290 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
291 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
292 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
293 /**
294 * @}
295 */
296
297 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
298 * @{
299 */
300 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
301 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
302 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
303 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
304 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
305 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
306 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI1 FS A output */
307 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to SAI1 FS B output */
308 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI2 FS A output */
309 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to SAI2 FS B output */
310 #define LL_LPTIM3_TRIG_SOURCE_LPTIM2_CH1 LPTIM_CFGR_TRIGSEL_1 /*!<LPTIM3 External input trigger is connected to LPTIM2 Channel 1 */
311 #define LL_LPTIM3_TRIG_SOURCE_LPTIM4 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<LPTIM3 External input trigger is connected to LPTIM4 output */
312 #define LL_LPTIM3_TRIG_SOURCE_LPTIM5 LPTIM_CFGR_TRIGSEL_2 /*!<LPTIM3 External input trigger is connected to LPTIM5 output */
313 #define LL_LPTIM4_TRIG_SOURCE_LPTIM2_CH1 LPTIM_CFGR_TRIGSEL_0 /*!<LPTIM4 External input trigger is connected to LPTIM2 Channel 1 */
314 #define LL_LPTIM4_TRIG_SOURCE_LPTIM3_CH1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<LPTIM4 External input trigger is connected to LPTIM3 Channel 1 */
315 #define LL_LPTIM4_TRIG_SOURCE_LPTIM5 LPTIM_CFGR_TRIGSEL_2 /*!<LPTIM4 External input trigger is connected to LPTIM5 output */
316 #define LL_LPTIM5_TRIG_SOURCE_LPTIM2_CH1 LPTIM_CFGR_TRIGSEL_0 /*!<LPTIM5 External input trigger is connected to LPTIM2 Channel 1 */
317 #define LL_LPTIM5_TRIG_SOURCE_LPTIM3_CH1 LPTIM_CFGR_TRIGSEL_1 /*!<LPTIM5 External input trigger is connected to LPTIM3 Channel 1 */
318 #define LL_LPTIM5_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_2 /*!<LPTIM5 External input trigger is connected to LPTIM4 output */
319 /**
320 * @}
321 */
322
323 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
324 * @{
325 */
326 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
327 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
328 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
329 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
330 /**
331 * @}
332 */
333
334 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
335 * @{
336 */
337 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
338 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
339 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
340 /**
341 * @}
342 */
343
344 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
345 * @{
346 */
347 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
348 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
349 /**
350 * @}
351 */
352
353 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
354 * @{
355 */
356 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
357 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
358 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
359 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
360 /**
361 * @}
362 */
363
364 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
365 * @{
366 */
367 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
368 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
369 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
370 /**
371 * @}
372 */
373
374 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
375 * @{
376 */
377 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
378 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
379 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
380 /**
381 * @}
382 */
383
384 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
385 * @{
386 */
387 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */
388 /**
389 * @}
390 */
391
392 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
393 * @{
394 */
395 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */
396 /**
397 * @}
398 */
399
400 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
401 * @{
402 */
403 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
404 /**
405 * @}
406 */
407
408 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
409 * @{
410 */
411 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
412 #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
413 #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
414 /**
415 * @}
416 */
417
418 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
419 * @{
420 */
421 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
422 /**
423 * @}
424 */
425
426 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
427 * @{
428 */
429 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
430 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI/1024 */
431 #define LL_LPTIM_LPTIM2_IC2_RMP_CSI_128 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to CSI/128 */
432 /**
433 * @}
434 */
435
436 /** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
437 * @{
438 */
439 #define LL_LPTIM_LPTIM3_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
440 /**
441 * @}
442 */
443
444 /** @defgroup LPTIM_EC_LPTIM3_IC2_RMP LPTIM3 Input Ch2 Remap
445 * @{
446 */
447
448 #define LL_LPTIM_LPTIM3_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
449 /**
450 * @}
451 */
452
453
454 /**
455 * @}
456 */
457
458 /* Exported macro ------------------------------------------------------------*/
459 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
460 * @{
461 */
462
463 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
464 * @{
465 */
466
467 /**
468 * @brief Write a value in LPTIM register
469 * @param __INSTANCE__ LPTIM Instance
470 * @param __REG__ Register to be written
471 * @param __VALUE__ Value to be written in the register
472 * @retval None
473 */
474 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
475
476 /**
477 * @brief Read a value in LPTIM register
478 * @param __INSTANCE__ LPTIM Instance
479 * @param __REG__ Register to be read
480 * @retval Register value
481 */
482 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
483
484 /**
485 * @brief LPTimer Input Capture Get Offset(in counter step unit)
486 * @note The real capture value corresponding to the input capture trigger can be calculated using
487 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
488 * The Offset value is depending on the glitch filter value for the channel
489 * and the value of the prescaler for the kernel clock.
490 * Please check Errata Sheet V1_8 for more details under "variable latency
491 * on input capture channel" section.
492 * @param __PSC__ This parameter can be one of the following values:
493 * @arg @ref LL_LPTIM_PRESCALER_DIV1
494 * @arg @ref LL_LPTIM_PRESCALER_DIV2
495 * @arg @ref LL_LPTIM_PRESCALER_DIV4
496 * @arg @ref LL_LPTIM_PRESCALER_DIV8
497 * @arg @ref LL_LPTIM_PRESCALER_DIV16
498 * @arg @ref LL_LPTIM_PRESCALER_DIV32
499 * @arg @ref LL_LPTIM_PRESCALER_DIV64
500 * @arg @ref LL_LPTIM_PRESCALER_DIV128
501 * @param __FLT__ This parameter can be one of the following values:
502 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
503 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
504 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
505 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
506 * @retval offset value
507 */
508 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
509 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
510 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
511 /**
512 * @}
513 */
514
515 /**
516 * @}
517 */
518
519 /* Exported functions --------------------------------------------------------*/
520 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
521 * @{
522 */
523
524 /** Legacy definitions for compatibility purpose
525 @cond 0
526 */
527 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
528 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
529 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
530 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
531 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
532 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
533 /**
534 @endcond
535 */
536
537 #if defined(USE_FULL_LL_DRIVER)
538 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
539 * @{
540 */
541
542 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
543 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
544 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
545 /**
546 * @}
547 */
548 #endif /* USE_FULL_LL_DRIVER */
549
550 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
551 * @{
552 */
553
554 /**
555 * @brief Enable the LPTIM instance
556 * @note After setting the ENABLE bit, a delay of two counter clock is needed
557 * before the LPTIM instance is actually enabled.
558 * @rmtoll CR ENABLE LL_LPTIM_Enable
559 * @param LPTIMx Low-Power Timer instance
560 * @retval None
561 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)562 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
563 {
564 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
565 }
566
567 /**
568 * @brief Disable the LPTIM instance
569 * @rmtoll CR ENABLE LL_LPTIM_Disable
570 * @param LPTIMx Low-Power Timer instance
571 * @retval None
572 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)573 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
574 {
575 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
576 }
577
578 /**
579 * @brief Indicates whether the LPTIM instance is enabled.
580 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
581 * @param LPTIMx Low-Power Timer instance
582 * @retval State of bit (1 or 0).
583 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)584 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
585 {
586 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
587 }
588
589 /**
590 * @brief Starts the LPTIM counter in the desired mode.
591 * @note LPTIM instance must be enabled before starting the counter.
592 * @note It is possible to change on the fly from One Shot mode to
593 * Continuous mode.
594 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
595 * CR SNGSTRT LL_LPTIM_StartCounter
596 * @param LPTIMx Low-Power Timer instance
597 * @param OperatingMode This parameter can be one of the following values:
598 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
599 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
600 * @retval None
601 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)602 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
603 {
604 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
605 }
606
607 /**
608 * @brief Enable reset after read.
609 * @note After calling this function any read access to LPTIM_CNT
610 * register will asynchronously reset the LPTIM_CNT register content.
611 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
612 * @param LPTIMx Low-Power Timer instance
613 * @retval None
614 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)615 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
616 {
617 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
618 }
619
620 /**
621 * @brief Disable reset after read.
622 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
623 * @param LPTIMx Low-Power Timer instance
624 * @retval None
625 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)626 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
627 {
628 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
629 }
630
631 /**
632 * @brief Indicate whether the reset after read feature is enabled.
633 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
634 * @param LPTIMx Low-Power Timer instance
635 * @retval State of bit (1 or 0).
636 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)637 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
638 {
639 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
640 }
641
642 /**
643 * @brief Reset of the LPTIM_CNT counter register (synchronous).
644 * @note Due to the synchronous nature of this reset, it only takes
645 * place after a synchronization delay of 3 LPTIM core clock cycles
646 * (LPTIM core clock may be different from APB clock).
647 * @note COUNTRST is automatically cleared by hardware
648 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
649 * @param LPTIMx Low-Power Timer instance
650 * @retval None
651 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)652 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
653 {
654 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
655 }
656
657 /**
658 * @brief Set the LPTIM registers update mode (enable/disable register preload)
659 * @note This function must be called when the LPTIM instance is disabled.
660 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
661 * @param LPTIMx Low-Power Timer instance
662 * @param UpdateMode This parameter can be one of the following values:
663 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
664 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
665 * @retval None
666 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)667 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
668 {
669 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
670 }
671
672 /**
673 * @brief Get the LPTIM registers update mode
674 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
675 * @param LPTIMx Low-Power Timer instance
676 * @retval Returned value can be one of the following values:
677 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
678 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
679 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)680 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
681 {
682 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
683 }
684
685 /**
686 * @brief Set the auto reload value
687 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
688 * @note After a write to the LPTIMx_ARR register a new write operation to the
689 * same register can only be performed when the previous write operation
690 * is completed. Any successive write before the ARROK flag is set, will
691 * lead to unpredictable results.
692 * @note autoreload value be strictly greater than the compare value.
693 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
694 * @param LPTIMx Low-Power Timer instance
695 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
696 * @retval None
697 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)698 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
699 {
700 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
701 }
702
703 /**
704 * @brief Get actual auto reload value
705 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
706 * @param LPTIMx Low-Power Timer instance
707 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
708 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)709 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
710 {
711 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
712 }
713
714 /**
715 * @brief Set the repetition value
716 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
717 * @rmtoll RCR REP LL_LPTIM_SetRepetition
718 * @param LPTIMx Low-Power Timer instance
719 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
720 * @retval None
721 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)722 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
723 {
724 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
725 }
726
727 /**
728 * @brief Get the repetition value
729 * @rmtoll RCR REP LL_LPTIM_GetRepetition
730 * @param LPTIMx Low-Power Timer instance
731 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
732 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)733 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
734 {
735 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
736 }
737
738 /**
739 * @brief Enable capture/compare channel.
740 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
741 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
742 * @param LPTIMx LPTimer instance
743 * @param Channel This parameter can be one of the following values:
744 * @arg @ref LL_LPTIM_CHANNEL_CH1
745 * @arg @ref LL_LPTIM_CHANNEL_CH2
746 * @retval None
747 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)748 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
749 {
750 SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
751 }
752
753 /**
754 * @brief Disable capture/compare channel.
755 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
756 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
757 * @param LPTIMx LPTimer instance
758 * @param Channel This parameter can be one of the following values:
759 * @arg @ref LL_LPTIM_CHANNEL_CH1
760 * @arg @ref LL_LPTIM_CHANNEL_CH2
761 * @retval None
762 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)763 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
764 {
765 CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
766 }
767
768 /**
769 * @brief Indicate whether channel is enabled.
770 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
771 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
772 * @param LPTIMx LPTimer instance
773 * @param Channel This parameter can be one of the following values:
774 * @arg @ref LL_LPTIM_CHANNEL_CH1
775 * @arg @ref LL_LPTIM_CHANNEL_CH2
776 * @retval State of bit (1 or 0).
777 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)778 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
779 {
780 return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
781 (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
782
783 }
784
785 /**
786 * @brief Set the compare value
787 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
788 * same register can only be performed when the previous write operation
789 * is completed. Any successive write before the CMP1OK flag is set, will
790 * lead to unpredictable results.
791 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
792 * @param LPTIMx Low-Power Timer instance
793 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
794 * @retval None
795 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)796 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
797 {
798 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
799 }
800
801 /**
802 * @brief Get actual compare value
803 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
804 * @param LPTIMx Low-Power Timer instance
805 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
806 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)807 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
808 {
809 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
810 }
811
812 /**
813 * @brief Set the compare value
814 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
815 * same register can only be performed when the previous write operation
816 * is completed. Any successive write before the CMP2OK flag is set, will
817 * lead to unpredictable results.
818 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
819 * @param LPTIMx Low-Power Timer instance
820 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
821 * @retval None
822 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)823 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
824 {
825 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
826 }
827
828 /**
829 * @brief Get actual compare value
830 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
831 * @param LPTIMx Low-Power Timer instance
832 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
833 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)834 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
835 {
836 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
837 }
838
839 /**
840 * @brief Get actual counter value
841 * @note When the LPTIM instance is running with an asynchronous clock, reading
842 * the LPTIMx_CNT register may return unreliable values. So in this case
843 * it is necessary to perform two consecutive read accesses and verify
844 * that the two returned values are identical.
845 * @rmtoll CNT CNT LL_LPTIM_GetCounter
846 * @param LPTIMx Low-Power Timer instance
847 * @retval Counter value
848 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)849 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
850 {
851 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
852 }
853
854 /**
855 * @brief Set the counter mode (selection of the LPTIM counter clock source).
856 * @note The counter mode can be set only when the LPTIM instance is disabled.
857 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
858 * @param LPTIMx Low-Power Timer instance
859 * @param CounterMode This parameter can be one of the following values:
860 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
861 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
862 * @retval None
863 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)864 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
865 {
866 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
867 }
868
869 /**
870 * @brief Get the counter mode
871 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
872 * @param LPTIMx Low-Power Timer instance
873 * @retval Returned value can be one of the following values:
874 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
875 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
876 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)877 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
878 {
879 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
880 }
881
882 /**
883 * @brief Set waveform shape
884 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
885 * @param LPTIMx Low-Power Timer instance
886 * @param Waveform This parameter can be one of the following values:
887 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
888 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
889 * @retval None
890 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)891 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
892 {
893 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
894 }
895
896 /**
897 * @brief Get actual waveform shape
898 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
899 * @param LPTIMx Low-Power Timer instance
900 * @retval Returned value can be one of the following values:
901 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
902 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
903 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)904 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
905 {
906 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
907 }
908
909 /**
910 * @brief Set the polarity of an output channel.
911 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
912 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
913 * @param LPTIMx Low-Power Timer instance
914 * @param Channel This parameter can be one of the following values:
915 * @arg @ref LL_LPTIM_CHANNEL_CH1
916 * @arg @ref LL_LPTIM_CHANNEL_CH2
917 * @param Polarity This parameter can be one of the following values:
918 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
919 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
920 * @retval None
921 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)922 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
923 {
924 if ((LPTIMx == LPTIM4) || (LPTIMx == LPTIM5))
925 {
926 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
927 }
928 else
929 {
930 MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
931 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
932 }
933 }
934
935 /**
936 * @brief Get the polarity of an output channel.
937 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
938 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
939 * @param LPTIMx Low-Power Timer instance
940 * @param Channel This parameter can be one of the following values:
941 * @arg @ref LL_LPTIM_CHANNEL_CH1
942 * @arg @ref LL_LPTIM_CHANNEL_CH2
943 * @retval Returned value can be one of the following values:
944 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
945 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
946 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)947 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
948 {
949 if ((LPTIMx == LPTIM4) || (LPTIMx == LPTIM5))
950 {
951 return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
952 }
953 else
954 {
955 return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \
956 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
957 }
958 }
959
960 /**
961 * @brief Set actual prescaler division ratio.
962 * @note This function must be called when the LPTIM instance is disabled.
963 * @note When the LPTIM is configured to be clocked by an internal clock source
964 * and the LPTIM counter is configured to be updated by active edges
965 * detected on the LPTIM external Input1, the internal clock provided to
966 * the LPTIM must be not be prescaled.
967 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
968 * @param LPTIMx Low-Power Timer instance
969 * @param Prescaler This parameter can be one of the following values:
970 * @arg @ref LL_LPTIM_PRESCALER_DIV1
971 * @arg @ref LL_LPTIM_PRESCALER_DIV2
972 * @arg @ref LL_LPTIM_PRESCALER_DIV4
973 * @arg @ref LL_LPTIM_PRESCALER_DIV8
974 * @arg @ref LL_LPTIM_PRESCALER_DIV16
975 * @arg @ref LL_LPTIM_PRESCALER_DIV32
976 * @arg @ref LL_LPTIM_PRESCALER_DIV64
977 * @arg @ref LL_LPTIM_PRESCALER_DIV128
978 * @retval None
979 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)980 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
981 {
982 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
983 }
984
985 /**
986 * @brief Get actual prescaler division ratio.
987 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
988 * @param LPTIMx Low-Power Timer instance
989 * @retval Returned value can be one of the following values:
990 * @arg @ref LL_LPTIM_PRESCALER_DIV1
991 * @arg @ref LL_LPTIM_PRESCALER_DIV2
992 * @arg @ref LL_LPTIM_PRESCALER_DIV4
993 * @arg @ref LL_LPTIM_PRESCALER_DIV8
994 * @arg @ref LL_LPTIM_PRESCALER_DIV16
995 * @arg @ref LL_LPTIM_PRESCALER_DIV32
996 * @arg @ref LL_LPTIM_PRESCALER_DIV64
997 * @arg @ref LL_LPTIM_PRESCALER_DIV128
998 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)999 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
1000 {
1001 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
1002 }
1003
1004 /**
1005 * @brief Set LPTIM input 1 source (default GPIO).
1006 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
1007 * @param LPTIMx Low-Power Timer instance
1008 * @param Src This parameter can be one of the following values:
1009 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
1010 * @retval None
1011 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1012 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1013 {
1014 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
1015 }
1016
1017 /**
1018 * @brief Set LPTIM input 2 source (default GPIO).
1019 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
1020 * @param LPTIMx Low-Power Timer instance
1021 * @param Src This parameter can be one of the following values:
1022 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1023 * @retval None
1024 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1025 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1026 {
1027 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1028 }
1029
1030 /**
1031 * @brief Set LPTIM input source (default GPIO).
1032 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
1033 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
1034 * @param LPTIMx Low-Power Timer instance
1035 * @param Src This parameter can be one of the following values:
1036 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1037 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1038 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
1039 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
1040 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1041 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1042 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024
1043 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_CSI_128
1044 * @retval None
1045 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1046 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1047 {
1048 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
1049 }
1050
1051 /**
1052 * @brief Set the polarity of IC channel 1.
1053 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1054 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1055 * @param LPTIMx Low-Power Timer instance
1056 * @param Channel This parameter can be one of the following values:
1057 * @arg @ref LL_LPTIM_CHANNEL_CH1
1058 * @arg @ref LL_LPTIM_CHANNEL_CH2
1059 * @param Polarity This parameter can be one of the following values:
1060 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1061 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1062 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1063 * @retval None
1064 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1065 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1066 {
1067 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
1068 Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1069 }
1070
1071 /**
1072 * @brief Get the polarity of IC channels.
1073 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1074 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1075 * @param LPTIMx Low-Power Timer instance
1076 * @param Channel This parameter can be one of the following values:
1077 * @arg @ref LL_LPTIM_CHANNEL_CH1
1078 * @arg @ref LL_LPTIM_CHANNEL_CH2
1079 * @retval Returned value can be one of the following values:
1080 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1081 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1082 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1083 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1084 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1085 {
1086 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1087 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1088
1089 }
1090
1091 /**
1092 * @brief Set the filter of IC channels.
1093 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1094 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1095 * @param LPTIMx Low-Power Timer instance
1096 * @param Channel This parameter can be one of the following values:
1097 * @arg @ref LL_LPTIM_CHANNEL_CH1
1098 * @arg @ref LL_LPTIM_CHANNEL_CH2
1099 * @param Filter This parameter can be one of the following values:
1100 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1101 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1102 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1103 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1104 * @retval None
1105 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1106 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1107 {
1108 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
1109 Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1110 }
1111
1112 /**
1113 * @brief Get the filter of IC channels.
1114 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1115 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1116 * @param LPTIMx Low-Power Timer instance
1117 * @param Channel This parameter can be one of the following values:
1118 * @arg @ref LL_LPTIM_CHANNEL_CH1
1119 * @arg @ref LL_LPTIM_CHANNEL_CH2
1120 * @retval Returned value can be one of the following values:
1121 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1122 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1123 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1124 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1125 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1126 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1127 {
1128 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1129 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1130 }
1131
1132 /**
1133 * @brief Set the prescaler of IC channels.
1134 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1135 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1136 * @param LPTIMx Low-Power Timer instance
1137 * @param Channel This parameter can be one of the following values:
1138 * @arg @ref LL_LPTIM_CHANNEL_CH1
1139 * @arg @ref LL_LPTIM_CHANNEL_CH2
1140 * @param Prescaler This parameter can be one of the following values:
1141 * @arg @ref LL_LPTIM_ICPSC_DIV1
1142 * @arg @ref LL_LPTIM_ICPSC_DIV2
1143 * @arg @ref LL_LPTIM_ICPSC_DIV4
1144 * @arg @ref LL_LPTIM_ICPSC_DIV8
1145 * @retval None
1146 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1147 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1148 {
1149 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1150 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1151 }
1152
1153 /**
1154 * @brief Get the prescaler of IC channels.
1155 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1156 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1157 * @param LPTIMx Low-Power Timer instance
1158 * @param Channel This parameter can be one of the following values:
1159 * @arg @ref LL_LPTIM_CHANNEL_CH1
1160 * @arg @ref LL_LPTIM_CHANNEL_CH2
1161 * @retval Returned value can be one of the following values:
1162 * @arg @ref LL_LPTIM_ICPSC_DIV1
1163 * @arg @ref LL_LPTIM_ICPSC_DIV2
1164 * @arg @ref LL_LPTIM_ICPSC_DIV4
1165 * @arg @ref LL_LPTIM_ICPSC_DIV8
1166 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1167 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1168 {
1169 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1170 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1171 }
1172
1173 /**
1174 * @brief Set the Channel Mode.
1175 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1176 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
1177 * @param LPTIMx Low-Power Timer instance
1178 * @param Channel This parameter can be one of the following values:
1179 * @arg @ref LL_LPTIM_CHANNEL_CH1
1180 * @arg @ref LL_LPTIM_CHANNEL_CH2
1181 * @param CCMode This parameter can be one of the following values:
1182 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1183 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1184 * @retval None
1185 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1186 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1187 {
1188 SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1189 }
1190
1191 /**
1192 * @brief Get the Channel Mode.
1193 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1194 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
1195 * @param LPTIMx Low-Power Timer instance
1196 * @param Channel This parameter can be one of the following values:
1197 * @arg @ref LL_LPTIM_CHANNEL_CH1
1198 * @arg @ref LL_LPTIM_CHANNEL_CH2
1199 * @retval Returned value can be one of the following values:
1200 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1201 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1202 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1203 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1204 {
1205 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1206 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1207 }
1208
1209 /**
1210 * @brief Get captured value for input channel 1.
1211 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1212 * @note The real capture value corresponding to the input capture trigger can be calculated using
1213 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1214 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1215 * @param LPTIMx Low-Power Timer instance
1216 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1217 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1218 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1219 {
1220 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1221 }
1222
1223 /**
1224 * @brief Get captured value for input channel 2.
1225 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1226 * @note The real capture value corresponding to the input capture trigger can be calculated using
1227 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1228 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1229 * @param LPTIMx Low-Power Timer instance
1230 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1231 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1232 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1233 {
1234 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1235 }
1236
1237 /**
1238 * @}
1239 */
1240
1241 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1242 * @{
1243 */
1244
1245 /**
1246 * @brief Enable the timeout function
1247 * @note This function must be called when the LPTIM instance is disabled.
1248 * @note The first trigger event will start the timer, any successive trigger
1249 * event will reset the counter and the timer will restart.
1250 * @note The timeout value corresponds to the compare value; if no trigger
1251 * occurs within the expected time frame, the MCU is waked-up by the
1252 * compare match event.
1253 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1254 * @param LPTIMx Low-Power Timer instance
1255 * @retval None
1256 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1257 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1258 {
1259 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1260 }
1261
1262 /**
1263 * @brief Disable the timeout function
1264 * @note This function must be called when the LPTIM instance is disabled.
1265 * @note A trigger event arriving when the timer is already started will be
1266 * ignored.
1267 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1268 * @param LPTIMx Low-Power Timer instance
1269 * @retval None
1270 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1271 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1272 {
1273 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1274 }
1275
1276 /**
1277 * @brief Indicate whether the timeout function is enabled.
1278 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1279 * @param LPTIMx Low-Power Timer instance
1280 * @retval State of bit (1 or 0).
1281 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1282 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1283 {
1284 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1285 }
1286
1287 /**
1288 * @brief Start the LPTIM counter
1289 * @note This function must be called when the LPTIM instance is disabled.
1290 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1291 * @param LPTIMx Low-Power Timer instance
1292 * @retval None
1293 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1294 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1295 {
1296 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1297 }
1298
1299 /**
1300 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1301 * @note This function must be called when the LPTIM instance is disabled.
1302 * @note An internal clock source must be present when a digital filter is
1303 * required for the trigger.
1304 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1305 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1306 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1307 * @param LPTIMx Low-Power Timer instance
1308 * @param Source This parameter can be one of the following values:
1309 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1310 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1311 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1312 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1313 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1314 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1315 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A
1316 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B
1317 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A
1318 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B
1319 * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM2_CH1
1320 * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM4
1321 * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM5
1322 * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM2_CH1
1323 * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM3_CH1
1324 * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM5
1325 * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM2_CH1
1326 * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM3_CH1
1327 * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM4
1328 * @param Filter This parameter can be one of the following values:
1329 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1330 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1331 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1332 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1333 * @param Polarity This parameter can be one of the following values:
1334 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1335 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1336 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1337 * @retval None
1338 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1339 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1340 {
1341 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1342 }
1343
1344 /**
1345 * @brief Get actual external trigger source.
1346 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1347 * @param LPTIMx Low-Power Timer instance
1348 * @retval Returned value can be one of the following values:
1349 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1350 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1351 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1352 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1353 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1354 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1355 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A
1356 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B
1357 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A
1358 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B
1359 * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM2_CH1
1360 * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM4
1361 * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM5
1362 * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM2_CH1
1363 * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM3_CH1
1364 * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM5
1365 * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM2_CH1
1366 * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM3_CH1
1367 * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM4
1368 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1369 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1370 {
1371 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1372 }
1373
1374 /**
1375 * @brief Get actual external trigger filter.
1376 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1377 * @param LPTIMx Low-Power Timer instance
1378 * @retval Returned value can be one of the following values:
1379 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1380 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1381 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1382 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1383 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1384 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1385 {
1386 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1387 }
1388
1389 /**
1390 * @brief Get actual external trigger polarity.
1391 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1392 * @param LPTIMx Low-Power Timer instance
1393 * @retval Returned value can be one of the following values:
1394 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1395 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1396 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1397 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1398 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1399 {
1400 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1401 }
1402
1403 /**
1404 * @}
1405 */
1406
1407 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1408 * @{
1409 */
1410
1411 /**
1412 * @brief Set the source of the clock used by the LPTIM instance.
1413 * @note This function must be called when the LPTIM instance is disabled.
1414 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1415 * @param LPTIMx Low-Power Timer instance
1416 * @param ClockSource This parameter can be one of the following values:
1417 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1418 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1419 * @retval None
1420 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1421 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1422 {
1423 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1424 }
1425
1426 /**
1427 * @brief Get actual LPTIM instance clock source.
1428 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1429 * @param LPTIMx Low-Power Timer instance
1430 * @retval Returned value can be one of the following values:
1431 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1432 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1433 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1434 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1435 {
1436 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1437 }
1438
1439 /**
1440 * @brief Configure the active edge or edges used by the counter when
1441 the LPTIM is clocked by an external clock source.
1442 * @note This function must be called when the LPTIM instance is disabled.
1443 * @note When both external clock signal edges are considered active ones,
1444 * the LPTIM must also be clocked by an internal clock source with a
1445 * frequency equal to at least four times the external clock frequency.
1446 * @note An internal clock source must be present when a digital filter is
1447 * required for external clock.
1448 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1449 * CFGR CKPOL LL_LPTIM_ConfigClock
1450 * @param LPTIMx Low-Power Timer instance
1451 * @param ClockFilter This parameter can be one of the following values:
1452 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1453 * @arg @ref LL_LPTIM_CLK_FILTER_2
1454 * @arg @ref LL_LPTIM_CLK_FILTER_4
1455 * @arg @ref LL_LPTIM_CLK_FILTER_8
1456 * @param ClockPolarity This parameter can be one of the following values:
1457 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1458 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1459 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1460 * @retval None
1461 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1462 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1463 {
1464 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1465 }
1466
1467 /**
1468 * @brief Get actual clock polarity
1469 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1470 * @param LPTIMx Low-Power Timer instance
1471 * @retval Returned value can be one of the following values:
1472 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1473 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1474 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1475 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1476 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1477 {
1478 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1479 }
1480
1481 /**
1482 * @brief Get actual clock digital filter
1483 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1484 * @param LPTIMx Low-Power Timer instance
1485 * @retval Returned value can be one of the following values:
1486 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1487 * @arg @ref LL_LPTIM_CLK_FILTER_2
1488 * @arg @ref LL_LPTIM_CLK_FILTER_4
1489 * @arg @ref LL_LPTIM_CLK_FILTER_8
1490 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1491 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1492 {
1493 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1494 }
1495
1496 /**
1497 * @}
1498 */
1499
1500 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1501 * @{
1502 */
1503
1504 /**
1505 * @brief Configure the encoder mode.
1506 * @note This function must be called when the LPTIM instance is disabled.
1507 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1508 * @param LPTIMx Low-Power Timer instance
1509 * @param EncoderMode This parameter can be one of the following values:
1510 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1511 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1512 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1513 * @retval None
1514 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1515 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1516 {
1517 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1518 }
1519
1520 /**
1521 * @brief Get actual encoder mode.
1522 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1523 * @param LPTIMx Low-Power Timer instance
1524 * @retval Returned value can be one of the following values:
1525 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1526 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1527 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1528 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1529 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1530 {
1531 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1532 }
1533
1534 /**
1535 * @brief Enable the encoder mode
1536 * @note This function must be called when the LPTIM instance is disabled.
1537 * @note In this mode the LPTIM instance must be clocked by an internal clock
1538 * source. Also, the prescaler division ratio must be equal to 1.
1539 * @note LPTIM instance must be configured in continuous mode prior enabling
1540 * the encoder mode.
1541 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1542 * @param LPTIMx Low-Power Timer instance
1543 * @retval None
1544 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1545 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1546 {
1547 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1548 }
1549
1550 /**
1551 * @brief Disable the encoder mode
1552 * @note This function must be called when the LPTIM instance is disabled.
1553 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1554 * @param LPTIMx Low-Power Timer instance
1555 * @retval None
1556 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1557 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1558 {
1559 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1560 }
1561
1562 /**
1563 * @brief Indicates whether the LPTIM operates in encoder mode.
1564 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1565 * @param LPTIMx Low-Power Timer instance
1566 * @retval State of bit (1 or 0).
1567 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1568 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1569 {
1570 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1571 }
1572
1573 /**
1574 * @}
1575 */
1576
1577 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1578 * @{
1579 */
1580
1581 /**
1582 * @brief Clear the compare match flag for channel 1 (CC1CF)
1583 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1584 * @param LPTIMx Low-Power Timer instance
1585 * @retval None
1586 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1587 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1588 {
1589 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1590 }
1591
1592 /**
1593 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1594 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1595 * @param LPTIMx Low-Power Timer instance
1596 * @retval State of bit (1 or 0).
1597 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1598 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1599 {
1600 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1601 }
1602
1603 /**
1604 * @brief Clear the compare match flag for channel 2 (CC2CF)
1605 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1606 * @param LPTIMx Low-Power Timer instance
1607 * @retval None
1608 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1609 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1610 {
1611 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1612 }
1613
1614 /**
1615 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1616 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1617 * @param LPTIMx Low-Power Timer instance
1618 * @retval State of bit (1 or 0).
1619 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1620 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1621 {
1622 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1623 }
1624
1625 /**
1626 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1627 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1628 * @param LPTIMx Low-Power Timer instance
1629 * @retval None
1630 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1631 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1632 {
1633 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1634 }
1635
1636 /**
1637 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1638 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1639 * @param LPTIMx Low-Power Timer instance
1640 * @retval State of bit (1 or 0).
1641 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1642 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1643 {
1644 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1645 }
1646
1647 /**
1648 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1649 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1650 * @param LPTIMx Low-Power Timer instance
1651 * @retval None
1652 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1653 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1654 {
1655 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1656 }
1657
1658 /**
1659 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1660 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1661 * @param LPTIMx Low-Power Timer instance
1662 * @retval State of bit (1 or 0).
1663 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1664 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1665 {
1666 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1667 }
1668 /**
1669 * @brief Clear the autoreload match flag (ARRMCF)
1670 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1671 * @param LPTIMx Low-Power Timer instance
1672 * @retval None
1673 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1674 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1675 {
1676 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1677 }
1678
1679 /**
1680 * @brief Inform application whether a autoreload match interrupt has occurred.
1681 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1682 * @param LPTIMx Low-Power Timer instance
1683 * @retval State of bit (1 or 0).
1684 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1685 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1686 {
1687 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1688 }
1689
1690 /**
1691 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1692 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1693 * @param LPTIMx Low-Power Timer instance
1694 * @retval None
1695 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1696 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1697 {
1698 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1699 }
1700
1701 /**
1702 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1703 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1704 * @param LPTIMx Low-Power Timer instance
1705 * @retval State of bit (1 or 0).
1706 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1707 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1708 {
1709 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1710 }
1711
1712 /**
1713 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
1714 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
1715 * @param LPTIMx Low-Power Timer instance
1716 * @retval None
1717 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)1718 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
1719 {
1720 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
1721 }
1722
1723 /**
1724 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
1725 completed. If so, a new one can be initiated.
1726 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
1727 * @param LPTIMx Low-Power Timer instance
1728 * @retval State of bit (1 or 0).
1729 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)1730 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
1731 {
1732 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
1733 }
1734
1735 /**
1736 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
1737 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
1738 * @param LPTIMx Low-Power Timer instance
1739 * @retval None
1740 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)1741 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
1742 {
1743 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
1744 }
1745
1746 /**
1747 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
1748 completed. If so, a new one can be initiated.
1749 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
1750 * @param LPTIMx Low-Power Timer instance
1751 * @retval State of bit (1 or 0).
1752 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)1753 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
1754 {
1755 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
1756 }
1757
1758 /**
1759 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
1760 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
1761 * @param LPTIMx Low-Power Timer instance
1762 * @retval None
1763 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)1764 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
1765 {
1766 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
1767 }
1768
1769 /**
1770 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
1771 completed. If so, a new one can be initiated.
1772 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
1773 * @param LPTIMx Low-Power Timer instance
1774 * @retval State of bit (1 or 0).
1775 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)1776 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
1777 {
1778 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
1779 }
1780
1781 /**
1782 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1783 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1784 * @param LPTIMx Low-Power Timer instance
1785 * @retval None
1786 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1787 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1788 {
1789 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1790 }
1791
1792 /**
1793 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1794 completed. If so, a new one can be initiated.
1795 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1796 * @param LPTIMx Low-Power Timer instance
1797 * @retval State of bit (1 or 0).
1798 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1799 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1800 {
1801 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1802 }
1803
1804 /**
1805 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1806 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1807 * @param LPTIMx Low-Power Timer instance
1808 * @retval None
1809 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1810 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1811 {
1812 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1813 }
1814
1815 /**
1816 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1817 operates in encoder mode).
1818 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1819 * @param LPTIMx Low-Power Timer instance
1820 * @retval State of bit (1 or 0).
1821 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1822 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1823 {
1824 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1825 }
1826
1827 /**
1828 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1829 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1830 * @param LPTIMx Low-Power Timer instance
1831 * @retval None
1832 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1833 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1834 {
1835 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1836 }
1837
1838 /**
1839 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1840 operates in encoder mode).
1841 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1842 * @param LPTIMx Low-Power Timer instance
1843 * @retval State of bit (1 or 0).
1844 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1845 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1846 {
1847 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1848 }
1849
1850 /**
1851 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1852 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1853 * @param LPTIMx Low-Power Timer instance
1854 * @retval None
1855 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1856 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1857 {
1858 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1859 }
1860
1861 /**
1862 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1863 completed; If so, a new one can be initiated.
1864 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1865 * @param LPTIMx Low-Power Timer instance
1866 * @retval State of bit (1 or 0).
1867 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1868 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1869 {
1870 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1871 }
1872
1873 /**
1874 * @brief Clear the update event flag (UECF).
1875 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1876 * @param LPTIMx Low-Power Timer instance
1877 * @retval None
1878 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1879 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1880 {
1881 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1882 }
1883
1884 /**
1885 * @brief Informs application whether the LPTIMx update event has occurred.
1886 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1887 * @param LPTIMx Low-Power Timer instance
1888 * @retval State of bit (1 or 0).
1889 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1890 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1891 {
1892 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1893 }
1894
1895 /**
1896 * @}
1897 */
1898
1899 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1900 * @{
1901 */
1902 /**
1903 * @brief Enable capture/compare 1 interrupt (CC1IE).
1904 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
1905 * @param LPTIMx Low-Power Timer instance
1906 * @retval None
1907 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)1908 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
1909 {
1910 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1911 }
1912
1913 /**
1914 * @brief Disable capture/compare 1 interrupt (CC1IE).
1915 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
1916 * @param LPTIMx Low-Power Timer instance
1917 * @retval None
1918 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)1919 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
1920 {
1921 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1922 }
1923
1924 /**
1925 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
1926 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
1927 * @param LPTIMx Low-Power Timer instance
1928 * @retval State of bit (1 or 0).
1929 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)1930 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
1931 {
1932 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
1933 }
1934
1935 /**
1936 * @brief Enable capture/compare 1 interrupt (CC2IE).
1937 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
1938 * @param LPTIMx Low-Power Timer instance
1939 * @retval None
1940 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)1941 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
1942 {
1943 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1944 }
1945
1946 /**
1947 * @brief Disable capture/compare 2 interrupt (CC2IE).
1948 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
1949 * @param LPTIMx Low-Power Timer instance
1950 * @retval None
1951 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)1952 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
1953 {
1954 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1955 }
1956
1957 /**
1958 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
1959 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
1960 * @param LPTIMx Low-Power Timer instance
1961 * @retval State of bit (1 or 0).
1962 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)1963 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
1964 {
1965 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
1966 }
1967
1968 /**
1969 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
1970 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
1971 * @param LPTIMx Low-Power Timer instance
1972 * @retval None
1973 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)1974 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1975 {
1976 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1977 }
1978
1979 /**
1980 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
1981 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
1982 * @param LPTIMx Low-Power Timer instance
1983 * @retval None
1984 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)1985 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1986 {
1987 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1988 }
1989
1990 /**
1991 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
1992 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
1993 * @param LPTIMx Low-Power Timer instance
1994 * @retval State of bit (1 or 0).
1995 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)1996 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
1997 {
1998 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
1999 }
2000
2001 /**
2002 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
2003 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
2004 * @param LPTIMx Low-Power Timer instance
2005 * @retval None
2006 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)2007 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2008 {
2009 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2010 }
2011
2012 /**
2013 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
2014 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
2015 * @param LPTIMx Low-Power Timer instance
2016 * @retval None
2017 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)2018 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2019 {
2020 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2021 }
2022
2023 /**
2024 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
2025 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
2026 * @param LPTIMx Low-Power Timer instance
2027 * @retval State of bit (1 or 0).
2028 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)2029 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
2030 {
2031 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2032 }
2033
2034 /**
2035 * @brief Enable autoreload match interrupt (ARRMIE).
2036 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2037 * @param LPTIMx Low-Power Timer instance
2038 * @retval None
2039 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2040 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2041 {
2042 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2043 }
2044
2045 /**
2046 * @brief Disable autoreload match interrupt (ARRMIE).
2047 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2048 * @param LPTIMx Low-Power Timer instance
2049 * @retval None
2050 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2051 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2052 {
2053 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2054 }
2055
2056 /**
2057 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2058 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2059 * @param LPTIMx Low-Power Timer instance
2060 * @retval State of bit (1 or 0).
2061 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2062 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2063 {
2064 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2065 }
2066
2067 /**
2068 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2069 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2070 * @param LPTIMx Low-Power Timer instance
2071 * @retval None
2072 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2073 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2074 {
2075 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2076 }
2077
2078 /**
2079 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2080 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2081 * @param LPTIMx Low-Power Timer instance
2082 * @retval None
2083 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2084 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2085 {
2086 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2087 }
2088
2089 /**
2090 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2091 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2092 * @param LPTIMx Low-Power Timer instance
2093 * @retval State of bit (1 or 0).
2094 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2095 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2096 {
2097 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2098 }
2099
2100 /**
2101 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2102 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2103 * @param LPTIMx Low-Power Timer instance
2104 * @retval None
2105 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2106 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2107 {
2108 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2109 }
2110
2111 /**
2112 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2113 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2114 * @param LPTIMx Low-Power Timer instance
2115 * @retval None
2116 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2117 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2118 {
2119 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2120 }
2121
2122 /**
2123 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2124 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2125 * @param LPTIMx Low-Power Timer instance
2126 * @retval State of bit (1 or 0).
2127 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2128 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2129 {
2130 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2131 }
2132
2133 /**
2134 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2135 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2136 * @param LPTIMx Low-Power Timer instance
2137 * @retval None
2138 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2139 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2140 {
2141 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2142 }
2143
2144 /**
2145 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2146 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2147 * @param LPTIMx Low-Power Timer instance
2148 * @retval None
2149 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2150 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2151 {
2152 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2153 }
2154
2155 /**
2156 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2157 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2158 * @param LPTIMx Low-Power Timer instance
2159 * @retval State of bit (1 or 0).
2160 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2161 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2162 {
2163 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2164 }
2165
2166 /**
2167 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2168 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2169 * @param LPTIMx Low-Power Timer instance
2170 * @retval None
2171 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2172 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2173 {
2174 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2175 }
2176
2177 /**
2178 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2179 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2180 * @param LPTIMx Low-Power Timer instance
2181 * @retval None
2182 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2183 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2184 {
2185 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2186 }
2187
2188 /**
2189 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2190 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2191 * @param LPTIMx Low-Power Timer instance
2192 * @retval State of bit(1 or 0).
2193 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2194 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2195 {
2196 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2197 }
2198
2199 /**
2200 * @brief Enable direction change to up interrupt (UPIE).
2201 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2202 * @param LPTIMx Low-Power Timer instance
2203 * @retval None
2204 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2205 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2206 {
2207 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2208 }
2209
2210 /**
2211 * @brief Disable direction change to up interrupt (UPIE).
2212 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2213 * @param LPTIMx Low-Power Timer instance
2214 * @retval None
2215 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2216 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2217 {
2218 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2219 }
2220
2221 /**
2222 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2223 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2224 * @param LPTIMx Low-Power Timer instance
2225 * @retval State of bit(1 or 0).
2226 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2227 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2228 {
2229 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2230 }
2231
2232 /**
2233 * @brief Enable direction change to down interrupt (DOWNIE).
2234 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2235 * @param LPTIMx Low-Power Timer instance
2236 * @retval None
2237 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2238 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2239 {
2240 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2241 }
2242
2243 /**
2244 * @brief Disable direction change to down interrupt (DOWNIE).
2245 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2246 * @param LPTIMx Low-Power Timer instance
2247 * @retval None
2248 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2249 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2250 {
2251 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2252 }
2253
2254 /**
2255 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2256 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2257 * @param LPTIMx Low-Power Timer instance
2258 * @retval State of bit(1 or 0).
2259 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2260 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2261 {
2262 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2263 }
2264
2265 /**
2266 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2267 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2268 * @param LPTIMx Low-Power Timer instance
2269 * @retval None
2270 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2271 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2272 {
2273 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2274 }
2275
2276 /**
2277 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2278 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2279 * @param LPTIMx Low-Power Timer instance
2280 * @retval None
2281 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2282 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2283 {
2284 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2285 }
2286
2287 /**
2288 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2289 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2290 * @param LPTIMx Low-Power Timer instance
2291 * @retval State of bit(1 or 0).
2292 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2293 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2294 {
2295 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2296 }
2297
2298 /**
2299 * @brief Enable update event interrupt (UEIE).
2300 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2301 * @param LPTIMx Low-Power Timer instance
2302 * @retval None
2303 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2304 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2305 {
2306 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2307 }
2308
2309 /**
2310 * @brief Disable update event interrupt (UEIE).
2311 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2312 * @param LPTIMx Low-Power Timer instance
2313 * @retval None
2314 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2315 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2316 {
2317 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2318 }
2319
2320 /**
2321 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2322 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2323 * @param LPTIMx Low-Power Timer instance
2324 *@ retval State of bit(1 or 0).
2325 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2326 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2327 {
2328 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2329 }
2330 /**
2331 * @}
2332 */
2333
2334
2335 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2336 * @{
2337 */
2338 /**
2339 * @brief Enable update DMA request.
2340 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2341 * @param LPTIMx Low-Power Timer instance
2342 * @retval None
2343 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2344 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2345 {
2346 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2347 }
2348
2349 /**
2350 * @brief Disable update DMA request.
2351 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2352 * @param LPTIMx Low-Power Timer instance
2353 * @retval None
2354 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2355 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2356 {
2357 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2358 }
2359
2360 /**
2361 * @brief Indicates whether the update DMA request is enabled.
2362 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2363 * @param LPTIMx Low-Power Timer instance
2364 * @retval State of bit (1 or 0).
2365 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2366 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2367 {
2368 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2369 }
2370
2371 /**
2372 * @brief Enable capture/compare 1 DMA request (CC1DE).
2373 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2374 * @param LPTIMx Low-Power Timer instance
2375 * @retval None
2376 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2377 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2378 {
2379 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2380 }
2381
2382 /**
2383 * @brief Disable capture/compare 1 DMA request (CC1DE).
2384 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2385 * @param LPTIMx Low-Power Timer instance
2386 * @retval None
2387 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2388 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2389 {
2390 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2391 }
2392
2393 /**
2394 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2395 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2396 * @param LPTIMx Low-Power Timer instance
2397 * @retval State of bit (1 or 0).
2398 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2399 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2400 {
2401 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2402 }
2403
2404 /**
2405 * @brief Enable capture/compare 2 DMA request (CC2DE).
2406 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2407 * @param LPTIMx Low-Power Timer instance
2408 * @retval None
2409 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2410 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2411 {
2412 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2413 }
2414
2415 /**
2416 * @brief Disable capture/compare 2 DMA request (CC2DE).
2417 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2418 * @param LPTIMx Low-Power Timer instance
2419 * @retval None
2420 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2421 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2422 {
2423 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2424 }
2425
2426 /**
2427 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2428 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2429 * @param LPTIMx Low-Power Timer instance
2430 * @retval State of bit (1 or 0).
2431 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)2432 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
2433 {
2434 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
2435 }
2436
2437 /**
2438 * @}
2439 */
2440 /**
2441 * @}
2442 */
2443
2444 /**
2445 * @}
2446 */
2447
2448 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
2449
2450 /**
2451 * @}
2452 */
2453
2454 #ifdef __cplusplus
2455 }
2456 #endif
2457
2458 #endif /* STM32H7RSxx_LL_LPTIM_H */
2459
