1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32U5xx_LL_DMA_H
41 #define STM32U5xx_LL_DMA_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif /* __cplusplus */
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32u5xx.h"
49
50 /** @addtogroup STM32U5xx_LL_Driver
51 * @{
52 */
53
54 #if (defined (GPDMA1) || defined (LPDMA1))
55
56 /** @defgroup DMA_LL DMA
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62
63 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
64 * @{
65 */
66 #define DMA_CHANNEL0_OFFSET (0x00000050UL)
67 #define DMA_CHANNEL1_OFFSET (0x000000D0UL)
68 #define DMA_CHANNEL2_OFFSET (0x00000150UL)
69 #define DMA_CHANNEL3_OFFSET (0x000001D0UL)
70 #define DMA_CHANNEL4_OFFSET (0x00000250UL)
71 #define DMA_CHANNEL5_OFFSET (0x000002D0UL)
72 #define DMA_CHANNEL6_OFFSET (0x00000350UL)
73 #define DMA_CHANNEL7_OFFSET (0x000003D0UL)
74 #define DMA_CHANNEL8_OFFSET (0x00000450UL)
75 #define DMA_CHANNEL9_OFFSET (0x000004D0UL)
76 #define DMA_CHANNEL10_OFFSET (0x00000550UL)
77 #define DMA_CHANNEL11_OFFSET (0x000005D0UL)
78 #define DMA_CHANNEL12_OFFSET (0x00000650UL)
79 #define DMA_CHANNEL13_OFFSET (0x000006D0UL)
80 #define DMA_CHANNEL14_OFFSET (0x00000750UL)
81 #define DMA_CHANNEL15_OFFSET (0x000007D0UL)
82
83 /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
84 static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
85 {
86 DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
87 DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
88 DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET,
89 DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET,
90 };
91
92 /**
93 * @}
94 */
95
96 /* Private constants ---------------------------------------------------------*/
97 /* Private macros ------------------------------------------------------------*/
98 /* Exported types ------------------------------------------------------------*/
99
100 #if defined (USE_FULL_LL_DRIVER)
101 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
102 * @{
103 */
104
105 /**
106 * @brief LL DMA init structure definition.
107 */
108 typedef struct
109 {
110 uint32_t SrcAddress; /*!< This field specify the data transfer source address.
111 Programming this field is mandatory for all available DMA channels.
112 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
113 This feature can be modified afterwards using unitary function
114 @ref LL_DMA_SetSrcAddress(). */
115
116 uint32_t DestAddress; /*!< This field specify the data transfer destination address.
117 Programming this field is mandatory for all available DMA channels.
118 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
119 This feature can be modified afterwards using unitary function
120 @ref LL_DMA_SetDestAddress(). */
121
122 uint32_t Direction; /*!< This field specify the data transfer direction.
123 Programming this field is mandatory for all available DMA channels.
124 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
125 This feature can be modified afterwards using unitary function
126 @ref LL_DMA_SetDataTransferDirection(). */
127
128 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
129 Programming this field is mandatory for all available DMA channels.
130 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
131 This feature can be modified afterwards using unitary function
132 @ref LL_DMA_SetBlkHWRequest(). */
133
134 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
135 Programming this field is mandatory for all available DMA channels.
136 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
137 This feature can be modified afterwards using unitary function
138 @ref LL_DMA_SetDataAlignment(). */
139
140 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
141 Programming this field is not mandatory for LPDMA channels.
142 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
143 This feature can be modified afterwards using unitary function
144 @ref LL_DMA_SetSrcBurstLength(). */
145
146 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
147 Programming this field is not mandatory for LPDMA channels.
148 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
149 This feature can be modified afterwards using unitary function
150 @ref LL_DMA_SetDestBurstLength(). */
151
152 uint32_t SrcDataWidth; /*!< This field specify the source data width.
153 Programming this field is mandatory for all available DMA channels.
154 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
155 This feature can be modified afterwards using unitary function
156 @ref LL_DMA_SetSrcDataWidth(). */
157
158 uint32_t DestDataWidth; /*!< This field specify the destination data width.
159 Programming this field is mandatory for all available DMA channels.
160 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
161 This feature can be modified afterwards using unitary function
162 @ref LL_DMA_SetDestDataWidth(). */
163
164 uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
165 Programming this field is mandatory for all available DMA channels.
166 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
167 This feature can be modified afterwards using unitary function
168 @ref LL_DMA_SetSrcIncMode(). */
169
170 uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
171 Programming this field is mandatory for all available DMA channels.
172 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
173 This feature can be modified afterwards using unitary function
174 @ref LL_DMA_SetDestIncMode(). */
175
176 uint32_t Priority; /*!< This field specify the channel priority level.
177 Programming this field is mandatory for all available DMA channels.
178 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
179 This feature can be modified afterwards using unitary function
180 @ref LL_DMA_SetChannelPriorityLevel(). */
181
182 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
183 Programming this field is mandatory for all available DMA channels.
184 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
185 This feature can be modified afterwards using unitary function
186 @ref LL_DMA_SetBlkDataLength(). */
187
188 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
189 Programming this field is mandatory only for 2D addressing channels.
190 This parameter can be a value between 1 and 2048 Min_Data = 0
191 and Max_Data = 0x000007FF.
192 This feature can be modified afterwards using unitary function
193 @ref LL_DMA_SetBlkRptCount(). */
194
195 uint32_t TriggerMode; /*!< This field specify the trigger mode.
196 Programming this field is mandatory for all available DMA channels.
197 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
198 This feature can be modified afterwards using unitary function
199 @ref LL_DMA_SetTriggerMode(). */
200
201 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
202 Programming this field is mandatory for all available DMA channels.
203 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
204 This feature can be modified afterwards using unitary function
205 @ref LL_DMA_SetTriggerPolarity(). */
206
207 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
208 Programming this field is mandatory for all available DMA channels.
209 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
210 This feature can be modified afterwards using unitary function
211 @ref LL_DMA_SetHWTrigger(). */
212
213 uint32_t Request; /*!< This field specify the peripheral request selection.
214 Programming this field is mandatory for all available DMA channels.
215 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
216 This feature can be modified afterwards using unitary function
217 @ref LL_DMA_SetPeriphRequest(). */
218
219 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
220 Programming this field is mandatory for all available DMA channels.
221 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
222 This feature can be modified afterwards using unitary function
223 @ref LL_DMA_SetTransferEventMode(). */
224
225 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
226 Programming this field is not mandatory for LPDMA channels.
227 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
228 This feature can be modified afterwards using unitary function
229 @ref LL_DMA_SetDestHWordExchange(). */
230
231 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
232 Programming this field is not mandatory for LPDMA channels.
233 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
234 This feature can be modified afterwards using unitary function
235 @ref LL_DMA_SetDestByteExchange(). */
236
237 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
238 Programming this field is not mandatory for LPDMA channels.
239 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
240 This feature can be modified afterwards using unitary function
241 @ref LL_DMA_SetSrcByteExchange(). */
242
243 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
244 Programming this field is not mandatory for LPDMA channels.
245 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
246 This feature can be modified afterwards using unitary function
247 @ref LL_DMA_SetSrcAllocatedPort(). */
248
249 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
250 Programming this field is not mandatory for LPDMA channels.
251 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
252 This feature can be modified afterwards using unitary function
253 @ref LL_DMA_SetDestAllocatedPort(). */
254
255 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
256 Programming this field is not mandatory for LPDMA channels.
257 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
258 This feature can be modified afterwards using unitary function
259 @ref LL_DMA_SetLinkAllocatedPort(). */
260
261 uint32_t LinkStepMode; /*!< This field specify the link step mode.
262 Programming this field is mandatory for all available DMA channels.
263 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
264 This feature can be modified afterwards using unitary function
265 @ref LL_DMA_SetLinkStepMode(). */
266
267 uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode.
268 Programming this field is mandatory only for 2D addressing channels.
269 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.
270 This feature can be modified afterwards using unitary function
271 @ref LL_DMA_SetSrcAddrUpdate(). */
272
273 uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode.
274 Programming this field is mandatory only for 2D addressing channels.
275 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.
276 This feature can be modified afterwards using unitary function
277 @ref LL_DMA_SetDestAddrUpdate(). */
278
279 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
280 Programming this field is mandatory only for 2D addressing channels.
281 This parameter can be a value Between 0 to 0x00001FFF.
282 This feature can be modified afterwards using unitary function
283 @ref LL_DMA_SetSrcAddrUpdateValue(). */
284
285 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
286 Programming this field is mandatory only for 2D addressing channels.
287 This parameter can be a value Between 0 to 0x00001FFF.
288 This feature can be modified afterwards using unitary function
289 @ref LL_DMA_SetDestAddrUpdateValue(). */
290
291 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
292 Programming this field is mandatory only for 2D addressing channels.
293 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.
294 This feature can be modified afterwards using unitary function
295 @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */
296
297 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
298 Programming this field is mandatory only for 2D addressing channels.
299 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.
300 This feature can be modified afterwards using unitary function
301 @ref LL_DMA_SetBlkRptDestAddrUpdate(). */
302
303 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
304 Programming this field is mandatory only for 2D addressing channels.
305 This parameter can be a value Between 0 to 0x0000FFFF.
306 This feature can be modified afterwards using unitary function
307 @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */
308
309 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
310 Programming this field is mandatory only for 2D addressing channels.
311 This parameter can be a value Between 0 to 0x0000FFFF.
312 This feature can be modified afterwards using unitary function
313 @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */
314
315 uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
316 Programming this field is mandatory for all available DMA channels.
317 This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
318 bytes are always forced to 0).
319 This feature can be modified afterwards using unitary function
320 @ref LL_DMA_SetLinkedListBaseAddr(). */
321
322 uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
323 Programming this field is mandatory for all available DMA channels.
324 This parameter can be a value Between 0 to 0x0000FFFC.
325 This feature can be modified afterwards using unitary function
326 @ref LL_DMA_SetLinkedListAddrOffset(). */
327
328 } LL_DMA_InitTypeDef;
329
330
331 /**
332 * @brief LL DMA init linked list structure definition.
333 */
334 typedef struct
335 {
336 uint32_t Priority; /*!< This field specify the channel priority level.
337 Programming this field is mandatory for all available DMA channels.
338 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
339 This feature can be modified afterwards using unitary function
340 @ref LL_DMA_SetChannelPriorityLevel(). */
341
342 uint32_t LinkStepMode; /*!< This field specify the link step mode.
343 Programming this field is mandatory for all available DMA channels.
344 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
345 This feature can be modified afterwards using unitary function
346 @ref LL_DMA_SetLinkStepMode(). */
347
348 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
349 Programming this field is not mandatory for LPDMA channels.
350 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
351 This feature can be modified afterwards using unitary function
352 @ref LL_DMA_SetLinkAllocatedPort(). */
353
354 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
355 Programming this field is mandatory for all available DMA channels.
356 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
357 This feature can be modified afterwards using unitary function
358 @ref LL_DMA_SetTransferEventMode(). */
359 } LL_DMA_InitLinkedListTypeDef;
360
361
362 /**
363 * @brief LL DMA node init structure definition.
364 */
365 typedef struct
366 {
367 /* CTR1 register fields ******************************************************
368 If any CTR1 fields need to be updated comparing to previous node, it is
369 mandatory to update the new value in CTR1 register fields and enable update
370 CTR1 register in UpdateRegisters fields if it is not enabled in the
371 previous node.
372
373 If the node to be created is for LPDMA channels, there is no need to fill
374 the following fields for CTR1 register :
375 - DestAllocatedPort.
376 - DestHWordExchange.
377 - DestByteExchange.
378 - DestBurstLength.
379 - SrcAllocatedPort.
380 - SrcByteExchange.
381 - SrcBurstLength.
382
383 */
384 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
385 uint32_t DestSecure; /*!< This field specify the destination secure.
386 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
387 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
388
389 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
390 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
391
392 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
393 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
394
395 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
396 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
397
398 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
399 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
400
401 uint32_t DestIncMode; /*!< This field specify the destination increment mode.
402 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
403
404 uint32_t DestDataWidth; /*!< This field specify the destination data width.
405 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
406
407 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
408 uint32_t SrcSecure; /*!< This field specify the source secure.
409 This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */
410 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
411
412 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
413 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
414
415 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
416 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
417
418 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
419 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
420
421 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
422 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
423
424 uint32_t SrcIncMode; /*!< This field specify the source increment mode.
425 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
426
427 uint32_t SrcDataWidth; /*!< This field specify the source data width.
428 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
429
430
431 /* CTR2 register fields ******************************************************
432 If any CTR2 fields need to be updated comparing to previous node, it is
433 mandatory to update the new value in CTR2 register fields and enable update
434 CTR2 register in UpdateRegisters fields if it is not enabled in the
435 previous node.
436
437 For all node created, filling all fields is mandatory.
438 */
439 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
440 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
441
442 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
443 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
444
445 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
446 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
447
448 uint32_t TriggerMode; /*!< This field specify the trigger mode.
449 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
450
451 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
452 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
453
454 uint32_t Direction; /*!< This field specify the transfer direction.
455 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
456
457 uint32_t Request; /*!< This field specify the peripheral request selection.
458 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
459
460
461 /* CBR1 register fields ******************************************************
462 If any CBR1 fields need to be updated comparing to previous node, it is
463 mandatory to update the new value in CBR1 register fields and enable update
464 CBR1 register in UpdateRegisters fields if it is not enabled in the
465 previous node.
466
467 If the node to be created is not for 2D addressing channels, there is no
468 need to fill the following fields for CBR1 register :
469 - BlkReptDestAddrUpdate.
470 - BlkRptSrcAddrUpdate.
471 - DestAddrUpdate.
472 - SrcAddrUpdate.
473 - BlkRptCount.
474 */
475 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
476 This parameter can be a value of
477 @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */
478
479 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
480 This parameter can be a value of
481 @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */
482
483 uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode.
484 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */
485
486 uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode.
487 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */
488
489 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
490 This parameter can be a value between 1 and 2048 Min_Data = 0
491 and Max_Data = 0x000007FF. */
492
493 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
494 This parameter must be a value between Min_Data = 0
495 and Max_Data = 0x0000FFFF. */
496
497 /* CSAR register fields ******************************************************
498 If any CSAR fields need to be updated comparing to previous node, it is
499 mandatory to update the new value in CSAR register fields and enable update
500 CSAR register in UpdateRegisters fields if it is not enabled in the
501 previous node.
502
503 For all node created, filling all fields is mandatory.
504 */
505 uint32_t SrcAddress; /*!< This field specify the transfer source address.
506 This parameter must be a value between Min_Data = 0
507 and Max_Data = 0xFFFFFFFF. */
508
509
510 /* CDAR register fields ******************************************************
511 If any CDAR fields need to be updated comparing to previous node, it is
512 mandatory to update the new value in CDAR register fields and enable update
513 CDAR register in UpdateRegisters fields if it is not enabled in the
514 previous node.
515
516 For all node created, filling all fields is mandatory.
517 */
518 uint32_t DestAddress; /*!< This field specify the transfer destination address.
519 This parameter must be a value between Min_Data = 0
520 and Max_Data = 0xFFFFFFFF. */
521
522 /* CTR3 register fields ******************************************************
523 If any CTR3 fields need to be updated comparing to previous node, it is
524 mandatory to update the new value in CTR3 register fields and enable update
525 CTR3 register in UpdateRegisters fields if it is not enabled in the
526 previous node.
527
528 This register is used only for 2D addressing channels.
529 If used channel is linear addressing, this register will be overwritten by
530 CLLR register in memory.
531 When this register is enabled on UpdateRegisters and the selected channel
532 is linear addressing, LL APIs will discard this register update in memory.
533 */
534 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
535 This parameter can be a value Between 0 to 0x00001FFF. */
536
537 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
538 This parameter can be a value Between 0 to 0x00001FFF. */
539
540
541 /* CBR2 register fields ******************************************************
542 If any CBR2 fields need to be updated comparing to previous node, it is
543 mandatory to update the new value in CBR2 register fields and enable update
544 CBR2 register in UpdateRegisters fields if it is not enabled in the
545 previous node.
546
547 This register is used only for 2D addressing channels.
548 If used channel is linear addressing, this register will be discarded in
549 memory. When this register is enabled on UpdateRegisters and the selected
550 channel is linear addressing, LL APIs will discard this register update in
551 memory.
552 */
553 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
554 This parameter can be a value Between 0 to 0x0000FFFF. */
555
556 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
557 This parameter can be a value Between 0 to 0x0000FFFF. */
558
559 /* CLLR register fields ******************************************************
560 If any CLLR fields need to be updated comparing to previous node, it is
561 mandatory to update the new value in CLLR register fields and enable update
562 CLLR register in UpdateRegisters fields if it is not enabled in the
563 previous node.
564
565 If used channel is linear addressing, there is no need to enable/disable
566 CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded
567 by LL APIs.
568 */
569 uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
570 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
571
572 /* DMA Node type field *******************************************************
573 This parameter defines node types as node size and node content varies
574 between channels.
575 Thanks to this fields, linked list queue could be created independently
576 from channel selection. So, one queue could be executed by all DMA channels.
577 */
578 uint32_t NodeType; /*!< Specifies the node type to be created.
579 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
580 } LL_DMA_InitNodeTypeDef;
581
582 /**
583 * @brief LL DMA linked list node structure definition.
584 * @note For 2D addressing channels, the maximum node size is :
585 * (4 Bytes * 8 registers = 32 Bytes).
586 * For GPDMA linear addressing channels, the maximum node size is :
587 * (4 Bytes * 6 registers = 24 Bytes).
588 * For LPDMA linear addressing channels, the maximum node size is :
589 * (4 Bytes * 6 registers = 24 Bytes).
590 */
591 typedef struct
592 {
593 __IO uint32_t LinkRegisters[8U];
594
595 } LL_DMA_LinkNodeTypeDef;
596 /**
597 * @}
598 */
599
600 #endif /* USE_FULL_LL_DRIVER */
601
602 /* Exported constants --------------------------------------------------------*/
603
604 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
605 * @{
606 */
607
608 /** @defgroup DMA_LL_EC_CHANNEL Channel
609 * @{
610 */
611 #define LL_DMA_CHANNEL_0 (0x00U)
612 #define LL_DMA_CHANNEL_1 (0x01U)
613 #define LL_DMA_CHANNEL_2 (0x02U)
614 #define LL_DMA_CHANNEL_3 (0x03U)
615 #define LL_DMA_CHANNEL_4 (0x04U)
616 #define LL_DMA_CHANNEL_5 (0x05U)
617 #define LL_DMA_CHANNEL_6 (0x06U)
618 #define LL_DMA_CHANNEL_7 (0x07U)
619 #define LL_DMA_CHANNEL_8 (0x08U)
620 #define LL_DMA_CHANNEL_9 (0x09U)
621 #define LL_DMA_CHANNEL_10 (0x0AU)
622 #define LL_DMA_CHANNEL_11 (0x0BU)
623 #define LL_DMA_CHANNEL_12 (0x0CU)
624 #define LL_DMA_CHANNEL_13 (0x0DU)
625 #define LL_DMA_CHANNEL_14 (0x0EU)
626 #define LL_DMA_CHANNEL_15 (0x0FU)
627 #if defined (USE_FULL_LL_DRIVER)
628 #define LL_DMA_CHANNEL_ALL (0x10U)
629 #endif /* USE_FULL_LL_DRIVER */
630 /**
631 * @}
632 */
633
634 #if defined (USE_FULL_LL_DRIVER)
635 /** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
636 * @{
637 */
638 #define LL_DMA_CLLR_OFFSET0 (0x00U)
639 #define LL_DMA_CLLR_OFFSET1 (0x01U)
640 #define LL_DMA_CLLR_OFFSET2 (0x02U)
641 #define LL_DMA_CLLR_OFFSET3 (0x03U)
642 #define LL_DMA_CLLR_OFFSET4 (0x04U)
643 #define LL_DMA_CLLR_OFFSET5 (0x05U)
644 #define LL_DMA_CLLR_OFFSET6 (0x06U)
645 #define LL_DMA_CLLR_OFFSET7 (0x07U)
646 /**
647 * @}
648 */
649 #endif /* USE_FULL_LL_DRIVER */
650
651 /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level
652 * @{
653 */
654 #define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
655 #define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
656 #define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
657 #define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
658 /**
659 * @}
660 */
661
662 /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
663 * @{
664 */
665 #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
666 #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
667 /**
668 * @}
669 */
670
671 /** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
672 * @{
673 */
674 #define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
675 #define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
676 /**
677 * @}
678 */
679
680 /** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
681 * @{
682 */
683 #define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width
684 is word */
685 #define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width
686 is word */
687 /**
688 * @}
689 */
690
691 /** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
692 * @{
693 */
694 #define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
695 #define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
696 /**
697 * @}
698 */
699
700 /** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
701 * @{
702 */
703 #define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
704 #define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
705 /**
706 * @}
707 */
708
709 /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
710 * @{
711 */
712 #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
713 #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
714 /**
715 * @}
716 */
717
718 /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
719 * @{
720 */
721 #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
722 #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
723 /**
724 * @}
725 */
726
727 /** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
728 * @{
729 */
730 #define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
731 #define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
732 /**
733 * @}
734 */
735
736 /** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
737 * @{
738 */
739 #define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
740 #define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
741 #define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
742 /**
743 * @}
744 */
745
746 /** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
747 * @{
748 */
749 #define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
750 => Right Aligned padded with 0 up to destination
751 data width.
752 If src data width > dest data width :
753 => Right Aligned Left Truncated down to destination
754 data width. */
755 #define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
756 => Right Aligned padded with sign extended up to destination
757 data width.
758 If src data width > dest data width :
759 => Left Aligned Right Truncated down to the destination
760 data width */
761 #define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
762 => Packed at the destination data width (Not Available
763 for LPDMA)
764 If src data width > dest data width :
765 => Unpacked at the destination data width (Not Available
766 for LPDMA) */
767 /**
768 * @}
769 */
770
771 /** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
772 * @{
773 */
774 #define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
775 #define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
776 /**
777 * @}
778 */
779
780 /** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
781 * @{
782 */
783 #define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
784 #define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
785 #define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
786 /**
787 * @}
788 */
789
790 /** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
791 * @{
792 */
793 #define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
794 request/acknowledge protocol at a burst level */
795 #define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
796 request/acknowledge protocol at a block level */
797 /**
798 * @}
799 */
800
801 /** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
802 * @{
803 */
804 #define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
805 (respectively half) end of each block */
806 #define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
807 (respectively half) end of the repeated block */
808 #define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
809 (respectively half) end of each linked-list item */
810 #define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
811 (respectively half) end of the last linked-list item */
812 /**
813 * @}
814 */
815
816 /** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
817 * @{
818 */
819 #define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
820 Masked trigger event */
821 #define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
822 edge of the selected trigger event input */
823 #define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
824 edge of the selected trigger event input */
825 /**
826 * @}
827 */
828
829 /** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
830 * @{
831 */
832 #define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
833 one hit trigger */
834 #define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
835 one hit trigger */
836 #define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
837 one hit trigger */
838 #define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
839 one hit trigger */
840 /**
841 * @}
842 */
843
844 /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
845 * @{
846 */
847 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
848 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
849 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
850 /**
851 * @}
852 */
853
854 /** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode
855 * @{
856 */
857 #define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block
858 transfer by source update value */
859 #define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block
860 transfer by source update value */
861 /**
862 * @}
863 */
864
865 /** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode
866 * @{
867 */
868 #define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block
869 transfer by destination update value */
870 #define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block
871 transfer by destination update value */
872 /**
873 * @}
874 */
875
876 /** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode
877 * @{
878 */
879 #define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst
880 transfer by source update value */
881 #define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst
882 transfer by source update value */
883 /**
884 * @}
885 */
886
887 /** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode
888 * @{
889 */
890 #define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each
891 burst transfer by destination update value */
892 #define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each
893 burst transfer by destination update value */
894 /**
895 * @}
896 */
897
898 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
899 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
900 * @{
901 */
902 #define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
903 #define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */
904 /**
905 * @}
906 */
907
908 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
909 * @{
910 */
911 #define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */
912 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
913 /**
914 * @}
915 */
916
917 /** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
918 * @{
919 */
920 #define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */
921 #define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */
922 /**
923 * @}
924 */
925 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
926
927 /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
928 * @{
929 */
930 #define LL_DMA_LPDMA_LINEAR_NODE 0x00U /*!< LPDMA node : linear addressing node */
931 #define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
932 #define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */
933
934 /**
935 * @}
936 */
937
938 /** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
939 * @{
940 */
941 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
942 available for all DMA channels */
943 #define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
944 available for all DMA channels */
945 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
946 available for all DMA channels */
947 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
948 available for all DMA channels */
949 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
950 available for all DMA channels */
951 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
952 available only for 2D addressing DMA channels */
953 #define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory :
954 available only for 2D addressing DMA channels */
955 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
956 available for all DMA channels */
957 /**
958 * @}
959 */
960
961 /** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
962 * @{
963 */
964 /* GPDMA1 Hardware Requests */
965 #define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW Request is ADC1 */
966 #define LL_GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW Request is ADC4 */
967 #define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW Request is DAC1_CH1 */
968 #define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW Request is DAC1_CH2 */
969 #define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW Request is TIM6_UP */
970 #define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW Request is TIM7_UP */
971 #define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW Request is SPI1_RX */
972 #define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW Request is SPI1_TX */
973 #define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW Request is SPI2_RX */
974 #define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW Request is SPI2_TX */
975 #define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW Request is SPI3_RX */
976 #define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW Request is SPI3_TX */
977 #define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW Request is I2C1_RX */
978 #define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW Request is I2C1_TX */
979 #define LL_GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW Request is I2C1_EVC */
980 #define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW Request is I2C2_RX */
981 #define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW Request is I2C2_TX */
982 #define LL_GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW Request is I2C2_EVC */
983 #define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW Request is I2C3_RX */
984 #define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW Request is I2C3_TX */
985 #define LL_GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW Request is I2C3_EVC */
986 #define LL_GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW Request is I2C4_RX */
987 #define LL_GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW Request is I2C4_TX */
988 #define LL_GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW Request is I2C4_EVC */
989 #define LL_GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW Request is USART1_RX */
990 #define LL_GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW Request is USART1_TX */
991 #if defined(USART2)
992 #define LL_GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW Request is USART2_RX */
993 #define LL_GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW Request is USART2_TX */
994 #endif /* USART2 */
995 #define LL_GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW Request is USART3_RX */
996 #define LL_GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW Request is USART3_TX */
997 #define LL_GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW Request is UART4_RX */
998 #define LL_GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW Request is UART4_TX */
999 #define LL_GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW Request is UART5_RX */
1000 #define LL_GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW Request is UART5_TX */
1001 #define LL_GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW Request is LPUART1_RX */
1002 #define LL_GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW Request is LPUART1_TX */
1003 #define LL_GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW Request is SAI1_A */
1004 #define LL_GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW Request is SAI1_B */
1005 #if defined(SAI2)
1006 #define LL_GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW Request is SAI2_A */
1007 #define LL_GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW Request is SAI2_B */
1008 #endif /* SAI2 */
1009 #define LL_GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW Request is OCTOSPI1 */
1010 #if defined(OCTOSPI2)
1011 #define LL_GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW Request is OCTOSPI2 */
1012 #endif /* OCTOSPI2 */
1013 #define LL_GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW Request is TIM1_CH1 */
1014 #define LL_GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW Request is TIM1_CH2 */
1015 #define LL_GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW Request is TIM1_CH3 */
1016 #define LL_GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW Request is TIM1_CH4 */
1017 #define LL_GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW Request is TIM1_UP */
1018 #define LL_GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW Request is TIM1_TRIG */
1019 #define LL_GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW Request is TIM1_COM */
1020 #define LL_GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW Request is TIM8_CH1 */
1021 #define LL_GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW Request is TIM8_CH2 */
1022 #define LL_GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW Request is TIM8_CH3 */
1023 #define LL_GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW Request is TIM8_CH4 */
1024 #define LL_GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW Request is TIM8_UP */
1025 #define LL_GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW Request is TIM8_TRIG */
1026 #define LL_GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW Request is TIM8_COM */
1027 #define LL_GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW Request is TIM2_CH1 */
1028 #define LL_GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW Request is TIM2_CH2 */
1029 #define LL_GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW Request is TIM2_CH3 */
1030 #define LL_GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW Request is TIM2_CH4 */
1031 #define LL_GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW Request is TIM2_UP */
1032 #define LL_GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW Request is TIM3_CH1 */
1033 #define LL_GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW Request is TIM3_CH2 */
1034 #define LL_GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW Request is TIM3_CH3 */
1035 #define LL_GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW Request is TIM3_CH4 */
1036 #define LL_GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW Request is TIM3_UP */
1037 #define LL_GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW Request is TIM3_TRIG */
1038 #define LL_GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW Request is TIM4_CH1 */
1039 #define LL_GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW Request is TIM4_CH2 */
1040 #define LL_GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW Request is TIM4_CH3 */
1041 #define LL_GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW Request is TIM4_CH4 */
1042 #define LL_GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW Request is TIM4_UP */
1043 #define LL_GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW Request is TIM5_CH1 */
1044 #define LL_GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW Request is TIM5_CH2 */
1045 #define LL_GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW Request is TIM5_CH3 */
1046 #define LL_GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW Request is TIM5_CH4 */
1047 #define LL_GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW Request is TIM5_UP */
1048 #define LL_GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW Request is TIM5_TRIG */
1049 #define LL_GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW Request is TIM15_CH1 */
1050 #define LL_GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW Request is TIM15_UP */
1051 #define LL_GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW Request is TIM15_TRIG */
1052 #define LL_GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW Request is TIM15_COM */
1053 #define LL_GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW Request is TIM16_CH1 */
1054 #define LL_GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW Request is TIM16_UP */
1055 #define LL_GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW Request is TIM17_CH1 */
1056 #define LL_GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW Request is TIM17_UP */
1057 #define LL_GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW Request is DCMI_PSSI */
1058 #define LL_GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW Request is AES_IN */
1059 #define LL_GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW Request is AES_OUT */
1060 #define LL_GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW Request is HASH_IN */
1061 #if defined(UCPD1)
1062 #define LL_GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW Request is UCPD1_TX */
1063 #define LL_GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW Request is UCPD1_RX */
1064 #endif /* UCPD1 */
1065 #define LL_GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW Request is MDF1_FLT0 */
1066 #define LL_GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW Request is MDF1_FLT1 */
1067 #define LL_GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW Request is MDF1_FLT2 */
1068 #define LL_GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW Request is MDF1_FLT3 */
1069 #define LL_GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW Request is MDF1_FLT4 */
1070 #define LL_GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW Request is MDF1_FLT5 */
1071 #define LL_GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW Request is ADF1_FLT0 */
1072 #define LL_GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW Request is FMAC_READ */
1073 #define LL_GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW Request is FMAC_WRITE */
1074 #define LL_GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW Request is CORDIC_READ */
1075 #define LL_GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW Request is CORDIC_WRITE */
1076 #define LL_GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW Request is SAES_IN */
1077 #define LL_GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW Request is SAES_OUT */
1078 #define LL_GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW Request is LPTIM1_IC1 */
1079 #define LL_GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW Request is LPTIM1_IC2 */
1080 #define LL_GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW Request is LPTIM1_UE */
1081 #define LL_GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW Request is LPTIM2_IC1 */
1082 #define LL_GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW Request is LPTIM2_IC2 */
1083 #define LL_GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW Request is LPTIM2_UE */
1084 #define LL_GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW Request is LPTIM3_IC1 */
1085 #define LL_GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW Request is LPTIM3_IC2 */
1086 #define LL_GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW Request is LPTIM3_UE */
1087 #if defined (HSPI1_BASE)
1088 #define LL_GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */
1089 #endif /* HSPI1_BASE */
1090 #if defined (I2C5)
1091 #define LL_GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */
1092 #define LL_GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */
1093 #define LL_GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */
1094 #endif /* I2C5 */
1095 #if defined (I2C6)
1096 #define LL_GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */
1097 #define LL_GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */
1098 #define LL_GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */
1099 #endif /* I2C6 */
1100 #if defined (USART6)
1101 #define LL_GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */
1102 #define LL_GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */
1103 #endif /* USART6 */
1104 #if defined (ADC2)
1105 #define LL_GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */
1106 #endif /* ADC2 */
1107 #if defined (JPEG)
1108 #define LL_GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */
1109 #define LL_GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */
1110 #endif /* JPEG */
1111
1112 /* GPDMA1 Hardware Requests aliases */
1113 #define LL_GPDMA1_REQUEST_DCMI LL_GPDMA1_REQUEST_DCMI_PSSI
1114
1115 /* LPDMA1 Hardware Requests */
1116 #define LL_LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW Request is LPUART1_RX */
1117 #define LL_LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW Request is LPUART1_TX */
1118 #define LL_LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW Request is SPI3_RX */
1119 #define LL_LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW Request is SPI3_TX */
1120 #define LL_LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW Request is I2C3_RX */
1121 #define LL_LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW Request is I2C3_TX */
1122 #define LL_LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW Request is I2C3_EVC */
1123 #define LL_LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW Request is ADC4 */
1124 #define LL_LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW Request is DAC1_CH1 */
1125 #define LL_LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW Request is DAC1_CH2 */
1126 #define LL_LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW Request is ADF1_FLT0 */
1127 #define LL_LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW Request is LPTIM1_IC1 */
1128 #define LL_LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW Request is LPTIM1_IC2 */
1129 #define LL_LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW Request is LPTIM1_UE */
1130 #define LL_LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW Request is LPTIM3_IC1 */
1131 #define LL_LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW Request is LPTIM3_IC2 */
1132 #define LL_LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW Request is LPTIM3_UE */
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
1138 * @{
1139 */
1140 /* GPDMA1 Hardware Triggers */
1141 #define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger is EXTI_LINE0 */
1142 #define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger is EXTI_LINE1 */
1143 #define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger is EXTI_LINE2 */
1144 #define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger is EXTI_LINE3 */
1145 #define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger is EXTI_LINE4 */
1146 #define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger is EXTI_LINE5 */
1147 #define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger is EXTI_LINE6 */
1148 #define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger is EXTI_LINE7 */
1149 #define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger is TAMP_TRG1 */
1150 #define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger is TAMP_TRG2 */
1151 #define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger is TAMP_TRG3 */
1152 #define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger is LPTIM1_CH1 */
1153 #define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger is LPTIM1_CH2 */
1154 #define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger is LPTIM2_CH1 */
1155 #define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger is LPTIM2_CH2 */
1156 #define LL_GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger is LPTIM4_OUT */
1157 #define LL_GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger is COMP1_OUT */
1158 #if defined(COMP2)
1159 #define LL_GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger is COMP2_OUT */
1160 #endif /* COMP2 */
1161 #define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger is RTC_ALRA_TRG */
1162 #define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger is RTC_ALRB_TRG */
1163 #define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger is RTC_WUT_TRG */
1164 #define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger is GPDMA1_CH0_TCF */
1165 #define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger is GPDMA1_CH1_TCF */
1166 #define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger is GPDMA1_CH2_TCF */
1167 #define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger is GPDMA1_CH3_TCF */
1168 #define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger is GPDMA1_CH4_TCF */
1169 #define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger is GPDMA1_CH5_TCF */
1170 #define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger is GPDMA1_CH6_TCF */
1171 #define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger is GPDMA1_CH7_TCF */
1172 #define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger is GPDMA1_CH8_TCF */
1173 #define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger is GPDMA1_CH9_TCF */
1174 #define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger is GPDMA1_CH10_TCF */
1175 #define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger is GPDMA1_CH11_TCF */
1176 #define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger is GPDMA1_CH12_TCF */
1177 #define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger is GPDMA1_CH13_TCF */
1178 #define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger is GPDMA1_CH14_TCF */
1179 #define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger is GPDMA1_CH15_TCF */
1180 #define LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger is LPDMA1_CH0_TCF */
1181 #define LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger is LPDMA1_CH1_TCF */
1182 #define LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger is LPDMA1_CH2_TCF */
1183 #define LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger is LPDMA1_CH3_TCF */
1184 #define LL_GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger is TIM2_TRGO */
1185 #define LL_GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger is TIM15_TRGO */
1186 #define LL_GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger is ADC4_AWD1 */
1187 #define LL_GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger is ADC1_AWD1 */
1188 #if defined (TIM3_TRGO_TRIGGER_SUPPORT)
1189 #define LL_GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
1190 #endif /* TIM3_TRGO_TRIGGER_SUPPORT */
1191 #if defined (TIM4_TRGO_TRIGGER_SUPPORT)
1192 #define LL_GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */
1193 #endif /* TIM4_TRGO_TRIGGER_SUPPORT */
1194 #if defined (TIM5_TRGO_TRIGGER_SUPPORT)
1195 #define LL_GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */
1196 #endif /* TIM5_TRGO_TRIGGER_SUPPORT */
1197 #if defined (LTDC)
1198 #define LL_GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */
1199 #endif /* LTDC */
1200 #if defined (DSI)
1201 #define LL_GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */
1202 #define LL_GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */
1203 #endif /* DSI */
1204 #if defined (DMA2D)
1205 #define LL_GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */
1206 #define LL_GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */
1207 #define LL_GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */
1208 #endif /* DMA2D */
1209 #if defined (GPU2D)
1210 #define LL_GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */
1211 #define LL_GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */
1212 #define LL_GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */
1213 #define LL_GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */
1214 #endif /* GPU2D */
1215 #if defined (GFXTIM)
1216 #define LL_GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */
1217 #define LL_GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */
1218 #define LL_GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */
1219 #define LL_GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */
1220 #endif /* GFXTIM */
1221 #if defined (JPEG)
1222 #define LL_GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */
1223 #define LL_GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */
1224 #define LL_GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */
1225 #define LL_GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */
1226 #define LL_GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */
1227 #endif /* JPEG */
1228
1229 /* LPDMA1 triggers */
1230 #define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger is EXTI_LINE0 */
1231 #define LL_LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger is EXTI_LINE1 */
1232 #define LL_LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger is EXTI_LINE2 */
1233 #define LL_LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger is EXTI_LINE3 */
1234 #define LL_LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger is EXTI_LINE4 */
1235 #define LL_LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger is TAMP_TRG1 */
1236 #define LL_LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger is TAMP_TRG2 */
1237 #define LL_LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger is TAMP_TRG3 */
1238 #define LL_LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */
1239 #define LL_LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */
1240 #define LL_LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger is LPTIM3_CH1 */
1241 #define LL_LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger is LPTIM4_OUT */
1242 #define LL_LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger is COMP1_OUT */
1243 #if defined(COMP2)
1244 #define LL_LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger is COMP2_OUT */
1245 #endif /* COMP2 */
1246 #define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */
1247 #define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */
1248 #define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */
1249 #define LL_LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger is ADC4_AWD1 */
1250 #define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TCF */
1251 #define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TCF */
1252 #define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TCF */
1253 #define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TCF */
1254 #define LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger is GPDMA1_CH0_TCF */
1255 #define LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger is GPDMA1_CH1_TCF */
1256 #define LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger is GPDMA1_CH4_TCF */
1257 #define LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger is GPDMA1_CH5_TCF */
1258 #define LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger is GPDMA1_CH6_TCF */
1259 #define LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger is GPDMA1_CH7_TCF */
1260 #define LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger is GPDMA1_CH12_TCF */
1261 #define LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger is GPDMA1_CH13_TCF */
1262 #define LL_LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger is TIM2_TRGO */
1263 #define LL_LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger is TIM15_TRGO */
1264 /**
1265 * @}
1266 */
1267
1268 /**
1269 * @}
1270 */
1271
1272 /* Exported macro ------------------------------------------------------------*/
1273
1274 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
1275 * @{
1276 */
1277
1278 /** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
1279 * @{
1280 */
1281 /**
1282 * @brief Write a value in DMA register.
1283 * @param __INSTANCE__ DMA Instance.
1284 * @param __REG__ Register to be written.
1285 * @param __VALUE__ Value to be written in the register.
1286 * @retval None.
1287 */
1288 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1289
1290 /**
1291 * @brief Read a value in DMA register.
1292 * @param __INSTANCE__ DMA Instance.
1293 * @param __REG__ Register to be read.
1294 * @retval Register value.
1295 */
1296 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1297 /**
1298 * @}
1299 */
1300
1301 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
1302 * @{
1303 */
1304 /**
1305 * @brief Convert DMAx_Channely into DMAx.
1306 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1307 * @retval DMAx.
1308 */
1309 #define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
1310 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? LPDMA1 : GPDMA1)
1311
1312 /**
1313 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
1314 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1315 * @retval LL_DMA_CHANNEL_y.
1316 */
1317 #define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
1318 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
1319 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
1320 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
1321 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
1322 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
1323 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
1324 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
1325 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
1326 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
1327 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
1328 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
1329 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
1330 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \
1331 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \
1332 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
1333 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
1334 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
1335 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
1336 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
1337 LL_DMA_CHANNEL_15)
1338
1339 /**
1340 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
1341 * @param __DMA_INSTANCE__ DMAx.
1342 * @param __CHANNEL__ LL_DMA_CHANNEL_y.
1343 * @retval DMAx_Channely.
1344 */
1345 #define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
1346 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1347 ? GPDMA1_Channel0 : \
1348 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1349 ? LPDMA1_Channel0 : \
1350 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1351 ? GPDMA1_Channel1 : \
1352 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1353 ? LPDMA1_Channel1 : \
1354 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
1355 ? GPDMA1_Channel2 : \
1356 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
1357 ? LPDMA1_Channel2 : \
1358 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
1359 ? GPDMA1_Channel3 : \
1360 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
1361 ? LPDMA1_Channel3 : \
1362 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
1363 ? GPDMA1_Channel4 : \
1364 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
1365 ? GPDMA1_Channel5 : \
1366 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
1367 ? GPDMA1_Channel6 : \
1368 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
1369 ? GPDMA1_Channel7 : \
1370 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
1371 ? GPDMA1_Channel8 : \
1372 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
1373 ? GPDMA1_Channel9 : \
1374 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
1375 ? GPDMA1_Channel10 : \
1376 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
1377 ? GPDMA1_Channel11 : \
1378 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
1379 ? GPDMA1_Channel12 : \
1380 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
1381 ? GPDMA1_Channel13 : \
1382 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
1383 ? GPDMA1_Channel14 : GPDMA1_Channel15)
1384
1385 /**
1386 * @}
1387 */
1388
1389 /**
1390 * @}
1391 */
1392
1393 /* Exported functions --------------------------------------------------------*/
1394
1395 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
1396 * @{
1397 */
1398
1399 /** @defgroup DMA_LL_EF_Configuration Configuration
1400 * @{
1401 */
1402 /**
1403 * @brief Enable channel.
1404 * @note This API is used for all available DMA channels.
1405 * @rmtoll CCR EN LL_DMA_EnableChannel
1406 * @param DMAx DMAx Instance.
1407 * @param Channel This parameter can be one of the following values:
1408 * @arg @ref LL_DMA_CHANNEL_0
1409 * @arg @ref LL_DMA_CHANNEL_1
1410 * @arg @ref LL_DMA_CHANNEL_2
1411 * @arg @ref LL_DMA_CHANNEL_3
1412 * @arg @ref LL_DMA_CHANNEL_4
1413 * @arg @ref LL_DMA_CHANNEL_5
1414 * @arg @ref LL_DMA_CHANNEL_6
1415 * @arg @ref LL_DMA_CHANNEL_7
1416 * @arg @ref LL_DMA_CHANNEL_8
1417 * @arg @ref LL_DMA_CHANNEL_9
1418 * @arg @ref LL_DMA_CHANNEL_10
1419 * @arg @ref LL_DMA_CHANNEL_11
1420 * @arg @ref LL_DMA_CHANNEL_12
1421 * @arg @ref LL_DMA_CHANNEL_13
1422 * @arg @ref LL_DMA_CHANNEL_14
1423 * @arg @ref LL_DMA_CHANNEL_15
1424 * @retval None.
1425 */
LL_DMA_EnableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1426 __STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1427 {
1428 uint32_t dma_base_addr = (uint32_t)DMAx;
1429 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
1430 }
1431
1432 /**
1433 * @brief Disable channel.
1434 * @note This API is used for all available DMA channels.
1435 * @rmtoll CCR EN LL_DMA_DisableChannel
1436 * @param DMAx DMAx Instance.
1437 * @param Channel This parameter can be one of the following values:
1438 * @arg @ref LL_DMA_CHANNEL_0
1439 * @arg @ref LL_DMA_CHANNEL_1
1440 * @arg @ref LL_DMA_CHANNEL_2
1441 * @arg @ref LL_DMA_CHANNEL_3
1442 * @arg @ref LL_DMA_CHANNEL_4
1443 * @arg @ref LL_DMA_CHANNEL_5
1444 * @arg @ref LL_DMA_CHANNEL_6
1445 * @arg @ref LL_DMA_CHANNEL_7
1446 * @arg @ref LL_DMA_CHANNEL_8
1447 * @arg @ref LL_DMA_CHANNEL_9
1448 * @arg @ref LL_DMA_CHANNEL_10
1449 * @arg @ref LL_DMA_CHANNEL_11
1450 * @arg @ref LL_DMA_CHANNEL_12
1451 * @arg @ref LL_DMA_CHANNEL_13
1452 * @arg @ref LL_DMA_CHANNEL_14
1453 * @arg @ref LL_DMA_CHANNEL_15
1454 * @retval None.
1455 */
LL_DMA_DisableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1456 __STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1457 {
1458 uint32_t dma_base_addr = (uint32_t)DMAx;
1459 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1460 (DMA_CCR_SUSP | DMA_CCR_RESET));
1461 }
1462
1463 /**
1464 * @brief Check if channel is enabled or disabled.
1465 * @note This API is used for all available DMA channels.
1466 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
1467 * @param DMAx DMAx Instance
1468 * @param Channel This parameter can be one of the following values:
1469 * @arg @ref LL_DMA_CHANNEL_0
1470 * @arg @ref LL_DMA_CHANNEL_1
1471 * @arg @ref LL_DMA_CHANNEL_2
1472 * @arg @ref LL_DMA_CHANNEL_3
1473 * @arg @ref LL_DMA_CHANNEL_4
1474 * @arg @ref LL_DMA_CHANNEL_5
1475 * @arg @ref LL_DMA_CHANNEL_6
1476 * @arg @ref LL_DMA_CHANNEL_7
1477 * @arg @ref LL_DMA_CHANNEL_8
1478 * @arg @ref LL_DMA_CHANNEL_9
1479 * @arg @ref LL_DMA_CHANNEL_10
1480 * @arg @ref LL_DMA_CHANNEL_11
1481 * @arg @ref LL_DMA_CHANNEL_12
1482 * @arg @ref LL_DMA_CHANNEL_13
1483 * @arg @ref LL_DMA_CHANNEL_14
1484 * @arg @ref LL_DMA_CHANNEL_15
1485 * @retval State of bit (1 or 0).
1486 */
LL_DMA_IsEnabledChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1487 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1488 {
1489 uint32_t dma_base_addr = (uint32_t)DMAx;
1490 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
1491 == (DMA_CCR_EN)) ? 1UL : 0UL);
1492 }
1493
1494 /**
1495 * @brief Reset channel.
1496 * @note This API is used for all available DMA channels.
1497 * @rmtoll CCR RESET LL_DMA_ResetChannel
1498 * @param DMAx DMAx Instance
1499 * @param Channel This parameter can be one of the following values:
1500 * @arg @ref LL_DMA_CHANNEL_0
1501 * @arg @ref LL_DMA_CHANNEL_1
1502 * @arg @ref LL_DMA_CHANNEL_2
1503 * @arg @ref LL_DMA_CHANNEL_3
1504 * @arg @ref LL_DMA_CHANNEL_4
1505 * @arg @ref LL_DMA_CHANNEL_5
1506 * @arg @ref LL_DMA_CHANNEL_6
1507 * @arg @ref LL_DMA_CHANNEL_7
1508 * @arg @ref LL_DMA_CHANNEL_8
1509 * @arg @ref LL_DMA_CHANNEL_9
1510 * @arg @ref LL_DMA_CHANNEL_10
1511 * @arg @ref LL_DMA_CHANNEL_11
1512 * @arg @ref LL_DMA_CHANNEL_12
1513 * @arg @ref LL_DMA_CHANNEL_13
1514 * @arg @ref LL_DMA_CHANNEL_14
1515 * @arg @ref LL_DMA_CHANNEL_15
1516 * @retval None.
1517 */
LL_DMA_ResetChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1518 __STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1519 {
1520 uint32_t dma_base_addr = (uint32_t)DMAx;
1521 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
1522 }
1523
1524 /**
1525 * @brief Suspend channel.
1526 * @note This API is used for all available DMA channels.
1527 * @rmtoll CCR SUSP LL_DMA_SuspendChannel
1528 * @param DMAx DMAx Instance
1529 * @param Channel This parameter can be one of the following values:
1530 * @arg @ref LL_DMA_CHANNEL_0
1531 * @arg @ref LL_DMA_CHANNEL_1
1532 * @arg @ref LL_DMA_CHANNEL_2
1533 * @arg @ref LL_DMA_CHANNEL_3
1534 * @arg @ref LL_DMA_CHANNEL_4
1535 * @arg @ref LL_DMA_CHANNEL_5
1536 * @arg @ref LL_DMA_CHANNEL_6
1537 * @arg @ref LL_DMA_CHANNEL_7
1538 * @arg @ref LL_DMA_CHANNEL_8
1539 * @arg @ref LL_DMA_CHANNEL_9
1540 * @arg @ref LL_DMA_CHANNEL_10
1541 * @arg @ref LL_DMA_CHANNEL_11
1542 * @arg @ref LL_DMA_CHANNEL_12
1543 * @arg @ref LL_DMA_CHANNEL_13
1544 * @arg @ref LL_DMA_CHANNEL_14
1545 * @arg @ref LL_DMA_CHANNEL_15
1546 * @retval None.
1547 */
LL_DMA_SuspendChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1548 __STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1549 {
1550 uint32_t dma_base_addr = (uint32_t)DMAx;
1551 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1552 }
1553
1554 /**
1555 * @brief Resume channel.
1556 * @note This API is used for all available DMA channels.
1557 * @rmtoll CCR SUSP LL_DMA_ResumeChannel
1558 * @param DMAx DMAx Instance
1559 * @param Channel This parameter can be one of the following values:
1560 * @arg @ref LL_DMA_CHANNEL_0
1561 * @arg @ref LL_DMA_CHANNEL_1
1562 * @arg @ref LL_DMA_CHANNEL_2
1563 * @arg @ref LL_DMA_CHANNEL_3
1564 * @arg @ref LL_DMA_CHANNEL_4
1565 * @arg @ref LL_DMA_CHANNEL_5
1566 * @arg @ref LL_DMA_CHANNEL_6
1567 * @arg @ref LL_DMA_CHANNEL_7
1568 * @arg @ref LL_DMA_CHANNEL_8
1569 * @arg @ref LL_DMA_CHANNEL_9
1570 * @arg @ref LL_DMA_CHANNEL_10
1571 * @arg @ref LL_DMA_CHANNEL_11
1572 * @arg @ref LL_DMA_CHANNEL_12
1573 * @arg @ref LL_DMA_CHANNEL_13
1574 * @arg @ref LL_DMA_CHANNEL_14
1575 * @arg @ref LL_DMA_CHANNEL_15
1576 * @retval None.
1577 */
LL_DMA_ResumeChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1578 __STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1579 {
1580 uint32_t dma_base_addr = (uint32_t)DMAx;
1581 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1582 }
1583
1584 /**
1585 * @brief Check if channel is suspended.
1586 * @note This API is used for all available DMA channels.
1587 * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
1588 * @param DMAx DMAx Instance
1589 * @param Channel This parameter can be one of the following values:
1590 * @arg @ref LL_DMA_CHANNEL_0
1591 * @arg @ref LL_DMA_CHANNEL_1
1592 * @arg @ref LL_DMA_CHANNEL_2
1593 * @arg @ref LL_DMA_CHANNEL_3
1594 * @arg @ref LL_DMA_CHANNEL_4
1595 * @arg @ref LL_DMA_CHANNEL_5
1596 * @arg @ref LL_DMA_CHANNEL_6
1597 * @arg @ref LL_DMA_CHANNEL_7
1598 * @arg @ref LL_DMA_CHANNEL_8
1599 * @arg @ref LL_DMA_CHANNEL_9
1600 * @arg @ref LL_DMA_CHANNEL_10
1601 * @arg @ref LL_DMA_CHANNEL_11
1602 * @arg @ref LL_DMA_CHANNEL_12
1603 * @arg @ref LL_DMA_CHANNEL_13
1604 * @arg @ref LL_DMA_CHANNEL_14
1605 * @arg @ref LL_DMA_CHANNEL_15
1606 * @retval State of bit (1 or 0).
1607 */
LL_DMA_IsSuspendedChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1608 __STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1609 {
1610 uint32_t dma_base_addr = (uint32_t)DMAx;
1611 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
1612 == (DMA_CCR_SUSP)) ? 1UL : 0UL);
1613 }
1614
1615 /**
1616 * @brief Set linked-list base address.
1617 * @note This API is used for all available DMA channels.
1618 * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
1619 * @param DMAx DMAx Instance
1620 * @param Channel This parameter can be one of the following values:
1621 * @arg @ref LL_DMA_CHANNEL_0
1622 * @arg @ref LL_DMA_CHANNEL_1
1623 * @arg @ref LL_DMA_CHANNEL_2
1624 * @arg @ref LL_DMA_CHANNEL_3
1625 * @arg @ref LL_DMA_CHANNEL_4
1626 * @arg @ref LL_DMA_CHANNEL_5
1627 * @arg @ref LL_DMA_CHANNEL_6
1628 * @arg @ref LL_DMA_CHANNEL_7
1629 * @arg @ref LL_DMA_CHANNEL_8
1630 * @arg @ref LL_DMA_CHANNEL_9
1631 * @arg @ref LL_DMA_CHANNEL_10
1632 * @arg @ref LL_DMA_CHANNEL_11
1633 * @arg @ref LL_DMA_CHANNEL_12
1634 * @arg @ref LL_DMA_CHANNEL_13
1635 * @arg @ref LL_DMA_CHANNEL_14
1636 * @arg @ref LL_DMA_CHANNEL_15
1637 * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
1638 * are always 0)
1639 * @retval None.
1640 */
LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListBaseAddr)1641 __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel,
1642 uint32_t LinkedListBaseAddr)
1643 {
1644 uint32_t dma_base_addr = (uint32_t)DMAx;
1645 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
1646 (LinkedListBaseAddr & DMA_CLBAR_LBA));
1647 }
1648
1649 /**
1650 * @brief Get linked-list base address.
1651 * @note This API is used for all available DMA channels.
1652 * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
1653 * @param DMAx DMAx Instance
1654 * @param Channel This parameter can be one of the following values:
1655 * @arg @ref LL_DMA_CHANNEL_0
1656 * @arg @ref LL_DMA_CHANNEL_1
1657 * @arg @ref LL_DMA_CHANNEL_2
1658 * @arg @ref LL_DMA_CHANNEL_3
1659 * @arg @ref LL_DMA_CHANNEL_4
1660 * @arg @ref LL_DMA_CHANNEL_5
1661 * @arg @ref LL_DMA_CHANNEL_6
1662 * @arg @ref LL_DMA_CHANNEL_7
1663 * @arg @ref LL_DMA_CHANNEL_8
1664 * @arg @ref LL_DMA_CHANNEL_9
1665 * @arg @ref LL_DMA_CHANNEL_10
1666 * @arg @ref LL_DMA_CHANNEL_11
1667 * @arg @ref LL_DMA_CHANNEL_12
1668 * @arg @ref LL_DMA_CHANNEL_13
1669 * @arg @ref LL_DMA_CHANNEL_14
1670 * @arg @ref LL_DMA_CHANNEL_15
1671 * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
1672 */
LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel)1673 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel)
1674 {
1675 uint32_t dma_base_addr = (uint32_t)DMAx;
1676 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
1677 }
1678
1679 /**
1680 * @brief Configure all parameters linked to channel control.
1681 * @note This API is used for all available DMA channels.
1682 * For LPDMA channels, LAP field programming is discarded.
1683 * @rmtoll CCR PRIO LL_DMA_ConfigControl\n
1684 * CCR LAP LL_DMA_ConfigControl\n
1685 * CCR LSM LL_DMA_ConfigControl
1686 * @param DMAx DMAx Instance
1687 * @param Channel This parameter can be one of the following values:
1688 * @arg @ref LL_DMA_CHANNEL_0
1689 * @arg @ref LL_DMA_CHANNEL_1
1690 * @arg @ref LL_DMA_CHANNEL_2
1691 * @arg @ref LL_DMA_CHANNEL_3
1692 * @arg @ref LL_DMA_CHANNEL_4
1693 * @arg @ref LL_DMA_CHANNEL_5
1694 * @arg @ref LL_DMA_CHANNEL_6
1695 * @arg @ref LL_DMA_CHANNEL_7
1696 * @arg @ref LL_DMA_CHANNEL_8
1697 * @arg @ref LL_DMA_CHANNEL_9
1698 * @arg @ref LL_DMA_CHANNEL_10
1699 * @arg @ref LL_DMA_CHANNEL_11
1700 * @arg @ref LL_DMA_CHANNEL_12
1701 * @arg @ref LL_DMA_CHANNEL_13
1702 * @arg @ref LL_DMA_CHANNEL_14
1703 * @arg @ref LL_DMA_CHANNEL_15
1704 * @param Configuration This parameter must be a combination of all the following values:
1705 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
1706 * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
1707 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
1708 * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
1709 *@retval None.
1710 */
LL_DMA_ConfigControl(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1711 __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1712 {
1713 uint32_t dma_base_addr = (uint32_t)DMAx;
1714 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1715 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
1716 }
1717
1718 /**
1719 * @brief Set priority level.
1720 * @note This API is used for all available DMA channels.
1721 * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
1722 * @param DMAx DMAx Instance
1723 * @param Channel This parameter can be one of the following values:
1724 * @arg @ref LL_DMA_CHANNEL_0
1725 * @arg @ref LL_DMA_CHANNEL_1
1726 * @arg @ref LL_DMA_CHANNEL_2
1727 * @arg @ref LL_DMA_CHANNEL_3
1728 * @arg @ref LL_DMA_CHANNEL_4
1729 * @arg @ref LL_DMA_CHANNEL_5
1730 * @arg @ref LL_DMA_CHANNEL_6
1731 * @arg @ref LL_DMA_CHANNEL_7
1732 * @arg @ref LL_DMA_CHANNEL_8
1733 * @arg @ref LL_DMA_CHANNEL_9
1734 * @arg @ref LL_DMA_CHANNEL_10
1735 * @arg @ref LL_DMA_CHANNEL_11
1736 * @arg @ref LL_DMA_CHANNEL_12
1737 * @arg @ref LL_DMA_CHANNEL_13
1738 * @arg @ref LL_DMA_CHANNEL_14
1739 * @arg @ref LL_DMA_CHANNEL_15
1740 * @param Priority This parameter can be one of the following values:
1741 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1742 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1743 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1744 * @arg @ref LL_DMA_HIGH_PRIORITY
1745 * @retval None.
1746 */
LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)1747 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
1748 {
1749 uint32_t dma_base_addr = (uint32_t)DMAx;
1750 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
1751 }
1752
1753 /**
1754 * @brief Get Channel priority level.
1755 * @note This API is used for all available DMA channels.
1756 * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
1757 * @param DMAx DMAx Instance
1758 * @param Channel This parameter can be one of the following values:
1759 * @arg @ref LL_DMA_CHANNEL_0
1760 * @arg @ref LL_DMA_CHANNEL_1
1761 * @arg @ref LL_DMA_CHANNEL_2
1762 * @arg @ref LL_DMA_CHANNEL_3
1763 * @arg @ref LL_DMA_CHANNEL_4
1764 * @arg @ref LL_DMA_CHANNEL_5
1765 * @arg @ref LL_DMA_CHANNEL_6
1766 * @arg @ref LL_DMA_CHANNEL_7
1767 * @arg @ref LL_DMA_CHANNEL_8
1768 * @arg @ref LL_DMA_CHANNEL_9
1769 * @arg @ref LL_DMA_CHANNEL_10
1770 * @arg @ref LL_DMA_CHANNEL_11
1771 * @arg @ref LL_DMA_CHANNEL_12
1772 * @arg @ref LL_DMA_CHANNEL_13
1773 * @arg @ref LL_DMA_CHANNEL_14
1774 * @arg @ref LL_DMA_CHANNEL_15
1775 * @retval Returned value can be one of the following values:
1776 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1777 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1778 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1779 * @arg @ref LL_DMA_HIGH_PRIORITY
1780 */
LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel)1781 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
1782 {
1783 uint32_t dma_base_addr = (uint32_t)DMAx;
1784 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
1785 }
1786
1787 /**
1788 * @brief Set linked-list allocated port.
1789 * @note This API is not used for LPDMA channels.
1790 * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
1791 * @param DMAx DMAx Instance
1792 * @param Channel This parameter can be one of the following values:
1793 * @arg @ref LL_DMA_CHANNEL_0
1794 * @arg @ref LL_DMA_CHANNEL_1
1795 * @arg @ref LL_DMA_CHANNEL_2
1796 * @arg @ref LL_DMA_CHANNEL_3
1797 * @arg @ref LL_DMA_CHANNEL_4
1798 * @arg @ref LL_DMA_CHANNEL_5
1799 * @arg @ref LL_DMA_CHANNEL_6
1800 * @arg @ref LL_DMA_CHANNEL_7
1801 * @arg @ref LL_DMA_CHANNEL_8
1802 * @arg @ref LL_DMA_CHANNEL_9
1803 * @arg @ref LL_DMA_CHANNEL_10
1804 * @arg @ref LL_DMA_CHANNEL_11
1805 * @arg @ref LL_DMA_CHANNEL_12
1806 * @arg @ref LL_DMA_CHANNEL_13
1807 * @arg @ref LL_DMA_CHANNEL_14
1808 * @arg @ref LL_DMA_CHANNEL_15
1809 * @param LinkAllocatedPort This parameter can be one of the following values:
1810 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1811 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1812 * @retval None.
1813 */
LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkAllocatedPort)1814 __STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
1815 {
1816 uint32_t dma_base_addr = (uint32_t)DMAx;
1817 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1818 DMA_CCR_LAP, LinkAllocatedPort);
1819 }
1820
1821 /**
1822 * @brief Get linked-list allocated port.
1823 * @note This API is not used for LPDMA channels.
1824 * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
1825 * @param DMAx DMAx Instance
1826 * @param Channel This parameter can be one of the following values:
1827 * @arg @ref LL_DMA_CHANNEL_0
1828 * @arg @ref LL_DMA_CHANNEL_1
1829 * @arg @ref LL_DMA_CHANNEL_2
1830 * @arg @ref LL_DMA_CHANNEL_3
1831 * @arg @ref LL_DMA_CHANNEL_4
1832 * @arg @ref LL_DMA_CHANNEL_5
1833 * @arg @ref LL_DMA_CHANNEL_6
1834 * @arg @ref LL_DMA_CHANNEL_7
1835 * @arg @ref LL_DMA_CHANNEL_8
1836 * @arg @ref LL_DMA_CHANNEL_9
1837 * @arg @ref LL_DMA_CHANNEL_10
1838 * @arg @ref LL_DMA_CHANNEL_11
1839 * @arg @ref LL_DMA_CHANNEL_12
1840 * @arg @ref LL_DMA_CHANNEL_13
1841 * @arg @ref LL_DMA_CHANNEL_14
1842 * @arg @ref LL_DMA_CHANNEL_15
1843 * @retval Returned value can be one of the following values:
1844 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1845 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1846 */
LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1847 __STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1848 {
1849 uint32_t dma_base_addr = (uint32_t)DMAx;
1850 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
1851 }
1852
1853 /**
1854 * @brief Set link step mode.
1855 * @note This API is used for all available DMA channels.
1856 * @rmtoll CCR LSM LL_DMA_SetLinkStepMode
1857 * @param DMAx DMAx Instance
1858 * @param Channel This parameter can be one of the following values:
1859 * @arg @ref LL_DMA_CHANNEL_0
1860 * @arg @ref LL_DMA_CHANNEL_1
1861 * @arg @ref LL_DMA_CHANNEL_2
1862 * @arg @ref LL_DMA_CHANNEL_3
1863 * @arg @ref LL_DMA_CHANNEL_4
1864 * @arg @ref LL_DMA_CHANNEL_5
1865 * @arg @ref LL_DMA_CHANNEL_6
1866 * @arg @ref LL_DMA_CHANNEL_7
1867 * @arg @ref LL_DMA_CHANNEL_8
1868 * @arg @ref LL_DMA_CHANNEL_9
1869 * @arg @ref LL_DMA_CHANNEL_10
1870 * @arg @ref LL_DMA_CHANNEL_11
1871 * @arg @ref LL_DMA_CHANNEL_12
1872 * @arg @ref LL_DMA_CHANNEL_13
1873 * @arg @ref LL_DMA_CHANNEL_14
1874 * @arg @ref LL_DMA_CHANNEL_15
1875 * @param LinkStepMode This parameter can be one of the following values:
1876 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1877 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1878 * @retval None.
1879 */
LL_DMA_SetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkStepMode)1880 __STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
1881 {
1882 uint32_t dma_base_addr = (uint32_t)DMAx;
1883 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
1884 }
1885
1886 /**
1887 * @brief Get Link step mode.
1888 * @note This API is used for all available DMA channels.
1889 * @rmtoll CCR LSM LL_DMA_GetLinkStepMode
1890 * @param DMAx DMAx Instance
1891 * @param Channel This parameter can be one of the following values:
1892 * @arg @ref LL_DMA_CHANNEL_0
1893 * @arg @ref LL_DMA_CHANNEL_1
1894 * @arg @ref LL_DMA_CHANNEL_2
1895 * @arg @ref LL_DMA_CHANNEL_3
1896 * @arg @ref LL_DMA_CHANNEL_4
1897 * @arg @ref LL_DMA_CHANNEL_5
1898 * @arg @ref LL_DMA_CHANNEL_6
1899 * @arg @ref LL_DMA_CHANNEL_7
1900 * @arg @ref LL_DMA_CHANNEL_8
1901 * @arg @ref LL_DMA_CHANNEL_9
1902 * @arg @ref LL_DMA_CHANNEL_10
1903 * @arg @ref LL_DMA_CHANNEL_11
1904 * @arg @ref LL_DMA_CHANNEL_12
1905 * @arg @ref LL_DMA_CHANNEL_13
1906 * @arg @ref LL_DMA_CHANNEL_14
1907 * @arg @ref LL_DMA_CHANNEL_15
1908 * @retval Returned value can be one of the following values:
1909 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1910 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1911 */
LL_DMA_GetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel)1912 __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel)
1913 {
1914 uint32_t dma_base_addr = (uint32_t)DMAx;
1915 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
1916 }
1917
1918 /**
1919 * @brief Configure data transfer.
1920 * @note This API is used for all available DMA channels.
1921 * For LPDMA channels DAP, DHX, DBX, SAP, SBX fields programming is
1922 * discarded.
1923 * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
1924 * CTR1 DHX LL_DMA_ConfigTransfer\n
1925 * CTR1 DBX LL_DMA_ConfigTransfer\n
1926 * CTR1 DINC LL_DMA_ConfigTransfer\n
1927 * CTR1 SAP LL_DMA_ConfigTransfer\n
1928 * CTR1 SBX LL_DMA_ConfigTransfer\n
1929 * CTR1 PAM LL_DMA_ConfigTransfer\n
1930 * CTR1 SINC LL_DMA_ConfigTransfer
1931 * @param DMAx DMAx Instance
1932 * @param Channel This parameter can be one of the following values:
1933 * @arg @ref LL_DMA_CHANNEL_0
1934 * @arg @ref LL_DMA_CHANNEL_1
1935 * @arg @ref LL_DMA_CHANNEL_2
1936 * @arg @ref LL_DMA_CHANNEL_3
1937 * @arg @ref LL_DMA_CHANNEL_4
1938 * @arg @ref LL_DMA_CHANNEL_5
1939 * @arg @ref LL_DMA_CHANNEL_6
1940 * @arg @ref LL_DMA_CHANNEL_7
1941 * @arg @ref LL_DMA_CHANNEL_8
1942 * @arg @ref LL_DMA_CHANNEL_9
1943 * @arg @ref LL_DMA_CHANNEL_10
1944 * @arg @ref LL_DMA_CHANNEL_11
1945 * @arg @ref LL_DMA_CHANNEL_12
1946 * @arg @ref LL_DMA_CHANNEL_13
1947 * @arg @ref LL_DMA_CHANNEL_14
1948 * @arg @ref LL_DMA_CHANNEL_15
1949 * @param Configuration This parameter must be a combination of all the following values:
1950 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
1951 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
1952 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
1953 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
1954 * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
1955 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
1956 * @ref LL_DMA_DEST_DATAWIDTH_WORD
1957 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
1958 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
1959 * @ref LL_DMA_DATA_PACK_UNPACK
1960 * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
1961 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
1962 * @ref LL_DMA_SRC_DATAWIDTH_WORD
1963 *@retval None.
1964 */
LL_DMA_ConfigTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1965 __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1966 {
1967 uint32_t dma_base_addr = (uint32_t)DMAx;
1968 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1969 DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \
1970 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
1971 }
1972
1973 /**
1974 * @brief Configure source and destination burst length.
1975 * @note This API is not used for LPDMA channels.
1976 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
1977 * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
1978 * @param DMAx DMAx Instance
1979 * @param Channel This parameter can be one of the following values:
1980 * @arg @ref LL_DMA_CHANNEL_0
1981 * @arg @ref LL_DMA_CHANNEL_1
1982 * @arg @ref LL_DMA_CHANNEL_2
1983 * @arg @ref LL_DMA_CHANNEL_3
1984 * @arg @ref LL_DMA_CHANNEL_4
1985 * @arg @ref LL_DMA_CHANNEL_5
1986 * @arg @ref LL_DMA_CHANNEL_6
1987 * @arg @ref LL_DMA_CHANNEL_7
1988 * @arg @ref LL_DMA_CHANNEL_8
1989 * @arg @ref LL_DMA_CHANNEL_9
1990 * @arg @ref LL_DMA_CHANNEL_10
1991 * @arg @ref LL_DMA_CHANNEL_11
1992 * @arg @ref LL_DMA_CHANNEL_12
1993 * @arg @ref LL_DMA_CHANNEL_13
1994 * @arg @ref LL_DMA_CHANNEL_14
1995 * @arg @ref LL_DMA_CHANNEL_15
1996 * @param SrcBurstLength Between 1 to 64
1997 * @param DestBurstLength Between 1 to 64
1998 * @retval None.
1999 */
LL_DMA_ConfigBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength,uint32_t DestBurstLength)2000 __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
2001 uint32_t DestBurstLength)
2002 {
2003 uint32_t dma_base_addr = (uint32_t)DMAx;
2004 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2005 (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
2006 (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
2007 }
2008
2009 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2010 /**
2011 * @brief Configure all secure parameters linked to DMA channel.
2012 * @note This API is used for all available DMA channels.
2013 * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n
2014 * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n
2015 * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure
2016 * @param DMAx DMAx Instance
2017 * @param Channel This parameter can be one of the following values:
2018 * @arg @ref LL_DMA_CHANNEL_0
2019 * @arg @ref LL_DMA_CHANNEL_1
2020 * @arg @ref LL_DMA_CHANNEL_2
2021 * @arg @ref LL_DMA_CHANNEL_3
2022 * @arg @ref LL_DMA_CHANNEL_4
2023 * @arg @ref LL_DMA_CHANNEL_5
2024 * @arg @ref LL_DMA_CHANNEL_6
2025 * @arg @ref LL_DMA_CHANNEL_7
2026 * @arg @ref LL_DMA_CHANNEL_8
2027 * @arg @ref LL_DMA_CHANNEL_9
2028 * @arg @ref LL_DMA_CHANNEL_10
2029 * @arg @ref LL_DMA_CHANNEL_11
2030 * @arg @ref LL_DMA_CHANNEL_12
2031 * @arg @ref LL_DMA_CHANNEL_13
2032 * @arg @ref LL_DMA_CHANNEL_14
2033 * @arg @ref LL_DMA_CHANNEL_15
2034 * @param Configuration This parameter must be a combination of all the following values:
2035 * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC
2036 * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC
2037 * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
2038 * @retval None.
2039 */
LL_DMA_ConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2040 __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2041 {
2042 uint32_t dma_base_addr = (uint32_t)DMAx;
2043 MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
2044 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2045 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
2046 }
2047
2048 /**
2049 * @brief Enable security attribute of the DMA transfer to the destination.
2050 * @note This API is used for all available DMA channels.
2051 * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure
2052 * @param DMAx DMAx Instance
2053 * @param Channel This parameter can be one of the following values:
2054 * @arg @ref LL_DMA_CHANNEL_0
2055 * @arg @ref LL_DMA_CHANNEL_1
2056 * @arg @ref LL_DMA_CHANNEL_2
2057 * @arg @ref LL_DMA_CHANNEL_3
2058 * @arg @ref LL_DMA_CHANNEL_4
2059 * @arg @ref LL_DMA_CHANNEL_5
2060 * @arg @ref LL_DMA_CHANNEL_6
2061 * @arg @ref LL_DMA_CHANNEL_7
2062 * @arg @ref LL_DMA_CHANNEL_8
2063 * @arg @ref LL_DMA_CHANNEL_9
2064 * @arg @ref LL_DMA_CHANNEL_10
2065 * @arg @ref LL_DMA_CHANNEL_11
2066 * @arg @ref LL_DMA_CHANNEL_12
2067 * @arg @ref LL_DMA_CHANNEL_13
2068 * @arg @ref LL_DMA_CHANNEL_14
2069 * @arg @ref LL_DMA_CHANNEL_15
2070 * @retval None.
2071 */
LL_DMA_EnableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2072 __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2073 {
2074 uint32_t dma_base_addr = (uint32_t)DMAx;
2075 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
2076 }
2077
2078 /**
2079 * @brief Disable security attribute of the DMA transfer to the destination.
2080 * @note This API is used for all available DMA channels.
2081 * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure
2082 * @param DMAx DMAx Instance
2083 * @param Channel This parameter can be one of the following values:
2084 * @arg @ref LL_DMA_CHANNEL_0
2085 * @arg @ref LL_DMA_CHANNEL_1
2086 * @arg @ref LL_DMA_CHANNEL_2
2087 * @arg @ref LL_DMA_CHANNEL_3
2088 * @arg @ref LL_DMA_CHANNEL_4
2089 * @arg @ref LL_DMA_CHANNEL_5
2090 * @arg @ref LL_DMA_CHANNEL_6
2091 * @arg @ref LL_DMA_CHANNEL_7
2092 * @arg @ref LL_DMA_CHANNEL_8
2093 * @arg @ref LL_DMA_CHANNEL_9
2094 * @arg @ref LL_DMA_CHANNEL_10
2095 * @arg @ref LL_DMA_CHANNEL_11
2096 * @arg @ref LL_DMA_CHANNEL_12
2097 * @arg @ref LL_DMA_CHANNEL_13
2098 * @arg @ref LL_DMA_CHANNEL_14
2099 * @arg @ref LL_DMA_CHANNEL_15
2100 * @retval None.
2101 */
LL_DMA_DisableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2102 __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2103 {
2104 uint32_t dma_base_addr = (uint32_t)DMAx;
2105 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
2106 }
2107 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2108
2109 /**
2110 * @brief Check security attribute of the DMA transfer to the destination.
2111 * @note This API is used for all available DMA channels.
2112 * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure
2113 * @param DMAx DMAx Instance
2114 * @param Channel This parameter can be one of the following values:
2115 * @arg @ref LL_DMA_CHANNEL_0
2116 * @arg @ref LL_DMA_CHANNEL_1
2117 * @arg @ref LL_DMA_CHANNEL_2
2118 * @arg @ref LL_DMA_CHANNEL_3
2119 * @arg @ref LL_DMA_CHANNEL_4
2120 * @arg @ref LL_DMA_CHANNEL_5
2121 * @arg @ref LL_DMA_CHANNEL_6
2122 * @arg @ref LL_DMA_CHANNEL_7
2123 * @arg @ref LL_DMA_CHANNEL_8
2124 * @arg @ref LL_DMA_CHANNEL_9
2125 * @arg @ref LL_DMA_CHANNEL_10
2126 * @arg @ref LL_DMA_CHANNEL_11
2127 * @arg @ref LL_DMA_CHANNEL_12
2128 * @arg @ref LL_DMA_CHANNEL_13
2129 * @arg @ref LL_DMA_CHANNEL_14
2130 * @arg @ref LL_DMA_CHANNEL_15
2131 * @retval State of bit (1 or 0).
2132 */
LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2133 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2134 {
2135 uint32_t dma_base_addr = (uint32_t)DMAx;
2136 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
2137 == (DMA_CTR1_DSEC)) ? 1UL : 0UL);
2138 }
2139
2140 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2141 /**
2142 * @brief Enable security attribute of the DMA transfer from the source.
2143 * @note This API is used for all available DMA channels.
2144 * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure
2145 * @param DMAx DMAx Instance
2146 * @param Channel This parameter can be one of the following values:
2147 * @arg @ref LL_DMA_CHANNEL_0
2148 * @arg @ref LL_DMA_CHANNEL_1
2149 * @arg @ref LL_DMA_CHANNEL_2
2150 * @arg @ref LL_DMA_CHANNEL_3
2151 * @arg @ref LL_DMA_CHANNEL_4
2152 * @arg @ref LL_DMA_CHANNEL_5
2153 * @arg @ref LL_DMA_CHANNEL_6
2154 * @arg @ref LL_DMA_CHANNEL_7
2155 * @arg @ref LL_DMA_CHANNEL_8
2156 * @arg @ref LL_DMA_CHANNEL_9
2157 * @arg @ref LL_DMA_CHANNEL_10
2158 * @arg @ref LL_DMA_CHANNEL_11
2159 * @arg @ref LL_DMA_CHANNEL_12
2160 * @arg @ref LL_DMA_CHANNEL_13
2161 * @arg @ref LL_DMA_CHANNEL_14
2162 * @arg @ref LL_DMA_CHANNEL_15
2163 * @retval None.
2164 */
LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2165 __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2166 {
2167 uint32_t dma_base_addr = (uint32_t)DMAx;
2168 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
2169 }
2170
2171 /**
2172 * @brief Disable security attribute of the DMA transfer from the source.
2173 * @note This API is used for all available DMA channels.
2174 * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure
2175 * @param DMAx DMAx Instance
2176 * @param Channel This parameter can be one of the following values:
2177 * @arg @ref LL_DMA_CHANNEL_0
2178 * @arg @ref LL_DMA_CHANNEL_1
2179 * @arg @ref LL_DMA_CHANNEL_2
2180 * @arg @ref LL_DMA_CHANNEL_3
2181 * @arg @ref LL_DMA_CHANNEL_4
2182 * @arg @ref LL_DMA_CHANNEL_5
2183 * @arg @ref LL_DMA_CHANNEL_6
2184 * @arg @ref LL_DMA_CHANNEL_7
2185 * @arg @ref LL_DMA_CHANNEL_8
2186 * @arg @ref LL_DMA_CHANNEL_9
2187 * @arg @ref LL_DMA_CHANNEL_10
2188 * @arg @ref LL_DMA_CHANNEL_11
2189 * @arg @ref LL_DMA_CHANNEL_12
2190 * @arg @ref LL_DMA_CHANNEL_13
2191 * @arg @ref LL_DMA_CHANNEL_14
2192 * @arg @ref LL_DMA_CHANNEL_15
2193 * @retval None.
2194 */
LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2195 __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2196 {
2197 uint32_t dma_base_addr = (uint32_t)DMAx;
2198 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
2199 }
2200 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2201
2202 /**
2203 * @brief Check security attribute of the DMA transfer from the source.
2204 * @note This API is used for all available DMA channels.
2205 * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure
2206 * @param DMAx DMAx Instance
2207 * @param Channel This parameter can be one of the following values:
2208 * @arg @ref LL_DMA_CHANNEL_0
2209 * @arg @ref LL_DMA_CHANNEL_1
2210 * @arg @ref LL_DMA_CHANNEL_2
2211 * @arg @ref LL_DMA_CHANNEL_3
2212 * @arg @ref LL_DMA_CHANNEL_4
2213 * @arg @ref LL_DMA_CHANNEL_5
2214 * @arg @ref LL_DMA_CHANNEL_6
2215 * @arg @ref LL_DMA_CHANNEL_7
2216 * @arg @ref LL_DMA_CHANNEL_8
2217 * @arg @ref LL_DMA_CHANNEL_9
2218 * @arg @ref LL_DMA_CHANNEL_10
2219 * @arg @ref LL_DMA_CHANNEL_11
2220 * @arg @ref LL_DMA_CHANNEL_12
2221 * @arg @ref LL_DMA_CHANNEL_13
2222 * @arg @ref LL_DMA_CHANNEL_14
2223 * @arg @ref LL_DMA_CHANNEL_15
2224 * @retval State of bit (1 or 0).
2225 */
LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2226 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2227 {
2228 uint32_t dma_base_addr = (uint32_t)DMAx;
2229 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
2230 == (DMA_CTR1_SSEC)) ? 1UL : 0UL);
2231 }
2232
2233 /**
2234 * @brief Set destination allocated port.
2235 * @note This API is not used for LPDMA channels.
2236 * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
2237 * @param DMAx DMAx Instance
2238 * @param Channel This parameter can be one of the following values:
2239 * @arg @ref LL_DMA_CHANNEL_0
2240 * @arg @ref LL_DMA_CHANNEL_1
2241 * @arg @ref LL_DMA_CHANNEL_2
2242 * @arg @ref LL_DMA_CHANNEL_3
2243 * @arg @ref LL_DMA_CHANNEL_4
2244 * @arg @ref LL_DMA_CHANNEL_5
2245 * @arg @ref LL_DMA_CHANNEL_6
2246 * @arg @ref LL_DMA_CHANNEL_7
2247 * @arg @ref LL_DMA_CHANNEL_8
2248 * @arg @ref LL_DMA_CHANNEL_9
2249 * @arg @ref LL_DMA_CHANNEL_10
2250 * @arg @ref LL_DMA_CHANNEL_11
2251 * @arg @ref LL_DMA_CHANNEL_12
2252 * @arg @ref LL_DMA_CHANNEL_13
2253 * @arg @ref LL_DMA_CHANNEL_14
2254 * @arg @ref LL_DMA_CHANNEL_15
2255 * @param DestAllocatedPort This parameter can be one of the following values:
2256 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2257 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2258 * @retval None.
2259 */
LL_DMA_SetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAllocatedPort)2260 __STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
2261 {
2262 uint32_t dma_base_addr = (uint32_t)DMAx;
2263 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
2264 DestAllocatedPort);
2265 }
2266
2267 /**
2268 * @brief Get destination allocated port.
2269 * @note This API is not used for LPDMA channels.
2270 * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
2271 * @param DMAx DMAx Instance
2272 * @param Channel This parameter can be one of the following values:
2273 * @arg @ref LL_DMA_CHANNEL_0
2274 * @arg @ref LL_DMA_CHANNEL_1
2275 * @arg @ref LL_DMA_CHANNEL_2
2276 * @arg @ref LL_DMA_CHANNEL_3
2277 * @arg @ref LL_DMA_CHANNEL_4
2278 * @arg @ref LL_DMA_CHANNEL_5
2279 * @arg @ref LL_DMA_CHANNEL_6
2280 * @arg @ref LL_DMA_CHANNEL_7
2281 * @arg @ref LL_DMA_CHANNEL_8
2282 * @arg @ref LL_DMA_CHANNEL_9
2283 * @arg @ref LL_DMA_CHANNEL_10
2284 * @arg @ref LL_DMA_CHANNEL_11
2285 * @arg @ref LL_DMA_CHANNEL_12
2286 * @arg @ref LL_DMA_CHANNEL_13
2287 * @arg @ref LL_DMA_CHANNEL_14
2288 * @arg @ref LL_DMA_CHANNEL_15
2289 * @retval Returned value can be one of the following values:
2290 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2291 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2292 */
LL_DMA_GetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)2293 __STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
2294 {
2295 uint32_t dma_base_addr = (uint32_t)DMAx;
2296 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
2297 }
2298
2299 /**
2300 * @brief Set destination half-word exchange.
2301 * @note This API is not used for LPDMA channels.
2302 * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
2303 * @param DMAx DMAx Instance
2304 * @param Channel This parameter can be one of the following values:
2305 * @arg @ref LL_DMA_CHANNEL_0
2306 * @arg @ref LL_DMA_CHANNEL_1
2307 * @arg @ref LL_DMA_CHANNEL_2
2308 * @arg @ref LL_DMA_CHANNEL_3
2309 * @arg @ref LL_DMA_CHANNEL_4
2310 * @arg @ref LL_DMA_CHANNEL_5
2311 * @arg @ref LL_DMA_CHANNEL_6
2312 * @arg @ref LL_DMA_CHANNEL_7
2313 * @arg @ref LL_DMA_CHANNEL_8
2314 * @arg @ref LL_DMA_CHANNEL_9
2315 * @arg @ref LL_DMA_CHANNEL_10
2316 * @arg @ref LL_DMA_CHANNEL_11
2317 * @arg @ref LL_DMA_CHANNEL_12
2318 * @arg @ref LL_DMA_CHANNEL_13
2319 * @arg @ref LL_DMA_CHANNEL_14
2320 * @arg @ref LL_DMA_CHANNEL_15
2321 * @param DestHWordExchange This parameter can be one of the following values:
2322 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2323 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2324 * @retval None.
2325 */
LL_DMA_SetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestHWordExchange)2326 __STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
2327 {
2328 uint32_t dma_base_addr = (uint32_t)DMAx;
2329 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
2330 DestHWordExchange);
2331 }
2332
2333 /**
2334 * @brief Get destination half-word exchange.
2335 * @note This API is not used for LPDMA channels.
2336 * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
2337 * @param DMAx DMAx Instance
2338 * @param Channel This parameter can be one of the following values:
2339 * @arg @ref LL_DMA_CHANNEL_0
2340 * @arg @ref LL_DMA_CHANNEL_1
2341 * @arg @ref LL_DMA_CHANNEL_2
2342 * @arg @ref LL_DMA_CHANNEL_3
2343 * @arg @ref LL_DMA_CHANNEL_4
2344 * @arg @ref LL_DMA_CHANNEL_5
2345 * @arg @ref LL_DMA_CHANNEL_6
2346 * @arg @ref LL_DMA_CHANNEL_7
2347 * @arg @ref LL_DMA_CHANNEL_8
2348 * @arg @ref LL_DMA_CHANNEL_9
2349 * @arg @ref LL_DMA_CHANNEL_10
2350 * @arg @ref LL_DMA_CHANNEL_11
2351 * @arg @ref LL_DMA_CHANNEL_12
2352 * @arg @ref LL_DMA_CHANNEL_13
2353 * @arg @ref LL_DMA_CHANNEL_14
2354 * @arg @ref LL_DMA_CHANNEL_15
2355 * @retval Returned value can be one of the following values:
2356 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2357 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2358 */
LL_DMA_GetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2359 __STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2360 {
2361 uint32_t dma_base_addr = (uint32_t)DMAx;
2362 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
2363 }
2364
2365 /**
2366 * @brief Set destination byte exchange.
2367 * @note This API is not used for LPDMA channels.
2368 * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
2369 * @param DMAx DMAx Instance
2370 * @param Channel This parameter can be one of the following values:
2371 * @arg @ref LL_DMA_CHANNEL_0
2372 * @arg @ref LL_DMA_CHANNEL_1
2373 * @arg @ref LL_DMA_CHANNEL_2
2374 * @arg @ref LL_DMA_CHANNEL_3
2375 * @arg @ref LL_DMA_CHANNEL_4
2376 * @arg @ref LL_DMA_CHANNEL_5
2377 * @arg @ref LL_DMA_CHANNEL_6
2378 * @arg @ref LL_DMA_CHANNEL_7
2379 * @arg @ref LL_DMA_CHANNEL_8
2380 * @arg @ref LL_DMA_CHANNEL_9
2381 * @arg @ref LL_DMA_CHANNEL_10
2382 * @arg @ref LL_DMA_CHANNEL_11
2383 * @arg @ref LL_DMA_CHANNEL_12
2384 * @arg @ref LL_DMA_CHANNEL_13
2385 * @arg @ref LL_DMA_CHANNEL_14
2386 * @arg @ref LL_DMA_CHANNEL_15
2387 * @param DestByteExchange This parameter can be one of the following values:
2388 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
2389 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
2390 * @retval None.
2391 */
LL_DMA_SetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestByteExchange)2392 __STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
2393 {
2394 uint32_t dma_base_addr = (uint32_t)DMAx;
2395 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
2396 DestByteExchange);
2397 }
2398
2399 /**
2400 * @brief Get destination byte exchange.
2401 * @note This API is not used for LPDMA channels.
2402 * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
2403 * @param DMAx DMAx Instance
2404 * @param Channel This parameter can be one of the following values:
2405 * @arg @ref LL_DMA_CHANNEL_0
2406 * @arg @ref LL_DMA_CHANNEL_1
2407 * @arg @ref LL_DMA_CHANNEL_2
2408 * @arg @ref LL_DMA_CHANNEL_3
2409 * @arg @ref LL_DMA_CHANNEL_4
2410 * @arg @ref LL_DMA_CHANNEL_5
2411 * @arg @ref LL_DMA_CHANNEL_6
2412 * @arg @ref LL_DMA_CHANNEL_7
2413 * @arg @ref LL_DMA_CHANNEL_8
2414 * @arg @ref LL_DMA_CHANNEL_9
2415 * @arg @ref LL_DMA_CHANNEL_10
2416 * @arg @ref LL_DMA_CHANNEL_11
2417 * @arg @ref LL_DMA_CHANNEL_12
2418 * @arg @ref LL_DMA_CHANNEL_13
2419 * @arg @ref LL_DMA_CHANNEL_14
2420 * @arg @ref LL_DMA_CHANNEL_15
2421 * @retval Returned value can be one of the following values:
2422 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
2423 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
2424 */
LL_DMA_GetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2425 __STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2426 {
2427 uint32_t dma_base_addr = (uint32_t)DMAx;
2428 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
2429 }
2430
2431 /**
2432 * @brief Set source byte exchange.
2433 * @note This API is not used for LPDMA channels.
2434 * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
2435 * @param DMAx DMAx Instance
2436 * @param Channel This parameter can be one of the following values:
2437 * @arg @ref LL_DMA_CHANNEL_0
2438 * @arg @ref LL_DMA_CHANNEL_1
2439 * @arg @ref LL_DMA_CHANNEL_2
2440 * @arg @ref LL_DMA_CHANNEL_3
2441 * @arg @ref LL_DMA_CHANNEL_4
2442 * @arg @ref LL_DMA_CHANNEL_5
2443 * @arg @ref LL_DMA_CHANNEL_6
2444 * @arg @ref LL_DMA_CHANNEL_7
2445 * @arg @ref LL_DMA_CHANNEL_8
2446 * @arg @ref LL_DMA_CHANNEL_9
2447 * @arg @ref LL_DMA_CHANNEL_10
2448 * @arg @ref LL_DMA_CHANNEL_11
2449 * @arg @ref LL_DMA_CHANNEL_12
2450 * @arg @ref LL_DMA_CHANNEL_13
2451 * @arg @ref LL_DMA_CHANNEL_14
2452 * @arg @ref LL_DMA_CHANNEL_15
2453 * @param SrcByteExchange This parameter can be one of the following values:
2454 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
2455 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
2456 * @retval None.
2457 */
LL_DMA_SetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcByteExchange)2458 __STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
2459 {
2460 uint32_t dma_base_addr = (uint32_t)DMAx;
2461 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
2462 SrcByteExchange);
2463 }
2464
2465 /**
2466 * @brief Get source byte exchange.
2467 * @note This API is not used for LPDMA channels.
2468 * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
2469 * @param DMAx DMAx Instance
2470 * @param Channel This parameter can be one of the following values:
2471 * @arg @ref LL_DMA_CHANNEL_0
2472 * @arg @ref LL_DMA_CHANNEL_1
2473 * @arg @ref LL_DMA_CHANNEL_2
2474 * @arg @ref LL_DMA_CHANNEL_3
2475 * @arg @ref LL_DMA_CHANNEL_4
2476 * @arg @ref LL_DMA_CHANNEL_5
2477 * @arg @ref LL_DMA_CHANNEL_6
2478 * @arg @ref LL_DMA_CHANNEL_7
2479 * @arg @ref LL_DMA_CHANNEL_8
2480 * @arg @ref LL_DMA_CHANNEL_9
2481 * @arg @ref LL_DMA_CHANNEL_10
2482 * @arg @ref LL_DMA_CHANNEL_11
2483 * @arg @ref LL_DMA_CHANNEL_12
2484 * @arg @ref LL_DMA_CHANNEL_13
2485 * @arg @ref LL_DMA_CHANNEL_14
2486 * @arg @ref LL_DMA_CHANNEL_15
2487 * @retval Returned value can be one of the following values:
2488 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
2489 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
2490 */
LL_DMA_GetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2491 __STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2492 {
2493 uint32_t dma_base_addr = (uint32_t)DMAx;
2494 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
2495 }
2496
2497 /**
2498 * @brief Set destination burst length.
2499 * @note This API is not used for LPDMA channels.
2500 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
2501 * @param DMAx DMAx Instance
2502 * @param Channel This parameter can be one of the following values:
2503 * @arg @ref LL_DMA_CHANNEL_0
2504 * @arg @ref LL_DMA_CHANNEL_1
2505 * @arg @ref LL_DMA_CHANNEL_2
2506 * @arg @ref LL_DMA_CHANNEL_3
2507 * @arg @ref LL_DMA_CHANNEL_4
2508 * @arg @ref LL_DMA_CHANNEL_5
2509 * @arg @ref LL_DMA_CHANNEL_6
2510 * @arg @ref LL_DMA_CHANNEL_7
2511 * @arg @ref LL_DMA_CHANNEL_8
2512 * @arg @ref LL_DMA_CHANNEL_9
2513 * @arg @ref LL_DMA_CHANNEL_10
2514 * @arg @ref LL_DMA_CHANNEL_11
2515 * @arg @ref LL_DMA_CHANNEL_12
2516 * @arg @ref LL_DMA_CHANNEL_13
2517 * @arg @ref LL_DMA_CHANNEL_14
2518 * @arg @ref LL_DMA_CHANNEL_15
2519 * @param DestBurstLength Between 1 to 64
2520 * @retval None.
2521 */
LL_DMA_SetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestBurstLength)2522 __STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
2523 {
2524 uint32_t dma_base_addr = (uint32_t)DMAx;
2525 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
2526 ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
2527 }
2528
2529 /**
2530 * @brief Get destination burst length.
2531 * @note This API is not used for LPDMA channels.
2532 * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
2533 * @param DMAx DMAx Instance
2534 * @param Channel This parameter can be one of the following values:
2535 * @arg @ref LL_DMA_CHANNEL_0
2536 * @arg @ref LL_DMA_CHANNEL_1
2537 * @arg @ref LL_DMA_CHANNEL_2
2538 * @arg @ref LL_DMA_CHANNEL_3
2539 * @arg @ref LL_DMA_CHANNEL_4
2540 * @arg @ref LL_DMA_CHANNEL_5
2541 * @arg @ref LL_DMA_CHANNEL_6
2542 * @arg @ref LL_DMA_CHANNEL_7
2543 * @arg @ref LL_DMA_CHANNEL_8
2544 * @arg @ref LL_DMA_CHANNEL_9
2545 * @arg @ref LL_DMA_CHANNEL_10
2546 * @arg @ref LL_DMA_CHANNEL_11
2547 * @arg @ref LL_DMA_CHANNEL_12
2548 * @arg @ref LL_DMA_CHANNEL_13
2549 * @arg @ref LL_DMA_CHANNEL_14
2550 * @arg @ref LL_DMA_CHANNEL_15
2551 * @retval Between 1 to 64.
2552 */
LL_DMA_GetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)2553 __STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2554 {
2555 uint32_t dma_base_addr = (uint32_t)DMAx;
2556 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2557 DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
2558 }
2559
2560 /**
2561 * @brief Set destination increment mode.
2562 * @note This API is not used for LPDMA channels.
2563 * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
2564 * @param DMAx DMAx Instance
2565 * @param Channel This parameter can be one of the following values:
2566 * @arg @ref LL_DMA_CHANNEL_0
2567 * @arg @ref LL_DMA_CHANNEL_1
2568 * @arg @ref LL_DMA_CHANNEL_2
2569 * @arg @ref LL_DMA_CHANNEL_3
2570 * @arg @ref LL_DMA_CHANNEL_4
2571 * @arg @ref LL_DMA_CHANNEL_5
2572 * @arg @ref LL_DMA_CHANNEL_6
2573 * @arg @ref LL_DMA_CHANNEL_7
2574 * @arg @ref LL_DMA_CHANNEL_8
2575 * @arg @ref LL_DMA_CHANNEL_9
2576 * @arg @ref LL_DMA_CHANNEL_10
2577 * @arg @ref LL_DMA_CHANNEL_11
2578 * @arg @ref LL_DMA_CHANNEL_12
2579 * @arg @ref LL_DMA_CHANNEL_13
2580 * @arg @ref LL_DMA_CHANNEL_14
2581 * @arg @ref LL_DMA_CHANNEL_15
2582 * @param DestInc This parameter can be one of the following values:
2583 * @arg @ref LL_DMA_DEST_FIXED
2584 * @arg @ref LL_DMA_DEST_INCREMENT
2585 * @retval None.
2586 */
LL_DMA_SetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestInc)2587 __STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
2588 {
2589 uint32_t dma_base_addr = (uint32_t)DMAx;
2590 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
2591 }
2592
2593 /**
2594 * @brief Get destination increment mode.
2595 * @note This API is used for all available DMA channels.
2596 * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode
2597 * @param DMAx DMAx Instance
2598 * @param Channel This parameter can be one of the following values:
2599 * @arg @ref LL_DMA_CHANNEL_0
2600 * @arg @ref LL_DMA_CHANNEL_1
2601 * @arg @ref LL_DMA_CHANNEL_2
2602 * @arg @ref LL_DMA_CHANNEL_3
2603 * @arg @ref LL_DMA_CHANNEL_4
2604 * @arg @ref LL_DMA_CHANNEL_5
2605 * @arg @ref LL_DMA_CHANNEL_6
2606 * @arg @ref LL_DMA_CHANNEL_7
2607 * @arg @ref LL_DMA_CHANNEL_8
2608 * @arg @ref LL_DMA_CHANNEL_9
2609 * @arg @ref LL_DMA_CHANNEL_10
2610 * @arg @ref LL_DMA_CHANNEL_11
2611 * @arg @ref LL_DMA_CHANNEL_12
2612 * @arg @ref LL_DMA_CHANNEL_13
2613 * @arg @ref LL_DMA_CHANNEL_14
2614 * @arg @ref LL_DMA_CHANNEL_15
2615 * @retval Returned value can be one of the following values:
2616 * @arg @ref LL_DMA_DEST_FIXED
2617 * @arg @ref LL_DMA_DEST_INCREMENT
2618 */
LL_DMA_GetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)2619 __STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2620 {
2621 uint32_t dma_base_addr = (uint32_t)DMAx;
2622 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
2623 }
2624
2625 /**
2626 * @brief Set destination data width.
2627 * @note This API is used for all available DMA channels.
2628 * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
2629 * @param DMAx DMAx Instance
2630 * @param Channel This parameter can be one of the following values:
2631 * @arg @ref LL_DMA_CHANNEL_0
2632 * @arg @ref LL_DMA_CHANNEL_1
2633 * @arg @ref LL_DMA_CHANNEL_2
2634 * @arg @ref LL_DMA_CHANNEL_3
2635 * @arg @ref LL_DMA_CHANNEL_4
2636 * @arg @ref LL_DMA_CHANNEL_5
2637 * @arg @ref LL_DMA_CHANNEL_6
2638 * @arg @ref LL_DMA_CHANNEL_7
2639 * @arg @ref LL_DMA_CHANNEL_8
2640 * @arg @ref LL_DMA_CHANNEL_9
2641 * @arg @ref LL_DMA_CHANNEL_10
2642 * @arg @ref LL_DMA_CHANNEL_11
2643 * @arg @ref LL_DMA_CHANNEL_12
2644 * @arg @ref LL_DMA_CHANNEL_13
2645 * @arg @ref LL_DMA_CHANNEL_14
2646 * @arg @ref LL_DMA_CHANNEL_15
2647 * @param DestDataWidth This parameter can be one of the following values:
2648 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
2649 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
2650 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
2651 * @retval None.
2652 */
LL_DMA_SetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestDataWidth)2653 __STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
2654 {
2655 uint32_t dma_base_addr = (uint32_t)DMAx;
2656 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
2657 DestDataWidth);
2658 }
2659
2660 /**
2661 * @brief Get destination data width.
2662 * @note This API is used for all available DMA channels.
2663 * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
2664 * @param DMAx DMAx Instance
2665 * @param Channel This parameter can be one of the following values:
2666 * @arg @ref LL_DMA_CHANNEL_0
2667 * @arg @ref LL_DMA_CHANNEL_1
2668 * @arg @ref LL_DMA_CHANNEL_2
2669 * @arg @ref LL_DMA_CHANNEL_3
2670 * @arg @ref LL_DMA_CHANNEL_4
2671 * @arg @ref LL_DMA_CHANNEL_5
2672 * @arg @ref LL_DMA_CHANNEL_6
2673 * @arg @ref LL_DMA_CHANNEL_7
2674 * @arg @ref LL_DMA_CHANNEL_8
2675 * @arg @ref LL_DMA_CHANNEL_9
2676 * @arg @ref LL_DMA_CHANNEL_10
2677 * @arg @ref LL_DMA_CHANNEL_11
2678 * @arg @ref LL_DMA_CHANNEL_12
2679 * @arg @ref LL_DMA_CHANNEL_13
2680 * @arg @ref LL_DMA_CHANNEL_14
2681 * @arg @ref LL_DMA_CHANNEL_15
2682 * @retval Returned value can be one of the following values:
2683 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
2684 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
2685 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
2686 */
LL_DMA_GetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)2687 __STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
2688 {
2689 uint32_t dma_base_addr = (uint32_t)DMAx;
2690 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
2691 }
2692
2693 /**
2694 * @brief Set source allocated port.
2695 * @note This API is not used for LPDMA channels.
2696 * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
2697 * @param DMAx DMAx Instance
2698 * @param Channel This parameter can be one of the following values:
2699 * @arg @ref LL_DMA_CHANNEL_0
2700 * @arg @ref LL_DMA_CHANNEL_1
2701 * @arg @ref LL_DMA_CHANNEL_2
2702 * @arg @ref LL_DMA_CHANNEL_3
2703 * @arg @ref LL_DMA_CHANNEL_4
2704 * @arg @ref LL_DMA_CHANNEL_5
2705 * @arg @ref LL_DMA_CHANNEL_6
2706 * @arg @ref LL_DMA_CHANNEL_7
2707 * @arg @ref LL_DMA_CHANNEL_8
2708 * @arg @ref LL_DMA_CHANNEL_9
2709 * @arg @ref LL_DMA_CHANNEL_10
2710 * @arg @ref LL_DMA_CHANNEL_11
2711 * @arg @ref LL_DMA_CHANNEL_12
2712 * @arg @ref LL_DMA_CHANNEL_13
2713 * @arg @ref LL_DMA_CHANNEL_14
2714 * @arg @ref LL_DMA_CHANNEL_15
2715 * @param SrcAllocatedPort This parameter can be one of the following values:
2716 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
2717 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
2718 * @retval None.
2719 */
LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAllocatedPort)2720 __STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
2721 {
2722 uint32_t dma_base_addr = (uint32_t)DMAx;
2723 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
2724 SrcAllocatedPort);
2725 }
2726
2727 /**
2728 * @brief Get source allocated port.
2729 * @note This API is not used for LPDMA channels.
2730 * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
2731 * @param DMAx DMAx Instance
2732 * @param Channel This parameter can be one of the following values:
2733 * @arg @ref LL_DMA_CHANNEL_0
2734 * @arg @ref LL_DMA_CHANNEL_1
2735 * @arg @ref LL_DMA_CHANNEL_2
2736 * @arg @ref LL_DMA_CHANNEL_3
2737 * @arg @ref LL_DMA_CHANNEL_4
2738 * @arg @ref LL_DMA_CHANNEL_5
2739 * @arg @ref LL_DMA_CHANNEL_6
2740 * @arg @ref LL_DMA_CHANNEL_7
2741 * @arg @ref LL_DMA_CHANNEL_8
2742 * @arg @ref LL_DMA_CHANNEL_9
2743 * @arg @ref LL_DMA_CHANNEL_10
2744 * @arg @ref LL_DMA_CHANNEL_11
2745 * @arg @ref LL_DMA_CHANNEL_12
2746 * @arg @ref LL_DMA_CHANNEL_13
2747 * @arg @ref LL_DMA_CHANNEL_14
2748 * @arg @ref LL_DMA_CHANNEL_15
2749 * @retval Returned value can be one of the following values:
2750 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
2751 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
2752 */
LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)2753 __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
2754 {
2755 uint32_t dma_base_addr = (uint32_t)DMAx;
2756 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
2757 }
2758
2759 /**
2760 * @brief Set data alignment mode.
2761 * @note This API is used for all available DMA channels.
2762 * For LPDMA channels, PAM field is reduced to one bit.
2763 * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
2764 * @param DMAx DMAx Instance
2765 * @param Channel This parameter can be one of the following values:
2766 * @arg @ref LL_DMA_CHANNEL_0
2767 * @arg @ref LL_DMA_CHANNEL_1
2768 * @arg @ref LL_DMA_CHANNEL_2
2769 * @arg @ref LL_DMA_CHANNEL_3
2770 * @arg @ref LL_DMA_CHANNEL_4
2771 * @arg @ref LL_DMA_CHANNEL_5
2772 * @arg @ref LL_DMA_CHANNEL_6
2773 * @arg @ref LL_DMA_CHANNEL_7
2774 * @arg @ref LL_DMA_CHANNEL_8
2775 * @arg @ref LL_DMA_CHANNEL_9
2776 * @arg @ref LL_DMA_CHANNEL_10
2777 * @arg @ref LL_DMA_CHANNEL_11
2778 * @arg @ref LL_DMA_CHANNEL_12
2779 * @arg @ref LL_DMA_CHANNEL_13
2780 * @arg @ref LL_DMA_CHANNEL_14
2781 * @arg @ref LL_DMA_CHANNEL_15
2782 * @param DataAlignment This parameter can be one of the following values:
2783 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2784 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2785 * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels)
2786 * @retval None.
2787 */
LL_DMA_SetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DataAlignment)2788 __STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
2789 {
2790 uint32_t dma_base_addr = (uint32_t)DMAx;
2791 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
2792 DataAlignment);
2793 }
2794
2795 /**
2796 * @brief Get data alignment mode.
2797 * @note This API is used for all available DMA channels.
2798 * For LPDMA channels, PAM field is reduced to one bit.
2799 * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
2800 * @param DMAx DMAx Instance
2801 * @param Channel This parameter can be one of the following values:
2802 * @arg @ref LL_DMA_CHANNEL_0
2803 * @arg @ref LL_DMA_CHANNEL_1
2804 * @arg @ref LL_DMA_CHANNEL_2
2805 * @arg @ref LL_DMA_CHANNEL_3
2806 * @arg @ref LL_DMA_CHANNEL_4
2807 * @arg @ref LL_DMA_CHANNEL_5
2808 * @arg @ref LL_DMA_CHANNEL_6
2809 * @arg @ref LL_DMA_CHANNEL_7
2810 * @arg @ref LL_DMA_CHANNEL_8
2811 * @arg @ref LL_DMA_CHANNEL_9
2812 * @arg @ref LL_DMA_CHANNEL_10
2813 * @arg @ref LL_DMA_CHANNEL_11
2814 * @arg @ref LL_DMA_CHANNEL_12
2815 * @arg @ref LL_DMA_CHANNEL_13
2816 * @arg @ref LL_DMA_CHANNEL_14
2817 * @arg @ref LL_DMA_CHANNEL_15
2818 * @retval Returned value can be one of the following values:
2819 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2820 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2821 * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels)
2822 */
LL_DMA_GetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel)2823 __STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel)
2824 {
2825 uint32_t dma_base_addr = (uint32_t)DMAx;
2826 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
2827 }
2828
2829 /**
2830 * @brief Set source burst length.
2831 * @note This API is not used for LPDMA channels.
2832 * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
2833 * @param DMAx DMAx Instance
2834 * @param Channel This parameter can be one of the following values:
2835 * @arg @ref LL_DMA_CHANNEL_0
2836 * @arg @ref LL_DMA_CHANNEL_1
2837 * @arg @ref LL_DMA_CHANNEL_2
2838 * @arg @ref LL_DMA_CHANNEL_3
2839 * @arg @ref LL_DMA_CHANNEL_4
2840 * @arg @ref LL_DMA_CHANNEL_5
2841 * @arg @ref LL_DMA_CHANNEL_6
2842 * @arg @ref LL_DMA_CHANNEL_7
2843 * @arg @ref LL_DMA_CHANNEL_8
2844 * @arg @ref LL_DMA_CHANNEL_9
2845 * @arg @ref LL_DMA_CHANNEL_10
2846 * @arg @ref LL_DMA_CHANNEL_11
2847 * @arg @ref LL_DMA_CHANNEL_12
2848 * @arg @ref LL_DMA_CHANNEL_13
2849 * @arg @ref LL_DMA_CHANNEL_14
2850 * @arg @ref LL_DMA_CHANNEL_15
2851 * @param SrcBurstLength Between 1 to 64
2852 * @retval None.
2853 */
LL_DMA_SetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength)2854 __STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
2855 {
2856 uint32_t dma_base_addr = (uint32_t)DMAx;
2857 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
2858 ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
2859 }
2860
2861 /**
2862 * @brief Get source burst length.
2863 * @note This API is not used for LPDMA channels.
2864 * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
2865 * @param DMAx DMAx Instance
2866 * @param Channel This parameter can be one of the following values:
2867 * @arg @ref LL_DMA_CHANNEL_0
2868 * @arg @ref LL_DMA_CHANNEL_1
2869 * @arg @ref LL_DMA_CHANNEL_2
2870 * @arg @ref LL_DMA_CHANNEL_3
2871 * @arg @ref LL_DMA_CHANNEL_4
2872 * @arg @ref LL_DMA_CHANNEL_5
2873 * @arg @ref LL_DMA_CHANNEL_6
2874 * @arg @ref LL_DMA_CHANNEL_7
2875 * @arg @ref LL_DMA_CHANNEL_8
2876 * @arg @ref LL_DMA_CHANNEL_9
2877 * @arg @ref LL_DMA_CHANNEL_10
2878 * @arg @ref LL_DMA_CHANNEL_11
2879 * @arg @ref LL_DMA_CHANNEL_12
2880 * @arg @ref LL_DMA_CHANNEL_13
2881 * @arg @ref LL_DMA_CHANNEL_14
2882 * @arg @ref LL_DMA_CHANNEL_15
2883 * @retval Between 1 to 64
2884 * @retval None.
2885 */
LL_DMA_GetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)2886 __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2887 {
2888 uint32_t dma_base_addr = (uint32_t)DMAx;
2889 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2890 DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
2891 }
2892
2893 /**
2894 * @brief Set source increment mode.
2895 * @note This API is used for all available DMA channels.
2896 * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
2897 * @param DMAx DMAx Instance
2898 * @param Channel This parameter can be one of the following values:
2899 * @arg @ref LL_DMA_CHANNEL_0
2900 * @arg @ref LL_DMA_CHANNEL_1
2901 * @arg @ref LL_DMA_CHANNEL_2
2902 * @arg @ref LL_DMA_CHANNEL_3
2903 * @arg @ref LL_DMA_CHANNEL_4
2904 * @arg @ref LL_DMA_CHANNEL_5
2905 * @arg @ref LL_DMA_CHANNEL_6
2906 * @arg @ref LL_DMA_CHANNEL_7
2907 * @arg @ref LL_DMA_CHANNEL_8
2908 * @arg @ref LL_DMA_CHANNEL_9
2909 * @arg @ref LL_DMA_CHANNEL_10
2910 * @arg @ref LL_DMA_CHANNEL_11
2911 * @arg @ref LL_DMA_CHANNEL_12
2912 * @arg @ref LL_DMA_CHANNEL_13
2913 * @arg @ref LL_DMA_CHANNEL_14
2914 * @arg @ref LL_DMA_CHANNEL_15
2915 * @param SrcInc This parameter can be one of the following values:
2916 * @arg @ref LL_DMA_SRC_FIXED
2917 * @arg @ref LL_DMA_SRC_INCREMENT
2918 * @retval None.
2919 */
LL_DMA_SetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcInc)2920 __STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
2921 {
2922 uint32_t dma_base_addr = (uint32_t)DMAx;
2923 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
2924 }
2925
2926 /**
2927 * @brief Get source increment mode.
2928 * @note This API is used for all available DMA channels.
2929 * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
2930 * @param DMAx DMAx Instance
2931 * @param Channel This parameter can be one of the following values:
2932 * @arg @ref LL_DMA_CHANNEL_0
2933 * @arg @ref LL_DMA_CHANNEL_1
2934 * @arg @ref LL_DMA_CHANNEL_2
2935 * @arg @ref LL_DMA_CHANNEL_3
2936 * @arg @ref LL_DMA_CHANNEL_4
2937 * @arg @ref LL_DMA_CHANNEL_5
2938 * @arg @ref LL_DMA_CHANNEL_6
2939 * @arg @ref LL_DMA_CHANNEL_7
2940 * @arg @ref LL_DMA_CHANNEL_8
2941 * @arg @ref LL_DMA_CHANNEL_9
2942 * @arg @ref LL_DMA_CHANNEL_10
2943 * @arg @ref LL_DMA_CHANNEL_11
2944 * @arg @ref LL_DMA_CHANNEL_12
2945 * @arg @ref LL_DMA_CHANNEL_13
2946 * @arg @ref LL_DMA_CHANNEL_14
2947 * @arg @ref LL_DMA_CHANNEL_15
2948 * @retval Returned value can be one of the following values:
2949 * @arg @ref LL_DMA_SRC_FIXED
2950 * @arg @ref LL_DMA_SRC_INCREMENT
2951 */
LL_DMA_GetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)2952 __STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2953 {
2954 uint32_t dma_base_addr = (uint32_t)DMAx;
2955 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
2956 }
2957
2958 /**
2959 * @brief Set source data width.
2960 * @note This API is used for all available DMA channels.
2961 * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
2962 * @param DMAx DMAx Instance
2963 * @param Channel This parameter can be one of the following values:
2964 * @arg @ref LL_DMA_CHANNEL_0
2965 * @arg @ref LL_DMA_CHANNEL_1
2966 * @arg @ref LL_DMA_CHANNEL_2
2967 * @arg @ref LL_DMA_CHANNEL_3
2968 * @arg @ref LL_DMA_CHANNEL_4
2969 * @arg @ref LL_DMA_CHANNEL_5
2970 * @arg @ref LL_DMA_CHANNEL_6
2971 * @arg @ref LL_DMA_CHANNEL_7
2972 * @arg @ref LL_DMA_CHANNEL_8
2973 * @arg @ref LL_DMA_CHANNEL_9
2974 * @arg @ref LL_DMA_CHANNEL_10
2975 * @arg @ref LL_DMA_CHANNEL_11
2976 * @arg @ref LL_DMA_CHANNEL_12
2977 * @arg @ref LL_DMA_CHANNEL_13
2978 * @arg @ref LL_DMA_CHANNEL_14
2979 * @arg @ref LL_DMA_CHANNEL_15
2980 * @param SrcDataWidth This parameter can be one of the following values:
2981 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2982 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2983 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2984 * @retval None.
2985 */
LL_DMA_SetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcDataWidth)2986 __STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
2987 {
2988 uint32_t dma_base_addr = (uint32_t)DMAx;
2989 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
2990 SrcDataWidth);
2991 }
2992
2993 /**
2994 * @brief Get Source Data width.
2995 * @note This API is used for all available DMA channels.
2996 * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
2997 * @param DMAx DMAx Instance
2998 * @param Channel This parameter can be one of the following values:
2999 * @arg @ref LL_DMA_CHANNEL_0
3000 * @arg @ref LL_DMA_CHANNEL_1
3001 * @arg @ref LL_DMA_CHANNEL_2
3002 * @arg @ref LL_DMA_CHANNEL_3
3003 * @arg @ref LL_DMA_CHANNEL_4
3004 * @arg @ref LL_DMA_CHANNEL_5
3005 * @arg @ref LL_DMA_CHANNEL_6
3006 * @arg @ref LL_DMA_CHANNEL_7
3007 * @arg @ref LL_DMA_CHANNEL_8
3008 * @arg @ref LL_DMA_CHANNEL_9
3009 * @arg @ref LL_DMA_CHANNEL_10
3010 * @arg @ref LL_DMA_CHANNEL_11
3011 * @arg @ref LL_DMA_CHANNEL_12
3012 * @arg @ref LL_DMA_CHANNEL_13
3013 * @arg @ref LL_DMA_CHANNEL_14
3014 * @arg @ref LL_DMA_CHANNEL_15
3015 * @retval Returned value can be one of the following values:
3016 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
3017 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
3018 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
3019 */
LL_DMA_GetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)3020 __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
3021 {
3022 uint32_t dma_base_addr = (uint32_t)DMAx;
3023 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
3024 }
3025
3026 /**
3027 * @brief Configure channel transfer.
3028 * @note This API is used for all available DMA channels.
3029 * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
3030 * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
3031 * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
3032 * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
3033 * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
3034 * CTR2 SWREQ LL_DMA_ConfigChannelTransfer
3035 * @param DMAx DMAx Instance
3036 * @param Channel This parameter can be one of the following values:
3037 * @arg @ref LL_DMA_CHANNEL_0
3038 * @arg @ref LL_DMA_CHANNEL_1
3039 * @arg @ref LL_DMA_CHANNEL_2
3040 * @arg @ref LL_DMA_CHANNEL_3
3041 * @arg @ref LL_DMA_CHANNEL_4
3042 * @arg @ref LL_DMA_CHANNEL_5
3043 * @arg @ref LL_DMA_CHANNEL_6
3044 * @arg @ref LL_DMA_CHANNEL_7
3045 * @arg @ref LL_DMA_CHANNEL_8
3046 * @arg @ref LL_DMA_CHANNEL_9
3047 * @arg @ref LL_DMA_CHANNEL_10
3048 * @arg @ref LL_DMA_CHANNEL_11
3049 * @arg @ref LL_DMA_CHANNEL_12
3050 * @arg @ref LL_DMA_CHANNEL_13
3051 * @arg @ref LL_DMA_CHANNEL_14
3052 * @arg @ref LL_DMA_CHANNEL_15
3053 * @param Configuration This parameter must be a combination of all the following values:
3054 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
3055 * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3056 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK
3057 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or
3058 * @ref LL_DMA_TRIG_POLARITY_FALLING
3059 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
3060 * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3061 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
3062 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3063 *@retval None.
3064 */
LL_DMA_ConfigChannelTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)3065 __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
3066 {
3067 uint32_t dma_base_addr = (uint32_t)DMAx;
3068 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3069 (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ),
3070 Configuration);
3071 }
3072
3073 /**
3074 * @brief Set transfer event mode.
3075 * @note This API is used for all available DMA channels.
3076 * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
3077 * @param DMAx DMAx Instance
3078 * @param Channel This parameter can be one of the following values:
3079 * @arg @ref LL_DMA_CHANNEL_0
3080 * @arg @ref LL_DMA_CHANNEL_1
3081 * @arg @ref LL_DMA_CHANNEL_2
3082 * @arg @ref LL_DMA_CHANNEL_3
3083 * @arg @ref LL_DMA_CHANNEL_4
3084 * @arg @ref LL_DMA_CHANNEL_5
3085 * @arg @ref LL_DMA_CHANNEL_6
3086 * @arg @ref LL_DMA_CHANNEL_7
3087 * @arg @ref LL_DMA_CHANNEL_8
3088 * @arg @ref LL_DMA_CHANNEL_9
3089 * @arg @ref LL_DMA_CHANNEL_10
3090 * @arg @ref LL_DMA_CHANNEL_11
3091 * @arg @ref LL_DMA_CHANNEL_12
3092 * @arg @ref LL_DMA_CHANNEL_13
3093 * @arg @ref LL_DMA_CHANNEL_14
3094 * @arg @ref LL_DMA_CHANNEL_15
3095 * @param TransferEventMode This parameter can be one of the following values:
3096 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
3097 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
3098 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
3099 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3100 * @retval None.
3101 */
LL_DMA_SetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TransferEventMode)3102 __STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
3103 {
3104 uint32_t dma_base_addr = (uint32_t)DMAx;
3105 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
3106 TransferEventMode);
3107 }
3108
3109 /**
3110 * @brief Get transfer event mode.
3111 * @note This API is used for all available DMA channels.
3112 * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
3113 * @param DMAx DMAx Instance
3114 * @param Channel This parameter can be one of the following values:
3115 * @arg @ref LL_DMA_CHANNEL_0
3116 * @arg @ref LL_DMA_CHANNEL_1
3117 * @arg @ref LL_DMA_CHANNEL_2
3118 * @arg @ref LL_DMA_CHANNEL_3
3119 * @arg @ref LL_DMA_CHANNEL_4
3120 * @arg @ref LL_DMA_CHANNEL_5
3121 * @arg @ref LL_DMA_CHANNEL_6
3122 * @arg @ref LL_DMA_CHANNEL_7
3123 * @arg @ref LL_DMA_CHANNEL_8
3124 * @arg @ref LL_DMA_CHANNEL_9
3125 * @arg @ref LL_DMA_CHANNEL_10
3126 * @arg @ref LL_DMA_CHANNEL_11
3127 * @arg @ref LL_DMA_CHANNEL_12
3128 * @arg @ref LL_DMA_CHANNEL_13
3129 * @arg @ref LL_DMA_CHANNEL_14
3130 * @arg @ref LL_DMA_CHANNEL_15
3131 * @retval Returned value can be one of the following values:
3132 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
3133 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
3134 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
3135 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3136 */
LL_DMA_GetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel)3137 __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3138 {
3139 uint32_t dma_base_addr = (uint32_t)DMAx;
3140 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
3141 }
3142
3143 /**
3144 * @brief Set trigger polarity.
3145 * @note This API is used for all available DMA channels.
3146 * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
3147 * @param DMAx DMAx Instance
3148 * @param Channel This parameter can be one of the following values:
3149 * @arg @ref LL_DMA_CHANNEL_0
3150 * @arg @ref LL_DMA_CHANNEL_1
3151 * @arg @ref LL_DMA_CHANNEL_2
3152 * @arg @ref LL_DMA_CHANNEL_3
3153 * @arg @ref LL_DMA_CHANNEL_4
3154 * @arg @ref LL_DMA_CHANNEL_5
3155 * @arg @ref LL_DMA_CHANNEL_6
3156 * @arg @ref LL_DMA_CHANNEL_7
3157 * @arg @ref LL_DMA_CHANNEL_8
3158 * @arg @ref LL_DMA_CHANNEL_9
3159 * @arg @ref LL_DMA_CHANNEL_10
3160 * @arg @ref LL_DMA_CHANNEL_11
3161 * @arg @ref LL_DMA_CHANNEL_12
3162 * @arg @ref LL_DMA_CHANNEL_13
3163 * @arg @ref LL_DMA_CHANNEL_14
3164 * @arg @ref LL_DMA_CHANNEL_15
3165 * @param TriggerPolarity This parameter can be one of the following values:
3166 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
3167 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
3168 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
3169 * @retval None.
3170 */
LL_DMA_SetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerPolarity)3171 __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
3172 {
3173 uint32_t dma_base_addr = (uint32_t)DMAx;
3174 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
3175 TriggerPolarity);
3176 }
3177
3178 /**
3179 * @brief Get trigger polarity.
3180 * @note This API is used for all available DMA channels.
3181 * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
3182 * @param DMAx DMAx Instance
3183 * @param Channel This parameter can be one of the following values:
3184 * @arg @ref LL_DMA_CHANNEL_0
3185 * @arg @ref LL_DMA_CHANNEL_1
3186 * @arg @ref LL_DMA_CHANNEL_2
3187 * @arg @ref LL_DMA_CHANNEL_3
3188 * @arg @ref LL_DMA_CHANNEL_4
3189 * @arg @ref LL_DMA_CHANNEL_5
3190 * @arg @ref LL_DMA_CHANNEL_6
3191 * @arg @ref LL_DMA_CHANNEL_7
3192 * @arg @ref LL_DMA_CHANNEL_8
3193 * @arg @ref LL_DMA_CHANNEL_9
3194 * @arg @ref LL_DMA_CHANNEL_10
3195 * @arg @ref LL_DMA_CHANNEL_11
3196 * @arg @ref LL_DMA_CHANNEL_12
3197 * @arg @ref LL_DMA_CHANNEL_13
3198 * @arg @ref LL_DMA_CHANNEL_14
3199 * @arg @ref LL_DMA_CHANNEL_15
3200 * @retval Returned value can be one of the following values:
3201 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
3202 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
3203 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
3204 */
LL_DMA_GetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel)3205 __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel)
3206 {
3207 uint32_t dma_base_addr = (uint32_t)DMAx;
3208 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
3209 }
3210
3211 /**
3212 * @brief Set trigger Mode.
3213 * @note This API is used for all available DMA channels.
3214 * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
3215 * @param DMAx DMAx Instance
3216 * @param Channel This parameter can be one of the following values:
3217 * @arg @ref LL_DMA_CHANNEL_0
3218 * @arg @ref LL_DMA_CHANNEL_1
3219 * @arg @ref LL_DMA_CHANNEL_2
3220 * @arg @ref LL_DMA_CHANNEL_3
3221 * @arg @ref LL_DMA_CHANNEL_4
3222 * @arg @ref LL_DMA_CHANNEL_5
3223 * @arg @ref LL_DMA_CHANNEL_6
3224 * @arg @ref LL_DMA_CHANNEL_7
3225 * @arg @ref LL_DMA_CHANNEL_8
3226 * @arg @ref LL_DMA_CHANNEL_9
3227 * @arg @ref LL_DMA_CHANNEL_10
3228 * @arg @ref LL_DMA_CHANNEL_11
3229 * @arg @ref LL_DMA_CHANNEL_12
3230 * @arg @ref LL_DMA_CHANNEL_13
3231 * @arg @ref LL_DMA_CHANNEL_14
3232 * @arg @ref LL_DMA_CHANNEL_15
3233 * @param TriggerMode This parameter can be one of the following values:
3234 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3235 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3236 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3237 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3238 * @retval None.
3239 */
LL_DMA_SetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerMode)3240 __STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
3241 {
3242 uint32_t dma_base_addr = (uint32_t)DMAx;
3243 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
3244 TriggerMode);
3245 }
3246
3247 /**
3248 * @brief Get trigger Mode.
3249 * @note This API is used for all available DMA channels.
3250 * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
3251 * @param DMAx DMAx Instance
3252 * @param Channel This parameter can be one of the following values:
3253 * @arg @ref LL_DMA_CHANNEL_0
3254 * @arg @ref LL_DMA_CHANNEL_1
3255 * @arg @ref LL_DMA_CHANNEL_2
3256 * @arg @ref LL_DMA_CHANNEL_3
3257 * @arg @ref LL_DMA_CHANNEL_4
3258 * @arg @ref LL_DMA_CHANNEL_5
3259 * @arg @ref LL_DMA_CHANNEL_6
3260 * @arg @ref LL_DMA_CHANNEL_7
3261 * @arg @ref LL_DMA_CHANNEL_8
3262 * @arg @ref LL_DMA_CHANNEL_9
3263 * @arg @ref LL_DMA_CHANNEL_10
3264 * @arg @ref LL_DMA_CHANNEL_11
3265 * @arg @ref LL_DMA_CHANNEL_12
3266 * @arg @ref LL_DMA_CHANNEL_13
3267 * @arg @ref LL_DMA_CHANNEL_14
3268 * @arg @ref LL_DMA_CHANNEL_15
3269 * @retval Returned value can be one of the following values:
3270 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3271 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3272 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3273 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3274 */
LL_DMA_GetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel)3275 __STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3276 {
3277 uint32_t dma_base_addr = (uint32_t)DMAx;
3278 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
3279 }
3280
3281 /**
3282 * @brief Set destination hardware and software transfer request.
3283 * @note This API is used for all available DMA channels.
3284 * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
3285 * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
3286 * @param DMAx DMAx Instance
3287 * @param Channel This parameter can be one of the following values:
3288 * @arg @ref LL_DMA_CHANNEL_0
3289 * @arg @ref LL_DMA_CHANNEL_1
3290 * @arg @ref LL_DMA_CHANNEL_2
3291 * @arg @ref LL_DMA_CHANNEL_3
3292 * @arg @ref LL_DMA_CHANNEL_4
3293 * @arg @ref LL_DMA_CHANNEL_5
3294 * @arg @ref LL_DMA_CHANNEL_6
3295 * @arg @ref LL_DMA_CHANNEL_7
3296 * @arg @ref LL_DMA_CHANNEL_8
3297 * @arg @ref LL_DMA_CHANNEL_9
3298 * @arg @ref LL_DMA_CHANNEL_10
3299 * @arg @ref LL_DMA_CHANNEL_11
3300 * @arg @ref LL_DMA_CHANNEL_12
3301 * @arg @ref LL_DMA_CHANNEL_13
3302 * @arg @ref LL_DMA_CHANNEL_14
3303 * @arg @ref LL_DMA_CHANNEL_15
3304 * @param Direction This parameter can be one of the following values:
3305 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3306 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels)
3307 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels)
3308 * @retval None.
3309 */
LL_DMA_SetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)3310 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
3311 {
3312 uint32_t dma_base_addr = (uint32_t)DMAx;
3313 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3314 DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
3315 }
3316
3317 /**
3318 * @brief Get destination hardware and software transfer request.
3319 * @note This API is used for all available DMA channels.
3320 * For LPDMA channels, DREQ fields programming is discarded.
3321 * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
3322 * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
3323 * @param DMAx DMAx Instance
3324 * @param Channel This parameter can be one of the following values:
3325 * @arg @ref LL_DMA_CHANNEL_0
3326 * @arg @ref LL_DMA_CHANNEL_1
3327 * @arg @ref LL_DMA_CHANNEL_2
3328 * @arg @ref LL_DMA_CHANNEL_3
3329 * @arg @ref LL_DMA_CHANNEL_4
3330 * @arg @ref LL_DMA_CHANNEL_5
3331 * @arg @ref LL_DMA_CHANNEL_6
3332 * @arg @ref LL_DMA_CHANNEL_7
3333 * @arg @ref LL_DMA_CHANNEL_8
3334 * @arg @ref LL_DMA_CHANNEL_9
3335 * @arg @ref LL_DMA_CHANNEL_10
3336 * @arg @ref LL_DMA_CHANNEL_11
3337 * @arg @ref LL_DMA_CHANNEL_12
3338 * @arg @ref LL_DMA_CHANNEL_13
3339 * @arg @ref LL_DMA_CHANNEL_14
3340 * @arg @ref LL_DMA_CHANNEL_15
3341 * @retval Returned value can be one of the following values:
3342 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3343 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels)
3344 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels)
3345 */
LL_DMA_GetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel)3346 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
3347 {
3348 uint32_t dma_base_addr = (uint32_t)DMAx;
3349 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3350 DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
3351 }
3352
3353 /**
3354 * @brief Set block hardware request.
3355 * @note This API is used for all available DMA channels.
3356 * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
3357 * @param DMAx DMAx Instance
3358 * @param Channel This parameter can be one of the following values:
3359 * @arg @ref LL_DMA_CHANNEL_0
3360 * @arg @ref LL_DMA_CHANNEL_1
3361 * @arg @ref LL_DMA_CHANNEL_2
3362 * @arg @ref LL_DMA_CHANNEL_3
3363 * @arg @ref LL_DMA_CHANNEL_4
3364 * @arg @ref LL_DMA_CHANNEL_5
3365 * @arg @ref LL_DMA_CHANNEL_6
3366 * @arg @ref LL_DMA_CHANNEL_7
3367 * @arg @ref LL_DMA_CHANNEL_8
3368 * @arg @ref LL_DMA_CHANNEL_9
3369 * @arg @ref LL_DMA_CHANNEL_10
3370 * @arg @ref LL_DMA_CHANNEL_11
3371 * @arg @ref LL_DMA_CHANNEL_12
3372 * @arg @ref LL_DMA_CHANNEL_13
3373 * @arg @ref LL_DMA_CHANNEL_14
3374 * @arg @ref LL_DMA_CHANNEL_15
3375 * @param BlkHWRequest This parameter can be one of the following values:
3376 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3377 * @arg @ref LL_DMA_HWREQUEST_BLK
3378 * @retval None.
3379 */
LL_DMA_SetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkHWRequest)3380 __STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
3381 {
3382 uint32_t dma_base_addr = (uint32_t)DMAx;
3383 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
3384 BlkHWRequest);
3385 }
3386
3387 /**
3388 * @brief Get block hardware request.
3389 * @note This API is used for all available DMA channels.
3390 * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
3391 * @param DMAx DMAx Instance
3392 * @param Channel This parameter can be one of the following values:
3393 * @arg @ref LL_DMA_CHANNEL_0
3394 * @arg @ref LL_DMA_CHANNEL_1
3395 * @arg @ref LL_DMA_CHANNEL_2
3396 * @arg @ref LL_DMA_CHANNEL_3
3397 * @arg @ref LL_DMA_CHANNEL_4
3398 * @arg @ref LL_DMA_CHANNEL_5
3399 * @arg @ref LL_DMA_CHANNEL_6
3400 * @arg @ref LL_DMA_CHANNEL_7
3401 * @arg @ref LL_DMA_CHANNEL_8
3402 * @arg @ref LL_DMA_CHANNEL_9
3403 * @arg @ref LL_DMA_CHANNEL_10
3404 * @arg @ref LL_DMA_CHANNEL_11
3405 * @arg @ref LL_DMA_CHANNEL_12
3406 * @arg @ref LL_DMA_CHANNEL_13
3407 * @arg @ref LL_DMA_CHANNEL_14
3408 * @arg @ref LL_DMA_CHANNEL_15
3409 * @retval Returned value can be one of the following values:
3410 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3411 * @arg @ref LL_DMA_HWREQUEST_BLK
3412 */
LL_DMA_GetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel)3413 __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
3414 {
3415 uint32_t dma_base_addr = (uint32_t)DMAx;
3416 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
3417 }
3418
3419 /**
3420 * @brief Set hardware request.
3421 * @note This API is used for all available DMA channels.
3422 * For LPDMA channels, REQSEL fields is reduced to 5 bits.
3423 * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
3424 * @param DMAx DMAx Instance
3425 * @param Channel This parameter can be one of the following values:
3426 * @arg @ref LL_DMA_CHANNEL_0
3427 * @arg @ref LL_DMA_CHANNEL_1
3428 * @arg @ref LL_DMA_CHANNEL_2
3429 * @arg @ref LL_DMA_CHANNEL_3
3430 * @arg @ref LL_DMA_CHANNEL_4
3431 * @arg @ref LL_DMA_CHANNEL_5
3432 * @arg @ref LL_DMA_CHANNEL_6
3433 * @arg @ref LL_DMA_CHANNEL_7
3434 * @arg @ref LL_DMA_CHANNEL_8
3435 * @arg @ref LL_DMA_CHANNEL_9
3436 * @arg @ref LL_DMA_CHANNEL_10
3437 * @arg @ref LL_DMA_CHANNEL_11
3438 * @arg @ref LL_DMA_CHANNEL_12
3439 * @arg @ref LL_DMA_CHANNEL_13
3440 * @arg @ref LL_DMA_CHANNEL_14
3441 * @arg @ref LL_DMA_CHANNEL_15
3442 * @param Request This parameter can be one of the following values:
3443 * @arg @ref LL_GPDMA1_REQUEST_ADC1
3444 * @arg @ref LL_GPDMA1_REQUEST_ADC4
3445 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
3446 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
3447 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
3448 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
3449 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
3450 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
3451 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
3452 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
3453 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
3454 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
3455 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
3456 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
3457 * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC
3458 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
3459 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
3460 * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC
3461 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
3462 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
3463 * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
3464 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
3465 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
3466 * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC
3467 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
3468 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
3469 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*)
3470 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*)
3471 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
3472 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
3473 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX
3474 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX
3475 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX
3476 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX
3477 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
3478 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
3479 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
3480 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
3481 * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*)
3482 * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*)
3483 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
3484 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*)
3485 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
3486 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
3487 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
3488 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
3489 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
3490 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
3491 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
3492 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
3493 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
3494 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
3495 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
3496 * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
3497 * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
3498 * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
3499 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
3500 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
3501 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
3502 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
3503 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
3504 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
3505 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
3506 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
3507 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
3508 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
3509 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
3510 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
3511 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
3512 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
3513 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
3514 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
3515 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
3516 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
3517 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
3518 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
3519 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
3520 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
3521 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
3522 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
3523 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
3524 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
3525 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
3526 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
3527 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
3528 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
3529 * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI
3530 * @arg @ref LL_GPDMA1_REQUEST_AES_IN
3531 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT
3532 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
3533 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*)
3534 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*)
3535 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
3536 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
3537 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
3538 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
3539 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
3540 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
3541 * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
3542 * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ
3543 * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE
3544 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ
3545 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE
3546 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN
3547 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
3548 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
3549 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
3550 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
3551 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
3552 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
3553 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
3554 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
3555 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
3556 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
3557 * @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*)
3558 * @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*)
3559 * @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*)
3560 * @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*)
3561 * @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*)
3562 * @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*)
3563 * @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*)
3564 * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*)
3565 * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*)
3566 * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*)
3567 * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX (*)
3568 * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX (*)
3569 *
3570 * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX
3571 * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX
3572 * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX
3573 * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX
3574 * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX
3575 * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX
3576 * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC
3577 * @arg @ref LL_LPDMA1_REQUEST_ADC4
3578 * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1
3579 * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2
3580 * @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0
3581 * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1
3582 * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2
3583 * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE
3584 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1
3585 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2
3586 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE
3587 *
3588 * @note (*) Availability depends on devices.
3589 * @retval None.
3590 */
LL_DMA_SetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)3591 __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
3592 {
3593 uint32_t dma_base_addr = (uint32_t)DMAx;
3594 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
3595 }
3596
3597 /**
3598 * @brief Get hardware request.
3599 * @note This API is used for all available DMA channels.
3600 * For LPDMA channels, REQSEL fields is reduced to 5 bits.
3601 * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
3602 * @param DMAx DMAx Instance
3603 * @param Channel This parameter can be one of the following values:
3604 * @arg @ref LL_DMA_CHANNEL_0
3605 * @arg @ref LL_DMA_CHANNEL_1
3606 * @arg @ref LL_DMA_CHANNEL_2
3607 * @arg @ref LL_DMA_CHANNEL_3
3608 * @arg @ref LL_DMA_CHANNEL_4
3609 * @arg @ref LL_DMA_CHANNEL_5
3610 * @arg @ref LL_DMA_CHANNEL_6
3611 * @arg @ref LL_DMA_CHANNEL_7
3612 * @arg @ref LL_DMA_CHANNEL_8
3613 * @arg @ref LL_DMA_CHANNEL_9
3614 * @arg @ref LL_DMA_CHANNEL_10
3615 * @arg @ref LL_DMA_CHANNEL_11
3616 * @arg @ref LL_DMA_CHANNEL_12
3617 * @arg @ref LL_DMA_CHANNEL_13
3618 * @arg @ref LL_DMA_CHANNEL_14
3619 * @arg @ref LL_DMA_CHANNEL_15
3620 * @retval Returned value can be one of the following values:
3621 * @arg @ref LL_GPDMA1_REQUEST_ADC1
3622 * @arg @ref LL_GPDMA1_REQUEST_ADC4
3623 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
3624 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
3625 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
3626 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
3627 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
3628 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
3629 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
3630 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
3631 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
3632 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
3633 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
3634 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
3635 * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC
3636 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
3637 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
3638 * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC
3639 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
3640 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
3641 * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
3642 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
3643 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
3644 * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC
3645 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
3646 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
3647 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*)
3648 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*)
3649 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
3650 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
3651 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX
3652 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX
3653 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX
3654 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX
3655 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
3656 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
3657 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
3658 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
3659 * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*)
3660 * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*)
3661 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
3662 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*)
3663 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
3664 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
3665 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
3666 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
3667 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
3668 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
3669 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
3670 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
3671 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
3672 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
3673 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
3674 * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
3675 * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
3676 * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
3677 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
3678 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
3679 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
3680 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
3681 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
3682 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
3683 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
3684 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
3685 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
3686 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
3687 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
3688 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
3689 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
3690 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
3691 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
3692 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
3693 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
3694 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
3695 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
3696 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
3697 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
3698 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
3699 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
3700 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
3701 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
3702 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
3703 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
3704 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
3705 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
3706 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
3707 * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI
3708 * @arg @ref LL_GPDMA1_REQUEST_AES_IN
3709 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT
3710 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
3711 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*)
3712 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*)
3713 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
3714 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
3715 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
3716 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
3717 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
3718 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
3719 * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
3720 * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ
3721 * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE
3722 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ
3723 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE
3724 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN
3725 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
3726 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
3727 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
3728 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
3729 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
3730 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
3731 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
3732 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
3733 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
3734 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
3735 * @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*)
3736 * @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*)
3737 * @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*)
3738 * @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*)
3739 * @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*)
3740 * @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*)
3741 * @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*)
3742 * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*)
3743 * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*)
3744 * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*)
3745 * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX (*)
3746 * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX (*)
3747 *
3748 * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX
3749 * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX
3750 * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX
3751 * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX
3752 * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX
3753 * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX
3754 * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC
3755 * @arg @ref LL_LPDMA1_REQUEST_ADC4
3756 * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1
3757 * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2
3758 * @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0
3759 * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1
3760 * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2
3761 * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE
3762 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1
3763 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2
3764 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE
3765 *
3766 * @note (*) Availability depends on devices.
3767 */
LL_DMA_GetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel)3768 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
3769 {
3770 uint32_t dma_base_addr = (uint32_t)DMAx;
3771 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
3772 }
3773
3774 /**
3775 * @brief Set hardware trigger.
3776 * @note This API is used for all available DMA channels.
3777 * For LPDMA channels, TRIGSEL fields is reduced to 5 bits.
3778 * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
3779 * @param DMAx DMAx Instance
3780 * @param Channel This parameter can be one of the following values:
3781 * @arg @ref LL_DMA_CHANNEL_0
3782 * @arg @ref LL_DMA_CHANNEL_1
3783 * @arg @ref LL_DMA_CHANNEL_2
3784 * @arg @ref LL_DMA_CHANNEL_3
3785 * @arg @ref LL_DMA_CHANNEL_4
3786 * @arg @ref LL_DMA_CHANNEL_5
3787 * @arg @ref LL_DMA_CHANNEL_6
3788 * @arg @ref LL_DMA_CHANNEL_7
3789 * @arg @ref LL_DMA_CHANNEL_8
3790 * @arg @ref LL_DMA_CHANNEL_9
3791 * @arg @ref LL_DMA_CHANNEL_10
3792 * @arg @ref LL_DMA_CHANNEL_11
3793 * @arg @ref LL_DMA_CHANNEL_12
3794 * @arg @ref LL_DMA_CHANNEL_13
3795 * @arg @ref LL_DMA_CHANNEL_14
3796 * @arg @ref LL_DMA_CHANNEL_15
3797 * @param Trigger This parameter can be one of the following values:
3798 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
3799 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
3800 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
3801 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
3802 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
3803 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
3804 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
3805 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
3806 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
3807 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
3808 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
3809 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
3810 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT
3811 * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*)
3812 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
3813 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
3814 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
3815 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
3816 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
3817 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
3818 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
3819 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
3820 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
3821 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
3822 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
3823 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
3824 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
3825 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
3826 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
3827 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
3828 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
3829 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
3830 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
3831 * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF
3832 * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF
3833 * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF
3834 * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF
3835 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
3836 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
3837 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*)
3838 * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*)
3839 * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*)
3840 * @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*)
3841 * @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*)
3842 * @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*)
3843 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*)
3844 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*)
3845 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*)
3846 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*)
3847 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*)
3848 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*)
3849 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*)
3850 * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1
3851 * @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1
3852 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT3 (*)
3853 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT2 (*)
3854 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT1 (*)
3855 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT0 (*)
3856 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC (*)
3857 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF (*)
3858 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT (*)
3859 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE (*)
3860 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT (*)
3861 *
3862 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0
3863 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1
3864 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2
3865 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3
3866 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4
3867 * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1
3868 * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2
3869 * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3
3870 * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1
3871 * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2
3872 * @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1
3873 * @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT
3874 * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT
3875 * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT (*)
3876 * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG
3877 * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG
3878 * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG
3879 * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1
3880 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF
3881 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF
3882 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF
3883 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF
3884 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF
3885 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF
3886 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF
3887 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF
3888 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF
3889 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF
3890 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF
3891 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF
3892 * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO
3893 * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO
3894 * @note (*) Availability depends on devices.
3895 * @retval None.
3896 */
LL_DMA_SetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Trigger)3897 __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
3898 {
3899 uint32_t dma_base_addr = (uint32_t)DMAx;
3900 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
3901 (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
3902 }
3903
3904 /**
3905 * @brief Get hardware triggers.
3906 * @note This API is used for all available DMA channels.
3907 * For LPDMA channels, TRIGSEL fields is reduced to 5 bits.
3908 * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
3909 * @param DMAx DMAx Instance
3910 * @param Channel This parameter can be one of the following values:
3911 * @arg @ref LL_DMA_CHANNEL_0
3912 * @arg @ref LL_DMA_CHANNEL_1
3913 * @arg @ref LL_DMA_CHANNEL_2
3914 * @arg @ref LL_DMA_CHANNEL_3
3915 * @arg @ref LL_DMA_CHANNEL_4
3916 * @arg @ref LL_DMA_CHANNEL_5
3917 * @arg @ref LL_DMA_CHANNEL_6
3918 * @arg @ref LL_DMA_CHANNEL_7
3919 * @arg @ref LL_DMA_CHANNEL_8
3920 * @arg @ref LL_DMA_CHANNEL_9
3921 * @arg @ref LL_DMA_CHANNEL_10
3922 * @arg @ref LL_DMA_CHANNEL_11
3923 * @arg @ref LL_DMA_CHANNEL_12
3924 * @arg @ref LL_DMA_CHANNEL_13
3925 * @arg @ref LL_DMA_CHANNEL_14
3926 * @arg @ref LL_DMA_CHANNEL_15
3927 * @retval Returned value can be one of the following values:
3928 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
3929 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
3930 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
3931 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
3932 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
3933 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
3934 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
3935 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
3936 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
3937 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
3938 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
3939 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
3940 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT
3941 * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*)
3942 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
3943 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
3944 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
3945 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
3946 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
3947 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
3948 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
3949 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
3950 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
3951 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
3952 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
3953 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
3954 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
3955 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
3956 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
3957 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
3958 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
3959 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
3960 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
3961 * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF
3962 * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF
3963 * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF
3964 * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF
3965 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
3966 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
3967 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*)
3968 * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*)
3969 * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*)
3970 * @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*)
3971 * @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*)
3972 * @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*)
3973 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*)
3974 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*)
3975 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*)
3976 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*)
3977 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*)
3978 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*)
3979 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*)
3980 * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1
3981 * @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1
3982 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT3 (*)
3983 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT2 (*)
3984 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT1 (*)
3985 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT0 (*)
3986 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC (*)
3987 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF (*)
3988 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT (*)
3989 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE (*)
3990 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT (*)
3991 *
3992 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0
3993 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1
3994 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2
3995 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3
3996 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4
3997 * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1
3998 * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2
3999 * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3
4000 * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1
4001 * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2
4002 * @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1
4003 * @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT
4004 * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT
4005 * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT (*)
4006 * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG
4007 * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG
4008 * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG
4009 * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1
4010 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF
4011 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF
4012 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF
4013 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF
4014 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF
4015 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF
4016 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF
4017 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF
4018 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF
4019 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF
4020 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF
4021 * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF
4022 * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO
4023 * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO
4024 * @note (*) Availability depends on devices.
4025 */
LL_DMA_GetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel)4026 __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel)
4027 {
4028 uint32_t dma_base_addr = (uint32_t)DMAx;
4029 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
4030 DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
4031 }
4032
4033 /**
4034 * @brief Configure addresses update.
4035 * @note This API is used only for 2D addressing channels.
4036 * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4037 * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4038 * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4039 * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate
4040 * @param DMAx DMAx Instance
4041 * @param Channel This parameter can be one of the following values:
4042 * @arg @ref LL_DMA_CHANNEL_12
4043 * @arg @ref LL_DMA_CHANNEL_13
4044 * @arg @ref LL_DMA_CHANNEL_14
4045 * @arg @ref LL_DMA_CHANNEL_15
4046 * @param Configuration This parameter must be a combination of all the following values:
4047 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4048 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4049 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4050 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4051 *@retval None.
4052 */
LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)4053 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
4054 {
4055 uint32_t dma_base_addr = (uint32_t)DMAx;
4056 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4057 DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration);
4058 }
4059
4060 /**
4061 * @brief Configure DMA Block number of data and repeat Count.
4062 * @note This API is used only for 2D addressing channels.
4063 * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n
4064 * CBR1 BRC LL_DMA_ConfigBlkCounters
4065 * @param DMAx DMAx Instance
4066 * @param Channel This parameter can be one of the following values:
4067 * @arg @ref LL_DMA_CHANNEL_12
4068 * @arg @ref LL_DMA_CHANNEL_13
4069 * @arg @ref LL_DMA_CHANNEL_14
4070 * @arg @ref LL_DMA_CHANNEL_15
4071 * @param BlkDataLength Block transfer length
4072 Value between 0 to 0x0000FFFF
4073 * @param BlkRptCount Block repeat counter
4074 * Value between 0 to 0x000007FF
4075 *@retval None.
4076 */
LL_DMA_ConfigBlkCounters(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength,uint32_t BlkRptCount)4077 __STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength,
4078 uint32_t BlkRptCount)
4079 {
4080 uint32_t dma_base_addr = (uint32_t)DMAx;
4081 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4082 (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos)));
4083 }
4084
4085 /**
4086 * @brief Set block repeat destination address update.
4087 * @note This API is used only for 2D addressing channels.
4088 * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate
4089 * @param DMAx DMAx Instance
4090 * @param Channel This parameter can be one of the following values:
4091 * @arg @ref LL_DMA_CHANNEL_12
4092 * @arg @ref LL_DMA_CHANNEL_13
4093 * @arg @ref LL_DMA_CHANNEL_14
4094 * @arg @ref LL_DMA_CHANNEL_15
4095 * @param BlkRptDestAddrUpdate This parameter can be one of the following values:
4096 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
4097 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4098 * @retval None.
4099 */
LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrUpdate)4100 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
4101 uint32_t BlkRptDestAddrUpdate)
4102 {
4103 uint32_t dma_base_addr = (uint32_t)DMAx;
4104 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC,
4105 BlkRptDestAddrUpdate);
4106 }
4107
4108 /**
4109 * @brief Get block repeat destination address update.
4110 * @note This API is used only for 2D addressing channels.
4111 * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate
4112 * @param DMAx DMAx Instance
4113 * @param Channel This parameter can be one of the following values:
4114 * @arg @ref LL_DMA_CHANNEL_12
4115 * @arg @ref LL_DMA_CHANNEL_13
4116 * @arg @ref LL_DMA_CHANNEL_14
4117 * @arg @ref LL_DMA_CHANNEL_15
4118 * @retval Returned value can be one of the following values:
4119 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
4120 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4121 */
LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4122 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4123 {
4124 uint32_t dma_base_addr = (uint32_t)DMAx;
4125 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC));
4126 }
4127
4128 /**
4129 * @brief Set block repeat source address update.
4130 * @note This API is used only for 2D addressing channels.
4131 * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate
4132 * @param DMAx DMAx Instance
4133 * @param Channel This parameter can be one of the following values:
4134 * @arg @ref LL_DMA_CHANNEL_12
4135 * @arg @ref LL_DMA_CHANNEL_13
4136 * @arg @ref LL_DMA_CHANNEL_14
4137 * @arg @ref LL_DMA_CHANNEL_15
4138 * @param BlkRptSrcAddrUpdate This parameter can be one of the following values:
4139 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
4140 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4141 * @retval None.
4142 */
LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrUpdate)4143 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
4144 uint32_t BlkRptSrcAddrUpdate)
4145 {
4146 uint32_t dma_base_addr = (uint32_t)DMAx;
4147 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC,
4148 BlkRptSrcAddrUpdate);
4149 }
4150
4151 /**
4152 * @brief Get block repeat source address update.
4153 * @note This API is used only for 2D addressing channels.
4154 * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate
4155 * @param DMAx DMAx Instance
4156 * @param Channel This parameter can be one of the following values:
4157 * @arg @ref LL_DMA_CHANNEL_12
4158 * @arg @ref LL_DMA_CHANNEL_13
4159 * @arg @ref LL_DMA_CHANNEL_14
4160 * @arg @ref LL_DMA_CHANNEL_15
4161 * @retval Returned value can be one of the following values:
4162 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
4163 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4164 */
LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4165 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4166 {
4167 uint32_t dma_base_addr = (uint32_t)DMAx;
4168 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC));
4169 }
4170
4171 /**
4172 * @brief Set destination address update.
4173 * @note This API is used only for 2D addressing channels.
4174 * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate
4175 * @param DMAx DMAx Instance
4176 * @param Channel This parameter can be one of the following values:
4177 * @arg @ref LL_DMA_CHANNEL_12
4178 * @arg @ref LL_DMA_CHANNEL_13
4179 * @arg @ref LL_DMA_CHANNEL_14
4180 * @arg @ref LL_DMA_CHANNEL_15
4181 * @param DestAddrUpdate This parameter can be one of the following values:
4182 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
4183 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4184 * @retval None.
4185 */
LL_DMA_SetDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrUpdate)4186 __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate)
4187 {
4188 uint32_t dma_base_addr = (uint32_t)DMAx;
4189 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC,
4190 DestAddrUpdate);
4191 }
4192
4193 /**
4194 * @brief Get destination address update.
4195 * @note This API is used only for 2D addressing channels.
4196 * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate
4197 * @param DMAx DMAx Instance
4198 * @param Channel This parameter can be one of the following values:
4199 * @arg @ref LL_DMA_CHANNEL_12
4200 * @arg @ref LL_DMA_CHANNEL_13
4201 * @arg @ref LL_DMA_CHANNEL_14
4202 * @arg @ref LL_DMA_CHANNEL_15
4203 * @retval Returned value can be one of the following values:
4204 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
4205 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4206 */
LL_DMA_GetDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4207 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4208 {
4209 uint32_t dma_base_addr = (uint32_t)DMAx;
4210 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC));
4211 }
4212
4213 /**
4214 * @brief Set source address update.
4215 * @note This API is used only for 2D addressing channels.
4216 * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate
4217 * @param DMAx DMAx Instance
4218 * @param Channel This parameter can be one of the following values:
4219 * @arg @ref LL_DMA_CHANNEL_12
4220 * @arg @ref LL_DMA_CHANNEL_13
4221 * @arg @ref LL_DMA_CHANNEL_14
4222 * @arg @ref LL_DMA_CHANNEL_15
4223 * @param SrcAddrUpdate This parameter can be one of the following values:
4224 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
4225 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4226 * @retval None.
4227 */
LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrUpdate)4228 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate)
4229 {
4230 uint32_t dma_base_addr = (uint32_t)DMAx;
4231 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC,
4232 SrcAddrUpdate);
4233 }
4234
4235 /**
4236 * @brief Get source address update.
4237 * @note This API is used only for 2D addressing channels.
4238 * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate
4239 * @param DMAx DMAx Instance
4240 * @param Channel This parameter can be one of the following values:
4241 * @arg @ref LL_DMA_CHANNEL_12
4242 * @arg @ref LL_DMA_CHANNEL_13
4243 * @arg @ref LL_DMA_CHANNEL_14
4244 * @arg @ref LL_DMA_CHANNEL_15
4245 * @retval Returned value can be one of the following values:
4246 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
4247 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4248 */
LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4249 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4250 {
4251 uint32_t dma_base_addr = (uint32_t)DMAx;
4252 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC));
4253 }
4254
4255 /**
4256 * @brief Set block repeat count.
4257 * @note This API is used only for 2D addressing channels.
4258 * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount
4259 * @param DMAx DMAx Instance
4260 * @param Channel This parameter can be one of the following values:
4261 * @arg @ref LL_DMA_CHANNEL_12
4262 * @arg @ref LL_DMA_CHANNEL_13
4263 * @arg @ref LL_DMA_CHANNEL_14
4264 * @arg @ref LL_DMA_CHANNEL_15
4265 * @param BlkRptCount Block repeat counter
4266 * Value between 0 to 0x000007FF
4267 * @retval None.
4268 */
LL_DMA_SetBlkRptCount(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptCount)4269 __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount)
4270 {
4271 uint32_t dma_base_addr = (uint32_t)DMAx;
4272 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC,
4273 (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
4274 }
4275
4276 /**
4277 * @brief Get block repeat count.
4278 * @note This API is used only for 2D addressing channels.
4279 * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount
4280 * @param DMAx DMAx Instance
4281 * @param Channel This parameter can be one of the following values:
4282 * @arg @ref LL_DMA_CHANNEL_12
4283 * @arg @ref LL_DMA_CHANNEL_13
4284 * @arg @ref LL_DMA_CHANNEL_14
4285 * @arg @ref LL_DMA_CHANNEL_15
4286 * @retval Between 0 to 0x000007FF
4287 */
LL_DMA_GetBlkRptCount(const DMA_TypeDef * DMAx,uint32_t Channel)4288 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel)
4289 {
4290 uint32_t dma_base_addr = (uint32_t)DMAx;
4291 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4292 DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos);
4293 }
4294
4295 /**
4296 * @brief Set block data length in bytes to transfer.
4297 * @note This API is used for all available DMA channels.
4298 * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
4299 * @param DMAx DMAx Instance
4300 * @param Channel This parameter can be one of the following values:
4301 * @arg @ref LL_DMA_CHANNEL_0
4302 * @arg @ref LL_DMA_CHANNEL_1
4303 * @arg @ref LL_DMA_CHANNEL_2
4304 * @arg @ref LL_DMA_CHANNEL_3
4305 * @arg @ref LL_DMA_CHANNEL_4
4306 * @arg @ref LL_DMA_CHANNEL_5
4307 * @arg @ref LL_DMA_CHANNEL_6
4308 * @arg @ref LL_DMA_CHANNEL_7
4309 * @arg @ref LL_DMA_CHANNEL_8
4310 * @arg @ref LL_DMA_CHANNEL_9
4311 * @arg @ref LL_DMA_CHANNEL_10
4312 * @arg @ref LL_DMA_CHANNEL_11
4313 * @arg @ref LL_DMA_CHANNEL_12
4314 * @arg @ref LL_DMA_CHANNEL_13
4315 * @arg @ref LL_DMA_CHANNEL_14
4316 * @arg @ref LL_DMA_CHANNEL_15
4317 * @param BlkDataLength Between 0 to 0x0000FFFF
4318 * @retval None.
4319 */
LL_DMA_SetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength)4320 __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
4321 {
4322 uint32_t dma_base_addr = (uint32_t)DMAx;
4323 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
4324 BlkDataLength);
4325 }
4326
4327 /**
4328 * @brief Get block data length in bytes to transfer.
4329 * @note This API is used for all available DMA channels.
4330 * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
4331 * @param DMAx DMAx Instance
4332 * @param Channel This parameter can be one of the following values:
4333 * @arg @ref LL_DMA_CHANNEL_0
4334 * @arg @ref LL_DMA_CHANNEL_1
4335 * @arg @ref LL_DMA_CHANNEL_2
4336 * @arg @ref LL_DMA_CHANNEL_3
4337 * @arg @ref LL_DMA_CHANNEL_4
4338 * @arg @ref LL_DMA_CHANNEL_5
4339 * @arg @ref LL_DMA_CHANNEL_6
4340 * @arg @ref LL_DMA_CHANNEL_7
4341 * @arg @ref LL_DMA_CHANNEL_8
4342 * @arg @ref LL_DMA_CHANNEL_9
4343 * @arg @ref LL_DMA_CHANNEL_10
4344 * @arg @ref LL_DMA_CHANNEL_11
4345 * @arg @ref LL_DMA_CHANNEL_12
4346 * @arg @ref LL_DMA_CHANNEL_13
4347 * @arg @ref LL_DMA_CHANNEL_14
4348 * @arg @ref LL_DMA_CHANNEL_15
4349 * @retval Between 0 to 0x0000FFFF
4350 */
LL_DMA_GetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel)4351 __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
4352 {
4353 uint32_t dma_base_addr = (uint32_t)DMAx;
4354 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
4355 }
4356
4357 /**
4358 * @brief Configure the source and destination addresses.
4359 * @note This API is used for all available DMA channels.
4360 * @note This API must not be called when the DMA Channel is enabled.
4361 * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
4362 * CDAR DA LL_DMA_ConfigAddresses
4363 * @param DMAx DMAx Instance
4364 * @param Channel This parameter can be one of the following values:
4365 * @arg @ref LL_DMA_CHANNEL_0
4366 * @arg @ref LL_DMA_CHANNEL_1
4367 * @arg @ref LL_DMA_CHANNEL_2
4368 * @arg @ref LL_DMA_CHANNEL_3
4369 * @arg @ref LL_DMA_CHANNEL_4
4370 * @arg @ref LL_DMA_CHANNEL_5
4371 * @arg @ref LL_DMA_CHANNEL_6
4372 * @arg @ref LL_DMA_CHANNEL_7
4373 * @arg @ref LL_DMA_CHANNEL_8
4374 * @arg @ref LL_DMA_CHANNEL_9
4375 * @arg @ref LL_DMA_CHANNEL_10
4376 * @arg @ref LL_DMA_CHANNEL_11
4377 * @arg @ref LL_DMA_CHANNEL_12
4378 * @arg @ref LL_DMA_CHANNEL_13
4379 * @arg @ref LL_DMA_CHANNEL_14
4380 * @arg @ref LL_DMA_CHANNEL_15
4381 * @param SrcAddress Between 0 to 0xFFFFFFFF
4382 * @param DestAddress Between 0 to 0xFFFFFFFF
4383 * @retval None.
4384 */
LL_DMA_ConfigAddresses(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DestAddress)4385 __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
4386 DestAddress)
4387 {
4388 uint32_t dma_base_addr = (uint32_t)DMAx;
4389 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
4390 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
4391 }
4392
4393 /**
4394 * @brief Set source address.
4395 * @note This API is used for all available DMA channels.
4396 * @rmtoll CSAR SA LL_DMA_SetSrcAddress
4397 * @param DMAx DMAx Instance
4398 * @param Channel This parameter can be one of the following values:
4399 * @arg @ref LL_DMA_CHANNEL_0
4400 * @arg @ref LL_DMA_CHANNEL_1
4401 * @arg @ref LL_DMA_CHANNEL_2
4402 * @arg @ref LL_DMA_CHANNEL_3
4403 * @arg @ref LL_DMA_CHANNEL_4
4404 * @arg @ref LL_DMA_CHANNEL_5
4405 * @arg @ref LL_DMA_CHANNEL_6
4406 * @arg @ref LL_DMA_CHANNEL_7
4407 * @arg @ref LL_DMA_CHANNEL_8
4408 * @arg @ref LL_DMA_CHANNEL_9
4409 * @arg @ref LL_DMA_CHANNEL_10
4410 * @arg @ref LL_DMA_CHANNEL_11
4411 * @arg @ref LL_DMA_CHANNEL_12
4412 * @arg @ref LL_DMA_CHANNEL_13
4413 * @arg @ref LL_DMA_CHANNEL_14
4414 * @arg @ref LL_DMA_CHANNEL_15
4415 * @param SrcAddress Between 0 to 0xFFFFFFFF
4416 * @retval None.
4417 */
LL_DMA_SetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress)4418 __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
4419 {
4420 uint32_t dma_base_addr = (uint32_t)DMAx;
4421 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
4422 }
4423
4424 /**
4425 * @brief Get source address.
4426 * @note This API is used for all available DMA channels.
4427 * @rmtoll CSAR SA LL_DMA_GetSrcAddress
4428 * @param DMAx DMAx Instance
4429 * @param Channel This parameter can be one of the following values:
4430 * @arg @ref LL_DMA_CHANNEL_0
4431 * @arg @ref LL_DMA_CHANNEL_1
4432 * @arg @ref LL_DMA_CHANNEL_2
4433 * @arg @ref LL_DMA_CHANNEL_3
4434 * @arg @ref LL_DMA_CHANNEL_4
4435 * @arg @ref LL_DMA_CHANNEL_5
4436 * @arg @ref LL_DMA_CHANNEL_6
4437 * @arg @ref LL_DMA_CHANNEL_7
4438 * @arg @ref LL_DMA_CHANNEL_8
4439 * @arg @ref LL_DMA_CHANNEL_9
4440 * @arg @ref LL_DMA_CHANNEL_10
4441 * @arg @ref LL_DMA_CHANNEL_11
4442 * @arg @ref LL_DMA_CHANNEL_12
4443 * @arg @ref LL_DMA_CHANNEL_13
4444 * @arg @ref LL_DMA_CHANNEL_14
4445 * @arg @ref LL_DMA_CHANNEL_15
4446 * @retval Between 0 to 0xFFFFFFFF
4447 */
LL_DMA_GetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel)4448 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
4449 {
4450 uint32_t dma_base_addr = (uint32_t)DMAx;
4451 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
4452 }
4453
4454 /**
4455 * @brief Set destination address.
4456 * @note This API is used for all available DMA channels.
4457 * @rmtoll CDAR DA LL_DMA_SetDestAddress
4458 * @param DMAx DMAx Instance
4459 * @param Channel This parameter can be one of the following values:
4460 * @arg @ref LL_DMA_CHANNEL_0
4461 * @arg @ref LL_DMA_CHANNEL_1
4462 * @arg @ref LL_DMA_CHANNEL_2
4463 * @arg @ref LL_DMA_CHANNEL_3
4464 * @arg @ref LL_DMA_CHANNEL_4
4465 * @arg @ref LL_DMA_CHANNEL_5
4466 * @arg @ref LL_DMA_CHANNEL_6
4467 * @arg @ref LL_DMA_CHANNEL_7
4468 * @arg @ref LL_DMA_CHANNEL_8
4469 * @arg @ref LL_DMA_CHANNEL_9
4470 * @arg @ref LL_DMA_CHANNEL_10
4471 * @arg @ref LL_DMA_CHANNEL_11
4472 * @arg @ref LL_DMA_CHANNEL_12
4473 * @arg @ref LL_DMA_CHANNEL_13
4474 * @arg @ref LL_DMA_CHANNEL_14
4475 * @arg @ref LL_DMA_CHANNEL_15
4476 * @param DestAddress Between 0 to 0xFFFFFFFF
4477 * @retval None.
4478 */
LL_DMA_SetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddress)4479 __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
4480 {
4481 uint32_t dma_base_addr = (uint32_t)DMAx;
4482 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
4483 }
4484
4485 /**
4486 * @brief Get destination address.
4487 * @note This API is used for all available DMA channels.
4488 * @rmtoll CDAR DA LL_DMA_GetDestAddress
4489 * @param DMAx DMAx Instance
4490 * @param Channel This parameter can be one of the following values:
4491 * @arg @ref LL_DMA_CHANNEL_0
4492 * @arg @ref LL_DMA_CHANNEL_1
4493 * @arg @ref LL_DMA_CHANNEL_2
4494 * @arg @ref LL_DMA_CHANNEL_3
4495 * @arg @ref LL_DMA_CHANNEL_4
4496 * @arg @ref LL_DMA_CHANNEL_5
4497 * @arg @ref LL_DMA_CHANNEL_6
4498 * @arg @ref LL_DMA_CHANNEL_7
4499 * @arg @ref LL_DMA_CHANNEL_8
4500 * @arg @ref LL_DMA_CHANNEL_9
4501 * @arg @ref LL_DMA_CHANNEL_10
4502 * @arg @ref LL_DMA_CHANNEL_11
4503 * @arg @ref LL_DMA_CHANNEL_12
4504 * @arg @ref LL_DMA_CHANNEL_13
4505 * @arg @ref LL_DMA_CHANNEL_14
4506 * @arg @ref LL_DMA_CHANNEL_15
4507 * @retval Between 0 to 0xFFFFFFFF
4508 */
LL_DMA_GetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel)4509 __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
4510 {
4511 uint32_t dma_base_addr = (uint32_t)DMAx;
4512 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
4513 }
4514
4515 /**
4516 * @brief Configure source and destination addresses offset.
4517 * @note This API is used only for 2D addressing channels.
4518 * @note This API must not be called when the DMA Channel is enabled.
4519 * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n
4520 * CTR3 SAO LL_DMA_ConfigAddrUpdateValue
4521 * @param DMAx DMAx Instance
4522 * @param Channel This parameter can be one of the following values:
4523 * @arg @ref LL_DMA_CHANNEL_12
4524 * @arg @ref LL_DMA_CHANNEL_13
4525 * @arg @ref LL_DMA_CHANNEL_14
4526 * @arg @ref LL_DMA_CHANNEL_15
4527 * @param DestAddrOffset Between 0 to 0x00001FFF
4528 * @param SrcAddrOffset Between 0 to 0x00001FFF
4529 * @retval None.
4530 */
LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset,uint32_t DestAddrOffset)4531 __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset,
4532 uint32_t DestAddrOffset)
4533 {
4534 uint32_t dma_base_addr = (uint32_t)DMAx;
4535 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
4536 (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
4537 }
4538
4539 /**
4540 * @brief Set destination address offset.
4541 * @note This API is used only for 2D addressing channels.
4542 * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue
4543 * @param DMAx DMAx Instance
4544 * @param Channel This parameter can be one of the following values:
4545 * @arg @ref LL_DMA_CHANNEL_12
4546 * @arg @ref LL_DMA_CHANNEL_13
4547 * @arg @ref LL_DMA_CHANNEL_14
4548 * @arg @ref LL_DMA_CHANNEL_15
4549 * @param DestAddrOffset Between 0 to 0x00001FFF
4550 * @retval None.
4551 */
LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrOffset)4552 __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset)
4553 {
4554 uint32_t dma_base_addr = (uint32_t)DMAx;
4555 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO,
4556 ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
4557 }
4558
4559 /**
4560 * @brief Get destination address offset.
4561 * @note This API is used only for 2D addressing channels.
4562 * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue
4563 * @param DMAx DMAx Instance
4564 * @param Channel This parameter can be one of the following values:
4565 * @arg @ref LL_DMA_CHANNEL_12
4566 * @arg @ref LL_DMA_CHANNEL_13
4567 * @arg @ref LL_DMA_CHANNEL_14
4568 * @arg @ref LL_DMA_CHANNEL_15
4569 * @retval Between 0 to 0x00001FFF
4570 */
LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4571 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4572 {
4573 uint32_t dma_base_addr = (uint32_t)DMAx;
4574 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
4575 DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
4576 }
4577
4578 /**
4579 * @brief Set source address offset.
4580 * @note This API is used only for 2D addressing channels.
4581 * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue
4582 * @param DMAx DMAx Instance
4583 * @param Channel This parameter can be one of the following values:
4584 * @arg @ref LL_DMA_CHANNEL_12
4585 * @arg @ref LL_DMA_CHANNEL_13
4586 * @arg @ref LL_DMA_CHANNEL_14
4587 * @arg @ref LL_DMA_CHANNEL_15
4588 * @param SrcAddrOffset Between 0 to 0x00001FFF
4589 * @retval None.
4590 */
LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset)4591 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset)
4592 {
4593 uint32_t dma_base_addr = (uint32_t)DMAx;
4594 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO,
4595 SrcAddrOffset & DMA_CTR3_SAO);
4596 }
4597
4598 /**
4599 * @brief Get source address offset.
4600 * @note This API is used only for 2D addressing channels.
4601 * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue
4602 * @param DMAx DMAx Instance
4603 * @param Channel This parameter can be one of the following values:
4604 * @arg @ref LL_DMA_CHANNEL_12
4605 * @arg @ref LL_DMA_CHANNEL_13
4606 * @arg @ref LL_DMA_CHANNEL_14
4607 * @arg @ref LL_DMA_CHANNEL_15
4608 * @retval Between 0 to 0x00001FFF
4609 */
LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4610 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4611 {
4612 uint32_t dma_base_addr = (uint32_t)DMAx;
4613 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO));
4614 }
4615
4616 /**
4617 * @brief Configure the block repeated source and destination addresses offset.
4618 * @note This API is used only for 2D addressing channels.
4619 * @note This API must not be called when the DMA Channel is enabled.
4620 * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n
4621 * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue
4622 * @param DMAx DMAx Instance
4623 * @param Channel This parameter can be one of the following values:
4624 * @arg @ref LL_DMA_CHANNEL_12
4625 * @arg @ref LL_DMA_CHANNEL_13
4626 * @arg @ref LL_DMA_CHANNEL_14
4627 * @arg @ref LL_DMA_CHANNEL_15
4628 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
4629 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
4630 * @retval None.
4631 */
LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset,uint32_t BlkRptDestAddrOffset)4632 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4633 uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset)
4634 {
4635 uint32_t dma_base_addr = (uint32_t)DMAx;
4636 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
4637 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO));
4638 }
4639
4640 /**
4641 * @brief Set block repeated destination address offset.
4642 * @note This API is used only for 2D addressing channels.
4643 * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue
4644 * @param DMAx DMAx Instance
4645 * @param Channel This parameter can be one of the following values:
4646 * @arg @ref LL_DMA_CHANNEL_12
4647 * @arg @ref LL_DMA_CHANNEL_13
4648 * @arg @ref LL_DMA_CHANNEL_14
4649 * @arg @ref LL_DMA_CHANNEL_15
4650 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
4651 * @retval None.
4652 */
LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrOffset)4653 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4654 uint32_t BlkRptDestAddrOffset)
4655 {
4656 uint32_t dma_base_addr = (uint32_t)DMAx;
4657 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO,
4658 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO));
4659 }
4660
4661 /**
4662 * @brief Get block repeated destination address offset.
4663 * @note This API is used only for 2D addressing channels.
4664 * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue
4665 * @param DMAx DMAx Instance
4666 * @param Channel This parameter can be one of the following values:
4667 * @arg @ref LL_DMA_CHANNEL_12
4668 * @arg @ref LL_DMA_CHANNEL_13
4669 * @arg @ref LL_DMA_CHANNEL_14
4670 * @arg @ref LL_DMA_CHANNEL_15
4671 * @retval Between 0 to 0x0000FFFF.
4672 */
LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4673 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4674 {
4675 uint32_t dma_base_addr = (uint32_t)DMAx;
4676 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
4677 DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
4678 }
4679
4680 /**
4681 * @brief Set block repeated source address offset.
4682 * @note This API is used only for 2D addressing channels.
4683 * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue
4684 * @param DMAx DMAx Instance
4685 * @param Channel This parameter can be one of the following values:
4686 * @arg @ref LL_DMA_CHANNEL_12
4687 * @arg @ref LL_DMA_CHANNEL_13
4688 * @arg @ref LL_DMA_CHANNEL_14
4689 * @arg @ref LL_DMA_CHANNEL_15
4690 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
4691 * @retval None.
4692 */
LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset)4693 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4694 uint32_t BlkRptSrcAddrOffset)
4695 {
4696 uint32_t dma_base_addr = (uint32_t)DMAx;
4697 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO,
4698 BlkRptSrcAddrOffset);
4699 }
4700
4701 /**
4702 * @brief Get block repeated source address offset.
4703 * @note This API is used only for 2D addressing channels.
4704 * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue
4705 * @param DMAx DMAx Instance
4706 * @param Channel This parameter can be one of the following values:
4707 * @arg @ref LL_DMA_CHANNEL_12
4708 * @arg @ref LL_DMA_CHANNEL_13
4709 * @arg @ref LL_DMA_CHANNEL_14
4710 * @arg @ref LL_DMA_CHANNEL_15
4711 * @retval Between 0 to 0x0000FFFF
4712 */
LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4713 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4714 {
4715 uint32_t dma_base_addr = (uint32_t)DMAx;
4716 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO));
4717 }
4718
4719 /**
4720 * @brief Configure registers update and node address offset during the link transfer.
4721 * @note This API is used for all available DMA channels.
4722 * For linear addressing channels, UT3 and UB2 fields are discarded.
4723 * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n
4724 * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n
4725 * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n
4726 * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n
4727 * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n
4728 * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n
4729 * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n
4730 * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate
4731 * @param DMAx DMAx Instance
4732 * @param Channel This parameter can be one of the following values:
4733 * @arg @ref LL_DMA_CHANNEL_0
4734 * @arg @ref LL_DMA_CHANNEL_1
4735 * @arg @ref LL_DMA_CHANNEL_2
4736 * @arg @ref LL_DMA_CHANNEL_3
4737 * @arg @ref LL_DMA_CHANNEL_4
4738 * @arg @ref LL_DMA_CHANNEL_5
4739 * @arg @ref LL_DMA_CHANNEL_6
4740 * @arg @ref LL_DMA_CHANNEL_7
4741 * @arg @ref LL_DMA_CHANNEL_8
4742 * @arg @ref LL_DMA_CHANNEL_9
4743 * @arg @ref LL_DMA_CHANNEL_10
4744 * @arg @ref LL_DMA_CHANNEL_11
4745 * @arg @ref LL_DMA_CHANNEL_12
4746 * @arg @ref LL_DMA_CHANNEL_13
4747 * @arg @ref LL_DMA_CHANNEL_14
4748 * @arg @ref LL_DMA_CHANNEL_15
4749 * @param RegistersUpdate This parameter must be a combination of all the following values:
4750 * @arg @ref LL_DMA_UPDATE_CTR1
4751 * @arg @ref LL_DMA_UPDATE_CTR2
4752 * @arg @ref LL_DMA_UPDATE_CBR1
4753 * @arg @ref LL_DMA_UPDATE_CSAR
4754 * @arg @ref LL_DMA_UPDATE_CDAR
4755 * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels)
4756 * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels)
4757 * @arg @ref LL_DMA_UPDATE_CLLR
4758 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
4759 * @retval None.
4760 */
LL_DMA_ConfigLinkUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t RegistersUpdate,uint32_t LinkedListAddrOffset)4761 __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
4762 uint32_t LinkedListAddrOffset)
4763 {
4764 uint32_t dma_base_addr = (uint32_t)DMAx;
4765 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
4766 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \
4767 DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
4768 }
4769
4770 /**
4771 * @brief Enable CTR1 update during the link transfer.
4772 * @note This API is used for all available DMA channels.
4773 * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
4774 * @param DMAx DMAx Instance
4775 * @param Channel This parameter can be one of the following values:
4776 * @arg @ref LL_DMA_CHANNEL_0
4777 * @arg @ref LL_DMA_CHANNEL_1
4778 * @arg @ref LL_DMA_CHANNEL_2
4779 * @arg @ref LL_DMA_CHANNEL_3
4780 * @arg @ref LL_DMA_CHANNEL_4
4781 * @arg @ref LL_DMA_CHANNEL_5
4782 * @arg @ref LL_DMA_CHANNEL_6
4783 * @arg @ref LL_DMA_CHANNEL_7
4784 * @arg @ref LL_DMA_CHANNEL_8
4785 * @arg @ref LL_DMA_CHANNEL_9
4786 * @arg @ref LL_DMA_CHANNEL_10
4787 * @arg @ref LL_DMA_CHANNEL_11
4788 * @arg @ref LL_DMA_CHANNEL_12
4789 * @arg @ref LL_DMA_CHANNEL_13
4790 * @arg @ref LL_DMA_CHANNEL_14
4791 * @arg @ref LL_DMA_CHANNEL_15
4792 * @retval None.
4793 */
LL_DMA_EnableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4794 __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4795 {
4796 uint32_t dma_base_addr = (uint32_t)DMAx;
4797 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
4798 }
4799
4800 /**
4801 * @brief Disable CTR1 update during the link transfer.
4802 * @note This API is used for all available DMA channels.
4803 * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
4804 * @param DMAx DMAx Instance
4805 * @param Channel This parameter can be one of the following values:
4806 * @arg @ref LL_DMA_CHANNEL_0
4807 * @arg @ref LL_DMA_CHANNEL_1
4808 * @arg @ref LL_DMA_CHANNEL_2
4809 * @arg @ref LL_DMA_CHANNEL_3
4810 * @arg @ref LL_DMA_CHANNEL_4
4811 * @arg @ref LL_DMA_CHANNEL_5
4812 * @arg @ref LL_DMA_CHANNEL_6
4813 * @arg @ref LL_DMA_CHANNEL_7
4814 * @arg @ref LL_DMA_CHANNEL_8
4815 * @arg @ref LL_DMA_CHANNEL_9
4816 * @arg @ref LL_DMA_CHANNEL_10
4817 * @arg @ref LL_DMA_CHANNEL_11
4818 * @arg @ref LL_DMA_CHANNEL_12
4819 * @arg @ref LL_DMA_CHANNEL_13
4820 * @arg @ref LL_DMA_CHANNEL_14
4821 * @arg @ref LL_DMA_CHANNEL_15
4822 * @retval None.
4823 */
LL_DMA_DisableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4824 __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4825 {
4826 uint32_t dma_base_addr = (uint32_t)DMAx;
4827 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
4828 }
4829
4830 /**
4831 * @brief Check if CTR1 update during the link transfer is enabled.
4832 * @note This API is used for all available DMA channels.
4833 * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
4834 * @param DMAx DMAx Instance
4835 * @param Channel This parameter can be one of the following values:
4836 * @arg @ref LL_DMA_CHANNEL_0
4837 * @arg @ref LL_DMA_CHANNEL_1
4838 * @arg @ref LL_DMA_CHANNEL_2
4839 * @arg @ref LL_DMA_CHANNEL_3
4840 * @arg @ref LL_DMA_CHANNEL_4
4841 * @arg @ref LL_DMA_CHANNEL_5
4842 * @arg @ref LL_DMA_CHANNEL_6
4843 * @arg @ref LL_DMA_CHANNEL_7
4844 * @arg @ref LL_DMA_CHANNEL_8
4845 * @arg @ref LL_DMA_CHANNEL_9
4846 * @arg @ref LL_DMA_CHANNEL_10
4847 * @arg @ref LL_DMA_CHANNEL_11
4848 * @arg @ref LL_DMA_CHANNEL_12
4849 * @arg @ref LL_DMA_CHANNEL_13
4850 * @arg @ref LL_DMA_CHANNEL_14
4851 * @arg @ref LL_DMA_CHANNEL_15
4852 * @retval State of bit (1 or 0).
4853 */
LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4854 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4855 {
4856 uint32_t dma_base_addr = (uint32_t)DMAx;
4857 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
4858 == (DMA_CLLR_UT1)) ? 1UL : 0UL);
4859 }
4860
4861 /**
4862 * @brief Enable CTR2 update during the link transfer.
4863 * @note This API is used for all available DMA channels.
4864 * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
4865 * @param DMAx DMAx Instance
4866 * @param Channel This parameter can be one of the following values:
4867 * @arg @ref LL_DMA_CHANNEL_0
4868 * @arg @ref LL_DMA_CHANNEL_1
4869 * @arg @ref LL_DMA_CHANNEL_2
4870 * @arg @ref LL_DMA_CHANNEL_3
4871 * @arg @ref LL_DMA_CHANNEL_4
4872 * @arg @ref LL_DMA_CHANNEL_5
4873 * @arg @ref LL_DMA_CHANNEL_6
4874 * @arg @ref LL_DMA_CHANNEL_7
4875 * @arg @ref LL_DMA_CHANNEL_8
4876 * @arg @ref LL_DMA_CHANNEL_9
4877 * @arg @ref LL_DMA_CHANNEL_10
4878 * @arg @ref LL_DMA_CHANNEL_11
4879 * @arg @ref LL_DMA_CHANNEL_12
4880 * @arg @ref LL_DMA_CHANNEL_13
4881 * @arg @ref LL_DMA_CHANNEL_14
4882 * @arg @ref LL_DMA_CHANNEL_15
4883 * @retval None.
4884 */
LL_DMA_EnableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4885 __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4886 {
4887 uint32_t dma_base_addr = (uint32_t)DMAx;
4888 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
4889 }
4890
4891 /**
4892 * @brief Disable CTR2 update during the link transfer.
4893 * @note This API is used for all available DMA channels.
4894 * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
4895 * @param DMAx DMAx Instance
4896 * @param Channel This parameter can be one of the following values:
4897 * @arg @ref LL_DMA_CHANNEL_0
4898 * @arg @ref LL_DMA_CHANNEL_1
4899 * @arg @ref LL_DMA_CHANNEL_2
4900 * @arg @ref LL_DMA_CHANNEL_3
4901 * @arg @ref LL_DMA_CHANNEL_4
4902 * @arg @ref LL_DMA_CHANNEL_5
4903 * @arg @ref LL_DMA_CHANNEL_6
4904 * @arg @ref LL_DMA_CHANNEL_7
4905 * @arg @ref LL_DMA_CHANNEL_8
4906 * @arg @ref LL_DMA_CHANNEL_9
4907 * @arg @ref LL_DMA_CHANNEL_10
4908 * @arg @ref LL_DMA_CHANNEL_11
4909 * @arg @ref LL_DMA_CHANNEL_12
4910 * @arg @ref LL_DMA_CHANNEL_13
4911 * @arg @ref LL_DMA_CHANNEL_14
4912 * @arg @ref LL_DMA_CHANNEL_15
4913 * @retval None.
4914 */
LL_DMA_DisableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4915 __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4916 {
4917 uint32_t dma_base_addr = (uint32_t)DMAx;
4918 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
4919 }
4920
4921 /**
4922 * @brief Check if CTR2 update during the link transfer is enabled.
4923 * @note This API is used for all available DMA channels.
4924 * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
4925 * @param DMAx DMAx Instance
4926 * @param Channel This parameter can be one of the following values:
4927 * @arg @ref LL_DMA_CHANNEL_0
4928 * @arg @ref LL_DMA_CHANNEL_1
4929 * @arg @ref LL_DMA_CHANNEL_2
4930 * @arg @ref LL_DMA_CHANNEL_3
4931 * @arg @ref LL_DMA_CHANNEL_4
4932 * @arg @ref LL_DMA_CHANNEL_5
4933 * @arg @ref LL_DMA_CHANNEL_6
4934 * @arg @ref LL_DMA_CHANNEL_7
4935 * @arg @ref LL_DMA_CHANNEL_8
4936 * @arg @ref LL_DMA_CHANNEL_9
4937 * @arg @ref LL_DMA_CHANNEL_10
4938 * @arg @ref LL_DMA_CHANNEL_11
4939 * @arg @ref LL_DMA_CHANNEL_12
4940 * @arg @ref LL_DMA_CHANNEL_13
4941 * @arg @ref LL_DMA_CHANNEL_14
4942 * @arg @ref LL_DMA_CHANNEL_15
4943 * @retval State of bit (1 or 0).
4944 */
LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4945 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4946 {
4947 uint32_t dma_base_addr = (uint32_t)DMAx;
4948 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
4949 == (DMA_CLLR_UT2)) ? 1UL : 0UL);
4950 }
4951
4952 /**
4953 * @brief Enable CBR1 update during the link transfer.
4954 * @note This API is used for all available DMA channels.
4955 * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
4956 * @param DMAx DMAx Instance
4957 * @param Channel This parameter can be one of the following values:
4958 * @arg @ref LL_DMA_CHANNEL_0
4959 * @arg @ref LL_DMA_CHANNEL_1
4960 * @arg @ref LL_DMA_CHANNEL_2
4961 * @arg @ref LL_DMA_CHANNEL_3
4962 * @arg @ref LL_DMA_CHANNEL_4
4963 * @arg @ref LL_DMA_CHANNEL_5
4964 * @arg @ref LL_DMA_CHANNEL_6
4965 * @arg @ref LL_DMA_CHANNEL_7
4966 * @arg @ref LL_DMA_CHANNEL_8
4967 * @arg @ref LL_DMA_CHANNEL_9
4968 * @arg @ref LL_DMA_CHANNEL_10
4969 * @arg @ref LL_DMA_CHANNEL_11
4970 * @arg @ref LL_DMA_CHANNEL_12
4971 * @arg @ref LL_DMA_CHANNEL_13
4972 * @arg @ref LL_DMA_CHANNEL_14
4973 * @arg @ref LL_DMA_CHANNEL_15
4974 * @retval None.
4975 */
LL_DMA_EnableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4976 __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4977 {
4978 uint32_t dma_base_addr = (uint32_t)DMAx;
4979 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
4980 }
4981
4982 /**
4983 * @brief Disable CBR1 update during the link transfer.
4984 * @note This API is used for all available DMA channels.
4985 * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
4986 * @param DMAx DMAx Instance
4987 * @param Channel This parameter can be one of the following values:
4988 * @arg @ref LL_DMA_CHANNEL_0
4989 * @arg @ref LL_DMA_CHANNEL_1
4990 * @arg @ref LL_DMA_CHANNEL_2
4991 * @arg @ref LL_DMA_CHANNEL_3
4992 * @arg @ref LL_DMA_CHANNEL_4
4993 * @arg @ref LL_DMA_CHANNEL_5
4994 * @arg @ref LL_DMA_CHANNEL_6
4995 * @arg @ref LL_DMA_CHANNEL_7
4996 * @arg @ref LL_DMA_CHANNEL_8
4997 * @arg @ref LL_DMA_CHANNEL_9
4998 * @arg @ref LL_DMA_CHANNEL_10
4999 * @arg @ref LL_DMA_CHANNEL_11
5000 * @arg @ref LL_DMA_CHANNEL_12
5001 * @arg @ref LL_DMA_CHANNEL_13
5002 * @arg @ref LL_DMA_CHANNEL_14
5003 * @arg @ref LL_DMA_CHANNEL_15
5004 * @retval None.
5005 */
LL_DMA_DisableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)5006 __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5007 {
5008 uint32_t dma_base_addr = (uint32_t)DMAx;
5009 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
5010 }
5011
5012 /**
5013 * @brief Check if CBR1 update during the link transfer is enabled.
5014 * @note This API is used for all available DMA channels.
5015 * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
5016 * @param DMAx DMAx Instance
5017 * @param Channel This parameter can be one of the following values:
5018 * @arg @ref LL_DMA_CHANNEL_0
5019 * @arg @ref LL_DMA_CHANNEL_1
5020 * @arg @ref LL_DMA_CHANNEL_2
5021 * @arg @ref LL_DMA_CHANNEL_3
5022 * @arg @ref LL_DMA_CHANNEL_4
5023 * @arg @ref LL_DMA_CHANNEL_5
5024 * @arg @ref LL_DMA_CHANNEL_6
5025 * @arg @ref LL_DMA_CHANNEL_7
5026 * @arg @ref LL_DMA_CHANNEL_8
5027 * @arg @ref LL_DMA_CHANNEL_9
5028 * @arg @ref LL_DMA_CHANNEL_10
5029 * @arg @ref LL_DMA_CHANNEL_11
5030 * @arg @ref LL_DMA_CHANNEL_12
5031 * @arg @ref LL_DMA_CHANNEL_13
5032 * @arg @ref LL_DMA_CHANNEL_14
5033 * @arg @ref LL_DMA_CHANNEL_15
5034 * @retval State of bit (1 or 0).
5035 */
LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)5036 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5037 {
5038 uint32_t dma_base_addr = (uint32_t)DMAx;
5039 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
5040 == (DMA_CLLR_UB1)) ? 1UL : 0UL);
5041 }
5042
5043 /**
5044 * @brief Enable CSAR update during the link transfer.
5045 * @note This API is used for all available DMA channels.
5046 * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
5047 * @param DMAx DMAx Instance
5048 * @param Channel This parameter can be one of the following values:
5049 * @arg @ref LL_DMA_CHANNEL_0
5050 * @arg @ref LL_DMA_CHANNEL_1
5051 * @arg @ref LL_DMA_CHANNEL_2
5052 * @arg @ref LL_DMA_CHANNEL_3
5053 * @arg @ref LL_DMA_CHANNEL_4
5054 * @arg @ref LL_DMA_CHANNEL_5
5055 * @arg @ref LL_DMA_CHANNEL_6
5056 * @arg @ref LL_DMA_CHANNEL_7
5057 * @arg @ref LL_DMA_CHANNEL_8
5058 * @arg @ref LL_DMA_CHANNEL_9
5059 * @arg @ref LL_DMA_CHANNEL_10
5060 * @arg @ref LL_DMA_CHANNEL_11
5061 * @arg @ref LL_DMA_CHANNEL_12
5062 * @arg @ref LL_DMA_CHANNEL_13
5063 * @arg @ref LL_DMA_CHANNEL_14
5064 * @arg @ref LL_DMA_CHANNEL_15
5065 * @retval None.
5066 */
LL_DMA_EnableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5067 __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5068 {
5069 uint32_t dma_base_addr = (uint32_t)DMAx;
5070 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
5071 }
5072
5073 /**
5074 * @brief Disable CSAR update during the link transfer.
5075 * @note This API is used for all available DMA channels.
5076 * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
5077 * @param DMAx DMAx Instance
5078 * @param Channel This parameter can be one of the following values:
5079 * @arg @ref LL_DMA_CHANNEL_0
5080 * @arg @ref LL_DMA_CHANNEL_1
5081 * @arg @ref LL_DMA_CHANNEL_2
5082 * @arg @ref LL_DMA_CHANNEL_3
5083 * @arg @ref LL_DMA_CHANNEL_4
5084 * @arg @ref LL_DMA_CHANNEL_5
5085 * @arg @ref LL_DMA_CHANNEL_6
5086 * @arg @ref LL_DMA_CHANNEL_7
5087 * @arg @ref LL_DMA_CHANNEL_8
5088 * @arg @ref LL_DMA_CHANNEL_9
5089 * @arg @ref LL_DMA_CHANNEL_10
5090 * @arg @ref LL_DMA_CHANNEL_11
5091 * @arg @ref LL_DMA_CHANNEL_12
5092 * @arg @ref LL_DMA_CHANNEL_13
5093 * @arg @ref LL_DMA_CHANNEL_14
5094 * @arg @ref LL_DMA_CHANNEL_15
5095 * @retval None.
5096 */
LL_DMA_DisableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5097 __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5098 {
5099 uint32_t dma_base_addr = (uint32_t)DMAx;
5100 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
5101 }
5102
5103 /**
5104 * @brief Check if CSAR update during the link transfer is enabled.
5105 * @note This API is used for all available DMA channels.
5106 * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
5107 * @param DMAx DMAx Instance
5108 * @param Channel This parameter can be one of the following values:
5109 * @arg @ref LL_DMA_CHANNEL_0
5110 * @arg @ref LL_DMA_CHANNEL_1
5111 * @arg @ref LL_DMA_CHANNEL_2
5112 * @arg @ref LL_DMA_CHANNEL_3
5113 * @arg @ref LL_DMA_CHANNEL_4
5114 * @arg @ref LL_DMA_CHANNEL_5
5115 * @arg @ref LL_DMA_CHANNEL_6
5116 * @arg @ref LL_DMA_CHANNEL_7
5117 * @arg @ref LL_DMA_CHANNEL_8
5118 * @arg @ref LL_DMA_CHANNEL_9
5119 * @arg @ref LL_DMA_CHANNEL_10
5120 * @arg @ref LL_DMA_CHANNEL_11
5121 * @arg @ref LL_DMA_CHANNEL_12
5122 * @arg @ref LL_DMA_CHANNEL_13
5123 * @arg @ref LL_DMA_CHANNEL_14
5124 * @arg @ref LL_DMA_CHANNEL_15
5125 * @retval State of bit (1 or 0).
5126 */
LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5127 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5128 {
5129 uint32_t dma_base_addr = (uint32_t)DMAx;
5130 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
5131 == (DMA_CLLR_USA)) ? 1UL : 0UL);
5132 }
5133
5134 /**
5135 * @brief Enable CDAR update during the link transfer.
5136 * @note This API is used for all available DMA channels.
5137 * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
5138 * @param DMAx DMAx Instance
5139 * @param Channel This parameter can be one of the following values:
5140 * @arg @ref LL_DMA_CHANNEL_0
5141 * @arg @ref LL_DMA_CHANNEL_1
5142 * @arg @ref LL_DMA_CHANNEL_2
5143 * @arg @ref LL_DMA_CHANNEL_3
5144 * @arg @ref LL_DMA_CHANNEL_4
5145 * @arg @ref LL_DMA_CHANNEL_5
5146 * @arg @ref LL_DMA_CHANNEL_6
5147 * @arg @ref LL_DMA_CHANNEL_7
5148 * @arg @ref LL_DMA_CHANNEL_8
5149 * @arg @ref LL_DMA_CHANNEL_9
5150 * @arg @ref LL_DMA_CHANNEL_10
5151 * @arg @ref LL_DMA_CHANNEL_11
5152 * @arg @ref LL_DMA_CHANNEL_12
5153 * @arg @ref LL_DMA_CHANNEL_13
5154 * @arg @ref LL_DMA_CHANNEL_14
5155 * @arg @ref LL_DMA_CHANNEL_15
5156 * @retval None.
5157 */
LL_DMA_EnableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5158 __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5159 {
5160 uint32_t dma_base_addr = (uint32_t)DMAx;
5161 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
5162 }
5163
5164 /**
5165 * @brief Disable CDAR update during the link transfer.
5166 * @note This API is used for all available DMA channels.
5167 * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
5168 * @param DMAx DMAx Instance
5169 * @param Channel This parameter can be one of the following values:
5170 * @arg @ref LL_DMA_CHANNEL_0
5171 * @arg @ref LL_DMA_CHANNEL_1
5172 * @arg @ref LL_DMA_CHANNEL_2
5173 * @arg @ref LL_DMA_CHANNEL_3
5174 * @arg @ref LL_DMA_CHANNEL_4
5175 * @arg @ref LL_DMA_CHANNEL_5
5176 * @arg @ref LL_DMA_CHANNEL_6
5177 * @arg @ref LL_DMA_CHANNEL_7
5178 * @arg @ref LL_DMA_CHANNEL_8
5179 * @arg @ref LL_DMA_CHANNEL_9
5180 * @arg @ref LL_DMA_CHANNEL_10
5181 * @arg @ref LL_DMA_CHANNEL_11
5182 * @arg @ref LL_DMA_CHANNEL_12
5183 * @arg @ref LL_DMA_CHANNEL_13
5184 * @arg @ref LL_DMA_CHANNEL_14
5185 * @arg @ref LL_DMA_CHANNEL_15
5186 * @retval None.
5187 */
LL_DMA_DisableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5188 __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5189 {
5190 uint32_t dma_base_addr = (uint32_t)DMAx;
5191 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
5192 }
5193
5194 /**
5195 * @brief Check if CDAR update during the link transfer is enabled.
5196 * @note This API is used for all available DMA channels.
5197 * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
5198 * @param DMAx DMAx Instance
5199 * @param Channel This parameter can be one of the following values:
5200 * @arg @ref LL_DMA_CHANNEL_0
5201 * @arg @ref LL_DMA_CHANNEL_1
5202 * @arg @ref LL_DMA_CHANNEL_2
5203 * @arg @ref LL_DMA_CHANNEL_3
5204 * @arg @ref LL_DMA_CHANNEL_4
5205 * @arg @ref LL_DMA_CHANNEL_5
5206 * @arg @ref LL_DMA_CHANNEL_6
5207 * @arg @ref LL_DMA_CHANNEL_7
5208 * @arg @ref LL_DMA_CHANNEL_8
5209 * @arg @ref LL_DMA_CHANNEL_9
5210 * @arg @ref LL_DMA_CHANNEL_10
5211 * @arg @ref LL_DMA_CHANNEL_11
5212 * @arg @ref LL_DMA_CHANNEL_12
5213 * @arg @ref LL_DMA_CHANNEL_13
5214 * @arg @ref LL_DMA_CHANNEL_14
5215 * @arg @ref LL_DMA_CHANNEL_15
5216 * @retval State of bit (1 or 0).
5217 */
LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5218 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5219 {
5220 uint32_t dma_base_addr = (uint32_t)DMAx;
5221 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
5222 == (DMA_CLLR_UDA)) ? 1UL : 0UL);
5223 }
5224
5225 /**
5226 * @brief Enable CTR3 update during the link transfer.
5227 * @note This API is used only for 2D addressing channels.
5228 * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update
5229 * @param DMAx DMAx Instance
5230 * @param Channel This parameter can be one of the following values:
5231 * @arg @ref LL_DMA_CHANNEL_12
5232 * @arg @ref LL_DMA_CHANNEL_13
5233 * @arg @ref LL_DMA_CHANNEL_14
5234 * @arg @ref LL_DMA_CHANNEL_15
5235 * @retval None.
5236 */
LL_DMA_EnableCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5237 __STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5238 {
5239 uint32_t dma_base_addr = (uint32_t)DMAx;
5240 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
5241 }
5242
5243 /**
5244 * @brief Disable CTR3 update during the link transfer.
5245 * @note This API is used only for 2D addressing channels.
5246 * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update
5247 * @param DMAx DMAx Instance
5248 * @param Channel This parameter can be one of the following values:
5249 * @arg @ref LL_DMA_CHANNEL_12
5250 * @arg @ref LL_DMA_CHANNEL_13
5251 * @arg @ref LL_DMA_CHANNEL_14
5252 * @arg @ref LL_DMA_CHANNEL_15
5253 * @retval None.
5254 */
LL_DMA_DisableCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5255 __STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5256 {
5257 uint32_t dma_base_addr = (uint32_t)DMAx;
5258 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
5259 }
5260
5261 /**
5262 * @brief Check if CTR3 update during the link transfer is enabled.
5263 * @note This API is used only for 2D addressing channels.
5264 * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update
5265 * @param DMAx DMAx Instance
5266 * @param Channel This parameter can be one of the following values:
5267 * @arg @ref LL_DMA_CHANNEL_12
5268 * @arg @ref LL_DMA_CHANNEL_13
5269 * @arg @ref LL_DMA_CHANNEL_14
5270 * @arg @ref LL_DMA_CHANNEL_15
5271 * @retval State of bit (1 or 0).
5272 */
LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5273 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5274 {
5275 uint32_t dma_base_addr = (uint32_t)DMAx;
5276 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3)
5277 == (DMA_CLLR_UT3)) ? 1UL : 0UL);
5278 }
5279
5280 /**
5281 * @brief Enable CBR2 update during the link transfer.
5282 * @note This API is used only for 2D addressing channels.
5283 * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update
5284 * @param DMAx DMAx Instance
5285 * @param Channel This parameter can be one of the following values:
5286 * @arg @ref LL_DMA_CHANNEL_12
5287 * @arg @ref LL_DMA_CHANNEL_13
5288 * @arg @ref LL_DMA_CHANNEL_14
5289 * @arg @ref LL_DMA_CHANNEL_15
5290 * @retval None.
5291 */
LL_DMA_EnableCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5292 __STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5293 {
5294 uint32_t dma_base_addr = (uint32_t)DMAx;
5295 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
5296 }
5297
5298 /**
5299 * @brief Disable CBR2 update during the link transfer.
5300 * @note This API is used only for 2D addressing channels.
5301 * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update
5302 * @param DMAx DMAx Instance
5303 * @param Channel This parameter can be one of the following values:
5304 * @arg @ref LL_DMA_CHANNEL_12
5305 * @arg @ref LL_DMA_CHANNEL_13
5306 * @arg @ref LL_DMA_CHANNEL_14
5307 * @arg @ref LL_DMA_CHANNEL_15
5308 * @retval None.
5309 */
LL_DMA_DisableCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5310 __STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5311 {
5312 uint32_t dma_base_addr = (uint32_t)DMAx;
5313 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
5314 }
5315
5316 /**
5317 * @brief Check if CBR2 update during the link transfer is enabled.
5318 * @note This API is used only for 2D addressing channels.
5319 * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update
5320 * @param DMAx DMAx Instance
5321 * @param Channel This parameter can be one of the following values:
5322 * @arg @ref LL_DMA_CHANNEL_12
5323 * @arg @ref LL_DMA_CHANNEL_13
5324 * @arg @ref LL_DMA_CHANNEL_14
5325 * @arg @ref LL_DMA_CHANNEL_15
5326 * @retval State of bit (1 or 0).
5327 */
LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5328 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5329 {
5330 uint32_t dma_base_addr = (uint32_t)DMAx;
5331 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2)
5332 == (DMA_CLLR_UB2)) ? 1UL : 0UL);
5333 }
5334
5335 /**
5336 * @brief Enable CLLR update during the link transfer.
5337 * @note This API is used for all available DMA channels.
5338 * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
5339 * @param DMAx DMAx Instance
5340 * @param Channel This parameter can be one of the following values:
5341 * @arg @ref LL_DMA_CHANNEL_0
5342 * @arg @ref LL_DMA_CHANNEL_1
5343 * @arg @ref LL_DMA_CHANNEL_2
5344 * @arg @ref LL_DMA_CHANNEL_3
5345 * @arg @ref LL_DMA_CHANNEL_4
5346 * @arg @ref LL_DMA_CHANNEL_5
5347 * @arg @ref LL_DMA_CHANNEL_6
5348 * @arg @ref LL_DMA_CHANNEL_7
5349 * @arg @ref LL_DMA_CHANNEL_8
5350 * @arg @ref LL_DMA_CHANNEL_9
5351 * @arg @ref LL_DMA_CHANNEL_10
5352 * @arg @ref LL_DMA_CHANNEL_11
5353 * @arg @ref LL_DMA_CHANNEL_12
5354 * @arg @ref LL_DMA_CHANNEL_13
5355 * @arg @ref LL_DMA_CHANNEL_14
5356 * @arg @ref LL_DMA_CHANNEL_15
5357 * @retval None.
5358 */
LL_DMA_EnableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5359 __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5360 {
5361 uint32_t dma_base_addr = (uint32_t)DMAx;
5362 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
5363 }
5364
5365 /**
5366 * @brief Disable CLLR update during the link transfer.
5367 * @note This API is used for all available DMA channels.
5368 * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
5369 * @param DMAx DMAx Instance
5370 * @param Channel This parameter can be one of the following values:
5371 * @arg @ref LL_DMA_CHANNEL_0
5372 * @arg @ref LL_DMA_CHANNEL_1
5373 * @arg @ref LL_DMA_CHANNEL_2
5374 * @arg @ref LL_DMA_CHANNEL_3
5375 * @arg @ref LL_DMA_CHANNEL_4
5376 * @arg @ref LL_DMA_CHANNEL_5
5377 * @arg @ref LL_DMA_CHANNEL_6
5378 * @arg @ref LL_DMA_CHANNEL_7
5379 * @arg @ref LL_DMA_CHANNEL_8
5380 * @arg @ref LL_DMA_CHANNEL_9
5381 * @arg @ref LL_DMA_CHANNEL_10
5382 * @arg @ref LL_DMA_CHANNEL_11
5383 * @arg @ref LL_DMA_CHANNEL_12
5384 * @arg @ref LL_DMA_CHANNEL_13
5385 * @arg @ref LL_DMA_CHANNEL_14
5386 * @arg @ref LL_DMA_CHANNEL_15
5387 * @retval None.
5388 */
LL_DMA_DisableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5389 __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5390 {
5391 uint32_t dma_base_addr = (uint32_t)DMAx;
5392 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
5393 }
5394
5395 /**
5396 * @brief Check if CLLR update during the link transfer is enabled.
5397 * @note This API is used for all available DMA channels.
5398 * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
5399 * @param DMAx DMAx Instance
5400 * @param Channel This parameter can be one of the following values:
5401 * @arg @ref LL_DMA_CHANNEL_0
5402 * @arg @ref LL_DMA_CHANNEL_1
5403 * @arg @ref LL_DMA_CHANNEL_2
5404 * @arg @ref LL_DMA_CHANNEL_3
5405 * @arg @ref LL_DMA_CHANNEL_4
5406 * @arg @ref LL_DMA_CHANNEL_5
5407 * @arg @ref LL_DMA_CHANNEL_6
5408 * @arg @ref LL_DMA_CHANNEL_7
5409 * @arg @ref LL_DMA_CHANNEL_8
5410 * @arg @ref LL_DMA_CHANNEL_9
5411 * @arg @ref LL_DMA_CHANNEL_10
5412 * @arg @ref LL_DMA_CHANNEL_11
5413 * @arg @ref LL_DMA_CHANNEL_12
5414 * @arg @ref LL_DMA_CHANNEL_13
5415 * @arg @ref LL_DMA_CHANNEL_14
5416 * @arg @ref LL_DMA_CHANNEL_15
5417 * @retval State of bit (1 or 0).
5418 */
LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5419 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5420 {
5421 uint32_t dma_base_addr = (uint32_t)DMAx;
5422 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
5423 == (DMA_CLLR_ULL)) ? 1UL : 0UL);
5424 }
5425
5426 /**
5427 * @brief Set linked list address offset.
5428 * @note This API is used for all available DMA channels.
5429 * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
5430 * @param DMAx DMAx Instance
5431 * @param Channel This parameter can be one of the following values:
5432 * @arg @ref LL_DMA_CHANNEL_0
5433 * @arg @ref LL_DMA_CHANNEL_1
5434 * @arg @ref LL_DMA_CHANNEL_2
5435 * @arg @ref LL_DMA_CHANNEL_3
5436 * @arg @ref LL_DMA_CHANNEL_4
5437 * @arg @ref LL_DMA_CHANNEL_5
5438 * @arg @ref LL_DMA_CHANNEL_6
5439 * @arg @ref LL_DMA_CHANNEL_7
5440 * @arg @ref LL_DMA_CHANNEL_8
5441 * @arg @ref LL_DMA_CHANNEL_9
5442 * @arg @ref LL_DMA_CHANNEL_10
5443 * @arg @ref LL_DMA_CHANNEL_11
5444 * @arg @ref LL_DMA_CHANNEL_12
5445 * @arg @ref LL_DMA_CHANNEL_13
5446 * @arg @ref LL_DMA_CHANNEL_14
5447 * @arg @ref LL_DMA_CHANNEL_15
5448 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
5449 * @retval None.
5450 */
LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListAddrOffset)5451 __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel,
5452 uint32_t LinkedListAddrOffset)
5453 {
5454 uint32_t dma_base_addr = (uint32_t)DMAx;
5455 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
5456 (LinkedListAddrOffset & DMA_CLLR_LA));
5457 }
5458
5459 /**
5460 * @brief Get linked list address offset.
5461 * @note This API is used for all available DMA channels.
5462 * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
5463 * @param DMAx DMAx Instance
5464 * @param Channel This parameter can be one of the following values:
5465 * @arg @ref LL_DMA_CHANNEL_0
5466 * @arg @ref LL_DMA_CHANNEL_1
5467 * @arg @ref LL_DMA_CHANNEL_2
5468 * @arg @ref LL_DMA_CHANNEL_3
5469 * @arg @ref LL_DMA_CHANNEL_4
5470 * @arg @ref LL_DMA_CHANNEL_5
5471 * @arg @ref LL_DMA_CHANNEL_6
5472 * @arg @ref LL_DMA_CHANNEL_7
5473 * @arg @ref LL_DMA_CHANNEL_8
5474 * @arg @ref LL_DMA_CHANNEL_9
5475 * @arg @ref LL_DMA_CHANNEL_10
5476 * @arg @ref LL_DMA_CHANNEL_11
5477 * @arg @ref LL_DMA_CHANNEL_12
5478 * @arg @ref LL_DMA_CHANNEL_13
5479 * @arg @ref LL_DMA_CHANNEL_14
5480 * @arg @ref LL_DMA_CHANNEL_15
5481 * @retval Between 0 to 0x0000FFFC.
5482 */
LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel)5483 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel)
5484 {
5485 uint32_t dma_base_addr = (uint32_t)DMAx;
5486 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
5487 DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
5488 }
5489
5490 /**
5491 * @brief Get FIFO level.
5492 * @note This API is not used for LPDMA channels.
5493 * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
5494 * @param DMAx DMAx Instance
5495 * @param Channel This parameter can be one of the following values:
5496 * @arg @ref LL_DMA_CHANNEL_0
5497 * @arg @ref LL_DMA_CHANNEL_1
5498 * @arg @ref LL_DMA_CHANNEL_2
5499 * @arg @ref LL_DMA_CHANNEL_3
5500 * @arg @ref LL_DMA_CHANNEL_4
5501 * @arg @ref LL_DMA_CHANNEL_5
5502 * @arg @ref LL_DMA_CHANNEL_6
5503 * @arg @ref LL_DMA_CHANNEL_7
5504 * @arg @ref LL_DMA_CHANNEL_8
5505 * @arg @ref LL_DMA_CHANNEL_9
5506 * @arg @ref LL_DMA_CHANNEL_10
5507 * @arg @ref LL_DMA_CHANNEL_11
5508 * @arg @ref LL_DMA_CHANNEL_12
5509 * @arg @ref LL_DMA_CHANNEL_13
5510 * @arg @ref LL_DMA_CHANNEL_14
5511 * @arg @ref LL_DMA_CHANNEL_15
5512 * @retval Between 0 to 0x000000FF.
5513 */
LL_DMA_GetFIFOLevel(const DMA_TypeDef * DMAx,uint32_t Channel)5514 __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
5515 {
5516 uint32_t dma_base_addr = (uint32_t)DMAx;
5517 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
5518 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
5519 }
5520
5521 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5522 /**
5523 * @brief Enable the DMA channel secure attribute.
5524 * @note This API is used for all available DMA channels.
5525 * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure
5526 * @param DMAx DMAx Instance
5527 * @param Channel This parameter can be one of the following values:
5528 * @arg @ref LL_DMA_CHANNEL_0
5529 * @arg @ref LL_DMA_CHANNEL_1
5530 * @arg @ref LL_DMA_CHANNEL_2
5531 * @arg @ref LL_DMA_CHANNEL_3
5532 * @arg @ref LL_DMA_CHANNEL_4
5533 * @arg @ref LL_DMA_CHANNEL_5
5534 * @arg @ref LL_DMA_CHANNEL_6
5535 * @arg @ref LL_DMA_CHANNEL_7
5536 * @arg @ref LL_DMA_CHANNEL_8
5537 * @arg @ref LL_DMA_CHANNEL_9
5538 * @arg @ref LL_DMA_CHANNEL_10
5539 * @arg @ref LL_DMA_CHANNEL_11
5540 * @arg @ref LL_DMA_CHANNEL_12
5541 * @arg @ref LL_DMA_CHANNEL_13
5542 * @arg @ref LL_DMA_CHANNEL_14
5543 * @arg @ref LL_DMA_CHANNEL_15
5544 * @retval None.
5545 */
LL_DMA_EnableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)5546 __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
5547 {
5548 SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
5549 }
5550
5551 /**
5552 * @brief Disable the DMA channel secure attribute.
5553 * @note This API is used for all available DMA channels.
5554 * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure
5555 * @param DMAx DMAx Instance
5556 * @param Channel This parameter can be one of the following values:
5557 * @arg @ref LL_DMA_CHANNEL_0
5558 * @arg @ref LL_DMA_CHANNEL_1
5559 * @arg @ref LL_DMA_CHANNEL_2
5560 * @arg @ref LL_DMA_CHANNEL_3
5561 * @arg @ref LL_DMA_CHANNEL_4
5562 * @arg @ref LL_DMA_CHANNEL_5
5563 * @arg @ref LL_DMA_CHANNEL_6
5564 * @arg @ref LL_DMA_CHANNEL_7
5565 * @arg @ref LL_DMA_CHANNEL_8
5566 * @arg @ref LL_DMA_CHANNEL_9
5567 * @arg @ref LL_DMA_CHANNEL_10
5568 * @arg @ref LL_DMA_CHANNEL_11
5569 * @arg @ref LL_DMA_CHANNEL_12
5570 * @arg @ref LL_DMA_CHANNEL_13
5571 * @arg @ref LL_DMA_CHANNEL_14
5572 * @arg @ref LL_DMA_CHANNEL_15
5573 * @retval None.
5574 */
LL_DMA_DisableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)5575 __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
5576 {
5577 CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
5578 }
5579 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
5580
5581 /**
5582 * @brief Check if DMA channel secure is enabled.
5583 * @note This API is used for all available DMA channels.
5584 * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure
5585 * @param DMAx DMAx Instance
5586 * @param Channel This parameter can be one of the following values:
5587 * @arg @ref LL_DMA_CHANNEL_0
5588 * @arg @ref LL_DMA_CHANNEL_1
5589 * @arg @ref LL_DMA_CHANNEL_2
5590 * @arg @ref LL_DMA_CHANNEL_3
5591 * @arg @ref LL_DMA_CHANNEL_4
5592 * @arg @ref LL_DMA_CHANNEL_5
5593 * @arg @ref LL_DMA_CHANNEL_6
5594 * @arg @ref LL_DMA_CHANNEL_7
5595 * @arg @ref LL_DMA_CHANNEL_8
5596 * @arg @ref LL_DMA_CHANNEL_9
5597 * @arg @ref LL_DMA_CHANNEL_10
5598 * @arg @ref LL_DMA_CHANNEL_11
5599 * @arg @ref LL_DMA_CHANNEL_12
5600 * @arg @ref LL_DMA_CHANNEL_13
5601 * @arg @ref LL_DMA_CHANNEL_14
5602 * @arg @ref LL_DMA_CHANNEL_15
5603 * @retval State of bit (1 or 0).
5604 */
LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef * DMAx,uint32_t Channel)5605 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
5606 {
5607 return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
5608 == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5609 }
5610
5611 /**
5612 * @brief Enable the DMA channel privilege attribute.
5613 * @note This API is used for all available DMA channels.
5614 * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
5615 * @param DMAx DMAx Instance
5616 * @param Channel This parameter can be one of the following values:
5617 * @arg @ref LL_DMA_CHANNEL_0
5618 * @arg @ref LL_DMA_CHANNEL_1
5619 * @arg @ref LL_DMA_CHANNEL_2
5620 * @arg @ref LL_DMA_CHANNEL_3
5621 * @arg @ref LL_DMA_CHANNEL_4
5622 * @arg @ref LL_DMA_CHANNEL_5
5623 * @arg @ref LL_DMA_CHANNEL_6
5624 * @arg @ref LL_DMA_CHANNEL_7
5625 * @arg @ref LL_DMA_CHANNEL_8
5626 * @arg @ref LL_DMA_CHANNEL_9
5627 * @arg @ref LL_DMA_CHANNEL_10
5628 * @arg @ref LL_DMA_CHANNEL_11
5629 * @arg @ref LL_DMA_CHANNEL_12
5630 * @arg @ref LL_DMA_CHANNEL_13
5631 * @arg @ref LL_DMA_CHANNEL_14
5632 * @arg @ref LL_DMA_CHANNEL_15
5633 * @retval None.
5634 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)5635 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
5636 {
5637 SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
5638 }
5639
5640 /**
5641 * @brief Disable the DMA channel privilege attribute.
5642 * @note This API is used for all available DMA channels.
5643 * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
5644 * @param DMAx DMAx Instance
5645 * @param Channel This parameter can be one of the following values:
5646 * @arg @ref LL_DMA_CHANNEL_0
5647 * @arg @ref LL_DMA_CHANNEL_1
5648 * @arg @ref LL_DMA_CHANNEL_2
5649 * @arg @ref LL_DMA_CHANNEL_3
5650 * @arg @ref LL_DMA_CHANNEL_4
5651 * @arg @ref LL_DMA_CHANNEL_5
5652 * @arg @ref LL_DMA_CHANNEL_6
5653 * @arg @ref LL_DMA_CHANNEL_7
5654 * @arg @ref LL_DMA_CHANNEL_8
5655 * @arg @ref LL_DMA_CHANNEL_9
5656 * @arg @ref LL_DMA_CHANNEL_10
5657 * @arg @ref LL_DMA_CHANNEL_11
5658 * @arg @ref LL_DMA_CHANNEL_12
5659 * @arg @ref LL_DMA_CHANNEL_13
5660 * @arg @ref LL_DMA_CHANNEL_14
5661 * @arg @ref LL_DMA_CHANNEL_15
5662 * @retval None.
5663 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)5664 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
5665 {
5666 CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
5667 }
5668
5669 /**
5670 * @brief Check if DMA Channel privilege is enabled.
5671 * @note This API is used for all available DMA channels.
5672 * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege
5673 * @param DMAx DMAx Instance
5674 * @param Channel This parameter can be one of the following values:
5675 * @arg @ref LL_DMA_CHANNEL_0
5676 * @arg @ref LL_DMA_CHANNEL_1
5677 * @arg @ref LL_DMA_CHANNEL_2
5678 * @arg @ref LL_DMA_CHANNEL_3
5679 * @arg @ref LL_DMA_CHANNEL_4
5680 * @arg @ref LL_DMA_CHANNEL_5
5681 * @arg @ref LL_DMA_CHANNEL_6
5682 * @arg @ref LL_DMA_CHANNEL_7
5683 * @arg @ref LL_DMA_CHANNEL_8
5684 * @arg @ref LL_DMA_CHANNEL_9
5685 * @arg @ref LL_DMA_CHANNEL_10
5686 * @arg @ref LL_DMA_CHANNEL_11
5687 * @arg @ref LL_DMA_CHANNEL_12
5688 * @arg @ref LL_DMA_CHANNEL_13
5689 * @arg @ref LL_DMA_CHANNEL_14
5690 * @arg @ref LL_DMA_CHANNEL_15
5691 * @retval State of bit (1 or 0).
5692 */
LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef * DMAx,uint32_t Channel)5693 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel)
5694 {
5695 return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
5696 == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5697 }
5698
5699 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5700 /**
5701 * @brief Enable the DMA channel lock attributes.
5702 * @note This API is used for all available DMA channels.
5703 * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
5704 * @param DMAx DMAx Instance
5705 * @param Channel This parameter can be one of the following values:
5706 * @arg @ref LL_DMA_CHANNEL_0
5707 * @arg @ref LL_DMA_CHANNEL_1
5708 * @arg @ref LL_DMA_CHANNEL_2
5709 * @arg @ref LL_DMA_CHANNEL_3
5710 * @arg @ref LL_DMA_CHANNEL_4
5711 * @arg @ref LL_DMA_CHANNEL_5
5712 * @arg @ref LL_DMA_CHANNEL_6
5713 * @arg @ref LL_DMA_CHANNEL_7
5714 * @arg @ref LL_DMA_CHANNEL_8
5715 * @arg @ref LL_DMA_CHANNEL_9
5716 * @arg @ref LL_DMA_CHANNEL_10
5717 * @arg @ref LL_DMA_CHANNEL_11
5718 * @arg @ref LL_DMA_CHANNEL_12
5719 * @arg @ref LL_DMA_CHANNEL_13
5720 * @arg @ref LL_DMA_CHANNEL_14
5721 * @arg @ref LL_DMA_CHANNEL_15
5722 * @retval None.
5723 */
LL_DMA_EnableChannelLockAttribute(DMA_TypeDef * DMAx,uint32_t Channel)5724 __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
5725 {
5726 SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
5727 }
5728 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
5729
5730 /**
5731 * @brief Check if DMA channel attributes are locked.
5732 * @note This API is used for all available DMA channels.
5733 * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
5734 * @param DMAx DMAx Instance
5735 * @param Channel This parameter can be one of the following values:
5736 * @arg @ref LL_DMA_CHANNEL_0
5737 * @arg @ref LL_DMA_CHANNEL_1
5738 * @arg @ref LL_DMA_CHANNEL_2
5739 * @arg @ref LL_DMA_CHANNEL_3
5740 * @arg @ref LL_DMA_CHANNEL_4
5741 * @arg @ref LL_DMA_CHANNEL_5
5742 * @arg @ref LL_DMA_CHANNEL_6
5743 * @arg @ref LL_DMA_CHANNEL_7
5744 * @arg @ref LL_DMA_CHANNEL_8
5745 * @arg @ref LL_DMA_CHANNEL_9
5746 * @arg @ref LL_DMA_CHANNEL_10
5747 * @arg @ref LL_DMA_CHANNEL_11
5748 * @arg @ref LL_DMA_CHANNEL_12
5749 * @arg @ref LL_DMA_CHANNEL_13
5750 * @arg @ref LL_DMA_CHANNEL_14
5751 * @arg @ref LL_DMA_CHANNEL_15
5752 * @retval State of bit (1 or 0).
5753 */
LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef * DMAx,uint32_t Channel)5754 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel)
5755 {
5756 return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
5757 == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5758 }
5759
5760 /**
5761 * @}
5762 */
5763
5764 /** @defgroup DMA_LL_EF_FLAG_Management Flag Management
5765 * @{
5766 */
5767
5768 /**
5769 * @brief Clear trigger overrun flag.
5770 * @note This API is used for all available DMA channels.
5771 * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
5772 * @param DMAx DMAx Instance
5773 * @param Channel This parameter can be one of the following values:
5774 * @arg @ref LL_DMA_CHANNEL_0
5775 * @arg @ref LL_DMA_CHANNEL_1
5776 * @arg @ref LL_DMA_CHANNEL_2
5777 * @arg @ref LL_DMA_CHANNEL_3
5778 * @arg @ref LL_DMA_CHANNEL_4
5779 * @arg @ref LL_DMA_CHANNEL_5
5780 * @arg @ref LL_DMA_CHANNEL_6
5781 * @arg @ref LL_DMA_CHANNEL_7
5782 * @arg @ref LL_DMA_CHANNEL_8
5783 * @arg @ref LL_DMA_CHANNEL_9
5784 * @arg @ref LL_DMA_CHANNEL_10
5785 * @arg @ref LL_DMA_CHANNEL_11
5786 * @arg @ref LL_DMA_CHANNEL_12
5787 * @arg @ref LL_DMA_CHANNEL_13
5788 * @arg @ref LL_DMA_CHANNEL_14
5789 * @arg @ref LL_DMA_CHANNEL_15
5790 * @retval None.
5791 */
LL_DMA_ClearFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)5792 __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
5793 {
5794 uint32_t dma_base_addr = (uint32_t)DMAx;
5795 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
5796 }
5797
5798 /**
5799 * @brief Clear suspension flag.
5800 * @note This API is used for all available DMA channels.
5801 * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
5802 * @param DMAx DMAx Instance
5803 * @param Channel This parameter can be one of the following values:
5804 * @arg @ref LL_DMA_CHANNEL_0
5805 * @arg @ref LL_DMA_CHANNEL_1
5806 * @arg @ref LL_DMA_CHANNEL_2
5807 * @arg @ref LL_DMA_CHANNEL_3
5808 * @arg @ref LL_DMA_CHANNEL_4
5809 * @arg @ref LL_DMA_CHANNEL_5
5810 * @arg @ref LL_DMA_CHANNEL_6
5811 * @arg @ref LL_DMA_CHANNEL_7
5812 * @arg @ref LL_DMA_CHANNEL_8
5813 * @arg @ref LL_DMA_CHANNEL_9
5814 * @arg @ref LL_DMA_CHANNEL_10
5815 * @arg @ref LL_DMA_CHANNEL_11
5816 * @arg @ref LL_DMA_CHANNEL_12
5817 * @arg @ref LL_DMA_CHANNEL_13
5818 * @arg @ref LL_DMA_CHANNEL_14
5819 * @arg @ref LL_DMA_CHANNEL_15
5820 * @retval None.
5821 */
LL_DMA_ClearFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)5822 __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
5823 {
5824 uint32_t dma_base_addr = (uint32_t)DMAx;
5825 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
5826 }
5827
5828 /**
5829 * @brief Clear user setting error flag.
5830 * @note This API is used for all available DMA channels.
5831 * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
5832 * @param DMAx DMAx Instance
5833 * @param Channel This parameter can be one of the following values:
5834 * @arg @ref LL_DMA_CHANNEL_0
5835 * @arg @ref LL_DMA_CHANNEL_1
5836 * @arg @ref LL_DMA_CHANNEL_2
5837 * @arg @ref LL_DMA_CHANNEL_3
5838 * @arg @ref LL_DMA_CHANNEL_4
5839 * @arg @ref LL_DMA_CHANNEL_5
5840 * @arg @ref LL_DMA_CHANNEL_6
5841 * @arg @ref LL_DMA_CHANNEL_7
5842 * @arg @ref LL_DMA_CHANNEL_8
5843 * @arg @ref LL_DMA_CHANNEL_9
5844 * @arg @ref LL_DMA_CHANNEL_10
5845 * @arg @ref LL_DMA_CHANNEL_11
5846 * @arg @ref LL_DMA_CHANNEL_12
5847 * @arg @ref LL_DMA_CHANNEL_13
5848 * @arg @ref LL_DMA_CHANNEL_14
5849 * @arg @ref LL_DMA_CHANNEL_15
5850 * @retval None.
5851 */
LL_DMA_ClearFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)5852 __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
5853 {
5854 uint32_t dma_base_addr = (uint32_t)DMAx;
5855 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
5856 }
5857
5858 /**
5859 * @brief Clear link transfer error flag.
5860 * @note This API is used for all available DMA channels.
5861 * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
5862 * @param DMAx DMAx Instance
5863 * @param Channel This parameter can be one of the following values:
5864 * @arg @ref LL_DMA_CHANNEL_0
5865 * @arg @ref LL_DMA_CHANNEL_1
5866 * @arg @ref LL_DMA_CHANNEL_2
5867 * @arg @ref LL_DMA_CHANNEL_3
5868 * @arg @ref LL_DMA_CHANNEL_4
5869 * @arg @ref LL_DMA_CHANNEL_5
5870 * @arg @ref LL_DMA_CHANNEL_6
5871 * @arg @ref LL_DMA_CHANNEL_7
5872 * @arg @ref LL_DMA_CHANNEL_8
5873 * @arg @ref LL_DMA_CHANNEL_9
5874 * @arg @ref LL_DMA_CHANNEL_10
5875 * @arg @ref LL_DMA_CHANNEL_11
5876 * @arg @ref LL_DMA_CHANNEL_12
5877 * @arg @ref LL_DMA_CHANNEL_13
5878 * @arg @ref LL_DMA_CHANNEL_14
5879 * @arg @ref LL_DMA_CHANNEL_15
5880 * @retval None.
5881 */
LL_DMA_ClearFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)5882 __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
5883 {
5884 uint32_t dma_base_addr = (uint32_t)DMAx;
5885 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
5886 }
5887
5888 /**
5889 * @brief Clear data transfer error flag.
5890 * @note This API is used for all available DMA channels.
5891 * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
5892 * @param DMAx DMAx Instance
5893 * @param Channel This parameter can be one of the following values:
5894 * @arg @ref LL_DMA_CHANNEL_0
5895 * @arg @ref LL_DMA_CHANNEL_1
5896 * @arg @ref LL_DMA_CHANNEL_2
5897 * @arg @ref LL_DMA_CHANNEL_3
5898 * @arg @ref LL_DMA_CHANNEL_4
5899 * @arg @ref LL_DMA_CHANNEL_5
5900 * @arg @ref LL_DMA_CHANNEL_6
5901 * @arg @ref LL_DMA_CHANNEL_7
5902 * @arg @ref LL_DMA_CHANNEL_8
5903 * @arg @ref LL_DMA_CHANNEL_9
5904 * @arg @ref LL_DMA_CHANNEL_10
5905 * @arg @ref LL_DMA_CHANNEL_11
5906 * @arg @ref LL_DMA_CHANNEL_12
5907 * @arg @ref LL_DMA_CHANNEL_13
5908 * @arg @ref LL_DMA_CHANNEL_14
5909 * @arg @ref LL_DMA_CHANNEL_15
5910 * @retval None.
5911 */
LL_DMA_ClearFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)5912 __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
5913 {
5914 uint32_t dma_base_addr = (uint32_t)DMAx;
5915 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
5916 }
5917
5918 /**
5919 * @brief Clear half transfer flag.
5920 * @note This API is used for all available DMA channels.
5921 * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
5922 * @param DMAx DMAx Instance
5923 * @param Channel This parameter can be one of the following values:
5924 * @arg @ref LL_DMA_CHANNEL_0
5925 * @arg @ref LL_DMA_CHANNEL_1
5926 * @arg @ref LL_DMA_CHANNEL_2
5927 * @arg @ref LL_DMA_CHANNEL_3
5928 * @arg @ref LL_DMA_CHANNEL_4
5929 * @arg @ref LL_DMA_CHANNEL_5
5930 * @arg @ref LL_DMA_CHANNEL_6
5931 * @arg @ref LL_DMA_CHANNEL_7
5932 * @arg @ref LL_DMA_CHANNEL_8
5933 * @arg @ref LL_DMA_CHANNEL_9
5934 * @arg @ref LL_DMA_CHANNEL_10
5935 * @arg @ref LL_DMA_CHANNEL_11
5936 * @arg @ref LL_DMA_CHANNEL_12
5937 * @arg @ref LL_DMA_CHANNEL_13
5938 * @arg @ref LL_DMA_CHANNEL_14
5939 * @arg @ref LL_DMA_CHANNEL_15
5940 * @retval None.
5941 */
LL_DMA_ClearFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)5942 __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
5943 {
5944 uint32_t dma_base_addr = (uint32_t)DMAx;
5945 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
5946 }
5947
5948 /**
5949 * @brief Clear transfer complete flag.
5950 * @note This API is used for all available DMA channels.
5951 * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
5952 * @param DMAx DMAx Instance
5953 * @param Channel This parameter can be one of the following values:
5954 * @arg @ref LL_DMA_CHANNEL_0
5955 * @arg @ref LL_DMA_CHANNEL_1
5956 * @arg @ref LL_DMA_CHANNEL_2
5957 * @arg @ref LL_DMA_CHANNEL_3
5958 * @arg @ref LL_DMA_CHANNEL_4
5959 * @arg @ref LL_DMA_CHANNEL_5
5960 * @arg @ref LL_DMA_CHANNEL_6
5961 * @arg @ref LL_DMA_CHANNEL_7
5962 * @arg @ref LL_DMA_CHANNEL_8
5963 * @arg @ref LL_DMA_CHANNEL_9
5964 * @arg @ref LL_DMA_CHANNEL_10
5965 * @arg @ref LL_DMA_CHANNEL_11
5966 * @arg @ref LL_DMA_CHANNEL_12
5967 * @arg @ref LL_DMA_CHANNEL_13
5968 * @arg @ref LL_DMA_CHANNEL_14
5969 * @arg @ref LL_DMA_CHANNEL_15
5970 * @retval None.
5971 */
LL_DMA_ClearFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)5972 __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
5973 {
5974 uint32_t dma_base_addr = (uint32_t)DMAx;
5975 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
5976 }
5977
5978 /**
5979 * @brief Get trigger overrun flag.
5980 * @note This API is used for all available DMA channels.
5981 * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
5982 * @param DMAx DMAx Instance
5983 * @param Channel This parameter can be one of the following values:
5984 * @arg @ref LL_DMA_CHANNEL_0
5985 * @arg @ref LL_DMA_CHANNEL_1
5986 * @arg @ref LL_DMA_CHANNEL_2
5987 * @arg @ref LL_DMA_CHANNEL_3
5988 * @arg @ref LL_DMA_CHANNEL_4
5989 * @arg @ref LL_DMA_CHANNEL_5
5990 * @arg @ref LL_DMA_CHANNEL_6
5991 * @arg @ref LL_DMA_CHANNEL_7
5992 * @arg @ref LL_DMA_CHANNEL_8
5993 * @arg @ref LL_DMA_CHANNEL_9
5994 * @arg @ref LL_DMA_CHANNEL_10
5995 * @arg @ref LL_DMA_CHANNEL_11
5996 * @arg @ref LL_DMA_CHANNEL_12
5997 * @arg @ref LL_DMA_CHANNEL_13
5998 * @arg @ref LL_DMA_CHANNEL_14
5999 * @arg @ref LL_DMA_CHANNEL_15
6000 * @retval State of bit (1 or 0).
6001 */
LL_DMA_IsActiveFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6002 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6003 {
6004 uint32_t dma_base_addr = (uint32_t)DMAx;
6005 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
6006 == (DMA_CSR_TOF)) ? 1UL : 0UL);
6007 }
6008
6009 /**
6010 * @brief Get suspension flag.
6011 * @note This API is used for all available DMA channels.
6012 * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
6013 * @param DMAx DMAx Instance
6014 * @param Channel This parameter can be one of the following values:
6015 * @arg @ref LL_DMA_CHANNEL_0
6016 * @arg @ref LL_DMA_CHANNEL_1
6017 * @arg @ref LL_DMA_CHANNEL_2
6018 * @arg @ref LL_DMA_CHANNEL_3
6019 * @arg @ref LL_DMA_CHANNEL_4
6020 * @arg @ref LL_DMA_CHANNEL_5
6021 * @arg @ref LL_DMA_CHANNEL_6
6022 * @arg @ref LL_DMA_CHANNEL_7
6023 * @arg @ref LL_DMA_CHANNEL_8
6024 * @arg @ref LL_DMA_CHANNEL_9
6025 * @arg @ref LL_DMA_CHANNEL_10
6026 * @arg @ref LL_DMA_CHANNEL_11
6027 * @arg @ref LL_DMA_CHANNEL_12
6028 * @arg @ref LL_DMA_CHANNEL_13
6029 * @arg @ref LL_DMA_CHANNEL_14
6030 * @arg @ref LL_DMA_CHANNEL_15
6031 * @retval State of bit (1 or 0).
6032 */
LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6033 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6034 {
6035 uint32_t dma_base_addr = (uint32_t)DMAx;
6036 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
6037 == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
6038 }
6039
6040 /**
6041 * @brief Get user setting error flag.
6042 * @note This API is used for all available DMA channels.
6043 * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
6044 * @param DMAx DMAx Instance
6045 * @param Channel This parameter can be one of the following values:
6046 * @arg @ref LL_DMA_CHANNEL_0
6047 * @arg @ref LL_DMA_CHANNEL_1
6048 * @arg @ref LL_DMA_CHANNEL_2
6049 * @arg @ref LL_DMA_CHANNEL_3
6050 * @arg @ref LL_DMA_CHANNEL_4
6051 * @arg @ref LL_DMA_CHANNEL_5
6052 * @arg @ref LL_DMA_CHANNEL_6
6053 * @arg @ref LL_DMA_CHANNEL_7
6054 * @arg @ref LL_DMA_CHANNEL_8
6055 * @arg @ref LL_DMA_CHANNEL_9
6056 * @arg @ref LL_DMA_CHANNEL_10
6057 * @arg @ref LL_DMA_CHANNEL_11
6058 * @arg @ref LL_DMA_CHANNEL_12
6059 * @arg @ref LL_DMA_CHANNEL_13
6060 * @arg @ref LL_DMA_CHANNEL_14
6061 * @arg @ref LL_DMA_CHANNEL_15
6062 * @retval State of bit (1 or 0).
6063 */
LL_DMA_IsActiveFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6064 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6065 {
6066 uint32_t dma_base_addr = (uint32_t)DMAx;
6067 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
6068 == (DMA_CSR_USEF)) ? 1UL : 0UL);
6069 }
6070
6071 /**
6072 * @brief Get user setting error flag.
6073 * @note This API is used for all available DMA channels.
6074 * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
6075 * @param DMAx DMAx Instance
6076 * @param Channel This parameter can be one of the following values:
6077 * @arg @ref LL_DMA_CHANNEL_0
6078 * @arg @ref LL_DMA_CHANNEL_1
6079 * @arg @ref LL_DMA_CHANNEL_2
6080 * @arg @ref LL_DMA_CHANNEL_3
6081 * @arg @ref LL_DMA_CHANNEL_4
6082 * @arg @ref LL_DMA_CHANNEL_5
6083 * @arg @ref LL_DMA_CHANNEL_6
6084 * @arg @ref LL_DMA_CHANNEL_7
6085 * @arg @ref LL_DMA_CHANNEL_8
6086 * @arg @ref LL_DMA_CHANNEL_9
6087 * @arg @ref LL_DMA_CHANNEL_10
6088 * @arg @ref LL_DMA_CHANNEL_11
6089 * @arg @ref LL_DMA_CHANNEL_12
6090 * @arg @ref LL_DMA_CHANNEL_13
6091 * @arg @ref LL_DMA_CHANNEL_14
6092 * @arg @ref LL_DMA_CHANNEL_15
6093 * @retval State of bit (1 or 0).
6094 */
LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6095 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6096 {
6097 uint32_t dma_base_addr = (uint32_t)DMAx;
6098 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
6099 == (DMA_CSR_ULEF)) ? 1UL : 0UL);
6100 }
6101
6102 /**
6103 * @brief Get data transfer error flag.
6104 * @note This API is used for all available DMA channels.
6105 * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
6106 * @param DMAx DMAx Instance
6107 * @param Channel This parameter can be one of the following values:
6108 * @arg @ref LL_DMA_CHANNEL_0
6109 * @arg @ref LL_DMA_CHANNEL_1
6110 * @arg @ref LL_DMA_CHANNEL_2
6111 * @arg @ref LL_DMA_CHANNEL_3
6112 * @arg @ref LL_DMA_CHANNEL_4
6113 * @arg @ref LL_DMA_CHANNEL_5
6114 * @arg @ref LL_DMA_CHANNEL_6
6115 * @arg @ref LL_DMA_CHANNEL_7
6116 * @arg @ref LL_DMA_CHANNEL_8
6117 * @arg @ref LL_DMA_CHANNEL_9
6118 * @arg @ref LL_DMA_CHANNEL_10
6119 * @arg @ref LL_DMA_CHANNEL_11
6120 * @arg @ref LL_DMA_CHANNEL_12
6121 * @arg @ref LL_DMA_CHANNEL_13
6122 * @arg @ref LL_DMA_CHANNEL_14
6123 * @arg @ref LL_DMA_CHANNEL_15
6124 * @retval State of bit (1 or 0).
6125 */
LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6126 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6127 {
6128 uint32_t dma_base_addr = (uint32_t)DMAx;
6129 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
6130 == (DMA_CSR_DTEF)) ? 1UL : 0UL);
6131 }
6132
6133 /**
6134 * @brief Get half transfer flag.
6135 * @note This API is used for all available DMA channels.
6136 * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
6137 * @param DMAx DMAx Instance
6138 * @param Channel This parameter can be one of the following values:
6139 * @arg @ref LL_DMA_CHANNEL_0
6140 * @arg @ref LL_DMA_CHANNEL_1
6141 * @arg @ref LL_DMA_CHANNEL_2
6142 * @arg @ref LL_DMA_CHANNEL_3
6143 * @arg @ref LL_DMA_CHANNEL_4
6144 * @arg @ref LL_DMA_CHANNEL_5
6145 * @arg @ref LL_DMA_CHANNEL_6
6146 * @arg @ref LL_DMA_CHANNEL_7
6147 * @arg @ref LL_DMA_CHANNEL_8
6148 * @arg @ref LL_DMA_CHANNEL_9
6149 * @arg @ref LL_DMA_CHANNEL_10
6150 * @arg @ref LL_DMA_CHANNEL_11
6151 * @arg @ref LL_DMA_CHANNEL_12
6152 * @arg @ref LL_DMA_CHANNEL_13
6153 * @arg @ref LL_DMA_CHANNEL_14
6154 * @arg @ref LL_DMA_CHANNEL_15
6155 * @retval State of bit (1 or 0).
6156 */
LL_DMA_IsActiveFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6157 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6158 {
6159 uint32_t dma_base_addr = (uint32_t)DMAx;
6160 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
6161 == (DMA_CSR_HTF)) ? 1UL : 0UL);
6162 }
6163
6164 /**
6165 * @brief Get transfer complete flag.
6166 * @note This API is used for all available DMA channels.
6167 * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
6168 * @param DMAx DMAx Instance
6169 * @param Channel This parameter can be one of the following values:
6170 * @arg @ref LL_DMA_CHANNEL_0
6171 * @arg @ref LL_DMA_CHANNEL_1
6172 * @arg @ref LL_DMA_CHANNEL_2
6173 * @arg @ref LL_DMA_CHANNEL_3
6174 * @arg @ref LL_DMA_CHANNEL_4
6175 * @arg @ref LL_DMA_CHANNEL_5
6176 * @arg @ref LL_DMA_CHANNEL_6
6177 * @arg @ref LL_DMA_CHANNEL_7
6178 * @arg @ref LL_DMA_CHANNEL_8
6179 * @arg @ref LL_DMA_CHANNEL_9
6180 * @arg @ref LL_DMA_CHANNEL_10
6181 * @arg @ref LL_DMA_CHANNEL_11
6182 * @arg @ref LL_DMA_CHANNEL_12
6183 * @arg @ref LL_DMA_CHANNEL_13
6184 * @arg @ref LL_DMA_CHANNEL_14
6185 * @arg @ref LL_DMA_CHANNEL_15
6186 * @retval State of bit (1 or 0).
6187 */
LL_DMA_IsActiveFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6188 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6189 {
6190 uint32_t dma_base_addr = (uint32_t)DMAx;
6191 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
6192 == (DMA_CSR_TCF)) ? 1UL : 0UL);
6193 }
6194
6195 /**
6196 * @brief Get idle flag.
6197 * @note This API is used for all available DMA channels.
6198 * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
6199 * @param DMAx DMAx Instance
6200 * @param Channel This parameter can be one of the following values:
6201 * @arg @ref LL_DMA_CHANNEL_0
6202 * @arg @ref LL_DMA_CHANNEL_1
6203 * @arg @ref LL_DMA_CHANNEL_2
6204 * @arg @ref LL_DMA_CHANNEL_3
6205 * @arg @ref LL_DMA_CHANNEL_4
6206 * @arg @ref LL_DMA_CHANNEL_5
6207 * @arg @ref LL_DMA_CHANNEL_6
6208 * @arg @ref LL_DMA_CHANNEL_7
6209 * @arg @ref LL_DMA_CHANNEL_8
6210 * @arg @ref LL_DMA_CHANNEL_9
6211 * @arg @ref LL_DMA_CHANNEL_10
6212 * @arg @ref LL_DMA_CHANNEL_11
6213 * @arg @ref LL_DMA_CHANNEL_12
6214 * @arg @ref LL_DMA_CHANNEL_13
6215 * @arg @ref LL_DMA_CHANNEL_14
6216 * @arg @ref LL_DMA_CHANNEL_15
6217 * @retval State of bit (1 or 0).
6218 */
LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef * DMAx,uint32_t Channel)6219 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel)
6220 {
6221 uint32_t dma_base_addr = (uint32_t)DMAx;
6222 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
6223 == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
6224 }
6225
6226 /**
6227 * @brief Check if nsecure masked interrupt is active.
6228 * @note This API is used for all available DMA channels.
6229 * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS
6230 * @param DMAx DMAx Instance
6231 * @param Channel This parameter can be one of the following values:
6232 * @arg @ref LL_DMA_CHANNEL_0
6233 * @arg @ref LL_DMA_CHANNEL_1
6234 * @arg @ref LL_DMA_CHANNEL_2
6235 * @arg @ref LL_DMA_CHANNEL_3
6236 * @arg @ref LL_DMA_CHANNEL_4
6237 * @arg @ref LL_DMA_CHANNEL_5
6238 * @arg @ref LL_DMA_CHANNEL_6
6239 * @arg @ref LL_DMA_CHANNEL_7
6240 * @arg @ref LL_DMA_CHANNEL_8
6241 * @arg @ref LL_DMA_CHANNEL_9
6242 * @arg @ref LL_DMA_CHANNEL_10
6243 * @arg @ref LL_DMA_CHANNEL_11
6244 * @arg @ref LL_DMA_CHANNEL_12
6245 * @arg @ref LL_DMA_CHANNEL_13
6246 * @arg @ref LL_DMA_CHANNEL_14
6247 * @arg @ref LL_DMA_CHANNEL_15
6248 * @retval State of bit (1 or 0).
6249 */
LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef * DMAx,uint32_t Channel)6250 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel)
6251 {
6252 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
6253 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
6254 }
6255
6256 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
6257 /**
6258 * @brief Check if secure masked interrupt is active.
6259 * @note This API is used for all available DMA channels.
6260 * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS
6261 * @param DMAx DMAx Instance
6262 * @param Channel This parameter can be one of the following values:
6263 * @arg @ref LL_DMA_CHANNEL_0
6264 * @arg @ref LL_DMA_CHANNEL_1
6265 * @arg @ref LL_DMA_CHANNEL_2
6266 * @arg @ref LL_DMA_CHANNEL_3
6267 * @arg @ref LL_DMA_CHANNEL_4
6268 * @arg @ref LL_DMA_CHANNEL_5
6269 * @arg @ref LL_DMA_CHANNEL_6
6270 * @arg @ref LL_DMA_CHANNEL_7
6271 * @arg @ref LL_DMA_CHANNEL_8
6272 * @arg @ref LL_DMA_CHANNEL_9
6273 * @arg @ref LL_DMA_CHANNEL_10
6274 * @arg @ref LL_DMA_CHANNEL_11
6275 * @arg @ref LL_DMA_CHANNEL_12
6276 * @arg @ref LL_DMA_CHANNEL_13
6277 * @arg @ref LL_DMA_CHANNEL_14
6278 * @arg @ref LL_DMA_CHANNEL_15
6279 * @retval State of bit (1 or 0).
6280 */
LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef * DMAx,uint32_t Channel)6281 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel)
6282 {
6283 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
6284 == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
6285 }
6286 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
6287 /**
6288 * @}
6289 */
6290
6291 /** @defgroup DMA_LL_EF_IT_Management Interrupt Management
6292 * @{
6293 */
6294
6295 /**
6296 * @brief Enable trigger overrun interrupt.
6297 * @note This API is used for all available DMA channels.
6298 * @rmtoll CCR TOIE LL_DMA_EnableIT_TO
6299 * @param DMAx DMAx Instance
6300 * @param Channel This parameter can be one of the following values:
6301 * @arg @ref LL_DMA_CHANNEL_0
6302 * @arg @ref LL_DMA_CHANNEL_1
6303 * @arg @ref LL_DMA_CHANNEL_2
6304 * @arg @ref LL_DMA_CHANNEL_3
6305 * @arg @ref LL_DMA_CHANNEL_4
6306 * @arg @ref LL_DMA_CHANNEL_5
6307 * @arg @ref LL_DMA_CHANNEL_6
6308 * @arg @ref LL_DMA_CHANNEL_7
6309 * @arg @ref LL_DMA_CHANNEL_8
6310 * @arg @ref LL_DMA_CHANNEL_9
6311 * @arg @ref LL_DMA_CHANNEL_10
6312 * @arg @ref LL_DMA_CHANNEL_11
6313 * @arg @ref LL_DMA_CHANNEL_12
6314 * @arg @ref LL_DMA_CHANNEL_13
6315 * @arg @ref LL_DMA_CHANNEL_14
6316 * @arg @ref LL_DMA_CHANNEL_15
6317 * @retval None.
6318 */
LL_DMA_EnableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6319 __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6320 {
6321 uint32_t dma_base_addr = (uint32_t)DMAx;
6322 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
6323 }
6324
6325 /**
6326 * @brief Enable suspension interrupt.
6327 * @note This API is used for all available DMA channels.
6328 * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
6329 * @param DMAx DMAx Instance
6330 * @param Channel This parameter can be one of the following values:
6331 * @arg @ref LL_DMA_CHANNEL_0
6332 * @arg @ref LL_DMA_CHANNEL_1
6333 * @arg @ref LL_DMA_CHANNEL_2
6334 * @arg @ref LL_DMA_CHANNEL_3
6335 * @arg @ref LL_DMA_CHANNEL_4
6336 * @arg @ref LL_DMA_CHANNEL_5
6337 * @arg @ref LL_DMA_CHANNEL_6
6338 * @arg @ref LL_DMA_CHANNEL_7
6339 * @arg @ref LL_DMA_CHANNEL_8
6340 * @arg @ref LL_DMA_CHANNEL_9
6341 * @arg @ref LL_DMA_CHANNEL_10
6342 * @arg @ref LL_DMA_CHANNEL_11
6343 * @arg @ref LL_DMA_CHANNEL_12
6344 * @arg @ref LL_DMA_CHANNEL_13
6345 * @arg @ref LL_DMA_CHANNEL_14
6346 * @arg @ref LL_DMA_CHANNEL_15
6347 * @retval None.
6348 */
LL_DMA_EnableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6349 __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6350 {
6351 uint32_t dma_base_addr = (uint32_t)DMAx;
6352 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
6353 }
6354
6355 /**
6356 * @brief Enable user setting error interrupt.
6357 * @note This API is used for all available DMA channels.
6358 * @rmtoll CCR USEIE LL_DMA_EnableIT_USE
6359 * @param DMAx DMAx Instance
6360 * @param Channel This parameter can be one of the following values:
6361 * @arg @ref LL_DMA_CHANNEL_0
6362 * @arg @ref LL_DMA_CHANNEL_1
6363 * @arg @ref LL_DMA_CHANNEL_2
6364 * @arg @ref LL_DMA_CHANNEL_3
6365 * @arg @ref LL_DMA_CHANNEL_4
6366 * @arg @ref LL_DMA_CHANNEL_5
6367 * @arg @ref LL_DMA_CHANNEL_6
6368 * @arg @ref LL_DMA_CHANNEL_7
6369 * @arg @ref LL_DMA_CHANNEL_8
6370 * @arg @ref LL_DMA_CHANNEL_9
6371 * @arg @ref LL_DMA_CHANNEL_10
6372 * @arg @ref LL_DMA_CHANNEL_11
6373 * @arg @ref LL_DMA_CHANNEL_12
6374 * @arg @ref LL_DMA_CHANNEL_13
6375 * @arg @ref LL_DMA_CHANNEL_14
6376 * @arg @ref LL_DMA_CHANNEL_15
6377 * @retval None.
6378 */
LL_DMA_EnableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6379 __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6380 {
6381 uint32_t dma_base_addr = (uint32_t)DMAx;
6382 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
6383 }
6384
6385 /**
6386 * @brief Enable update link transfer error interrupt.
6387 * @note This API is used for all available DMA channels.
6388 * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
6389 * @param DMAx DMAx Instance
6390 * @param Channel This parameter can be one of the following values:
6391 * @arg @ref LL_DMA_CHANNEL_0
6392 * @arg @ref LL_DMA_CHANNEL_1
6393 * @arg @ref LL_DMA_CHANNEL_2
6394 * @arg @ref LL_DMA_CHANNEL_3
6395 * @arg @ref LL_DMA_CHANNEL_4
6396 * @arg @ref LL_DMA_CHANNEL_5
6397 * @arg @ref LL_DMA_CHANNEL_6
6398 * @arg @ref LL_DMA_CHANNEL_7
6399 * @arg @ref LL_DMA_CHANNEL_8
6400 * @arg @ref LL_DMA_CHANNEL_9
6401 * @arg @ref LL_DMA_CHANNEL_10
6402 * @arg @ref LL_DMA_CHANNEL_11
6403 * @arg @ref LL_DMA_CHANNEL_12
6404 * @arg @ref LL_DMA_CHANNEL_13
6405 * @arg @ref LL_DMA_CHANNEL_14
6406 * @arg @ref LL_DMA_CHANNEL_15
6407 * @retval None.
6408 */
LL_DMA_EnableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6409 __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6410 {
6411 uint32_t dma_base_addr = (uint32_t)DMAx;
6412 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
6413 }
6414
6415 /**
6416 * @brief Enable data transfer error interrupt.
6417 * @note This API is used for all available DMA channels.
6418 * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
6419 * @param DMAx DMAx Instance
6420 * @param Channel This parameter can be one of the following values:
6421 * @arg @ref LL_DMA_CHANNEL_0
6422 * @arg @ref LL_DMA_CHANNEL_1
6423 * @arg @ref LL_DMA_CHANNEL_2
6424 * @arg @ref LL_DMA_CHANNEL_3
6425 * @arg @ref LL_DMA_CHANNEL_4
6426 * @arg @ref LL_DMA_CHANNEL_5
6427 * @arg @ref LL_DMA_CHANNEL_6
6428 * @arg @ref LL_DMA_CHANNEL_7
6429 * @arg @ref LL_DMA_CHANNEL_8
6430 * @arg @ref LL_DMA_CHANNEL_9
6431 * @arg @ref LL_DMA_CHANNEL_10
6432 * @arg @ref LL_DMA_CHANNEL_11
6433 * @arg @ref LL_DMA_CHANNEL_12
6434 * @arg @ref LL_DMA_CHANNEL_13
6435 * @arg @ref LL_DMA_CHANNEL_14
6436 * @arg @ref LL_DMA_CHANNEL_15
6437 * @retval None.
6438 */
LL_DMA_EnableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6439 __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6440 {
6441 uint32_t dma_base_addr = (uint32_t)DMAx;
6442 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
6443 }
6444
6445 /**
6446 * @brief Enable half transfer complete interrupt.
6447 * @note This API is used for all available DMA channels.
6448 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
6449 * @param DMAx DMAx Instance
6450 * @param Channel This parameter can be one of the following values:
6451 * @arg @ref LL_DMA_CHANNEL_0
6452 * @arg @ref LL_DMA_CHANNEL_1
6453 * @arg @ref LL_DMA_CHANNEL_2
6454 * @arg @ref LL_DMA_CHANNEL_3
6455 * @arg @ref LL_DMA_CHANNEL_4
6456 * @arg @ref LL_DMA_CHANNEL_5
6457 * @arg @ref LL_DMA_CHANNEL_6
6458 * @arg @ref LL_DMA_CHANNEL_7
6459 * @arg @ref LL_DMA_CHANNEL_8
6460 * @arg @ref LL_DMA_CHANNEL_9
6461 * @arg @ref LL_DMA_CHANNEL_10
6462 * @arg @ref LL_DMA_CHANNEL_11
6463 * @arg @ref LL_DMA_CHANNEL_12
6464 * @arg @ref LL_DMA_CHANNEL_13
6465 * @arg @ref LL_DMA_CHANNEL_14
6466 * @arg @ref LL_DMA_CHANNEL_15
6467 * @retval None.
6468 */
LL_DMA_EnableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6469 __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6470 {
6471 uint32_t dma_base_addr = (uint32_t)DMAx;
6472 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
6473 }
6474
6475 /**
6476 * @brief Enable transfer complete interrupt.
6477 * @note This API is used for all available DMA channels.
6478 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
6479 * @param DMAx DMAx Instance
6480 * @param Channel This parameter can be one of the following values:
6481 * @arg @ref LL_DMA_CHANNEL_0
6482 * @arg @ref LL_DMA_CHANNEL_1
6483 * @arg @ref LL_DMA_CHANNEL_2
6484 * @arg @ref LL_DMA_CHANNEL_3
6485 * @arg @ref LL_DMA_CHANNEL_4
6486 * @arg @ref LL_DMA_CHANNEL_5
6487 * @arg @ref LL_DMA_CHANNEL_6
6488 * @arg @ref LL_DMA_CHANNEL_7
6489 * @arg @ref LL_DMA_CHANNEL_8
6490 * @arg @ref LL_DMA_CHANNEL_9
6491 * @arg @ref LL_DMA_CHANNEL_10
6492 * @arg @ref LL_DMA_CHANNEL_11
6493 * @arg @ref LL_DMA_CHANNEL_12
6494 * @arg @ref LL_DMA_CHANNEL_13
6495 * @arg @ref LL_DMA_CHANNEL_14
6496 * @arg @ref LL_DMA_CHANNEL_15
6497 * @retval None.
6498 */
LL_DMA_EnableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6499 __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6500 {
6501 uint32_t dma_base_addr = (uint32_t)DMAx;
6502 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
6503 }
6504
6505 /**
6506 * @brief Disable trigger overrun interrupt.
6507 * @note This API is used for all available DMA channels.
6508 * @rmtoll CCR TOIE LL_DMA_DisableIT_TO
6509 * @param DMAx DMAx Instance
6510 * @param Channel This parameter can be one of the following values:
6511 * @arg @ref LL_DMA_CHANNEL_0
6512 * @arg @ref LL_DMA_CHANNEL_1
6513 * @arg @ref LL_DMA_CHANNEL_2
6514 * @arg @ref LL_DMA_CHANNEL_3
6515 * @arg @ref LL_DMA_CHANNEL_4
6516 * @arg @ref LL_DMA_CHANNEL_5
6517 * @arg @ref LL_DMA_CHANNEL_6
6518 * @arg @ref LL_DMA_CHANNEL_7
6519 * @arg @ref LL_DMA_CHANNEL_8
6520 * @arg @ref LL_DMA_CHANNEL_9
6521 * @arg @ref LL_DMA_CHANNEL_10
6522 * @arg @ref LL_DMA_CHANNEL_11
6523 * @arg @ref LL_DMA_CHANNEL_12
6524 * @arg @ref LL_DMA_CHANNEL_13
6525 * @arg @ref LL_DMA_CHANNEL_14
6526 * @arg @ref LL_DMA_CHANNEL_15
6527 * @retval None.
6528 */
LL_DMA_DisableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6529 __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6530 {
6531 uint32_t dma_base_addr = (uint32_t)DMAx;
6532 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
6533 }
6534
6535 /**
6536 * @brief Disable suspension interrupt.
6537 * @note This API is used for all available DMA channels.
6538 * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
6539 * @param DMAx DMAx Instance
6540 * @param Channel This parameter can be one of the following values:
6541 * @arg @ref LL_DMA_CHANNEL_0
6542 * @arg @ref LL_DMA_CHANNEL_1
6543 * @arg @ref LL_DMA_CHANNEL_2
6544 * @arg @ref LL_DMA_CHANNEL_3
6545 * @arg @ref LL_DMA_CHANNEL_4
6546 * @arg @ref LL_DMA_CHANNEL_5
6547 * @arg @ref LL_DMA_CHANNEL_6
6548 * @arg @ref LL_DMA_CHANNEL_7
6549 * @arg @ref LL_DMA_CHANNEL_8
6550 * @arg @ref LL_DMA_CHANNEL_9
6551 * @arg @ref LL_DMA_CHANNEL_10
6552 * @arg @ref LL_DMA_CHANNEL_11
6553 * @arg @ref LL_DMA_CHANNEL_12
6554 * @arg @ref LL_DMA_CHANNEL_13
6555 * @arg @ref LL_DMA_CHANNEL_14
6556 * @arg @ref LL_DMA_CHANNEL_15
6557 * @retval None.
6558 */
LL_DMA_DisableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6559 __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6560 {
6561 uint32_t dma_base_addr = (uint32_t)DMAx;
6562 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
6563 }
6564
6565 /**
6566 * @brief Disable user setting error interrupt.
6567 * @note This API is used for all available DMA channels.
6568 * @rmtoll CCR USEIE LL_DMA_DisableIT_USE
6569 * @param DMAx DMAx Instance
6570 * @param Channel This parameter can be one of the following values:
6571 * @arg @ref LL_DMA_CHANNEL_0
6572 * @arg @ref LL_DMA_CHANNEL_1
6573 * @arg @ref LL_DMA_CHANNEL_2
6574 * @arg @ref LL_DMA_CHANNEL_3
6575 * @arg @ref LL_DMA_CHANNEL_4
6576 * @arg @ref LL_DMA_CHANNEL_5
6577 * @arg @ref LL_DMA_CHANNEL_6
6578 * @arg @ref LL_DMA_CHANNEL_7
6579 * @arg @ref LL_DMA_CHANNEL_8
6580 * @arg @ref LL_DMA_CHANNEL_9
6581 * @arg @ref LL_DMA_CHANNEL_10
6582 * @arg @ref LL_DMA_CHANNEL_11
6583 * @arg @ref LL_DMA_CHANNEL_12
6584 * @arg @ref LL_DMA_CHANNEL_13
6585 * @arg @ref LL_DMA_CHANNEL_14
6586 * @arg @ref LL_DMA_CHANNEL_15
6587 * @retval None.
6588 */
LL_DMA_DisableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6589 __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6590 {
6591 uint32_t dma_base_addr = (uint32_t)DMAx;
6592 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
6593 }
6594
6595 /**
6596 * @brief Disable update link transfer error interrupt.
6597 * @note This API is used for all available DMA channels.
6598 * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
6599 * @param DMAx DMAx Instance
6600 * @param Channel This parameter can be one of the following values:
6601 * @arg @ref LL_DMA_CHANNEL_0
6602 * @arg @ref LL_DMA_CHANNEL_1
6603 * @arg @ref LL_DMA_CHANNEL_2
6604 * @arg @ref LL_DMA_CHANNEL_3
6605 * @arg @ref LL_DMA_CHANNEL_4
6606 * @arg @ref LL_DMA_CHANNEL_5
6607 * @arg @ref LL_DMA_CHANNEL_6
6608 * @arg @ref LL_DMA_CHANNEL_7
6609 * @arg @ref LL_DMA_CHANNEL_8
6610 * @arg @ref LL_DMA_CHANNEL_9
6611 * @arg @ref LL_DMA_CHANNEL_10
6612 * @arg @ref LL_DMA_CHANNEL_11
6613 * @arg @ref LL_DMA_CHANNEL_12
6614 * @arg @ref LL_DMA_CHANNEL_13
6615 * @arg @ref LL_DMA_CHANNEL_14
6616 * @arg @ref LL_DMA_CHANNEL_15
6617 * @retval None.
6618 */
LL_DMA_DisableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6619 __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6620 {
6621 uint32_t dma_base_addr = (uint32_t)DMAx;
6622 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
6623 }
6624
6625 /**
6626 * @brief Disable data transfer error interrupt.
6627 * @note This API is used for all available DMA channels.
6628 * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
6629 * @param DMAx DMAx Instance
6630 * @param Channel This parameter can be one of the following values:
6631 * @arg @ref LL_DMA_CHANNEL_0
6632 * @arg @ref LL_DMA_CHANNEL_1
6633 * @arg @ref LL_DMA_CHANNEL_2
6634 * @arg @ref LL_DMA_CHANNEL_3
6635 * @arg @ref LL_DMA_CHANNEL_4
6636 * @arg @ref LL_DMA_CHANNEL_5
6637 * @arg @ref LL_DMA_CHANNEL_6
6638 * @arg @ref LL_DMA_CHANNEL_7
6639 * @arg @ref LL_DMA_CHANNEL_8
6640 * @arg @ref LL_DMA_CHANNEL_9
6641 * @arg @ref LL_DMA_CHANNEL_10
6642 * @arg @ref LL_DMA_CHANNEL_11
6643 * @arg @ref LL_DMA_CHANNEL_12
6644 * @arg @ref LL_DMA_CHANNEL_13
6645 * @arg @ref LL_DMA_CHANNEL_14
6646 * @arg @ref LL_DMA_CHANNEL_15
6647 * @retval None.
6648 */
LL_DMA_DisableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6649 __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6650 {
6651 uint32_t dma_base_addr = (uint32_t)DMAx;
6652 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
6653 }
6654
6655 /**
6656 * @brief Disable half transfer complete interrupt.
6657 * @note This API is used for all available DMA channels.
6658 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
6659 * @param DMAx DMAx Instance
6660 * @param Channel This parameter can be one of the following values:
6661 * @arg @ref LL_DMA_CHANNEL_0
6662 * @arg @ref LL_DMA_CHANNEL_1
6663 * @arg @ref LL_DMA_CHANNEL_2
6664 * @arg @ref LL_DMA_CHANNEL_3
6665 * @arg @ref LL_DMA_CHANNEL_4
6666 * @arg @ref LL_DMA_CHANNEL_5
6667 * @arg @ref LL_DMA_CHANNEL_6
6668 * @arg @ref LL_DMA_CHANNEL_7
6669 * @arg @ref LL_DMA_CHANNEL_8
6670 * @arg @ref LL_DMA_CHANNEL_9
6671 * @arg @ref LL_DMA_CHANNEL_10
6672 * @arg @ref LL_DMA_CHANNEL_11
6673 * @arg @ref LL_DMA_CHANNEL_12
6674 * @arg @ref LL_DMA_CHANNEL_13
6675 * @arg @ref LL_DMA_CHANNEL_14
6676 * @arg @ref LL_DMA_CHANNEL_15
6677 * @retval None.
6678 */
LL_DMA_DisableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6679 __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6680 {
6681 uint32_t dma_base_addr = (uint32_t)DMAx;
6682 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
6683 }
6684
6685 /**
6686 * @brief Disable transfer complete interrupt.
6687 * @note This API is used for all available DMA channels.
6688 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
6689 * @param DMAx DMAx Instance
6690 * @param Channel This parameter can be one of the following values:
6691 * @arg @ref LL_DMA_CHANNEL_0
6692 * @arg @ref LL_DMA_CHANNEL_1
6693 * @arg @ref LL_DMA_CHANNEL_2
6694 * @arg @ref LL_DMA_CHANNEL_3
6695 * @arg @ref LL_DMA_CHANNEL_4
6696 * @arg @ref LL_DMA_CHANNEL_5
6697 * @arg @ref LL_DMA_CHANNEL_6
6698 * @arg @ref LL_DMA_CHANNEL_7
6699 * @arg @ref LL_DMA_CHANNEL_8
6700 * @arg @ref LL_DMA_CHANNEL_9
6701 * @arg @ref LL_DMA_CHANNEL_10
6702 * @arg @ref LL_DMA_CHANNEL_11
6703 * @arg @ref LL_DMA_CHANNEL_12
6704 * @arg @ref LL_DMA_CHANNEL_13
6705 * @arg @ref LL_DMA_CHANNEL_14
6706 * @arg @ref LL_DMA_CHANNEL_15
6707 * @retval None.
6708 */
LL_DMA_DisableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6709 __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6710 {
6711 uint32_t dma_base_addr = (uint32_t)DMAx;
6712 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
6713 }
6714
6715 /**
6716 * @brief Check if trigger overrun interrupt is enabled.
6717 * @note This API is used for all available DMA channels.
6718 * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
6719 * @param DMAx DMAx Instance
6720 * @param Channel This parameter can be one of the following values:
6721 * @arg @ref LL_DMA_CHANNEL_0
6722 * @arg @ref LL_DMA_CHANNEL_1
6723 * @arg @ref LL_DMA_CHANNEL_2
6724 * @arg @ref LL_DMA_CHANNEL_3
6725 * @arg @ref LL_DMA_CHANNEL_4
6726 * @arg @ref LL_DMA_CHANNEL_5
6727 * @arg @ref LL_DMA_CHANNEL_6
6728 * @arg @ref LL_DMA_CHANNEL_7
6729 * @arg @ref LL_DMA_CHANNEL_8
6730 * @arg @ref LL_DMA_CHANNEL_9
6731 * @arg @ref LL_DMA_CHANNEL_10
6732 * @arg @ref LL_DMA_CHANNEL_11
6733 * @arg @ref LL_DMA_CHANNEL_12
6734 * @arg @ref LL_DMA_CHANNEL_13
6735 * @arg @ref LL_DMA_CHANNEL_14
6736 * @arg @ref LL_DMA_CHANNEL_15
6737 * @retval State of bit (1 or 0).
6738 */
LL_DMA_IsEnabledIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6739 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6740 {
6741 uint32_t dma_base_addr = (uint32_t)DMAx;
6742 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
6743 == DMA_CCR_TOIE) ? 1UL : 0UL);
6744 }
6745
6746 /**
6747 * @brief Check if suspension interrupt is enabled.
6748 * @note This API is used for all available DMA channels.
6749 * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
6750 * @param DMAx DMAx Instance
6751 * @param Channel This parameter can be one of the following values:
6752 * @arg @ref LL_DMA_CHANNEL_0
6753 * @arg @ref LL_DMA_CHANNEL_1
6754 * @arg @ref LL_DMA_CHANNEL_2
6755 * @arg @ref LL_DMA_CHANNEL_3
6756 * @arg @ref LL_DMA_CHANNEL_4
6757 * @arg @ref LL_DMA_CHANNEL_5
6758 * @arg @ref LL_DMA_CHANNEL_6
6759 * @arg @ref LL_DMA_CHANNEL_7
6760 * @arg @ref LL_DMA_CHANNEL_8
6761 * @arg @ref LL_DMA_CHANNEL_9
6762 * @arg @ref LL_DMA_CHANNEL_10
6763 * @arg @ref LL_DMA_CHANNEL_11
6764 * @arg @ref LL_DMA_CHANNEL_12
6765 * @arg @ref LL_DMA_CHANNEL_13
6766 * @arg @ref LL_DMA_CHANNEL_14
6767 * @arg @ref LL_DMA_CHANNEL_15
6768 * @retval State of bit (1 or 0).
6769 */
LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6770 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6771 {
6772 uint32_t dma_base_addr = (uint32_t)DMAx;
6773 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
6774 == DMA_CCR_SUSPIE) ? 1UL : 0UL);
6775 }
6776
6777 /**
6778 * @brief Check if user setting error interrupt is enabled.
6779 * @note This API is used for all available DMA channels.
6780 * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
6781 * @param DMAx DMAx Instance
6782 * @param Channel This parameter can be one of the following values:
6783 * @arg @ref LL_DMA_CHANNEL_0
6784 * @arg @ref LL_DMA_CHANNEL_1
6785 * @arg @ref LL_DMA_CHANNEL_2
6786 * @arg @ref LL_DMA_CHANNEL_3
6787 * @arg @ref LL_DMA_CHANNEL_4
6788 * @arg @ref LL_DMA_CHANNEL_5
6789 * @arg @ref LL_DMA_CHANNEL_6
6790 * @arg @ref LL_DMA_CHANNEL_7
6791 * @arg @ref LL_DMA_CHANNEL_8
6792 * @arg @ref LL_DMA_CHANNEL_9
6793 * @arg @ref LL_DMA_CHANNEL_10
6794 * @arg @ref LL_DMA_CHANNEL_11
6795 * @arg @ref LL_DMA_CHANNEL_12
6796 * @arg @ref LL_DMA_CHANNEL_13
6797 * @arg @ref LL_DMA_CHANNEL_14
6798 * @arg @ref LL_DMA_CHANNEL_15
6799 * @retval State of bit (1 or 0).
6800 */
LL_DMA_IsEnabledIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6801 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6802 {
6803 uint32_t dma_base_addr = (uint32_t)DMAx;
6804 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
6805 == DMA_CCR_USEIE) ? 1UL : 0UL);
6806 }
6807
6808 /**
6809 * @brief Check if update link transfer error interrupt is enabled.
6810 * @note This API is used for all available DMA channels.
6811 * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
6812 * @param DMAx DMAx Instance
6813 * @param Channel This parameter can be one of the following values:
6814 * @arg @ref LL_DMA_CHANNEL_0
6815 * @arg @ref LL_DMA_CHANNEL_1
6816 * @arg @ref LL_DMA_CHANNEL_2
6817 * @arg @ref LL_DMA_CHANNEL_3
6818 * @arg @ref LL_DMA_CHANNEL_4
6819 * @arg @ref LL_DMA_CHANNEL_5
6820 * @arg @ref LL_DMA_CHANNEL_6
6821 * @arg @ref LL_DMA_CHANNEL_7
6822 * @arg @ref LL_DMA_CHANNEL_8
6823 * @arg @ref LL_DMA_CHANNEL_9
6824 * @arg @ref LL_DMA_CHANNEL_10
6825 * @arg @ref LL_DMA_CHANNEL_11
6826 * @arg @ref LL_DMA_CHANNEL_12
6827 * @arg @ref LL_DMA_CHANNEL_13
6828 * @arg @ref LL_DMA_CHANNEL_14
6829 * @arg @ref LL_DMA_CHANNEL_15
6830 * @retval State of bit (1 or 0).
6831 */
LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6832 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6833 {
6834 uint32_t dma_base_addr = (uint32_t)DMAx;
6835 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
6836 == DMA_CCR_ULEIE) ? 1UL : 0UL);
6837 }
6838
6839 /**
6840 * @brief Check if data transfer error interrupt is enabled.
6841 * @note This API is used for all available DMA channels.
6842 * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
6843 * @param DMAx DMAx Instance
6844 * @param Channel This parameter can be one of the following values:
6845 * @arg @ref LL_DMA_CHANNEL_0
6846 * @arg @ref LL_DMA_CHANNEL_1
6847 * @arg @ref LL_DMA_CHANNEL_2
6848 * @arg @ref LL_DMA_CHANNEL_3
6849 * @arg @ref LL_DMA_CHANNEL_4
6850 * @arg @ref LL_DMA_CHANNEL_5
6851 * @arg @ref LL_DMA_CHANNEL_6
6852 * @arg @ref LL_DMA_CHANNEL_7
6853 * @arg @ref LL_DMA_CHANNEL_8
6854 * @arg @ref LL_DMA_CHANNEL_9
6855 * @arg @ref LL_DMA_CHANNEL_10
6856 * @arg @ref LL_DMA_CHANNEL_11
6857 * @arg @ref LL_DMA_CHANNEL_12
6858 * @arg @ref LL_DMA_CHANNEL_13
6859 * @arg @ref LL_DMA_CHANNEL_14
6860 * @arg @ref LL_DMA_CHANNEL_15
6861 * @retval State of bit (1 or 0).
6862 */
LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6863 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6864 {
6865 uint32_t dma_base_addr = (uint32_t)DMAx;
6866 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
6867 == DMA_CCR_DTEIE) ? 1UL : 0UL);
6868 }
6869
6870 /**
6871 * @brief Check if half transfer complete interrupt is enabled.
6872 * @note This API is used for all available DMA channels.
6873 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
6874 * @param DMAx DMAx Instance
6875 * @param Channel This parameter can be one of the following values:
6876 * @arg @ref LL_DMA_CHANNEL_0
6877 * @arg @ref LL_DMA_CHANNEL_1
6878 * @arg @ref LL_DMA_CHANNEL_2
6879 * @arg @ref LL_DMA_CHANNEL_3
6880 * @arg @ref LL_DMA_CHANNEL_4
6881 * @arg @ref LL_DMA_CHANNEL_5
6882 * @arg @ref LL_DMA_CHANNEL_6
6883 * @arg @ref LL_DMA_CHANNEL_7
6884 * @arg @ref LL_DMA_CHANNEL_8
6885 * @arg @ref LL_DMA_CHANNEL_9
6886 * @arg @ref LL_DMA_CHANNEL_10
6887 * @arg @ref LL_DMA_CHANNEL_11
6888 * @arg @ref LL_DMA_CHANNEL_12
6889 * @arg @ref LL_DMA_CHANNEL_13
6890 * @arg @ref LL_DMA_CHANNEL_14
6891 * @arg @ref LL_DMA_CHANNEL_15
6892 * @retval State of bit (1 or 0).
6893 */
LL_DMA_IsEnabledIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6894 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6895 {
6896 uint32_t dma_base_addr = (uint32_t)DMAx;
6897 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
6898 == DMA_CCR_HTIE) ? 1UL : 0UL);
6899 }
6900
6901 /**
6902 * @brief Check if transfer complete interrupt is enabled.
6903 * @note This API is used for all available DMA channels.
6904 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
6905 * @param DMAx DMAx Instance
6906 * @param Channel This parameter can be one of the following values:
6907 * @arg @ref LL_DMA_CHANNEL_0
6908 * @arg @ref LL_DMA_CHANNEL_1
6909 * @arg @ref LL_DMA_CHANNEL_2
6910 * @arg @ref LL_DMA_CHANNEL_3
6911 * @arg @ref LL_DMA_CHANNEL_4
6912 * @arg @ref LL_DMA_CHANNEL_5
6913 * @arg @ref LL_DMA_CHANNEL_6
6914 * @arg @ref LL_DMA_CHANNEL_7
6915 * @arg @ref LL_DMA_CHANNEL_8
6916 * @arg @ref LL_DMA_CHANNEL_9
6917 * @arg @ref LL_DMA_CHANNEL_10
6918 * @arg @ref LL_DMA_CHANNEL_11
6919 * @arg @ref LL_DMA_CHANNEL_12
6920 * @arg @ref LL_DMA_CHANNEL_13
6921 * @arg @ref LL_DMA_CHANNEL_14
6922 * @arg @ref LL_DMA_CHANNEL_15
6923 * @retval State of bit (1 or 0).
6924 */
LL_DMA_IsEnabledIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6925 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6926 {
6927 uint32_t dma_base_addr = (uint32_t)DMAx;
6928 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
6929 == DMA_CCR_TCIE) ? 1UL : 0UL);
6930 }
6931 /**
6932 * @}
6933 */
6934
6935 #if defined (USE_FULL_LL_DRIVER)
6936 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
6937 * @{
6938 */
6939 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
6940 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
6941
6942 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
6943 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
6944 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
6945
6946 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
6947 LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
6948 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
6949
6950 uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
6951 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
6952 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
6953 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
6954 /**
6955 * @}
6956 */
6957 #endif /* USE_FULL_LL_DRIVER */
6958
6959 /**
6960 * @}
6961 */
6962
6963 /**
6964 * @}
6965 */
6966
6967 #endif /* GPDMA1 || LPDMA1 */
6968
6969 /**
6970 * @}
6971 */
6972
6973 #ifdef __cplusplus
6974 }
6975 #endif /* __cplusplus */
6976
6977 #endif /* STM32U5xx_LL_DMA_H */
6978
6979
