1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_hsem.h
4 * @author MCD Application Team
5 * @brief Header file of HSEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_HSEM_H
21 #define STM32WBAxx_LL_HSEM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined(HSEM)
35
36 /** @defgroup HSEM_LL HSEM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47
48 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
49 * @{
50 */
51
52 /** @defgroup HSEM_LL_EC_LOCKID LOCKID Defines
53 * @{
54 */
55 #define LL_HSEM_LOCKID_NONE 0U
56 #define LL_HSEM_LOCKID_CPU1 HSEM_CR_LOCKID_CPU1
57 #define LL_HSEM_LOCKID HSEM_CR_LOCKID_CURRENT
58 /**
59 * @}
60 */
61
62 /** @defgroup HSEM_LL_EC_ATTRIBUTES Attributes Defines
63 * @brief HSEM Privilege/NPrivilege and Secure/NSecure Attributes
64 * @{
65 */
66 #define LL_HSEM_NSEC_PRIV HSEM_R_PRIV /*!< NSecure and Privileged attribute */
67 #define LL_HSEM_NSEC_NPRIV 0x0U /*!< NSecure and NPrivileged attribute */
68 #define LL_HSEM_SEC_PRIV (HSEM_R_SEC | HSEM_R_PRIV) /*!< Secure and Privileged attribute */
69 #define LL_HSEM_SEC_NPRIV HSEM_R_SEC /*!< Secure and NPrivileged attribute */
70 /**
71 * @}
72 */
73
74 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
75 * @brief Flags defines which can be used with LL_HSEM_ReadReg function
76 * @{
77 */
78
79 #define LL_HSEM_SEMAPHORE_0 HSEM_IER_ISE0
80 #define LL_HSEM_SEMAPHORE_1 HSEM_IER_ISE1
81 #define LL_HSEM_SEMAPHORE_2 HSEM_IER_ISE2
82 #define LL_HSEM_SEMAPHORE_3 HSEM_IER_ISE3
83 #define LL_HSEM_SEMAPHORE_4 HSEM_IER_ISE4
84 #define LL_HSEM_SEMAPHORE_5 HSEM_IER_ISE5
85 #define LL_HSEM_SEMAPHORE_6 HSEM_IER_ISE6
86 #define LL_HSEM_SEMAPHORE_7 HSEM_IER_ISE7
87 #define LL_HSEM_SEMAPHORE_8 HSEM_IER_ISE8
88 #define LL_HSEM_SEMAPHORE_9 HSEM_IER_ISE9
89 #define LL_HSEM_SEMAPHORE_10 HSEM_IER_ISE10
90 #define LL_HSEM_SEMAPHORE_11 HSEM_IER_ISE11
91 #define LL_HSEM_SEMAPHORE_12 HSEM_IER_ISE12
92 #define LL_HSEM_SEMAPHORE_13 HSEM_IER_ISE13
93 #define LL_HSEM_SEMAPHORE_14 HSEM_IER_ISE14
94 #define LL_HSEM_SEMAPHORE_15 HSEM_IER_ISE15
95 #define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU
96 /**
97 * @}
98 */
99
100 /**
101 * @}
102 */
103
104 /* Exported macro ------------------------------------------------------------*/
105 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
106 * @{
107 */
108
109 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
110 * @{
111 */
112
113 /**
114 * @brief Write a value in HSEM register
115 * @param __INSTANCE__ HSEM Instance
116 * @param __REG__ Register to be written
117 * @param __VALUE__ Value to be written in the register
118 * @retval None
119 */
120 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
121
122 /**
123 * @brief Read a value in HSEM register
124 * @param __INSTANCE__ HSEM Instance
125 * @param __REG__ Register to be read
126 * @retval Register value
127 */
128 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
129 /**
130 * @}
131 */
132
133 /**
134 * @}
135 */
136
137 /* Exported functions --------------------------------------------------------*/
138 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
139 * @{
140 */
141
142 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
143 * @{
144 */
145
146
147 /**
148 * @brief Return 1 if the semaphore is locked, else return 0.
149 * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked
150 * @param HSEMx HSEM Instance.
151 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
152 * @retval State of bit (1 or 0).
153 */
LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef * HSEMx,uint32_t Semaphore)154 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
155 {
156 return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
157 }
158
159 /**
160 * @brief Get core id.
161 * @rmtoll R LOCKID LL_HSEM_GetCoreId
162 * @param HSEMx HSEM Instance.
163 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
164 * @retval Returned value can be one of the following values:
165 * @arg @ref LL_HSEM_LOCKID_NONE
166 * @arg @ref LL_HSEM_LOCKID_CPU1
167 */
LL_HSEM_GetCoreId(const HSEM_TypeDef * HSEMx,uint32_t Semaphore)168 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
169 {
170 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCKID_Msk));
171 }
172
173 /**
174 * @brief Get process id.
175 * @rmtoll R PROCID LL_HSEM_GetProcessId
176 * @param HSEMx HSEM Instance.
177 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
178 * @retval Process number. Value between Min_Data=0 and Max_Data=255
179 */
LL_HSEM_GetProcessId(const HSEM_TypeDef * HSEMx,uint32_t Semaphore)180 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
181 {
182 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
183 }
184
185 /**
186 * @brief Get the lock by writing in R register.
187 * @note The R register has to be read to determined if the lock is taken.
188 * @rmtoll R LOCK LL_HSEM_SetLock
189 * @rmtoll R LOCKID LL_HSEM_SetLock
190 * @rmtoll R PROCID LL_HSEM_SetLock
191 * @rmtoll R SEC LL_HSEM_SetLock
192 * @rmtoll R PRIV LL_HSEM_SetLock
193 * @param HSEMx HSEM Instance.
194 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
195 * @param process Process id. Value between Min_Data=0 and Max_Data=255
196 * @param attribute Security and privilege attributes. Value can be one of the following:
197 * @arg @ref LL_HSEM_NSEC_PRIV
198 * @arg @ref LL_HSEM_NSEC_NPRIV
199 * @arg @ref LL_HSEM_SEC_PRIV
200 * @arg @ref LL_HSEM_SEC_NPRIV
201 * @retval None
202 */
LL_HSEM_SetLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process,uint32_t attribute)203 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute)
204 {
205 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute));
206 }
207
208 /**
209 * @brief Get the lock with 2-step lock.
210 * @rmtoll R LOCK LL_HSEM_2StepLock
211 * @rmtoll R LOCKID LL_HSEM_2StepLock
212 * @rmtoll R PROCID LL_HSEM_2StepLock
213 * @rmtoll R SEC LL_HSEM_2StepLock
214 * @rmtoll R PRIV LL_HSEM_2StepLock
215 * @param HSEMx HSEM Instance.
216 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
217 * @param process Process id. Value between Min_Data=0 and Max_Data=255
218 * @param attribute Security and privilege attributes. Value can be one of the following:
219 * @arg @ref LL_HSEM_NSEC_PRIV
220 * @arg @ref LL_HSEM_NSEC_NPRIV
221 * @arg @ref LL_HSEM_SEC_PRIV
222 * @arg @ref LL_HSEM_SEC_NPRIV
223 * @retval 1 lock fail, 0 lock successful or already locked by same process and core
224 */
LL_HSEM_2StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process,uint32_t attribute)225 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute)
226 {
227 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute));
228 return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute)) ? 1UL : 0UL);
229 }
230
231 /**
232 * @brief Get the lock with 1-step lock.
233 * @rmtoll RLR LOCK LL_HSEM_1StepLock
234 * @rmtoll RLR LOCKID LL_HSEM_1StepLock
235 * @rmtoll RLR PROCID LL_HSEM_1StepLock
236 * @rmtoll RLR SEC LL_HSEM_1StepLock
237 * @rmtoll RLR PRIV LL_HSEM_1StepLock
238 * @param HSEMx HSEM Instance.
239 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
240 * @param attribute Security and privilege attributes. Value can be one of the following:
241 * @arg @ref LL_HSEM_NSEC_PRIV
242 * @arg @ref LL_HSEM_NSEC_NPRIV
243 * @arg @ref LL_HSEM_SEC_PRIV
244 * @arg @ref LL_HSEM_SEC_NPRIV
245 * @retval 1 lock fail, 0 lock successful or already locked by same core
246 */
LL_HSEM_1StepLock(const HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t attribute)247 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t attribute)
248 {
249 return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_LOCKID | attribute)) ? 1UL : 0UL);
250 }
251
252 /**
253 * @brief Release the lock of the semaphore.
254 * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
255 * @rmtoll R LOCK LL_HSEM_ReleaseLock
256 * @rmtoll R SEC LL_HSEM_ReleaseLock
257 * @rmtoll R PRIV LL_HSEM_ReleaseLock
258 * @param HSEMx HSEM Instance.
259 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
260 * @param process Process number. Value between Min_Data=0 and Max_Data=255
261 * @param attribute Security and privilege attributes. Value can be one of the following:
262 * @arg @ref LL_HSEM_NSEC_PRIV
263 * @arg @ref LL_HSEM_NSEC_NPRIV
264 * @arg @ref LL_HSEM_SEC_PRIV
265 * @arg @ref LL_HSEM_SEC_NPRIV
266 * @retval None
267 */
LL_HSEM_ReleaseLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process,uint32_t attribute)268 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute)
269 {
270 WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_LOCKID | process | attribute));
271 }
272
273 /**
274 * @brief Get the lock status of the semaphore.
275 * @rmtoll R LOCK LL_HSEM_GetStatus
276 * @param HSEMx HSEM Instance.
277 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
278 * @retval 0 semaphore is free, 1 semaphore is locked */
LL_HSEM_GetStatus(const HSEM_TypeDef * HSEMx,uint32_t Semaphore)279 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
280 {
281 return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
282 }
283
284 /**
285 * @brief Set the key.
286 * @rmtoll KEYR KEY LL_HSEM_SetKey
287 * @param HSEMx HSEM Instance.
288 * @param key Key value.
289 * @retval None
290 */
LL_HSEM_SetKey(HSEM_TypeDef * HSEMx,uint32_t key)291 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
292 {
293 WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
294 }
295
296 /**
297 * @brief Get the key.
298 * @rmtoll KEYR KEY LL_HSEM_GetKey
299 * @param HSEMx HSEM Instance.
300 * @retval key to unlock all semaphore from the same core
301 */
LL_HSEM_GetKey(const HSEM_TypeDef * HSEMx)302 __STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx)
303 {
304 return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
305 }
306
307 /**
308 * @brief Release all semaphore with the same core id.
309 * @rmtoll CR KEY LL_HSEM_ResetAllLock
310 * @param HSEMx HSEM Instance.
311 * @param key Key value.
312 * @param core This parameter can be one of the following values:
313 * @arg @ref LL_HSEM_LOCKID_CPU1
314 * @param attribute Security and privilege attributes. Value can be one of the following:
315 * @arg @ref LL_HSEM_NSEC_PRIV
316 * @arg @ref LL_HSEM_NSEC_NPRIV
317 * @arg @ref LL_HSEM_SEC_PRIV
318 * @arg @ref LL_HSEM_SEC_NPRIV
319 * @retval None
320 */
LL_HSEM_ResetAllLock(HSEM_TypeDef * HSEMx,uint32_t key,uint32_t core,uint32_t attribute)321 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core, uint32_t attribute)
322 {
323 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core | attribute);
324 }
325
326 #if defined(HSEM_SECCFGR_SEC0)
327 /**
328 * @brief Set semaphore accessible by secure only.
329 * @rmtoll SECCFGR SEC LL_HSEM_SetSemaphoreSecure
330 * @param HSEMx HSEM Instance.
331 * @param SemMask This parameter can be a combination of the following values:
332 * @arg @ref LL_HSEM_SEMAPHORE_0
333 * @arg @ref LL_HSEM_SEMAPHORE_1
334 * @arg @ref LL_HSEM_SEMAPHORE_2
335 * @arg @ref LL_HSEM_SEMAPHORE_3
336 * @arg @ref LL_HSEM_SEMAPHORE_4
337 * @arg @ref LL_HSEM_SEMAPHORE_5
338 * @arg @ref LL_HSEM_SEMAPHORE_6
339 * @arg @ref LL_HSEM_SEMAPHORE_7
340 * @arg @ref LL_HSEM_SEMAPHORE_8
341 * @arg @ref LL_HSEM_SEMAPHORE_9
342 * @arg @ref LL_HSEM_SEMAPHORE_10
343 * @arg @ref LL_HSEM_SEMAPHORE_11
344 * @arg @ref LL_HSEM_SEMAPHORE_12
345 * @arg @ref LL_HSEM_SEMAPHORE_13
346 * @arg @ref LL_HSEM_SEMAPHORE_14
347 * @arg @ref LL_HSEM_SEMAPHORE_15
348 * @arg @ref LL_HSEM_SEMAPHORE_ALL
349 * @retval None
350 */
LL_HSEM_SetSemaphoreSecure(HSEM_TypeDef * HSEMx,uint32_t SemMask)351 __STATIC_INLINE void LL_HSEM_SetSemaphoreSecure(HSEM_TypeDef *HSEMx, uint32_t SemMask)
352 {
353 SET_BIT(HSEMx->SECCFGR, SemMask);
354 }
355
356 /**
357 * @brief Set semaphore accessible by secure and non-secure.
358 * @rmtoll SECCFGR SEC LL_HSEM_SetSemaphoreNonSecure
359 * @param HSEMx HSEM Instance.
360 * @param SemMask This parameter can be a combination of the following values:
361 * @arg @ref LL_HSEM_SEMAPHORE_0
362 * @arg @ref LL_HSEM_SEMAPHORE_1
363 * @arg @ref LL_HSEM_SEMAPHORE_2
364 * @arg @ref LL_HSEM_SEMAPHORE_3
365 * @arg @ref LL_HSEM_SEMAPHORE_4
366 * @arg @ref LL_HSEM_SEMAPHORE_5
367 * @arg @ref LL_HSEM_SEMAPHORE_6
368 * @arg @ref LL_HSEM_SEMAPHORE_7
369 * @arg @ref LL_HSEM_SEMAPHORE_8
370 * @arg @ref LL_HSEM_SEMAPHORE_9
371 * @arg @ref LL_HSEM_SEMAPHORE_10
372 * @arg @ref LL_HSEM_SEMAPHORE_11
373 * @arg @ref LL_HSEM_SEMAPHORE_12
374 * @arg @ref LL_HSEM_SEMAPHORE_13
375 * @arg @ref LL_HSEM_SEMAPHORE_14
376 * @arg @ref LL_HSEM_SEMAPHORE_15
377 * @arg @ref LL_HSEM_SEMAPHORE_ALL
378 * @retval None
379 */
LL_HSEM_SetSemaphoreNonSecure(HSEM_TypeDef * HSEMx,uint32_t SemMask)380 __STATIC_INLINE void LL_HSEM_SetSemaphoreNonSecure(HSEM_TypeDef *HSEMx, uint32_t SemMask)
381 {
382 CLEAR_BIT(HSEMx->SECCFGR, SemMask);
383 }
384
385 /**
386 * @brief Get security attribute of semaphore.
387 * @rmtoll SECCFGR SEC LL_HSEM_GetSemaphoreSecure
388 * @param HSEMx HSEM Instance.
389 * @retval Security attribute of semaphores
390 */
LL_HSEM_GetSemaphoreSecure(const HSEM_TypeDef * HSEMx)391 __STATIC_INLINE uint32_t LL_HSEM_GetSemaphoreSecure(const HSEM_TypeDef *HSEMx)
392 {
393 return HSEMx->SECCFGR;
394 }
395
396 /**
397 * @brief Set semaphore accessible by privilege only.
398 * @rmtoll PRIVCFGR PRIV LL_HSEM_SetSemaphorePrivilege
399 * @param HSEMx HSEM Instance.
400 * @param SemMask This parameter can be a combination of the following values:
401 * @arg @ref LL_HSEM_SEMAPHORE_0
402 * @arg @ref LL_HSEM_SEMAPHORE_1
403 * @arg @ref LL_HSEM_SEMAPHORE_2
404 * @arg @ref LL_HSEM_SEMAPHORE_3
405 * @arg @ref LL_HSEM_SEMAPHORE_4
406 * @arg @ref LL_HSEM_SEMAPHORE_5
407 * @arg @ref LL_HSEM_SEMAPHORE_6
408 * @arg @ref LL_HSEM_SEMAPHORE_7
409 * @arg @ref LL_HSEM_SEMAPHORE_8
410 * @arg @ref LL_HSEM_SEMAPHORE_9
411 * @arg @ref LL_HSEM_SEMAPHORE_10
412 * @arg @ref LL_HSEM_SEMAPHORE_11
413 * @arg @ref LL_HSEM_SEMAPHORE_12
414 * @arg @ref LL_HSEM_SEMAPHORE_13
415 * @arg @ref LL_HSEM_SEMAPHORE_14
416 * @arg @ref LL_HSEM_SEMAPHORE_15
417 * @arg @ref LL_HSEM_SEMAPHORE_ALL
418 * @retval None
419 */
LL_HSEM_SetSemaphorePrivilege(HSEM_TypeDef * HSEMx,uint32_t SemMask)420 __STATIC_INLINE void LL_HSEM_SetSemaphorePrivilege(HSEM_TypeDef *HSEMx, uint32_t SemMask)
421 {
422 SET_BIT(HSEMx->PRIVCFGR, SemMask);
423 }
424
425 /**
426 * @brief Set semaphore accessible by privilege and non-privilege.
427 * @rmtoll PRIVCFGR PRIV LL_HSEM_SetSemaphoreNonPrivilege
428 * @param HSEMx HSEM Instance.
429 * @param SemMask This parameter can be a combination of the following values:
430 * @arg @ref LL_HSEM_SEMAPHORE_0
431 * @arg @ref LL_HSEM_SEMAPHORE_1
432 * @arg @ref LL_HSEM_SEMAPHORE_2
433 * @arg @ref LL_HSEM_SEMAPHORE_3
434 * @arg @ref LL_HSEM_SEMAPHORE_4
435 * @arg @ref LL_HSEM_SEMAPHORE_5
436 * @arg @ref LL_HSEM_SEMAPHORE_6
437 * @arg @ref LL_HSEM_SEMAPHORE_7
438 * @arg @ref LL_HSEM_SEMAPHORE_8
439 * @arg @ref LL_HSEM_SEMAPHORE_9
440 * @arg @ref LL_HSEM_SEMAPHORE_10
441 * @arg @ref LL_HSEM_SEMAPHORE_11
442 * @arg @ref LL_HSEM_SEMAPHORE_12
443 * @arg @ref LL_HSEM_SEMAPHORE_13
444 * @arg @ref LL_HSEM_SEMAPHORE_14
445 * @arg @ref LL_HSEM_SEMAPHORE_15
446 * @arg @ref LL_HSEM_SEMAPHORE_ALL
447 * @retval None
448 */
LL_HSEM_SetSemaphoreNonPrivilege(HSEM_TypeDef * HSEMx,uint32_t SemMask)449 __STATIC_INLINE void LL_HSEM_SetSemaphoreNonPrivilege(HSEM_TypeDef *HSEMx, uint32_t SemMask)
450 {
451 CLEAR_BIT(HSEMx->PRIVCFGR, SemMask);
452 }
453
454 /**
455 * @brief Get privilege attribute of semaphore.
456 * @rmtoll PRIVCFGR PRIV LL_HSEM_GetSemaphorePrivilege
457 * @param HSEMx HSEM Instance.
458 * @retval Privilege attribute of semaphores
459 */
LL_HSEM_GetSemaphorePrivilege(const HSEM_TypeDef * HSEMx)460 __STATIC_INLINE uint32_t LL_HSEM_GetSemaphorePrivilege(const HSEM_TypeDef *HSEMx)
461 {
462 return HSEMx->PRIVCFGR;
463 }
464
465 #endif
466 /**
467 * @}
468 */
469
470 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
471 * @{
472 */
473
474 /**
475 * @brief Enable interrupt.
476 * @rmtoll IER ISEM LL_HSEM_EnableIT_IER
477 * @param HSEMx HSEM Instance.
478 * @param SemaphoreMask This parameter can be a combination of the following values:
479 * @arg @ref LL_HSEM_SEMAPHORE_0
480 * @arg @ref LL_HSEM_SEMAPHORE_1
481 * @arg @ref LL_HSEM_SEMAPHORE_2
482 * @arg @ref LL_HSEM_SEMAPHORE_3
483 * @arg @ref LL_HSEM_SEMAPHORE_4
484 * @arg @ref LL_HSEM_SEMAPHORE_5
485 * @arg @ref LL_HSEM_SEMAPHORE_6
486 * @arg @ref LL_HSEM_SEMAPHORE_7
487 * @arg @ref LL_HSEM_SEMAPHORE_8
488 * @arg @ref LL_HSEM_SEMAPHORE_9
489 * @arg @ref LL_HSEM_SEMAPHORE_10
490 * @arg @ref LL_HSEM_SEMAPHORE_11
491 * @arg @ref LL_HSEM_SEMAPHORE_12
492 * @arg @ref LL_HSEM_SEMAPHORE_13
493 * @arg @ref LL_HSEM_SEMAPHORE_14
494 * @arg @ref LL_HSEM_SEMAPHORE_15
495 * @arg @ref LL_HSEM_SEMAPHORE_ALL
496 * @retval None
497 */
LL_HSEM_EnableIT_IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)498 __STATIC_INLINE void LL_HSEM_EnableIT_IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
499 {
500 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
501 SET_BIT(HSEMx->SIER, SemaphoreMask);
502 #else
503 SET_BIT(HSEMx->IER, SemaphoreMask);
504 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
505 }
506
507 /**
508 * @brief Disable interrupt.
509 * @rmtoll IER ISEM LL_HSEM_DisableIT_IER
510 * @param HSEMx HSEM Instance.
511 * @param SemaphoreMask This parameter can be a combination of the following values:
512 * @arg @ref LL_HSEM_SEMAPHORE_0
513 * @arg @ref LL_HSEM_SEMAPHORE_1
514 * @arg @ref LL_HSEM_SEMAPHORE_2
515 * @arg @ref LL_HSEM_SEMAPHORE_3
516 * @arg @ref LL_HSEM_SEMAPHORE_4
517 * @arg @ref LL_HSEM_SEMAPHORE_5
518 * @arg @ref LL_HSEM_SEMAPHORE_6
519 * @arg @ref LL_HSEM_SEMAPHORE_7
520 * @arg @ref LL_HSEM_SEMAPHORE_8
521 * @arg @ref LL_HSEM_SEMAPHORE_9
522 * @arg @ref LL_HSEM_SEMAPHORE_10
523 * @arg @ref LL_HSEM_SEMAPHORE_11
524 * @arg @ref LL_HSEM_SEMAPHORE_12
525 * @arg @ref LL_HSEM_SEMAPHORE_13
526 * @arg @ref LL_HSEM_SEMAPHORE_14
527 * @arg @ref LL_HSEM_SEMAPHORE_15
528 * @arg @ref LL_HSEM_SEMAPHORE_ALL
529 * @retval None
530 */
LL_HSEM_DisableIT_IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)531 __STATIC_INLINE void LL_HSEM_DisableIT_IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
532 {
533 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
534 CLEAR_BIT(HSEMx->SIER, SemaphoreMask);
535 #else
536 CLEAR_BIT(HSEMx->IER, SemaphoreMask);
537 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
538 }
539
540 /**
541 * @brief Check if interrupt is enabled.
542 * @rmtoll IER ISEM LL_HSEM_IsEnabledIT_IER
543 * @param HSEMx HSEM Instance.
544 * @param SemaphoreMask This parameter can be a combination of the following values:
545 * @arg @ref LL_HSEM_SEMAPHORE_0
546 * @arg @ref LL_HSEM_SEMAPHORE_1
547 * @arg @ref LL_HSEM_SEMAPHORE_2
548 * @arg @ref LL_HSEM_SEMAPHORE_3
549 * @arg @ref LL_HSEM_SEMAPHORE_4
550 * @arg @ref LL_HSEM_SEMAPHORE_5
551 * @arg @ref LL_HSEM_SEMAPHORE_6
552 * @arg @ref LL_HSEM_SEMAPHORE_7
553 * @arg @ref LL_HSEM_SEMAPHORE_8
554 * @arg @ref LL_HSEM_SEMAPHORE_9
555 * @arg @ref LL_HSEM_SEMAPHORE_10
556 * @arg @ref LL_HSEM_SEMAPHORE_11
557 * @arg @ref LL_HSEM_SEMAPHORE_12
558 * @arg @ref LL_HSEM_SEMAPHORE_13
559 * @arg @ref LL_HSEM_SEMAPHORE_14
560 * @arg @ref LL_HSEM_SEMAPHORE_15
561 * @arg @ref LL_HSEM_SEMAPHORE_ALL
562 * @retval State of bit (1 or 0).
563 */
LL_HSEM_IsEnabledIT_IER(const HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)564 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
565 {
566 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
567 return ((READ_BIT(HSEMx->SIER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
568 #else
569 return ((READ_BIT(HSEMx->IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
570 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
571 }
572
573
574 /**
575 * @}
576 */
577
578 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
579 * @{
580 */
581
582 /**
583 * @brief Clear interrupt status.
584 * @rmtoll ICR ISEM LL_HSEM_ClearFlag_ICR
585 * @param HSEMx HSEM Instance.
586 * @param SemaphoreMask This parameter can be a combination of the following values:
587 * @arg @ref LL_HSEM_SEMAPHORE_0
588 * @arg @ref LL_HSEM_SEMAPHORE_1
589 * @arg @ref LL_HSEM_SEMAPHORE_2
590 * @arg @ref LL_HSEM_SEMAPHORE_3
591 * @arg @ref LL_HSEM_SEMAPHORE_4
592 * @arg @ref LL_HSEM_SEMAPHORE_5
593 * @arg @ref LL_HSEM_SEMAPHORE_6
594 * @arg @ref LL_HSEM_SEMAPHORE_7
595 * @arg @ref LL_HSEM_SEMAPHORE_8
596 * @arg @ref LL_HSEM_SEMAPHORE_9
597 * @arg @ref LL_HSEM_SEMAPHORE_10
598 * @arg @ref LL_HSEM_SEMAPHORE_11
599 * @arg @ref LL_HSEM_SEMAPHORE_12
600 * @arg @ref LL_HSEM_SEMAPHORE_13
601 * @arg @ref LL_HSEM_SEMAPHORE_14
602 * @arg @ref LL_HSEM_SEMAPHORE_15
603 * @arg @ref LL_HSEM_SEMAPHORE_ALL
604 * @retval None
605 */
LL_HSEM_ClearFlag_ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)606 __STATIC_INLINE void LL_HSEM_ClearFlag_ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
607 {
608 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
609 WRITE_REG(HSEMx->SICR, SemaphoreMask);
610 #else
611 WRITE_REG(HSEMx->ICR, SemaphoreMask);
612 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
613 }
614
615 /**
616 * @brief Get interrupt status from ISR register.
617 * @rmtoll ISR ISEM LL_HSEM_IsActiveFlag_ISR
618 * @param HSEMx HSEM Instance.
619 * @param SemaphoreMask This parameter can be a combination of the following values:
620 * @arg @ref LL_HSEM_SEMAPHORE_0
621 * @arg @ref LL_HSEM_SEMAPHORE_1
622 * @arg @ref LL_HSEM_SEMAPHORE_2
623 * @arg @ref LL_HSEM_SEMAPHORE_3
624 * @arg @ref LL_HSEM_SEMAPHORE_4
625 * @arg @ref LL_HSEM_SEMAPHORE_5
626 * @arg @ref LL_HSEM_SEMAPHORE_6
627 * @arg @ref LL_HSEM_SEMAPHORE_7
628 * @arg @ref LL_HSEM_SEMAPHORE_8
629 * @arg @ref LL_HSEM_SEMAPHORE_9
630 * @arg @ref LL_HSEM_SEMAPHORE_10
631 * @arg @ref LL_HSEM_SEMAPHORE_11
632 * @arg @ref LL_HSEM_SEMAPHORE_12
633 * @arg @ref LL_HSEM_SEMAPHORE_13
634 * @arg @ref LL_HSEM_SEMAPHORE_14
635 * @arg @ref LL_HSEM_SEMAPHORE_15
636 * @arg @ref LL_HSEM_SEMAPHORE_ALL
637 * @retval State of bit (1 or 0).
638 */
LL_HSEM_IsActiveFlag_ISR(const HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)639 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
640 {
641 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
642 return ((READ_BIT(HSEMx->SISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
643 #else
644 return ((READ_BIT(HSEMx->ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
645 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
646 }
647
648 /**
649 * @brief Get interrupt status from MISR register.
650 * @rmtoll MISR ISEM LL_HSEM_IsActiveFlag_MISR
651 * @param HSEMx HSEM Instance.
652 * @param SemaphoreMask This parameter can be a combination of the following values:
653 * @arg @ref LL_HSEM_SEMAPHORE_0
654 * @arg @ref LL_HSEM_SEMAPHORE_1
655 * @arg @ref LL_HSEM_SEMAPHORE_2
656 * @arg @ref LL_HSEM_SEMAPHORE_3
657 * @arg @ref LL_HSEM_SEMAPHORE_4
658 * @arg @ref LL_HSEM_SEMAPHORE_5
659 * @arg @ref LL_HSEM_SEMAPHORE_6
660 * @arg @ref LL_HSEM_SEMAPHORE_7
661 * @arg @ref LL_HSEM_SEMAPHORE_8
662 * @arg @ref LL_HSEM_SEMAPHORE_9
663 * @arg @ref LL_HSEM_SEMAPHORE_10
664 * @arg @ref LL_HSEM_SEMAPHORE_11
665 * @arg @ref LL_HSEM_SEMAPHORE_12
666 * @arg @ref LL_HSEM_SEMAPHORE_13
667 * @arg @ref LL_HSEM_SEMAPHORE_14
668 * @arg @ref LL_HSEM_SEMAPHORE_15
669 * @arg @ref LL_HSEM_SEMAPHORE_ALL
670 * @retval State of bit (1 or 0).
671 */
LL_HSEM_IsActiveFlag_MISR(const HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)672 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
673 {
674 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
675 return ((READ_BIT(HSEMx->SMISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
676 #else
677 return ((READ_BIT(HSEMx->MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
678 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
679 }
680
681 /**
682 * @}
683 */
684
685 /**
686 * @}
687 */
688
689 /**
690 * @}
691 */
692
693 #endif /* defined(HSEM) */
694
695 /**
696 * @}
697 */
698
699 #ifdef __cplusplus
700 }
701 #endif
702
703 #endif /* __STM32WBAxx_LL_HSEM_H */
704
