1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_hrtim.h
4 * @author MCD Application Team
5 * @brief Header file of HRTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_HRTIM_H
21 #define STM32G4xx_LL_HRTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (HRTIM1)
35
36 /** @defgroup HRTIM_LL HRTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
43 * @{
44 */
45 static const uint16_t REG_OFFSET_TAB_TIMER[] =
46 {
47 0x00U, /* 0: MASTER */
48 0x80U, /* 1: TIMER A */
49 0x100U, /* 2: TIMER B */
50 0x180U, /* 3: TIMER C */
51 0x200U, /* 4: TIMER D */
52 0x280U, /* 5: TIMER E */
53 0x300U, /* 6: TIMER F */
54 };
55
56 static const uint8_t REG_OFFSET_TAB_ADCER[] =
57 {
58 0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_ADC1R */
59 0x04U, /* LL_HRTIM_ADCTRIG_2: HRTIM_ADC2R */
60 0x08U, /* LL_HRTIM_ADCTRIG_3: HRTIM_ADC3R */
61 0x0CU, /* LL_HRTIM_ADCTRIG_4: HRTIM_ADC4R */
62 0x3CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCER */
63 0x3CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCER */
64 0x3CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCER */
65 0x3CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCER */
66 0x3CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCER */
67 0x3CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCER */
68 };
69
70 static const uint8_t REG_OFFSET_TAB_ADCUR[] =
71 {
72 0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_CR1 */
73 0x00U, /* LL_HRTIM_ADCTRIG_2: HRTIM_CR1 */
74 0x00U, /* LL_HRTIM_ADCTRIG_3: HRTIM_CR1 */
75 0x00U, /* LL_HRTIM_ADCTRIG_4: HRTIM_CR1 */
76 0x7CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCUR */
77 0x7CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCUR */
78 0x7CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCUR */
79 0x7CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCUR */
80 0x7CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCUR */
81 0x7CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCUR */
82 };
83
84 static const uint8_t REG_SHIFT_TAB_ADCER[] =
85 {
86 0, /* LL_HRTIM_ADCTRIG_1 */
87 0, /* LL_HRTIM_ADCTRIG_2 */
88 0, /* LL_HRTIM_ADCTRIG_3 */
89 0, /* LL_HRTIM_ADCTRIG_4 */
90 0, /* LL_HRTIM_ADCTRIG_5 */
91 5, /* LL_HRTIM_ADCTRIG_6 */
92 10, /* LL_HRTIM_ADCTRIG_7 */
93 16, /* LL_HRTIM_ADCTRIG_8 */
94 21, /* LL_HRTIM_ADCTRIG_9 */
95 26 /* LL_HRTIM_ADCTRIG_10 */
96 };
97
98 static const uint8_t REG_SHIFT_TAB_ADCUR[] =
99 {
100 16, /* LL_HRTIM_ADCTRIG_1 */
101 19, /* LL_HRTIM_ADCTRIG_2 */
102 22, /* LL_HRTIM_ADCTRIG_3 */
103 25, /* LL_HRTIM_ADCTRIG_4 */
104 0, /* LL_HRTIM_ADCTRIG_5 */
105 4, /* LL_HRTIM_ADCTRIG_6 */
106 8, /* LL_HRTIM_ADCTRIG_7 */
107 12, /* LL_HRTIM_ADCTRIG_8 */
108 16, /* LL_HRTIM_ADCTRIG_9 */
109 20 /* LL_HRTIM_ADCTRIG_10 */
110 };
111
112 static const uint32_t REG_MASK_TAB_ADCER[] =
113 {
114 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_1 */
115 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_2 */
116 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_3 */
117 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_4 */
118 0x0000001FU, /* LL_HRTIM_ADCTRIG_5 */
119 0x000003E0U, /* LL_HRTIM_ADCTRIG_6 */
120 0x00007C00U, /* LL_HRTIM_ADCTRIG_7 */
121 0x001F0000U, /* LL_HRTIM_ADCTRIG_8 */
122 0x03E00000U, /* LL_HRTIM_ADCTRIG_9 */
123 0x7C000000U /* LL_HRTIM_ADCTRIG_10 */
124 };
125
126 static const uint32_t REG_MASK_TAB_ADCUR[] =
127 {
128 0x00070000U, /* LL_HRTIM_ADCTRIG_1 */
129 0x00380000U, /* LL_HRTIM_ADCTRIG_2 */
130 0x01C00000U, /* LL_HRTIM_ADCTRIG_3 */
131 0x0E000000U, /* LL_HRTIM_ADCTRIG_4 */
132 0x00000007U, /* LL_HRTIM_ADCTRIG_5 */
133 0x00000070U, /* LL_HRTIM_ADCTRIG_6 */
134 0x00000700U, /* LL_HRTIM_ADCTRIG_7 */
135 0x00007000U, /* LL_HRTIM_ADCTRIG_8 */
136 0x00070000U, /* LL_HRTIM_ADCTRIG_9 */
137 0x00700000U /* LL_HRTIM_ADCTRIG_10 */
138 };
139
140 static const uint8_t REG_OFFSET_TAB_ADCPSx[] =
141 {
142 0U, /* 0: HRTIM_ADC1R */
143 6U, /* 1: HRTIM_ADC2R */
144 12U, /* 2: HRTIM_ADC3R */
145 18U, /* 3: HRTIM_ADC4R */
146 24U, /* 4: HRTIM_ADC5R */
147 32U, /* 5: HRTIM_ADC6R */
148 38U, /* 6: HRTIM_ADC7R */
149 44U, /* 7: HRTIM_ADC8R */
150 50U, /* 8: HRTIM_ADC9R */
151 56U /* 9: HRTIM_ADC10R */
152 };
153
154 static const uint16_t REG_OFFSET_TAB_SETxR[] =
155 {
156 0x00U, /* 0: TA1 */
157 0x08U, /* 1: TA2 */
158 0x80U, /* 2: TB1 */
159 0x88U, /* 3: TB2 */
160 0x100U, /* 4: TC1 */
161 0x108U, /* 5: TC2 */
162 0x180U, /* 6: TD1 */
163 0x188U, /* 7: TD2 */
164 0x200U, /* 8: TE1 */
165 0x208U, /* 9: TE2 */
166 0x280U, /* 10: TF1 */
167 0x288U /* 11: TF2 */
168 };
169
170 static const uint16_t REG_OFFSET_TAB_OUTxR[] =
171 {
172 0x00U, /* 0: TA1 */
173 0x00U, /* 1: TA2 */
174 0x80U, /* 2: TB1 */
175 0x80U, /* 3: TB2 */
176 0x100U, /* 4: TC1 */
177 0x100U, /* 5: TC2 */
178 0x180U, /* 6: TD1 */
179 0x180U, /* 7: TD2 */
180 0x200U, /* 8: TE1 */
181 0x200U, /* 9: TE2 */
182 0x280U, /* 10: TF1 */
183 0x280U /* 11: TF2 */
184 };
185
186 static const uint8_t REG_OFFSET_TAB_EECR[] =
187 {
188 0x00U, /* LL_HRTIM_EVENT_1 */
189 0x00U, /* LL_HRTIM_EVENT_2 */
190 0x00U, /* LL_HRTIM_EVENT_3 */
191 0x00U, /* LL_HRTIM_EVENT_4 */
192 0x00U, /* LL_HRTIM_EVENT_5 */
193 0x04U, /* LL_HRTIM_EVENT_6 */
194 0x04U, /* LL_HRTIM_EVENT_7 */
195 0x04U, /* LL_HRTIM_EVENT_8 */
196 0x04U, /* LL_HRTIM_EVENT_9 */
197 0x04U /* LL_HRTIM_EVENT_10 */
198 };
199
200 static const uint8_t REG_OFFSET_TAB_FLTINR[] =
201 {
202 0x00U, /* LL_HRTIM_FAULT_1 */
203 0x00U, /* LL_HRTIM_FAULT_2 */
204 0x00U, /* LL_HRTIM_FAULT_3 */
205 0x00U, /* LL_HRTIM_FAULT_4 */
206 0x04U, /* LL_HRTIM_FAULT_5 */
207 0x04U /* LL_HRTIM_FAULT_6 */
208 };
209
210 static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
211 {
212 0x20000000U, /* 0: MASTER */
213 0x01FF0000U, /* 1: TIMER A */
214 0x01FF0000U, /* 2: TIMER B */
215 0x01FF0000U, /* 3: TIMER C */
216 0x01FF0000U, /* 4: TIMER D */
217 0x01FF0000U, /* 5: TIMER E */
218 0x01FF0000U, /* 5: TIMER E */
219 0x01FF0000U /* 6: TIMER F */
220 };
221
222 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
223 {
224 12U, /* 0: MASTER */
225 0U, /* 1: TIMER A */
226 0U, /* 2: TIMER B */
227 0U, /* 3: TIMER C */
228 0U, /* 4: TIMER D */
229 0U, /* 5: TIMER E */
230 0U /* 6: TIMER F */
231 };
232
233 static const uint8_t REG_SHIFT_TAB_EExSRC[] =
234 {
235 0U, /* LL_HRTIM_EVENT_1 */
236 6U, /* LL_HRTIM_EVENT_2 */
237 12U, /* LL_HRTIM_EVENT_3 */
238 18U, /* LL_HRTIM_EVENT_4 */
239 24U, /* LL_HRTIM_EVENT_5 */
240 0U, /* LL_HRTIM_EVENT_6 */
241 6U, /* LL_HRTIM_EVENT_7 */
242 12U, /* LL_HRTIM_EVENT_8 */
243 18U, /* LL_HRTIM_EVENT_9 */
244 24U /* LL_HRTIM_EVENT_10 */
245 };
246
247 static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
248 {
249 HRTIM_MCR_BRSTDMA, /* 0: MASTER */
250 HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
251 HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
252 HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
253 HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
254 HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
255 HRTIM_TIMCR_UPDGAT /* 6: TIMER F */
256 };
257
258 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
259 {
260 2U, /* 0: MASTER */
261 0U, /* 1: TIMER A */
262 0U, /* 2: TIMER B */
263 0U, /* 3: TIMER C */
264 0U, /* 4: TIMER D */
265 0U, /* 5: TIMER E */
266 0U /* 6: TIMER F */
267 };
268
269 static const uint8_t REG_SHIFT_TAB_OUTxR[] =
270 {
271 0U, /* 0: TA1 */
272 16U, /* 1: TA2 */
273 0U, /* 2: TB1 */
274 16U, /* 3: TB2 */
275 0U, /* 4: TC1 */
276 16U, /* 5: TC2 */
277 0U, /* 6: TD1 */
278 16U, /* 7: TD2 */
279 0U, /* 8: TE1 */
280 16U, /* 9: TE2 */
281 0U, /* 10: TF1 */
282 16U /* 11: TF2 */
283 };
284
285 static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
286 {
287 0U, /* 0: TA1 */
288 1U, /* 1: TA2 */
289 0U, /* 2: TB1 */
290 1U, /* 3: TB2 */
291 0U, /* 4: TC1 */
292 1U, /* 5: TC2 */
293 0U, /* 6: TD1 */
294 1U, /* 7: TD2 */
295 0U, /* 8: TE1 */
296 1U, /* 9: TE2 */
297 0U, /* 10: TF1 */
298 1U /* 11: TF2 */
299 };
300
301 static const uint8_t REG_SHIFT_TAB_FLTxE[] =
302 {
303 0U, /* LL_HRTIM_FAULT_1 */
304 8U, /* LL_HRTIM_FAULT_2 */
305 16U, /* LL_HRTIM_FAULT_3 */
306 24U, /* LL_HRTIM_FAULT_4 */
307 0U, /* LL_HRTIM_FAULT_5 */
308 8U /* LL_HRTIM_FAULT_6 */
309 };
310
311 static const uint8_t REG_SHIFT_TAB_FLTxF[] =
312 {
313 0U, /* LL_HRTIM_FAULT_1 */
314 8U, /* LL_HRTIM_FAULT_2 */
315 16U, /* LL_HRTIM_FAULT_3 */
316 24U, /* LL_HRTIM_FAULT_4 */
317 32U, /* LL_HRTIM_FAULT_5 */
318 40U /* LL_HRTIM_FAULT_6 */
319 };
320
321 static const uint8_t REG_SHIFT_TAB_FLTxCNT[] =
322 {
323 2U, /* LL_HRTIM_FAULT_1 */
324 10U, /* LL_HRTIM_FAULT_2 */
325 18U, /* LL_HRTIM_FAULT_3 */
326 26U, /* LL_HRTIM_FAULT_4 */
327 2U, /* LL_HRTIM_FAULT_5 */
328 10U /* LL_HRTIM_FAULT_6 */
329 };
330
331 static const uint8_t REG_SHIFT_TAB_FLTx[] =
332 {
333 0, /* LL_HRTIM_FAULT_1 */
334 1, /* LL_HRTIM_FAULT_2 */
335 2, /* LL_HRTIM_FAULT_3 */
336 3, /* LL_HRTIM_FAULT_4 */
337 4, /* LL_HRTIM_FAULT_5 */
338 5 /* LL_HRTIM_FAULT_6 */
339 };
340
341 static const uint8_t REG_SHIFT_TAB_INTLVD[] =
342 {
343 0U, /* 0: MASTER */
344 1U, /* 1: TIMER A */
345 1U, /* 2: TIMER B */
346 1U, /* 3: TIMER C */
347 1U, /* 4: TIMER D */
348 1U, /* 5: TIMER E */
349 1U, /* 6: TIMER F */
350 };
351
352 static const uint32_t REG_MASK_TAB_INTLVD[] =
353 {
354 0x000000E0U, /* 0: MASTER */
355 0x000001A0U, /* 1: TIMER A */
356 0x000001A0U, /* 2: TIMER B */
357 0x000001A0U, /* 3: TIMER C */
358 0x000001A0U, /* 4: TIMER D */
359 0x000001A0U, /* 5: TIMER E */
360 0x000001A0U, /* 6: TIMER F */
361 };
362
363 static const uint8_t REG_SHIFT_TAB_CPT[] =
364 {
365 12U, /* 1: TIMER A */
366 16U, /* 2: TIMER B */
367 20U, /* 3: TIMER C */
368 24U, /* 4: TIMER D */
369 28U, /* 5: TIMER E */
370 32U, /* 6: TIMER F */
371 };
372
373 static const uint32_t REG_MASK_TAB_CPT[] =
374 {
375 0xFFFF0000U, /* 1: TIMER A */
376 0xFFF0F000U, /* 2: TIMER B */
377 0xFF0FF000U, /* 3: TIMER C */
378 0xF0FFF000U, /* 4: TIMER D */
379 0x0FFFF000U, /* 5: TIMER E */
380 0xFFFFF000U, /* 6: TIMER F */
381 };
382
383 /**
384 * @}
385 */
386
387
388 /* Private constants ---------------------------------------------------------*/
389 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
390 * @{
391 */
392 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
393 HRTIM_CR1_TAUDIS |\
394 HRTIM_CR1_TBUDIS |\
395 HRTIM_CR1_TCUDIS |\
396 HRTIM_CR1_TDUDIS |\
397 HRTIM_CR1_TEUDIS |\
398 HRTIM_CR1_TFUDIS))
399
400 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
401 HRTIM_CR2_TASWU |\
402 HRTIM_CR2_TBSWU |\
403 HRTIM_CR2_TCSWU |\
404 HRTIM_CR2_TDSWU |\
405 HRTIM_CR2_TESWU |\
406 HRTIM_CR2_TFSWU))
407
408 #define HRTIM_CR2_SWAP_MASK ((uint32_t)(HRTIM_CR2_SWPA |\
409 HRTIM_CR2_SWPB |\
410 HRTIM_CR2_SWPC |\
411 HRTIM_CR2_SWPD |\
412 HRTIM_CR2_SWPE |\
413 HRTIM_CR2_SWPF))
414
415 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
416 HRTIM_CR2_TARST |\
417 HRTIM_CR2_TBRST |\
418 HRTIM_CR2_TCRST |\
419 HRTIM_CR2_TDRST |\
420 HRTIM_CR2_TERST |\
421 HRTIM_CR2_TFRST))
422
423 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
424 HRTIM_OENR_TA2OEN |\
425 HRTIM_OENR_TB1OEN |\
426 HRTIM_OENR_TB2OEN |\
427 HRTIM_OENR_TC1OEN |\
428 HRTIM_OENR_TC2OEN |\
429 HRTIM_OENR_TD1OEN |\
430 HRTIM_OENR_TD2OEN |\
431 HRTIM_OENR_TE1OEN |\
432 HRTIM_OENR_TE2OEN |\
433 HRTIM_OENR_TF1OEN |\
434 HRTIM_OENR_TF2OEN))
435
436 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
437 HRTIM_ODISR_TA2ODIS |\
438 HRTIM_ODISR_TB1ODIS |\
439 HRTIM_ODISR_TB2ODIS |\
440 HRTIM_ODISR_TC1ODIS |\
441 HRTIM_ODISR_TC2ODIS |\
442 HRTIM_ODISR_TD1ODIS |\
443 HRTIM_ODISR_TD2ODIS |\
444 HRTIM_ODISR_TE1ODIS |\
445 HRTIM_ODISR_TE2ODIS |\
446 HRTIM_ODISR_TF1ODIS |\
447 HRTIM_ODISR_TF2ODIS))
448
449 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
450 HRTIM_OUTR_IDLM1 |\
451 HRTIM_OUTR_IDLES1 |\
452 HRTIM_OUTR_FAULT1 |\
453 HRTIM_OUTR_CHP1 |\
454 HRTIM_OUTR_DIDL1))
455
456 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
457 HRTIM_EECR1_EE1POL |\
458 HRTIM_EECR1_EE1SNS |\
459 HRTIM_EECR1_EE1FAST))
460
461 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
462 HRTIM_FLTINR1_FLT1SRC_0 ))
463
464 #define HRTIM_FLT_SRC_1_MASK ((uint32_t)(HRTIM_FLTINR2_FLT6SRC_1 |\
465 HRTIM_FLTINR2_FLT5SRC_1 |\
466 HRTIM_FLTINR2_FLT4SRC_1 |\
467 HRTIM_FLTINR2_FLT3SRC_1 |\
468 HRTIM_FLTINR2_FLT2SRC_1 |\
469 HRTIM_FLTINR2_FLT1SRC_1))
470
471 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
472 HRTIM_BMCR_BMCLK |\
473 HRTIM_BMCR_BMOM))
474
475 /**
476 * @}
477 */
478
479
480 /* Private macros ------------------------------------------------------------*/
481 /* Exported types ------------------------------------------------------------*/
482 /* Exported constants --------------------------------------------------------*/
483 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
484 * @{
485 */
486
487 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
488 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
489 * @{
490 */
491 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
492 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
493 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
494 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
495 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
496 #define LL_HRTIM_ISR_FLT6 HRTIM_ISR_FLT6
497 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
498 #define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
499 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
500
501 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
502 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
503 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
504 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
505 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
506 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
507 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
508
509 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
510 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
511 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
512 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
513 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
514 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
515 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
516 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
517 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
518 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
519 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
520 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
521 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
522 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
523 /**
524 * @}
525 */
526
527 /** @defgroup HRTIM_LL_EC_IT IT Defines
528 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
529 * @{
530 */
531 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
532 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
533 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
534 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
535 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
536 #define LL_HRTIM_IER_FLT6IE HRTIM_IER_FLT6IE
537 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
538 #define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
539 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
540
541 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
542 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
543 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
544 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
545 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
546 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
547 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
548
549 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
550 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
551 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
552 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
553 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
554 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
555 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
556 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
557 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
558 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
559 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
560 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
561 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
562 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
563 /**
564 * @}
565 */
566
567 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
568 * @{
569 * @brief Constants defining defining the synchronization input source.
570 */
571 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
572 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
573 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
574 /**
575 * @}
576 */
577
578 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
579 * @{
580 * @brief Constants defining the source and event to be sent on the synchronization output.
581 */
582 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
583 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
584 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
585 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
586 /**
587 * @}
588 */
589
590 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
591 * @{
592 * @brief Constants defining the routing and conditioning of the synchronization output event.
593 */
594 #define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */
595 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
596 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
597 /**
598 * @}
599 */
600
601 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID
602 * @{
603 * @brief Constants identifying a timing unit.
604 */
605 #define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */
606 #define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
607 #define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
608 #define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
609 #define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
610 #define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
611 #define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
612 #define LL_HRTIM_TIMER_F HRTIM_MCR_TFCEN /*!< Timer F identifier */
613
614 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TFCEN | HRTIM_MCR_TACEN |\
615 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
616 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
617 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
618
619 /**
620 * @}
621 */
622
623 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
624 * @{
625 * @brief Constants identifying an HRTIM output.
626 */
627 #define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
628 #define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
629 #define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
630 #define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
631 #define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
632 #define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
633 #define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
634 #define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
635 #define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
636 #define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
637 #define LL_HRTIM_OUTPUT_TF1 HRTIM_OENR_TF1OEN /*!< Timer F - Output 1 identifier */
638 #define LL_HRTIM_OUTPUT_TF2 HRTIM_OENR_TF2OEN /*!< Timer F - Output 2 identifier */
639 /**
640 * @}
641 */
642
643 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
644 * @{
645 * @brief Constants identifying a compare unit.
646 */
647 #define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
648 #define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
649 /**
650 * @}
651 */
652
653 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
654 * @{
655 * @brief Constants identifying a capture unit.
656 */
657 #define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
658 #define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
659 /**
660 * @}
661 */
662
663 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID
664 * @{
665 * @brief Constants identifying a fault channel.
666 */
667 #define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
668 #define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
669 #define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
670 #define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
671 #define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
672 #define LL_HRTIM_FAULT_6 HRTIM_FLTR_FLT6EN /*!< Fault channel 6 identifier */
673 /**
674 * @}
675 */
676
677 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
678 * @{
679 * @brief Constants identifying an external event channel.
680 */
681 #define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
682 #define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
683 #define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
684 #define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
685 #define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
686 #define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
687 #define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
688 #define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
689 #define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
690 #define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
691 /**
692 * @}
693 */
694
695 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
696 * @{
697 * @brief Constants defining the state of an HRTIM output.
698 */
699 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
700 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
701 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
702 /**
703 * @}
704 */
705
706 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
707 * @{
708 * @brief Constants identifying an ADC trigger.
709 */
710 #define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
711 #define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
712 #define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
713 #define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
714 #define LL_HRTIM_ADCTRIG_5 ((uint32_t)0x00000004U) /*!< ADC trigger 5 identifier */
715 #define LL_HRTIM_ADCTRIG_6 ((uint32_t)0x00000005U) /*!< ADC trigger 6 identifier */
716 #define LL_HRTIM_ADCTRIG_7 ((uint32_t)0x00000006U) /*!< ADC trigger 7 identifier */
717 #define LL_HRTIM_ADCTRIG_8 ((uint32_t)0x00000007U) /*!< ADC trigger 8 identifier */
718 #define LL_HRTIM_ADCTRIG_9 ((uint32_t)0x00000008U) /*!< ADC trigger 9 identifier */
719 #define LL_HRTIM_ADCTRIG_10 ((uint32_t)0x00000009U) /*!< ADC trigger 10 identifier */
720 /**
721 * @}
722 */
723
724 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
725 * @{
726 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
727 */
728 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
729 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U /*!< HRTIM_ADCxR register update is triggered by the Timer A */
730 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U /*!< HRTIM_ADCxR register update is triggered by the Timer B */
731 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U /*!< HRTIM_ADCxR register update is triggered by the Timer C */
732 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U /*!< HRTIM_ADCxR register update is triggered by the Timer D */
733 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U /*!< HRTIM_ADCxR register update is triggered by the Timer E */
734 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U /*!< HRTIM_ADCxR register update is triggered by the Timer F */
735 /**
736 * @}
737 */
738
739 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
740 * @{
741 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
742 */
743 #define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */
744 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
745 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
746 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
747 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
748 #define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
749 #define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
750 #define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
751 #define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
752 #define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
753 #define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
754 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2 HRTIM_ADC1R_AD1TFC2 /*!< ADC Trigger on Timer F compare 2 */
755 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
756 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
757 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
758 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
759 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3 HRTIM_ADC1R_AD1TFC3 /*!< ADC Trigger on Timer F compare 3 */
760 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
761 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
762 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
763 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
764 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4 HRTIM_ADC1R_AD1TFC4 /*!< ADC Trigger on Timer F compare 4 */
765 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
766 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
767 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
768 #define LL_HRTIM_ADCTRIG_SRC13_TIMFPER HRTIM_ADC1R_AD1TFPER /*!< ADC Trigger on Timer F period */
769 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
770 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
771 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
772 #define LL_HRTIM_ADCTRIG_SRC13_TIMFRST HRTIM_ADC1R_AD1TFRST /*!< ADC Trigger on Timer F reset */
773 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
774 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
775 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
776 /**
777 * @}
778 */
779
780 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
781 * @{
782 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
783 */
784 #define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */
785 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
786 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
787 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
788 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
789 #define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
790 #define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
791 #define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
792 #define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
793 #define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
794 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
795 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
796 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2 HRTIM_ADC2R_AD2TFC2 /*!< ADC Trigger on Timer F compare 2 */
797 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
798 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
799 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
800 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3 HRTIM_ADC2R_AD2TFC3 /*!< ADC Trigger on Timer F compare 3 */
801 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
802 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
803 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
804 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4 HRTIM_ADC2R_AD2TFC4 /*!< ADC Trigger on Timer F compare 4 */
805 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
806 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
807 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
808 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
809 #define LL_HRTIM_ADCTRIG_SRC24_TIMFPER HRTIM_ADC2R_AD2TFPER /*!< ADC Trigger on Timer F period */
810 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
811 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
812 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
813 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
814 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
815 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
816 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
817 /**
818 * @}
819 */
820
821 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
822 * @{
823 * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10.
824 */
825 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
826 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
827 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
828 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
829 #define LL_HRTIM_ADCTRIG_SRC6810_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
830 #define LL_HRTIM_ADCTRIG_SRC6810_EEV6 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 6 */
831 #define LL_HRTIM_ADCTRIG_SRC6810_EEV7 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 7 */
832 #define LL_HRTIM_ADCTRIG_SRC6810_EEV8 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 8 */
833 #define LL_HRTIM_ADCTRIG_SRC6810_EEV9 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 9 */
834 #define LL_HRTIM_ADCTRIG_SRC6810_EEV10 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 10 */
835 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 2 */
836 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
837 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
838 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2 (uint32_t)0x0D /*!< ADC extended Trigger on Timer B Compare 2 */
839 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 4 */
840 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Period */
841 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2 (uint32_t)0x10 /*!< ADC extended Trigger on Timer C Compare 2 */
842 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4 (uint32_t)0x11 /*!< ADC extended Trigger on Timer C Compare 4 */
843 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Period */
844 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Reset and counter roll-over */
845 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2 (uint32_t)0x14 /*!< ADC extended Trigger on Timer D Compare 2 */
846 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 4 */
847 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Period */
848 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Reset and counter roll-over */
849 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 2 */
850 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 3 */
851 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4 (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Compare 4 */
852 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_RST (uint32_t)0x1B /*!< ADC extended Trigger on Timer E Reset and counter roll-over */
853 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 2 */
854 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 3 */
855 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4 (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Compare 4 */
856 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Period */
857 /**
858 * @}
859 */
860
861 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
862 * @{
863 * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9.
864 */
865 #define LL_HRTIM_ADCTRIG_SRC579_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
866 #define LL_HRTIM_ADCTRIG_SRC579_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
867 #define LL_HRTIM_ADCTRIG_SRC579_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
868 #define LL_HRTIM_ADCTRIG_SRC579_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
869 #define LL_HRTIM_ADCTRIG_SRC579_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
870 #define LL_HRTIM_ADCTRIG_SRC579_EEV1 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 1 */
871 #define LL_HRTIM_ADCTRIG_SRC579_EEV2 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 2 */
872 #define LL_HRTIM_ADCTRIG_SRC579_EEV3 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 3 */
873 #define LL_HRTIM_ADCTRIG_SRC579_EEV4 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 4 */
874 #define LL_HRTIM_ADCTRIG_SRC579_EEV5 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 5 */
875 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 3 */
876 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
877 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
878 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_RST (uint32_t)0x0D /*!< ADC extended Trigger on Timer A Period */
879 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 3 */
880 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4 (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Compare 4 */
881 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_PER (uint32_t)0x10 /*!< ADC extended Trigger on Timer B Period */
882 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_RST (uint32_t)0x11 /*!< ADC extended Trigger on Timer B Reset and counter roll-over */
883 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3 (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Compare 3 */
884 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4 (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Compare 4 */
885 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_PER (uint32_t)0x14 /*!< ADC extended Trigger on Timer C Period */
886 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 3 */
887 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4 (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Compare 4 */
888 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_PER (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Period */
889 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 3 */
890 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 4 */
891 #define LL_HRTIM_ADCTRIG_SRC579_TIME_PER (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Period */
892 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2 (uint32_t)0x1B /*!< ADC extended Trigger on Timer F Compare 2 */
893 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 3 */
894 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 4 */
895 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_PER (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Period */
896 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_RST (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Reset and counter roll-over */
897 /**
898 * @}
899 */
900
901 /** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
902 * @{
903 * @brief Constants defining the DLL calibration mode.
904 */
905 #define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT 0x00000000U /*!<Calibration is performed only once */
906 #define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
907 /**
908 * @}
909 */
910
911 /** @defgroup HRTIM_LL_EC_CALIBRATIONRATE DLL CALIBRATION RATE
912 * @{
913 * @brief Constants defining the DLL calibration periods (in micro seconds).
914 */
915 #define LL_HRTIM_DLLCALIBRATION_RATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
916 #define LL_HRTIM_DLLCALIBRATION_RATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
917 #define LL_HRTIM_DLLCALIBRATION_RATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
918 #define LL_HRTIM_DLLCALIBRATION_RATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
919 /**
920 * @}
921 */
922
923 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
924 * @{
925 * @brief Constants defining timer high-resolution clock prescaler ratio.
926 */
927 #define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
928 #define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
929 #define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
930 #define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
931 #define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
932 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
933 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
934 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
935 /**
936 * @}
937 */
938
939 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
940 * @{
941 * @brief Constants defining timer counter operating mode.
942 */
943 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
944 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
945 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
946 /**
947 * @}
948 */
949
950 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
951 * @{
952 * @brief Constants defining on which output the DAC synchronization event is sent.
953 */
954 #define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */
955 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
956 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
957 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
958 /**
959 * @}
960 */
961
962 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
963 * @{
964 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
965 */
966 #define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */
967 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
968 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
969 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
970 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
971 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
972 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
973 #define LL_HRTIM_UPDATETRIG_TIMER_F HRTIM_TIMCR_TFU /*!< Register update is triggered by the timer F update */
974 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
975 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
976 /**
977 * @}
978 */
979
980 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
981 * @{
982 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
983 */
984 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
985 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
986 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
987 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
988 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
989 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
990 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
991 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
992 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
993 /**
994 * @}
995 */
996
997 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
998 * @{
999 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
1000 */
1001 #define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */
1002 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
1003 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
1004 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
1005 /**
1006 * @}
1007 */
1008
1009 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
1010 * @{
1011 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
1012 */
1013 #define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */
1014 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
1015 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
1016 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
1017 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
1018 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
1019 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
1020 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
1021 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
1022 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
1023 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
1024 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
1025 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
1026 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
1027 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
1028 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
1029 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
1030 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
1031 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
1032 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1033 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1034 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1035 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1036 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1037 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1038 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1039 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1040 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1041 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1042 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1043 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1044 #define LL_HRTIM_RESETTRIG_OTHER5_CMP1 HRTIM_RSTR_TIMFCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1045 #define LL_HRTIM_RESETTRIG_OTHER5_CMP2 HRTIM_RSTR_TIMFCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1046 /**
1047 * @}
1048 */
1049
1050 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
1051 * @{
1052 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
1053 */
1054 #define LL_HRTIM_CAPTURETRIG_NONE (uint64_t)0 /*!< Capture trigger is disabled */
1055 #define LL_HRTIM_CAPTURETRIG_SW (uint64_t)HRTIM_CPT1CR_SWCPT /*!< The sw event triggers the Capture */
1056 #define LL_HRTIM_CAPTURETRIG_UPDATE (uint64_t)HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
1057 #define LL_HRTIM_CAPTURETRIG_EEV_1 (uint64_t)HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
1058 #define LL_HRTIM_CAPTURETRIG_EEV_2 (uint64_t)HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
1059 #define LL_HRTIM_CAPTURETRIG_EEV_3 (uint64_t)HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
1060 #define LL_HRTIM_CAPTURETRIG_EEV_4 (uint64_t)HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
1061 #define LL_HRTIM_CAPTURETRIG_EEV_5 (uint64_t)HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
1062 #define LL_HRTIM_CAPTURETRIG_EEV_6 (uint64_t)HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
1063 #define LL_HRTIM_CAPTURETRIG_EEV_7 (uint64_t)HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
1064 #define LL_HRTIM_CAPTURETRIG_EEV_8 (uint64_t)HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
1065 #define LL_HRTIM_CAPTURETRIG_EEV_9 (uint64_t)HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
1066 #define LL_HRTIM_CAPTURETRIG_EEV_10 (uint64_t)HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
1067 #define LL_HRTIM_CAPTURETRIG_TA1_SET (uint64_t)(HRTIM_CPT1CR_TA1SET ) <<32 /*!< Capture is triggered by TA1 output inactive to active transition */
1068 #define LL_HRTIM_CAPTURETRIG_TA1_RESET (uint64_t)(HRTIM_CPT1CR_TA1RST ) <<32 /*!< Capture is triggered by TA1 output active to inactive transition */
1069 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMACMP1 ) <<32 /*!< Timer A Compare 1 triggers Capture */
1070 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMACMP2 ) <<32 /*!< Timer A Compare 2 triggers Capture */
1071 #define LL_HRTIM_CAPTURETRIG_TB1_SET (uint64_t)(HRTIM_CPT1CR_TB1SET ) <<32 /*!< Capture is triggered by TB1 output inactive to active transition */
1072 #define LL_HRTIM_CAPTURETRIG_TB1_RESET (uint64_t)(HRTIM_CPT1CR_TB1RST ) <<32 /*!< Capture is triggered by TB1 output active to inactive transition */
1073 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMBCMP1 ) <<32 /*!< Timer B Compare 1 triggers Capture */
1074 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMBCMP2 ) <<32 /*!< Timer B Compare 2 triggers Capture */
1075 #define LL_HRTIM_CAPTURETRIG_TC1_SET (uint64_t)(HRTIM_CPT1CR_TC1SET ) <<32 /*!< Capture is triggered by TC1 output inactive to active transition */
1076 #define LL_HRTIM_CAPTURETRIG_TC1_RESET (uint64_t)(HRTIM_CPT1CR_TC1RST ) <<32 /*!< Capture is triggered by TC1 output active to inactive transition */
1077 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMCCMP1 ) <<32 /*!< Timer C Compare 1 triggers Capture */
1078 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMCCMP2 ) <<32 /*!< Timer C Compare 2 triggers Capture */
1079 #define LL_HRTIM_CAPTURETRIG_TD1_SET (uint64_t)(HRTIM_CPT1CR_TD1SET ) <<32 /*!< Capture is triggered by TD1 output inactive to active transition */
1080 #define LL_HRTIM_CAPTURETRIG_TD1_RESET (uint64_t)(HRTIM_CPT1CR_TD1RST ) <<32 /*!< Capture is triggered by TD1 output active to inactive transition */
1081 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMDCMP1 ) <<32 /*!< Timer D Compare 1 triggers Capture */
1082 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMDCMP2 ) <<32 /*!< Timer D Compare 2 triggers Capture */
1083 #define LL_HRTIM_CAPTURETRIG_TE1_SET (uint64_t)(HRTIM_CPT1CR_TE1SET ) <<32 /*!< Capture is triggered by TE1 output inactive to active transition */
1084 #define LL_HRTIM_CAPTURETRIG_TE1_RESET (uint64_t)(HRTIM_CPT1CR_TE1RST ) <<32 /*!< Capture is triggered by TE1 output active to inactive transition */
1085 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMECMP1 ) <<32 /*!< Timer E Compare 1 triggers Capture */
1086 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMECMP2 ) <<32 /*!< Timer E Compare 2 triggers Capture */
1087 #define LL_HRTIM_CAPTURETRIG_TF1_SET (uint64_t)(HRTIM_CPT1CR_TF1SET ) <<32 /*!< Capture is triggered by TF1 output inactive to active transition */
1088 #define LL_HRTIM_CAPTURETRIG_TF1_RESET (uint64_t)(HRTIM_CPT1CR_TF1RST ) <<32 /*!< Capture is triggered by TF1 output active to inactive transition */
1089 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMFCMP1 ) <<32 /*!< Timer F Compare 1 triggers Capture */
1090 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMFCMP2 ) <<32 /*!< Timer F Compare 2 triggers Capture */
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
1096 * @{
1097 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
1098 */
1099 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
1100 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
1101 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
1102 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
1103 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
1104 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
1105 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
1106 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
1107
1108 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
1109 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
1110 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
1111 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
1112 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
1113 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
1114 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
1115 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
1121 * @{
1122 * @brief Constants defining how the timer behaves during a burst mode operation.
1123 */
1124 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
1125 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
1126 /**
1127 * @}
1128 */
1129
1130 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
1131 * @{
1132 * @brief Constants defining the registers that can be written during a burst DMA operation.
1133 */
1134 #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
1135 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
1136 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
1137 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
1138 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
1139 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
1140 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
1141 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
1142 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
1143 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
1144 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
1145 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
1146 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
1147 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
1148 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
1149 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
1150 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
1151 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
1152 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
1153 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
1154 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
1155 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
1156 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
1157 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
1158 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
1159 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
1160 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
1161 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
1162 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
1163 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
1164 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
1165 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
1166 #define LL_HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */
1167 #define LL_HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
1173 * @{
1174 * @brief Constants defining on which output the signal is currently applied in push-pull mode.
1175 */
1176 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
1177 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
1178 /**
1179 * @}
1180 */
1181
1182 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
1183 * @{
1184 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
1185 */
1186 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
1187 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
1188 /**
1189 * @}
1190 */
1191
1192 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
1193 * @{
1194 * @brief Constants defining the event filtering applied to external events by a timer.
1195 */
1196 #define LL_HRTIM_EEFLTR_NONE (0x00000000U)
1197 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
1198 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
1199 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
1200 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
1201 /* Blanking Filter for TIMER A */
1202 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1203 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1204 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1205 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1206 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1207 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1208 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1209 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1210 /* Blanking Filter for TIMER B */
1211 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1212 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1213 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1214 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1215 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1216 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1217 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1218 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1219 /* Blanking Filter for TIMER C */
1220 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1221 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1222 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1223 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1224 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1225 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1226 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1227 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1228 /* Blanking Filter for TIMER D */
1229 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1230 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1231 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1232 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1233 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1234 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1235 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1236 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1237 /* Blanking Filter for TIMER E */
1238 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1239 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1240 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1241 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1242 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1243 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1244 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1245 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1246 /* Blanking Filter for TIMER F */
1247 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1248 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1249 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1250 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1251 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1252 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1253 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1254 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1255
1256 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
1257 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
1258 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
1259 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
1260 /**
1261 * @}
1262 */
1263
1264 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
1265 * @{
1266 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
1267 */
1268 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
1269 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
1270 /**
1271 * @}
1272 */
1273
1274 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
1275 * @{
1276 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
1277 */
1278 #define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */
1279 #define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
1280 #define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
1281 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
1282 #define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
1283 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
1284 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
1285 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
1286 /**
1287 * @}
1288 */
1289
1290 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
1291 * @{
1292 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
1293 */
1294 #define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */
1295 #define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
1296 /**
1297 * @}
1298 */
1299
1300 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
1301 * @{
1302 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
1303 */
1304 #define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */
1305 #define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
1306 /**
1307 * @}
1308 */
1309
1310 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
1311 * @{
1312 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
1313 */
1314 #define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */
1315 #define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
1316 #define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
1317 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
1318 #define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
1319 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
1320 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
1321 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
1322 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
1323 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
1324 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
1325 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
1326 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
1327 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
1328 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
1329 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
1330 /**
1331 * @}
1332 */
1333
1334 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
1335 * @{
1336 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
1337 */
1338 #define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */
1339 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
1340 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
1341 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
1342 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
1343 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
1344 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
1345 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
1346 /**
1347 * @}
1348 */
1349
1350 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
1351 * @{
1352 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
1353 */
1354 #define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */
1355 #define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
1356 #define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
1357 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
1358 #define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
1359 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
1360 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
1361 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
1362 #define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
1363 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
1364 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
1365 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
1366 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
1367 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
1368 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
1369 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
1370 /**
1371 * @}
1372 */
1373
1374 /** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
1375 * @{
1376 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
1377 */
1378 #define LL_HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
1379 #define LL_HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
1380 #define LL_HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */
1381 #define LL_HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */
1382 #define LL_HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */
1383 #define LL_HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */
1384 #define LL_HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */
1385 #define LL_HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */
1386 #define LL_HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */
1387 #define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */
1388 #define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */
1389 #define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */
1390 /* Timer Events mapping for Timer A */
1391 #define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1392 #define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1393 #define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1394 #define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1395 #define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1396 #define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1397 #define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1398 #define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1399 #define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1400 /* Timer Events mapping for Timer B */
1401 #define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1402 #define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1403 #define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1404 #define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1405 #define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1406 #define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1407 #define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1408 #define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1409 #define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1410 /* Timer Events mapping for Timer C */
1411 #define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1412 #define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1413 #define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1414 #define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1415 #define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1416 #define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1417 #define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1418 #define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1419 #define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1420 /* Timer Events mapping for Timer D */
1421 #define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1422 #define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1423 #define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1424 #define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1425 #define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1426 #define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1427 #define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1428 #define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1429 #define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1430 /* Timer Events mapping for Timer E */
1431 #define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1432 #define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1433 #define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1434 #define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1435 #define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1436 #define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1437 #define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1438 #define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1439 #define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1440 /* Timer Events mapping for Timer F */
1441 #define LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1442 #define LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1443 #define LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1444 #define LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1445 #define LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1446 #define LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1447 #define LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1448 #define LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1449 #define LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1450 #define LL_HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */
1451 #define LL_HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */
1452 #define LL_HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */
1453 #define LL_HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */
1454 #define LL_HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */
1455 #define LL_HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */
1456 #define LL_HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */
1457 #define LL_HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */
1458 #define LL_HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */
1459 #define LL_HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */
1460 #define LL_HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */
1461 /**
1462 * @}
1463 */
1464
1465 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
1466 * @{
1467 * @brief Constants defining the events that can be selected to configure the
1468 * set crossbar of a timer output
1469 */
1470 #define LL_HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
1471 #define LL_HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
1472 #define LL_HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
1473 #define LL_HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
1474 #define LL_HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
1475 #define LL_HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
1476 #define LL_HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
1477 #define LL_HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
1478 #define LL_HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
1479 #define LL_HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
1480 #define LL_HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
1481 #define LL_HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
1482 /* Timer Events mapping for Timer A */
1483 #define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1484 #define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1485 #define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1486 #define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1487 #define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1488 #define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1489 #define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1490 #define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1491 #define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1492 /* Timer Events mapping for Timer B */
1493 #define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1494 #define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1495 #define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1496 #define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1497 #define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1498 #define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1499 #define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1500 #define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1501 #define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1502 /* Timer Events mapping for Timer C */
1503 #define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1504 #define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1505 #define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1506 #define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1507 #define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1508 #define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1509 #define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1510 #define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1511 #define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1512 /* Timer Events mapping for Timer D */
1513 #define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1514 #define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1515 #define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1516 #define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1517 #define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1518 #define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1519 #define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1520 #define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1521 #define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1522 /* Timer Events mapping for Timer E */
1523 #define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1524 #define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1525 #define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1526 #define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1527 #define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1528 #define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1529 #define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1530 #define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1531 #define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1532 /* Timer Events mapping for Timer F */
1533 #define LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1534 #define LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1535 #define LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1536 #define LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1537 #define LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1538 #define LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1539 #define LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1540 #define LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1541 #define LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1542 #define LL_HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
1543 #define LL_HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
1544 #define LL_HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
1545 #define LL_HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
1546 #define LL_HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
1547 #define LL_HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
1548 #define LL_HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
1549 #define LL_HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
1550 #define LL_HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
1551 #define LL_HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
1552 #define LL_HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
1553 /**
1554 * @}
1555 */
1556
1557 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
1558 * @{
1559 * @brief Constants defining the polarity of a timer output.
1560 */
1561 #define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */
1562 #define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
1563 /**
1564 * @}
1565 */
1566
1567 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
1568 * @{
1569 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
1570 */
1571 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
1572 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1573 /**
1574 * @}
1575 */
1576
1577 /** @defgroup HRTIM_LL_EC_INTLVD_MODE INTLVD MODE
1578 * @{
1579 * @brief Constants defining the interleaved mode of an HRTIM Timer instance.
1580 */
1581 #define LL_HRTIM_INTERLEAVED_MODE_DISABLED 0x000U /*!< HRTIM interleaved Mode is disabled */
1582 #define LL_HRTIM_INTERLEAVED_MODE_DUAL HRTIM_MCR_HALF /*!< HRTIM interleaved Mode is Dual */
1583 #define LL_HRTIM_INTERLEAVED_MODE_TRIPLE HRTIM_MCR_INTLVD_0 /*!< HRTIM interleaved Mode is Triple */
1584 #define LL_HRTIM_INTERLEAVED_MODE_QUAD HRTIM_MCR_INTLVD_1 /*!< HRTIM interleaved Mode is Quad */
1585 /**
1586 * @}
1587 */
1588 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
1589 * @{
1590 * @brief Constants defining the half mode of an HRTIM Timer instance.
1591 */
1592 #define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */
1593 #define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */
1594 /**
1595 * @}
1596 */
1597
1598 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
1599 * @{
1600 * @brief Constants defining the output level when output is in IDLE state
1601 */
1602 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
1603 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1604 /**
1605 * @}
1606 */
1607
1608 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
1609 * @{
1610 * @brief Constants defining the output level when output is in FAULT state.
1611 */
1612 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
1613 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1614 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1615 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1616 /**
1617 * @}
1618 */
1619
1620 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
1621 * @{
1622 * @brief Constants defining whether or not chopper mode is enabled for a timer output.
1623 */
1624 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
1625 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1626 /**
1627 * @}
1628 */
1629
1630 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
1631 * @{
1632 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
1633 during a programmable period before the output takes its idle state.
1634 */
1635 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
1636 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1637 /**
1638 * @}
1639 */
1640 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
1641 * @{
1642 * @brief Constants defining the level of a timer output.
1643 */
1644 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
1645 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
1646 /**
1647 * @}
1648 */
1649
1650 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
1651 * @{
1652 * @brief Constants defining available sources associated to external events.
1653 */
1654 #define LL_HRTIM_EEV1SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 1 */
1655 #define LL_HRTIM_EEV2SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 2 */
1656 #define LL_HRTIM_EEV3SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 3 */
1657 #define LL_HRTIM_EEV4SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 4 */
1658 #define LL_HRTIM_EEV5SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 5 */
1659 #define LL_HRTIM_EEV6SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 6 */
1660 #define LL_HRTIM_EEV7SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 7 */
1661 #define LL_HRTIM_EEV8SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 8 */
1662 #define LL_HRTIM_EEV9SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 9 */
1663 #define LL_HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 10 */
1664 #define LL_HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 1 */
1665 #define LL_HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 2 */
1666 #define LL_HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 3 */
1667 #define LL_HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 4 */
1668 #define LL_HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 5 */
1669 #define LL_HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 6 */
1670 #define LL_HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 7 */
1671 #define LL_HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 8 */
1672 #define LL_HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 9 */
1673 #define LL_HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 10 */
1674 #define LL_HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 1 */
1675 #define LL_HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 2 */
1676 #define LL_HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 3 */
1677 #define LL_HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 4 */
1678 #define LL_HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 5 */
1679 #define LL_HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 6 */
1680 #define LL_HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 7 */
1681 #define LL_HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 8 */
1682 #define LL_HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 9 */
1683 #define LL_HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 10 */
1684 #define LL_HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 1 */
1685 #define LL_HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 2 */
1686 #define LL_HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 3 */
1687 #define LL_HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 4 */
1688 #define LL_HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 5 */
1689 #define LL_HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 6 */
1690 #define LL_HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 7 */
1691 #define LL_HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 8 */
1692 #define LL_HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 9 */
1693 #define LL_HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 10 */
1694 /**
1695 * @}
1696 */
1697 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
1698 * @{
1699 * @brief Constants defining the polarity of an external event.
1700 */
1701 #define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */
1702 #define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
1703 /**
1704 * @}
1705 */
1706
1707 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
1708 * @{
1709 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
1710 */
1711 #define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */
1712 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1713 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1714 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1715 /**
1716 * @}
1717 */
1718
1719 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
1720 * @{
1721 * @brief Constants defining whether or not an external event is programmed in fast mode.
1722 */
1723 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1724 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1725 /**
1726 * @}
1727 */
1728
1729 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
1730 * @{
1731 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
1732 */
1733 #define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */
1734 #define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
1735 #define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
1736 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
1737 #define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
1738 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
1739 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
1740 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
1741 #define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
1742 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
1743 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
1744 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
1745 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
1746 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
1747 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
1748 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
1749 /**
1750 * @}
1751 */
1752
1753 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
1754 * @{
1755 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
1756 */
1757 #define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */
1758 #define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
1759 #define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
1760 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
1761 /**
1762 * @}
1763 */
1764
1765 /** @defgroup HRTIM_LL_EC_EE_COUNTER EXTERNAL EVENT A or B COUNTER
1766 * @{
1767 * @brief Constants defining the external event counter.
1768 */
1769 #define LL_HRTIM_EE_COUNTER_A ((uint32_t)0U) /*!< External Event A Counter */
1770 #define LL_HRTIM_EE_COUNTER_B ((uint32_t)16U) /*!< External Event B Counter */
1771 /**
1772 * @}
1773 */
1774
1775 /** @defgroup HRTIM_LL_EC_EE_COUNTERRSTMODE EXTERNAL EVENT A or B RESET MODE
1776 * @{
1777 * @brief Constants defining the external event reset mode.
1778 */
1779 #define LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL ((uint32_t)0U) /*!< External Event counter is reset on each reset / roll-over event */
1780 #define LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL ((uint32_t)HRTIM_EEFR3_EEVARSTM) /*!< External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */
1781 /**
1782 * @}
1783 */
1784
1785 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
1786 * @{
1787 * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
1788 */
1789 #define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */
1790 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC_0 /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1791 #define LL_HRTIM_FLT_SRC_EEVINPUT HRTIM_FLTINR2_FLT1SRC_1 /*!< Fault input is external event pin */
1792 /**
1793 * @}
1794 */
1795
1796 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
1797 * @{
1798 * @brief Constants defining the polarity of a fault event.
1799 */
1800 #define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */
1801 #define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
1802 /**
1803 * @}
1804 */
1805
1806 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
1807 * @{
1808 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
1809 */
1810 #define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */
1811 #define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1812 #define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1813 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1814 #define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
1815 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1816 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1817 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1818 #define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
1819 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1820 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1821 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1822 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1823 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1824 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1825 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1826 /**
1827 * @}
1828 */
1829
1830 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
1831 * @{
1832 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
1833 */
1834 #define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */
1835 #define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
1836 #define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
1837 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
1838 /**
1839 * @}
1840 */
1841
1842 /** @defgroup HRTIM_LL_EC_FLT_BLKS FAULT BLANKING Source
1843 * @{
1844 * @brief Constants defining the Blanking Source of a fault event.
1845 */
1846 #define LL_HRTIM_FLT_BLANKING_RSTALIGNED 0x00000000U /*!< Fault blanking source is Reset-aligned */
1847 #define LL_HRTIM_FLT_BLANKING_MOVING (HRTIM_FLTINR3_FLT1BLKS) /*!< Fault blanking source is Moving window */
1848 /**
1849 * @}
1850 */
1851
1852 /** @defgroup HRTIM_LL_EC_FLT_RSTM FAULT Counter RESET Mode
1853 * @{
1854 * @brief Constants defining the Counter RESet Mode of a fault event.
1855 */
1856 #define LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL 0x00000000U /*!< Fault counter is reset on each reset / roll-over event */
1857 #define LL_HRTIM_FLT_COUNTERRST_CONDITIONAL (HRTIM_FLTINR3_FLT1RSTM) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting
1858 period. */
1859 /**
1860 * @}
1861 */
1862
1863 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
1864 * @{
1865 * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
1866 */
1867 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
1868 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1869 /**
1870 * @}
1871 */
1872
1873 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
1874 * @{
1875 * @brief Constants defining the clock source for the burst mode counter.
1876 */
1877 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1878 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1879 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1880 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1881 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1882 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1883 #define LL_HRTIM_BM_CLKSRC_TIMER_F (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
1884 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1885 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1886 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1887 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1888 /**
1889 * @}
1890 */
1891
1892 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
1893 * @{
1894 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
1895 */
1896 #define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */
1897 #define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
1898 #define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
1899 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
1900 #define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
1901 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
1902 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
1903 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
1904 #define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
1905 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
1906 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
1907 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
1908 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
1909 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
1910 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
1911 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
1912 /**
1913 * @}
1914 */
1915
1916 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
1917 * @{
1918 * @brief Constants defining the events that can be used to trig the burst mode operation.
1919 */
1920 #define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */
1921 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
1922 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
1923 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
1924 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
1925 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
1926 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
1927 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
1928 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
1929 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
1930 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
1931 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
1932 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
1933 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
1934 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
1935 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
1936 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
1937 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
1938 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
1939 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
1940 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
1941 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
1942 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
1943 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
1944 #define LL_HRTIM_BM_TRIG_TIMF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset event is starting the burst mode operation */
1945 #define LL_HRTIM_BM_TRIG_TIMF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition event is starting the burst mode operation */
1946 #define LL_HRTIM_BM_TRIG_TIMF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 event is starting the burst mode operation */
1947 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
1948 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
1949 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
1950 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
1951 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
1952 /**
1953 * @}
1954 */
1955
1956 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
1957 * @{
1958 * @brief Constants defining the operating state of the burst mode controller.
1959 */
1960 #define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */
1961 #define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */
1962 /**
1963 * @}
1964 */
1965
1966 /** @defgroup HRTIM_LL_COUNTER_MODE Counter Mode
1967 * @{
1968 * @brief Constants defining the Counter Up Down Mode.
1969 */
1970 #define LL_HRTIM_COUNTING_MODE_UP 0x00000000U /*!< counter is operating in up-counting mode */
1971 #define LL_HRTIM_COUNTING_MODE_UP_DOWN HRTIM_TIMCR2_UDM /*!< counter is operating in up-down counting mode */
1972 /**
1973 * @}
1974 */
1975
1976 /** @defgroup HRTIM_LL_COUNTER_Roll-Over counter Mode
1977 * @{
1978 * @brief Constants defining the Roll-Over counter Mode.
1979 */
1980 #define LL_HRTIM_ROLLOVER_MODE_PER 2U /*!< Event generated when counter reaches period value ('crest' mode) */
1981 #define LL_HRTIM_ROLLOVER_MODE_RST 1U /*!< Event generated when counter equals 0 ('valley' mode) */
1982 #define LL_HRTIM_ROLLOVER_MODE_BOTH 0U /*!< Event generated when counter reach both conditions (0 or HRTIM_PERxR value) */
1983 /**
1984 * @}
1985 */
1986
1987 /** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
1988 * @{
1989 * @brief Constants defining how the timer counter operates.
1990 */
1991 #define LL_HRTIM_TRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */
1992 #define LL_HRTIM_TRIGHALF_ENABLED HRTIM_TIMCR2_TRGHLF /*!< Timer Compare 2 register is behaving in triggered-half mode */
1993 /**
1994 * @}
1995 */
1996
1997 /** @defgroup HRTIM_LL_COUNTER_Compare Greater than compare PWM Mode
1998 * @{
1999 * @brief Constants defining the greater than compare 1 or 3 PWM Mode.
2000 */
2001 #define LL_HRTIM_GTCMP1_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
2002 #define LL_HRTIM_GTCMP1_GREATER HRTIM_TIMCR2_GTCMP1 /*!< event is generated when counter is greater than compare value */
2003 #define LL_HRTIM_GTCMP3_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
2004 #define LL_HRTIM_GTCMP3_GREATER HRTIM_TIMCR2_GTCMP3 /*!< event is generated when counter is greater than compare value */
2005 /**
2006 * @}
2007 */
2008
2009 /** @defgroup HRTIM_LL_COUNTER_DCDE Enabling the Dual Channel DAC Triggering
2010 * @{
2011 * @brief Constants enabling the Dual Channel DAC Reset trigger mechanism.
2012 */
2013 #define LL_HRTIM_DCDE_DISABLED 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
2014 #define LL_HRTIM_DCDE_ENABLED HRTIM_TIMCR2_DCDE /*!< Dual Channel DAC trigger is generated on output 1 set event */
2015 /**
2016 * @}
2017 */
2018
2019 /** @defgroup HRTIM_LL_COUNTER_DCDR Dual Channel DAC Reset Trigger
2020 * @{
2021 * @brief Constants defining the Dual Channel DAC Reset trigger.
2022 */
2023 #define LL_HRTIM_DCDR_COUNTER 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
2024 #define LL_HRTIM_DCDR_OUT1SET HRTIM_TIMCR2_DCDR /*!< Dual Channel DAC trigger is generated on output 1 set event */
2025 /**
2026 * @}
2027 */
2028
2029 /** @defgroup HRTIM_LL_COUNTER_DCDS Dual Channel DAC Step trigger
2030 * @{
2031 * @brief Constants defining the Dual Channel DAC Step trigger.
2032 */
2033 #define LL_HRTIM_DCDS_CMP2 0x00000000U /*!< trigger is generated on compare 2 event */
2034 #define LL_HRTIM_DCDS_OUT1RST HRTIM_TIMCR2_DCDS /*!< trigger is generated on output 1 reset event */
2035 /**
2036 * @}
2037 */
2038
2039 /**
2040 * @}
2041 */
2042
2043 /* Exported macro ------------------------------------------------------------*/
2044 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
2045 * @{
2046 */
2047
2048 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
2049 * @{
2050 */
2051
2052 /**
2053 * @brief Write a value in HRTIM register
2054 * @param __INSTANCE__ HRTIM Instance
2055 * @param __REG__ Register to be written
2056 * @param __VALUE__ Value to be written in the register
2057 * @retval None
2058 */
2059 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2060
2061 /**
2062 * @brief Read a value in HRTIM register
2063 * @param __INSTANCE__ HRTIM Instance
2064 * @param __REG__ Register to be read
2065 * @retval Register value
2066 */
2067 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2068 /**
2069 * @}
2070 */
2071
2072 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
2073 * @{
2074 */
2075 /**
2076 * @brief HELPER macro returning the output state from output enable/disable status
2077 * @param __OUTPUT_STATUS_EN__ output enable status
2078 * @param __OUTPUT_STATUS_DIS__ output Disable status
2079 * @retval Returned value can be one of the following values:
2080 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
2081 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
2082 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
2083 */
2084 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
2085 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
2086 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
2087 /**
2088 * @}
2089 */
2090
2091 /**
2092 * @}
2093 */
2094
2095 /* Exported functions --------------------------------------------------------*/
2096 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
2097 * @{
2098 */
2099 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
2100 * @{
2101 */
2102
2103 /**
2104 * @brief Select the HRTIM synchronization input source.
2105 * @note This function must not be called when the concerned timer(s) is (are) enabled .
2106 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
2107 * @param HRTIMx High Resolution Timer instance
2108 * @param SyncInSrc This parameter can be one of the following values:
2109 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
2110 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
2111 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
2112 * @retval None
2113 */
LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncInSrc)2114 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
2115 {
2116 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
2117 }
2118
2119 /**
2120 * @brief Get actual HRTIM synchronization input source.
2121 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
2122 * @param HRTIMx High Resolution Timer instance
2123 * @retval SyncInSrc Returned value can be one of the following values:
2124 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
2125 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
2126 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
2127 */
LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef * HRTIMx)2128 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx)
2129 {
2130 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
2131 }
2132
2133 /**
2134 * @brief Configure the HRTIM synchronization output.
2135 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
2136 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
2137 * @param HRTIMx High Resolution Timer instance
2138 * @param Config This parameter can be one of the following values:
2139 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2140 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2141 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2142 * @param Src This parameter can be one of the following values:
2143 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2144 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2145 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2146 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2147 * @retval None
2148 */
LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef * HRTIMx,uint32_t Config,uint32_t Src)2149 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
2150 {
2151 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
2152 }
2153
2154 /**
2155 * @brief Set the routing and conditioning of the synchronization output event.
2156 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
2157 * @note This function can be called only when the master timer is enabled.
2158 * @param HRTIMx High Resolution Timer instance
2159 * @param SyncOutConfig This parameter can be one of the following values:
2160 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2161 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2162 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2163 * @retval None
2164 */
LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutConfig)2165 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
2166 {
2167 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
2168 }
2169
2170 /**
2171 * @brief Get actual routing and conditioning of the synchronization output event.
2172 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
2173 * @param HRTIMx High Resolution Timer instance
2174 * @retval SyncOutConfig Returned value can be one of the following values:
2175 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2176 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2177 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2178 */
LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef * HRTIMx)2179 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx)
2180 {
2181 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
2182 }
2183
2184 /**
2185 * @brief Set the source and event to be sent on the HRTIM synchronization output.
2186 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
2187 * @param HRTIMx High Resolution Timer instance
2188 * @param SyncOutSrc This parameter can be one of the following values:
2189 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2190 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2191 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2192 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2193 * @retval None
2194 */
LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutSrc)2195 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
2196 {
2197 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
2198 }
2199
2200 /**
2201 * @brief Get actual source and event sent on the HRTIM synchronization output.
2202 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
2203 * @param HRTIMx High Resolution Timer instance
2204 * @retval SyncOutSrc Returned value can be one of the following values:
2205 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2206 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2207 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2208 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2209 */
LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef * HRTIMx)2210 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx)
2211 {
2212 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
2213 }
2214
2215 /**
2216 * @brief Disable (temporarily) update event generation.
2217 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
2218 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
2219 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
2220 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
2221 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
2222 * CR1 TEUDIS LL_HRTIM_SuspendUpdate\n
2223 * CR1 TFUDIS LL_HRTIM_SuspendUpdate
2224 * @note Allow to temporarily disable the transfer from preload to active
2225 * registers, whatever the selected update event. This allows to modify
2226 * several registers in multiple timers.
2227 * @param HRTIMx High Resolution Timer instance
2228 * @param Timers This parameter can be a combination of the following values:
2229 * @arg @ref LL_HRTIM_TIMER_MASTER
2230 * @arg @ref LL_HRTIM_TIMER_A
2231 * @arg @ref LL_HRTIM_TIMER_B
2232 * @arg @ref LL_HRTIM_TIMER_C
2233 * @arg @ref LL_HRTIM_TIMER_D
2234 * @arg @ref LL_HRTIM_TIMER_E
2235 * @arg @ref LL_HRTIM_TIMER_F
2236 * @retval None
2237 */
LL_HRTIM_SuspendUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2238 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2239 {
2240 /* clear register before applying the new value */
2241 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((LL_HRTIM_TIMER_ALL >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2242 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2243 }
2244
2245 /**
2246 * @brief Enable update event generation.
2247 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
2248 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
2249 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
2250 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
2251 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
2252 * CR1 TEUDIS LL_HRTIM_ResumeUpdate\n
2253 * CR1 TFUDIS LL_HRTIM_ResumeUpdate
2254 * @note The regular update event takes place.
2255 * @param HRTIMx High Resolution Timer instance
2256 * @param Timers This parameter can be a combination of the following values:
2257 * @arg @ref LL_HRTIM_TIMER_MASTER
2258 * @arg @ref LL_HRTIM_TIMER_A
2259 * @arg @ref LL_HRTIM_TIMER_B
2260 * @arg @ref LL_HRTIM_TIMER_C
2261 * @arg @ref LL_HRTIM_TIMER_D
2262 * @arg @ref LL_HRTIM_TIMER_E
2263 * @arg @ref LL_HRTIM_TIMER_F
2264 * @retval None
2265 */
LL_HRTIM_ResumeUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2266 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2267 {
2268 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2269 }
2270
2271 /**
2272 * @brief Force an immediate transfer from the preload to the active register .
2273 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
2274 * CR2 TASWU LL_HRTIM_ForceUpdate\n
2275 * CR2 TBSWU LL_HRTIM_ForceUpdate\n
2276 * CR2 TCSWU LL_HRTIM_ForceUpdate\n
2277 * CR2 TDSWU LL_HRTIM_ForceUpdate\n
2278 * CR2 TESWU LL_HRTIM_ForceUpdate\n
2279 * CR2 TFSWU LL_HRTIM_ForceUpdate
2280 * @note Any pending update request is cancelled.
2281 * @param HRTIMx High Resolution Timer instance
2282 * @param Timers This parameter can be a combination of the following values:
2283 * @arg @ref LL_HRTIM_TIMER_MASTER
2284 * @arg @ref LL_HRTIM_TIMER_A
2285 * @arg @ref LL_HRTIM_TIMER_B
2286 * @arg @ref LL_HRTIM_TIMER_C
2287 * @arg @ref LL_HRTIM_TIMER_D
2288 * @arg @ref LL_HRTIM_TIMER_E
2289 * @arg @ref LL_HRTIM_TIMER_F
2290 * @retval None
2291 */
LL_HRTIM_ForceUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2292 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2293 {
2294 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
2295 }
2296
2297 /**
2298 * @brief Reset the HRTIM timer(s) counter.
2299 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
2300 * CR2 TARST LL_HRTIM_CounterReset\n
2301 * CR2 TBRST LL_HRTIM_CounterReset\n
2302 * CR2 TCRST LL_HRTIM_CounterReset\n
2303 * CR2 TDRST LL_HRTIM_CounterReset\n
2304 * CR2 TERST LL_HRTIM_CounterReset\n
2305 * CR2 TFRST LL_HRTIM_CounterReset
2306 * @param HRTIMx High Resolution Timer instance
2307 * @param Timers This parameter can be a combination of the following values:
2308 * @arg @ref LL_HRTIM_TIMER_MASTER
2309 * @arg @ref LL_HRTIM_TIMER_A
2310 * @arg @ref LL_HRTIM_TIMER_B
2311 * @arg @ref LL_HRTIM_TIMER_C
2312 * @arg @ref LL_HRTIM_TIMER_D
2313 * @arg @ref LL_HRTIM_TIMER_E
2314 * @arg @ref LL_HRTIM_TIMER_F
2315 * @retval None
2316 */
LL_HRTIM_CounterReset(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2317 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2318 {
2319 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
2320 }
2321
2322 /**
2323 * @brief enable the swap of the Timer Output.
2324 * @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
2325 * and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
2326 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2327 * @rmtoll CR2 SWPA LL_HRTIM_EnableSwapOutputs\n
2328 * CR2 SWPB LL_HRTIM_EnableSwapOutputs\n
2329 * CR2 SWPC LL_HRTIM_EnableSwapOutputs\n
2330 * CR2 SWPD LL_HRTIM_EnableSwapOutputs\n
2331 * CR2 SWPE LL_HRTIM_EnableSwapOutputs\n
2332 * CR2 SWPF LL_HRTIM_EnableSwapOutputs
2333 * @param HRTIMx High Resolution Timer instance
2334 * @param Timer This parameter can be one of the following values:
2335 * @arg @ref LL_HRTIM_TIMER_A
2336 * @arg @ref LL_HRTIM_TIMER_B
2337 * @arg @ref LL_HRTIM_TIMER_C
2338 * @arg @ref LL_HRTIM_TIMER_D
2339 * @arg @ref LL_HRTIM_TIMER_E
2340 * @arg @ref LL_HRTIM_TIMER_F
2341 * @retval None
2342 */
LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2343 __STATIC_INLINE void LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2344 {
2345 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
2346
2347 SET_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer);
2348 }
2349
2350 /**
2351 * @brief disable the swap of the Timer Output.
2352 * @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
2353 * and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
2354 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2355 * @rmtoll CR2 SWPA LL_HRTIM_DisableSwapOutputs\n
2356 * CR2 SWPB LL_HRTIM_DisableSwapOutputs\n
2357 * CR2 SWPC LL_HRTIM_DisableSwapOutputs\n
2358 * CR2 SWPD LL_HRTIM_DisableSwapOutputs\n
2359 * CR2 SWPE LL_HRTIM_DisableSwapOutputs\n
2360 * CR2 SWPF LL_HRTIM_DisableSwapOutputs
2361 * @param HRTIMx High Resolution Timer instance
2362 * @param Timer This parameter can be one of the following values:
2363 * @arg @ref LL_HRTIM_TIMER_A
2364 * @arg @ref LL_HRTIM_TIMER_B
2365 * @arg @ref LL_HRTIM_TIMER_C
2366 * @arg @ref LL_HRTIM_TIMER_D
2367 * @arg @ref LL_HRTIM_TIMER_E
2368 * @arg @ref LL_HRTIM_TIMER_F
2369 * @retval None
2370 */
LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2371 __STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2372 {
2373 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
2374
2375 CLEAR_BIT(HRTIMx->sCommonRegs.CR2, (HRTIM_CR2_SWPA << iTimer));
2376 }
2377
2378 /**
2379 * @brief reports the Timer Outputs swap position.
2380 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2381 * @rmtoll CR2 SWPA LL_HRTIM_IsEnabledSwapOutputs\n
2382 * CR2 SWPB LL_HRTIM_IsEnabledSwapOutputs\n
2383 * CR2 SWPC LL_HRTIM_IsEnabledSwapOutputs\n
2384 * CR2 SWPD LL_HRTIM_IsEnabledSwapOutputs\n
2385 * CR2 SWPE LL_HRTIM_IsEnabledSwapOutputs\n
2386 * CR2 SWPF LL_HRTIM_IsEnabledSwapOutputs
2387 * @param HRTIMx High Resolution Timer instance
2388 * @param Timer This parameter can be one of the following values:
2389 * @arg @ref LL_HRTIM_TIMER_A
2390 * @arg @ref LL_HRTIM_TIMER_B
2391 * @arg @ref LL_HRTIM_TIMER_C
2392 * @arg @ref LL_HRTIM_TIMER_D
2393 * @arg @ref LL_HRTIM_TIMER_E
2394 * @arg @ref LL_HRTIM_TIMER_F
2395 * @retval
2396 * 1: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
2397 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
2398 * 0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
2399 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
2400 */
LL_HRTIM_IsEnabledSwapOutputs(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2401 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2402 {
2403 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU);
2404
2405 return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer)));
2406 }
2407
2408 /**
2409 * @brief Enable the HRTIM timer(s) output(s) .
2410 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
2411 * OENR TA2OEN LL_HRTIM_EnableOutput\n
2412 * OENR TB1OEN LL_HRTIM_EnableOutput\n
2413 * OENR TB2OEN LL_HRTIM_EnableOutput\n
2414 * OENR TC1OEN LL_HRTIM_EnableOutput\n
2415 * OENR TC2OEN LL_HRTIM_EnableOutput\n
2416 * OENR TD1OEN LL_HRTIM_EnableOutput\n
2417 * OENR TD2OEN LL_HRTIM_EnableOutput\n
2418 * OENR TE1OEN LL_HRTIM_EnableOutput\n
2419 * OENR TE2OEN LL_HRTIM_EnableOutput\n
2420 * OENR TF1OEN LL_HRTIM_EnableOutput\n
2421 * OENR TF2OEN LL_HRTIM_EnableOutput
2422 * @param HRTIMx High Resolution Timer instance
2423 * @param Outputs This parameter can be a combination of the following values:
2424 * @arg @ref LL_HRTIM_OUTPUT_TA1
2425 * @arg @ref LL_HRTIM_OUTPUT_TA2
2426 * @arg @ref LL_HRTIM_OUTPUT_TB1
2427 * @arg @ref LL_HRTIM_OUTPUT_TB2
2428 * @arg @ref LL_HRTIM_OUTPUT_TC1
2429 * @arg @ref LL_HRTIM_OUTPUT_TC2
2430 * @arg @ref LL_HRTIM_OUTPUT_TD1
2431 * @arg @ref LL_HRTIM_OUTPUT_TD2
2432 * @arg @ref LL_HRTIM_OUTPUT_TE1
2433 * @arg @ref LL_HRTIM_OUTPUT_TE2
2434 * @arg @ref LL_HRTIM_OUTPUT_TF1
2435 * @arg @ref LL_HRTIM_OUTPUT_TF2
2436 * @retval None
2437 */
LL_HRTIM_EnableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)2438 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
2439 {
2440 SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
2441 }
2442
2443 /**
2444 * @brief Disable the HRTIM timer(s) output(s) .
2445 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
2446 * OENR TA2OEN LL_HRTIM_DisableOutput\n
2447 * OENR TB1OEN LL_HRTIM_DisableOutput\n
2448 * OENR TB2OEN LL_HRTIM_DisableOutput\n
2449 * OENR TC1OEN LL_HRTIM_DisableOutput\n
2450 * OENR TC2OEN LL_HRTIM_DisableOutput\n
2451 * OENR TD1OEN LL_HRTIM_DisableOutput\n
2452 * OENR TD2OEN LL_HRTIM_DisableOutput\n
2453 * OENR TE1OEN LL_HRTIM_DisableOutput\n
2454 * OENR TE2OEN LL_HRTIM_DisableOutput\n
2455 * OENR TF1OEN LL_HRTIM_DisableOutput\n
2456 * OENR TF2OEN LL_HRTIM_DisableOutput
2457 * @param HRTIMx High Resolution Timer instance
2458 * @param Outputs This parameter can be a combination of the following values:
2459 * @arg @ref LL_HRTIM_OUTPUT_TA1
2460 * @arg @ref LL_HRTIM_OUTPUT_TA2
2461 * @arg @ref LL_HRTIM_OUTPUT_TB1
2462 * @arg @ref LL_HRTIM_OUTPUT_TB2
2463 * @arg @ref LL_HRTIM_OUTPUT_TC1
2464 * @arg @ref LL_HRTIM_OUTPUT_TC2
2465 * @arg @ref LL_HRTIM_OUTPUT_TD1
2466 * @arg @ref LL_HRTIM_OUTPUT_TD2
2467 * @arg @ref LL_HRTIM_OUTPUT_TE1
2468 * @arg @ref LL_HRTIM_OUTPUT_TE2
2469 * @arg @ref LL_HRTIM_OUTPUT_TF1
2470 * @arg @ref LL_HRTIM_OUTPUT_TF2
2471 * @retval None
2472 */
LL_HRTIM_DisableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)2473 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
2474 {
2475 SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
2476 }
2477
2478 /**
2479 * @brief Indicates whether the HRTIM timer output is enabled.
2480 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
2481 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
2482 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
2483 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
2484 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
2485 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
2486 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
2487 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
2488 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
2489 * OENR TE2OEN LL_HRTIM_IsEnabledOutput\n
2490 * OENR TF1OEN LL_HRTIM_IsEnabledOutput\n
2491 * OENR TF2OEN LL_HRTIM_IsEnabledOutput
2492 * @param HRTIMx High Resolution Timer instance
2493 * @param Output This parameter can be one of the following values:
2494 * @arg @ref LL_HRTIM_OUTPUT_TA1
2495 * @arg @ref LL_HRTIM_OUTPUT_TA2
2496 * @arg @ref LL_HRTIM_OUTPUT_TB1
2497 * @arg @ref LL_HRTIM_OUTPUT_TB2
2498 * @arg @ref LL_HRTIM_OUTPUT_TC1
2499 * @arg @ref LL_HRTIM_OUTPUT_TC2
2500 * @arg @ref LL_HRTIM_OUTPUT_TD1
2501 * @arg @ref LL_HRTIM_OUTPUT_TD2
2502 * @arg @ref LL_HRTIM_OUTPUT_TE1
2503 * @arg @ref LL_HRTIM_OUTPUT_TE2
2504 * @arg @ref LL_HRTIM_OUTPUT_TF1
2505 * @arg @ref LL_HRTIM_OUTPUT_TF2
2506 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
2507 */
LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef * HRTIMx,uint32_t Output)2508 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
2509 {
2510 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
2511 }
2512
2513 /**
2514 * @brief Indicates whether the HRTIM timer output is disabled.
2515 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
2516 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
2517 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
2518 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
2519 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
2520 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
2521 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
2522 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
2523 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
2524 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput\n
2525 * ODISR TF1ODIS LL_HRTIM_IsDisabledOutput\n
2526 * ODISR TF2ODIS LL_HRTIM_IsDisabledOutput
2527 * @param HRTIMx High Resolution Timer instance
2528 * @param Output This parameter can be one of the following values:
2529 * @arg @ref LL_HRTIM_OUTPUT_TA1
2530 * @arg @ref LL_HRTIM_OUTPUT_TA2
2531 * @arg @ref LL_HRTIM_OUTPUT_TB1
2532 * @arg @ref LL_HRTIM_OUTPUT_TB2
2533 * @arg @ref LL_HRTIM_OUTPUT_TC1
2534 * @arg @ref LL_HRTIM_OUTPUT_TC2
2535 * @arg @ref LL_HRTIM_OUTPUT_TD1
2536 * @arg @ref LL_HRTIM_OUTPUT_TD2
2537 * @arg @ref LL_HRTIM_OUTPUT_TE1
2538 * @arg @ref LL_HRTIM_OUTPUT_TE2
2539 * @arg @ref LL_HRTIM_OUTPUT_TF1
2540 * @arg @ref LL_HRTIM_OUTPUT_TF2
2541 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
2542 */
LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef * HRTIMx,uint32_t Output)2543 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
2544 {
2545 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
2546 }
2547
2548 /**
2549 * @brief Configure an ADC trigger.
2550 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
2551 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
2552 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
2553 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
2554 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
2555 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
2556 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
2557 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
2558 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
2559 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
2560 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
2561 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
2562 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
2563 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
2564 * ADC1R ADC1TFC2 LL_HRTIM_ConfigADCTrig\n
2565 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
2566 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
2567 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
2568 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
2569 * ADC1R ADC1TFC3 LL_HRTIM_ConfigADCTrig\n
2570 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
2571 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
2572 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
2573 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
2574 * ADC1R ADC1TFC4 LL_HRTIM_ConfigADCTrig\n
2575 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
2576 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
2577 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
2578 * ADC1R ADC1TFPER LL_HRTIM_ConfigADCTrig\n
2579 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
2580 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
2581 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
2582 * ADC1R ADC1TFRST LL_HRTIM_ConfigADCTrig\n
2583 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
2584 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
2585 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
2586 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
2587 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
2588 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
2589 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
2590 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
2591 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
2592 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
2593 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
2594 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
2595 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
2596 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
2597 * ADC2R ADC2TFC2 LL_HRTIM_ConfigADCTrig\n
2598 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
2599 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
2600 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
2601 * ADC2R ADC2TFC3 LL_HRTIM_ConfigADCTrig\n
2602 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
2603 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
2604 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
2605 * ADC2R ADC2TFC4 LL_HRTIM_ConfigADCTrig\n
2606 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
2607 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
2608 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
2609 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
2610 * ADC2R ADC2TFPER LL_HRTIM_ConfigADCTrig\n
2611 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
2612 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
2613 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
2614 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
2615 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
2616 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
2617 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
2618 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
2619 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
2620 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
2621 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
2622 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
2623 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
2624 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
2625 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
2626 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
2627 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
2628 * ADC3R ADC3TFC2 LL_HRTIM_ConfigADCTrig\n
2629 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
2630 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
2631 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
2632 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
2633 * ADC3R ADC3TFC3 LL_HRTIM_ConfigADCTrig\n
2634 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
2635 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
2636 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
2637 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
2638 * ADC3R ADC3TFC4 LL_HRTIM_ConfigADCTrig\n
2639 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
2640 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
2641 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
2642 * ADC3R ADC3TFPER LL_HRTIM_ConfigADCTrig\n
2643 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
2644 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
2645 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
2646 * ADC3R ADC3TFRST LL_HRTIM_ConfigADCTrig\n
2647 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
2648 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
2649 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
2650 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
2651 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
2652 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
2653 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
2654 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
2655 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
2656 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
2657 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
2658 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
2659 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
2660 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
2661 * ADC4R ADC4TFC2 LL_HRTIM_ConfigADCTrig\n
2662 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
2663 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
2664 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
2665 * ADC4R ADC4TFC3 LL_HRTIM_ConfigADCTrig\n
2666 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
2667 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
2668 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
2669 * ADC4R ADC4TFC4 LL_HRTIM_ConfigADCTrig\n
2670 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
2671 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
2672 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
2673 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
2674 * ADC4R ADC4TFPER LL_HRTIM_ConfigADCTrig\n
2675 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
2676 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
2677 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
2678 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
2679 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
2680 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
2681 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
2682 * @param HRTIMx High Resolution Timer instance
2683 * @param ADCTrig This parameter can be one of the following values:
2684 * @arg @ref LL_HRTIM_ADCTRIG_1
2685 * @arg @ref LL_HRTIM_ADCTRIG_2
2686 * @arg @ref LL_HRTIM_ADCTRIG_3
2687 * @arg @ref LL_HRTIM_ADCTRIG_4
2688 * @param Update This parameter can be one of the following values:
2689 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2690 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2691 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2692 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2693 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2694 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2695 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2696 * @param Src This parameter can be a combination of the following values:
2697 *
2698 * For ADC trigger 1 and ADC trigger 3:
2699 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2700 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2701 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2702 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2703 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2704 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2705 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2706 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2707 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2708 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2709 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2710 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2711 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2712 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2713 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2714 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2715 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2716 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2717 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2718 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2719 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2720 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2721 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2722 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2723 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2724 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2725 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2726 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2727 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
2728 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
2729 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
2730 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
2731 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
2732 *
2733 * For ADC trigger 2 and ADC trigger 4:
2734 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2735 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2736 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2737 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2738 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2739 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2740 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2741 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2742 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2743 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2744 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2745 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2746 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2747 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2748 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2749 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2750 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2751 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2752 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2753 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2754 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2755 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2756 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2757 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2758 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2759 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2760 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2761 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2762 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2763 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
2764 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
2765 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
2766 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
2767 *
2768 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
2769 * can be one of the following values:
2770 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
2771 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
2772 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
2773 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
2774 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
2775 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
2776 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
2777 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
2778 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
2779 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
2780 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
2781 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
2782 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
2783 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
2784 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
2785 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
2786 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
2787 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
2788 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
2789 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
2790 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
2791 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
2792 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
2793 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
2794 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
2795 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
2796 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
2797 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
2798 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
2799 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
2800 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
2801 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
2802 *
2803 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
2804 * can be one of the following values:
2805 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
2806 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
2807 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
2808 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
2809 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
2810 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
2811 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
2812 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
2813 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
2814 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
2815 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
2816 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
2817 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
2818 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
2819 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
2820 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
2821 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
2822 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
2823 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
2824 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
2825 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
2826 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
2827 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
2828 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
2829 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
2830 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
2831 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
2832 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
2833 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
2834 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
2835 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
2836 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
2837 * @retval None
2838 */
LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update,uint32_t Src)2839 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
2840 {
2841 __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2842 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2843 __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2844 REG_OFFSET_TAB_ADCER[ADCTrig]));
2845 MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
2846 MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
2847 }
2848
2849 /**
2850 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
2851 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
2852 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
2853 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
2854 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
2855 * ADCUR ADC5USRC LL_HRTIM_SetADCTrigUpdate\n
2856 * ADCUR ADC6USRC LL_HRTIM_SetADCTrigUpdate\n
2857 * ADCUR ADC7USRC LL_HRTIM_SetADCTrigUpdate\n
2858 * ADCUR ADC8USRC LL_HRTIM_SetADCTrigUpdate\n
2859 * ADCUR ADC9USRC LL_HRTIM_SetADCTrigUpdate\n
2860 * ADCUR ADC10USRC LL_HRTIM_SetADCTrigUpdate
2861 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
2862 * registers are not preloaded either: a write access will result in an
2863 * immediate update of the trigger source.
2864 * @param HRTIMx High Resolution Timer instance
2865 * @param ADCTrig This parameter can be one of the following values:
2866 * @arg @ref LL_HRTIM_ADCTRIG_1
2867 * @arg @ref LL_HRTIM_ADCTRIG_2
2868 * @arg @ref LL_HRTIM_ADCTRIG_3
2869 * @arg @ref LL_HRTIM_ADCTRIG_4
2870 * @arg @ref LL_HRTIM_ADCTRIG_5
2871 * @arg @ref LL_HRTIM_ADCTRIG_6
2872 * @arg @ref LL_HRTIM_ADCTRIG_7
2873 * @arg @ref LL_HRTIM_ADCTRIG_8
2874 * @arg @ref LL_HRTIM_ADCTRIG_9
2875 * @arg @ref LL_HRTIM_ADCTRIG_10
2876 * @param Update This parameter can be one of the following values:
2877 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2878 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2879 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2880 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2881 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2882 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2883 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2884 * @retval None
2885 */
LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update)2886 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
2887 {
2888 __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2889 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2890 MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
2891 }
2892
2893 /**
2894 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
2895 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
2896 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
2897 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
2898 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
2899 * ADCUR ADC5USRC LL_HRTIM_GetADCTrigUpdate\n
2900 * ADCUR ADC6USRC LL_HRTIM_GetADCTrigUpdate\n
2901 * ADCUR ADC7USRC LL_HRTIM_GetADCTrigUpdate\n
2902 * ADCUR ADC8USRC LL_HRTIM_GetADCTrigUpdate\n
2903 * ADCUR ADC9USRC LL_HRTIM_GetADCTrigUpdate\n
2904 * ADCUR ADC10USRC LL_HRTIM_GetADCTrigUpdate
2905 * @param HRTIMx High Resolution Timer instance
2906 * @param ADCTrig This parameter can be one of the following values:
2907 * @arg @ref LL_HRTIM_ADCTRIG_1
2908 * @arg @ref LL_HRTIM_ADCTRIG_2
2909 * @arg @ref LL_HRTIM_ADCTRIG_3
2910 * @arg @ref LL_HRTIM_ADCTRIG_4
2911 * @arg @ref LL_HRTIM_ADCTRIG_5
2912 * @arg @ref LL_HRTIM_ADCTRIG_6
2913 * @arg @ref LL_HRTIM_ADCTRIG_7
2914 * @arg @ref LL_HRTIM_ADCTRIG_8
2915 * @arg @ref LL_HRTIM_ADCTRIG_9
2916 * @arg @ref LL_HRTIM_ADCTRIG_10
2917 * @retval Update Returned value can be one of the following values:
2918 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2919 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2920 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2921 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2922 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2923 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2924 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2925 */
LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)2926 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
2927 {
2928 const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2929 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2930 return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]);
2931 }
2932
2933 /**
2934 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
2935 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
2936 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
2937 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
2938 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
2939 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
2940 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
2941 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
2942 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
2943 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
2944 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
2945 * ADC1R ADC1TFC2 LL_HRTIM_SetADCTrigSrc\n
2946 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
2947 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
2948 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
2949 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
2950 * ADC1R ADC1TFC3 LL_HRTIM_SetADCTrigSrc\n
2951 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
2952 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
2953 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
2954 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
2955 * ADC1R ADC1TFC4 LL_HRTIM_SetADCTrigSrc\n
2956 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
2957 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
2958 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
2959 * ADC1R ADC1TFPER LL_HRTIM_SetADCTrigSrc\n
2960 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
2961 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
2962 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
2963 * ADC1R ADC1TFRST LL_HRTIM_SetADCTrigSrc\n
2964 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
2965 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
2966 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
2967 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
2968 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
2969 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
2970 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
2971 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
2972 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
2973 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
2974 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
2975 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
2976 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
2977 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
2978 * ADC2R ADC2TFC2 LL_HRTIM_SetADCTrigSrc\n
2979 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
2980 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
2981 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
2982 * ADC2R ADC2TFC3 LL_HRTIM_SetADCTrigSrc\n
2983 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
2984 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
2985 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
2986 * ADC2R ADC2TFC4 LL_HRTIM_SetADCTrigSrc\n
2987 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
2988 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
2989 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
2990 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
2991 * ADC2R ADC2TFPER LL_HRTIM_SetADCTrigSrc\n
2992 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
2993 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
2994 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
2995 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
2996 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
2997 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
2998 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
2999 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
3000 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
3001 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
3002 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
3003 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
3004 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
3005 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
3006 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
3007 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
3008 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
3009 * ADC3R ADC3TFC2 LL_HRTIM_SetADCTrigSrc\n
3010 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
3011 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
3012 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
3013 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
3014 * ADC3R ADC3TFC3 LL_HRTIM_SetADCTrigSrc\n
3015 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
3016 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
3017 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
3018 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
3019 * ADC3R ADC3TFC4 LL_HRTIM_SetADCTrigSrc\n
3020 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
3021 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
3022 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
3023 * ADC3R ADC3TFPER LL_HRTIM_SetADCTrigSrc\n
3024 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
3025 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
3026 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
3027 * ADC3R ADC3TFRST LL_HRTIM_SetADCTrigSrc\n
3028 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
3029 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
3030 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
3031 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
3032 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
3033 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
3034 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
3035 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
3036 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
3037 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
3038 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
3039 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
3040 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
3041 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
3042 * ADC4R ADC4TFC2 LL_HRTIM_SetADCTrigSrc\n
3043 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
3044 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
3045 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
3046 * ADC4R ADC4TFC3 LL_HRTIM_SetADCTrigSrc\n
3047 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
3048 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
3049 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
3050 * ADC4R ADC4TFC4 LL_HRTIM_SetADCTrigSrc\n
3051 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
3052 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
3053 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
3054 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
3055 * ADC4R ADC4TFPER LL_HRTIM_SetADCTrigSrc\n
3056 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
3057 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
3058 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
3059 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
3060 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
3061 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
3062 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
3063 * ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
3064 * ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
3065 * ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
3066 * ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
3067 * ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
3068 * ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
3069 * @param HRTIMx High Resolution Timer instance
3070 * @param ADCTrig This parameter can be one of the following values:
3071 * @arg @ref LL_HRTIM_ADCTRIG_1
3072 * @arg @ref LL_HRTIM_ADCTRIG_2
3073 * @arg @ref LL_HRTIM_ADCTRIG_3
3074 * @arg @ref LL_HRTIM_ADCTRIG_4
3075 * @arg @ref LL_HRTIM_ADCTRIG_5
3076 * @arg @ref LL_HRTIM_ADCTRIG_6
3077 * @arg @ref LL_HRTIM_ADCTRIG_7
3078 * @arg @ref LL_HRTIM_ADCTRIG_8
3079 * @arg @ref LL_HRTIM_ADCTRIG_9
3080 * @arg @ref LL_HRTIM_ADCTRIG_10
3081 * @param Src
3082 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
3083 * combination of the following values:
3084 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
3085 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
3086 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
3087 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
3088 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
3089 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
3090 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
3091 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
3092 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
3093 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
3094 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
3095 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
3096 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
3097 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
3098 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
3099 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
3100 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
3101 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
3102 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
3103 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
3104 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
3105 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
3106 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
3107 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
3108 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
3109 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
3110 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
3111 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
3112 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
3113 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
3114 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
3115 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
3116 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
3117 *
3118 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
3119 * combination of the following values:
3120 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
3121 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
3122 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
3123 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
3124 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
3125 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
3126 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
3127 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
3128 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
3129 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
3130 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
3131 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
3132 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
3133 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
3134 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
3135 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
3136 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
3137 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
3138 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
3139 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
3140 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
3141 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
3142 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
3143 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
3144 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
3145 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
3146 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
3147 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
3148 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
3149 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
3150 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
3151 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
3152 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
3153 *
3154 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
3155 * can be one of the following values:
3156 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
3157 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
3158 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
3159 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
3160 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
3161 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
3162 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
3163 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
3164 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
3165 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
3166 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
3167 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
3168 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
3169 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
3170 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
3171 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
3172 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
3173 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
3174 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
3175 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
3176 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
3177 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
3178 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
3179 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
3180 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
3181 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
3182 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
3183 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
3184 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
3185 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
3186 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
3187 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
3188 *
3189 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
3190 * can be one of the following values:
3191 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
3192 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
3193 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
3194 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
3195 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
3196 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
3197 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
3198 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
3199 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
3200 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
3201 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
3202 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
3203 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
3204 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
3205 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
3206 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
3207 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
3208 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
3209 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
3210 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
3211 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
3212 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
3213 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
3214 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
3215 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
3216 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
3217 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
3218 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
3219 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
3220 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
3221 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
3222 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
3223 * @retval None
3224 */
LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Src)3225 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
3226 {
3227 __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
3228 REG_OFFSET_TAB_ADCER[ADCTrig]));
3229 MODIFY_REG(*preg, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
3230 }
3231
3232 /**
3233 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
3234 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n
3235 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n
3236 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n
3237 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
3238 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
3239 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
3240 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
3241 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
3242 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
3243 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
3244 * ADC1R ADC1TFC2 LL_HRTIM_GetADCTrigSrc\n
3245 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
3246 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
3247 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
3248 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
3249 * ADC1R ADC1TFC3 LL_HRTIM_GetADCTrigSrc\n
3250 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
3251 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
3252 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
3253 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
3254 * ADC1R ADC1TFC4 LL_HRTIM_GetADCTrigSrc\n
3255 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
3256 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
3257 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
3258 * ADC1R ADC1TFPER LL_HRTIM_GetADCTrigSrc\n
3259 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
3260 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
3261 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
3262 * ADC1R ADC1TFRST LL_HRTIM_GetADCTrigSrc\n
3263 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
3264 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
3265 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
3266 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
3267 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
3268 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
3269 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
3270 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
3271 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
3272 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
3273 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
3274 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
3275 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
3276 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
3277 * ADC2R ADC2TFC2 LL_HRTIM_GetADCTrigSrc\n
3278 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
3279 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
3280 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
3281 * ADC2R ADC2TFC3 LL_HRTIM_GetADCTrigSrc\n
3282 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
3283 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
3284 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
3285 * ADC2R ADC2TFC4 LL_HRTIM_GetADCTrigSrc\n
3286 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
3287 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
3288 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
3289 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
3290 * ADC2R ADC2TFPER LL_HRTIM_GetADCTrigSrc\n
3291 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
3292 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
3293 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
3294 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
3295 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
3296 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
3297 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
3298 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
3299 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
3300 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
3301 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
3302 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
3303 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
3304 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
3305 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
3306 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
3307 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
3308 * ADC3R ADC3TFC2 LL_HRTIM_GetADCTrigSrc\n
3309 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
3310 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
3311 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
3312 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
3313 * ADC3R ADC3TFC3 LL_HRTIM_GetADCTrigSrc\n
3314 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
3315 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
3316 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
3317 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
3318 * ADC3R ADC3TFC4 LL_HRTIM_GetADCTrigSrc\n
3319 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
3320 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
3321 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
3322 * ADC3R ADC3TFPER LL_HRTIM_GetADCTrigSrc\n
3323 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
3324 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
3325 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
3326 * ADC3R ADC3TFRST LL_HRTIM_GetADCTrigSrc\n
3327 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
3328 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
3329 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
3330 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
3331 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
3332 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
3333 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
3334 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
3335 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
3336 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
3337 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
3338 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
3339 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
3340 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
3341 * ADC4R ADC4TFC2 LL_HRTIM_GetADCTrigSrc\n
3342 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
3343 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
3344 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
3345 * ADC4R ADC4TFC3 LL_HRTIM_GetADCTrigSrc\n
3346 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
3347 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
3348 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
3349 * ADC4R ADC4TFC4 LL_HRTIM_GetADCTrigSrc\n
3350 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
3351 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
3352 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
3353 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
3354 * ADC4R ADC4TFPER LL_HRTIM_GetADCTrigSrc\n
3355 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
3356 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
3357 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
3358 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
3359 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
3360 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
3361 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
3362 * ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
3363 * ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
3364 * ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
3365 * ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
3366 * ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
3367 * ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
3368 * @param HRTIMx High Resolution Timer instance
3369 * @param HRTIMx High Resolution Timer instance
3370 * @param ADCTrig This parameter can be one of the following values:
3371 * @arg @ref LL_HRTIM_ADCTRIG_1
3372 * @arg @ref LL_HRTIM_ADCTRIG_2
3373 * @arg @ref LL_HRTIM_ADCTRIG_3
3374 * @arg @ref LL_HRTIM_ADCTRIG_4
3375 * @arg @ref LL_HRTIM_ADCTRIG_5
3376 * @arg @ref LL_HRTIM_ADCTRIG_6
3377 * @arg @ref LL_HRTIM_ADCTRIG_7
3378 * @arg @ref LL_HRTIM_ADCTRIG_8
3379 * @arg @ref LL_HRTIM_ADCTRIG_9
3380 * @arg @ref LL_HRTIM_ADCTRIG_10
3381 * @retval Src This parameter can be a combination of the following values:
3382 *
3383 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
3384 * combination of the following values:
3385 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
3386 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
3387 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
3388 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
3389 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
3390 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
3391 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
3392 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
3393 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
3394 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
3395 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
3396 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
3397 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
3398 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
3399 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
3400 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
3401 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
3402 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
3403 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
3404 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
3405 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
3406 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
3407 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
3408 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
3409 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
3410 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
3411 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
3412 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
3413 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
3414 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
3415 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
3416 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
3417 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
3418 *
3419 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
3420 * combination of the following values:
3421 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
3422 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
3423 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
3424 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
3425 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
3426 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
3427 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
3428 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
3429 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
3430 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
3431 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
3432 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
3433 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
3434 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
3435 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
3436 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
3437 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
3438 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
3439 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
3440 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
3441 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
3442 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
3443 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
3444 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
3445 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
3446 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
3447 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
3448 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
3449 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
3450 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
3451 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
3452 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
3453 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
3454 *
3455 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
3456 * can be one of the following values:
3457 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
3458 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
3459 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
3460 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
3461 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
3462 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
3463 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
3464 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
3465 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
3466 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
3467 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
3468 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
3469 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
3470 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
3471 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
3472 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
3473 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
3474 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
3475 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
3476 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
3477 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
3478 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
3479 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
3480 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
3481 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
3482 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
3483 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
3484 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
3485 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
3486 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
3487 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
3488 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
3489 *
3490 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
3491 * can be one of the following values:
3492 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
3493 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
3494 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
3495 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
3496 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
3497 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
3498 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
3499 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
3500 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
3501 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
3502 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
3503 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
3504 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
3505 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
3506 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
3507 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
3508 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
3509 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
3510 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
3511 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
3512 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
3513 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
3514 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
3515 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
3516 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
3517 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
3518 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
3519 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
3520 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
3521 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
3522 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
3523 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
3524 */
LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)3525 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
3526 {
3527 const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
3528 REG_OFFSET_TAB_ADCER[ADCTrig]));
3529 return (READ_BIT(*preg, (REG_MASK_TAB_ADCER[ADCTrig])) >> REG_SHIFT_TAB_ADCER[ADCTrig]);
3530
3531 }
3532
3533
3534 /**
3535 * @brief Select the ADC post scaler.
3536 * @note This function allows to adjust each ADC trigger rate individually.
3537 * @note In center-aligned mode, the ADC trigger rate is also dependent on
3538 * ADROM[1:0] bitfield, programmed in the source timer
3539 * (see function @ref LL_HRTIM_TIM_SetADCRollOverMode)
3540 * @rmtoll ADCPS2 ADC10PSC LL_HRTIM_SetADCPostScaler\n
3541 * ADCPS2 ADC9PSC LL_HRTIM_SetADCPostScaler\n
3542 * ADCPS2 ADC8PSC LL_HRTIM_SetADCPostScaler\n
3543 * ADCPS2 ADC7PSC LL_HRTIM_SetADCPostScaler\n
3544 * ADCPS2 ADC6PSC LL_HRTIM_SetADCPostScaler\n
3545 * ADCPS1 ADC5PSC LL_HRTIM_SetADCPostScaler\n
3546 * ADCPS1 ADC4PSC LL_HRTIM_SetADCPostScaler\n
3547 * ADCPS1 ADC3PSC LL_HRTIM_SetADCPostScaler\n
3548 * ADCPS1 ADC2PSC LL_HRTIM_SetADCPostScaler\n
3549 * ADCPS1 ADC1PSC LL_HRTIM_SetADCPostScaler
3550 * @param HRTIMx High Resolution Timer instance
3551 * @param ADCTrig This parameter can be one of the following values:
3552 * @arg @ref LL_HRTIM_ADCTRIG_1
3553 * @arg @ref LL_HRTIM_ADCTRIG_2
3554 * @arg @ref LL_HRTIM_ADCTRIG_3
3555 * @arg @ref LL_HRTIM_ADCTRIG_4
3556 * @arg @ref LL_HRTIM_ADCTRIG_5
3557 * @arg @ref LL_HRTIM_ADCTRIG_6
3558 * @arg @ref LL_HRTIM_ADCTRIG_7
3559 * @arg @ref LL_HRTIM_ADCTRIG_8
3560 * @arg @ref LL_HRTIM_ADCTRIG_9
3561 * @arg @ref LL_HRTIM_ADCTRIG_10
3562 * @param PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
3563 * @retval None
3564 */
LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t PostScaler)3565 __STATIC_INLINE void LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t PostScaler)
3566 {
3567
3568 uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3569 uint64_t ratio = (uint64_t)(PostScaler) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3570
3571 MODIFY_REG(HRTIMx->sCommonRegs.ADCPS1, (uint32_t)mask, (uint32_t)ratio);
3572 MODIFY_REG(HRTIMx->sCommonRegs.ADCPS2, (uint32_t)(mask >> 32U), (uint32_t)(ratio >> 32U));
3573
3574 }
3575
3576 /**
3577 * @brief Get the selected ADC post scaler.
3578 * @rmtoll ADCPS2 ADC10PSC LL_HRTIM_GetADCPostScaler\n
3579 * ADCPS2 ADC9PSC LL_HRTIM_GetADCPostScaler\n
3580 * ADCPS2 ADC8PSC LL_HRTIM_GetADCPostScaler\n
3581 * ADCPS2 ADC7PSC LL_HRTIM_GetADCPostScaler\n
3582 * ADCPS2 ADC6PSC LL_HRTIM_GetADCPostScaler\n
3583 * ADCPS1 ADC5PSC LL_HRTIM_GetADCPostScaler\n
3584 * ADCPS1 ADC4PSC LL_HRTIM_GetADCPostScaler\n
3585 * ADCPS1 ADC3PSC LL_HRTIM_GetADCPostScaler\n
3586 * ADCPS1 ADC2PSC LL_HRTIM_GetADCPostScaler\n
3587 * ADCPS1 ADC1PSC LL_HRTIM_GetADCPostScaler
3588 * @param HRTIMx High Resolution Timer instance
3589 * @param ADCTrig This parameter can be one of the following values:
3590 * @arg @ref LL_HRTIM_ADCTRIG_1
3591 * @arg @ref LL_HRTIM_ADCTRIG_2
3592 * @arg @ref LL_HRTIM_ADCTRIG_3
3593 * @arg @ref LL_HRTIM_ADCTRIG_4
3594 * @arg @ref LL_HRTIM_ADCTRIG_5
3595 * @arg @ref LL_HRTIM_ADCTRIG_6
3596 * @arg @ref LL_HRTIM_ADCTRIG_7
3597 * @arg @ref LL_HRTIM_ADCTRIG_8
3598 * @arg @ref LL_HRTIM_ADCTRIG_9
3599 * @arg @ref LL_HRTIM_ADCTRIG_10
3600 * @retval PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
3601 */
LL_HRTIM_GetADCPostScaler(const HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)3602 __STATIC_INLINE uint32_t LL_HRTIM_GetADCPostScaler(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
3603 {
3604
3605 uint32_t reg1 = READ_REG(HRTIMx->sCommonRegs.ADCPS1);
3606 uint32_t reg2 = READ_REG(HRTIMx->sCommonRegs.ADCPS2);
3607
3608 uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3609 uint64_t ratio = (uint64_t)(reg1) | ((uint64_t)(reg2) << 32U);
3610
3611 return (uint32_t)((ratio & mask) >> (REG_OFFSET_TAB_ADCPSx[ADCTrig])) ;
3612
3613 }
3614
3615 /**
3616 * @brief Configure the DLL calibration mode.
3617 * @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
3618 * DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
3619 * @param HRTIMx High Resolution Timer instance
3620 * @param Mode This parameter can be one of the following values:
3621 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
3622 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
3623 * @param Period This parameter can be one of the following values:
3624 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_0
3625 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_1
3626 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_2
3627 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_3
3628 * @retval None
3629 */
LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef * HRTIMx,uint32_t Mode,uint32_t Period)3630 __STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
3631 {
3632 MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
3633 }
3634
3635 /**
3636 * @brief Launch DLL calibration
3637 * @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
3638 * @param HRTIMx High Resolution Timer instance
3639 * @retval None
3640 */
LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef * HRTIMx)3641 __STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
3642 {
3643 SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
3644 }
3645
3646 /**
3647 * @}
3648 */
3649
3650 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
3651 * @{
3652 */
3653
3654 /**
3655 * @brief Enable timer(s) counter.
3656 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterEnable\n
3657 * MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
3658 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
3659 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
3660 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
3661 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
3662 * MDIER MCEN LL_HRTIM_TIM_CounterEnable
3663 * @param HRTIMx High Resolution Timer instance
3664 * @param Timers This parameter can be a combination of the following values:
3665 * @arg @ref LL_HRTIM_TIMER_MASTER
3666 * @arg @ref LL_HRTIM_TIMER_A
3667 * @arg @ref LL_HRTIM_TIMER_B
3668 * @arg @ref LL_HRTIM_TIMER_C
3669 * @arg @ref LL_HRTIM_TIMER_D
3670 * @arg @ref LL_HRTIM_TIMER_E
3671 * @arg @ref LL_HRTIM_TIMER_F
3672 * @retval None
3673 */
LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)3674 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
3675 {
3676 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
3677 }
3678
3679 /**
3680 * @brief Disable timer(s) counter.
3681 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterDisable\n
3682 * MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
3683 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
3684 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
3685 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
3686 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
3687 * MDIER MCEN LL_HRTIM_TIM_CounterDisable
3688 * @param HRTIMx High Resolution Timer instance
3689 * @param Timers This parameter can be a combination of the following values:
3690 * @arg @ref LL_HRTIM_TIMER_MASTER
3691 * @arg @ref LL_HRTIM_TIMER_A
3692 * @arg @ref LL_HRTIM_TIMER_B
3693 * @arg @ref LL_HRTIM_TIMER_C
3694 * @arg @ref LL_HRTIM_TIMER_D
3695 * @arg @ref LL_HRTIM_TIMER_E
3696 * @arg @ref LL_HRTIM_TIMER_F
3697 * @retval None
3698 */
LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)3699 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
3700 {
3701 CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
3702 }
3703
3704 /**
3705 * @brief Indicate whether the timer counter is enabled.
3706 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_IsCounterEnabled\n
3707 * MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
3708 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
3709 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
3710 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
3711 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
3712 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
3713 * @param HRTIMx High Resolution Timer instance
3714 * @param Timer This parameter can be one of the following values:
3715 * @arg @ref LL_HRTIM_TIMER_MASTER
3716 * @arg @ref LL_HRTIM_TIMER_A
3717 * @arg @ref LL_HRTIM_TIMER_B
3718 * @arg @ref LL_HRTIM_TIMER_C
3719 * @arg @ref LL_HRTIM_TIMER_D
3720 * @arg @ref LL_HRTIM_TIMER_E
3721 * @arg @ref LL_HRTIM_TIMER_F
3722 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
3723 */
LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3724 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3725 {
3726 return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
3727 }
3728
3729 /**
3730 * @brief Set the timer clock prescaler ratio.
3731 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
3732 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
3733 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
3734 * @note The prescaling ratio cannot be modified once the timer counter is enabled.
3735 * @param HRTIMx High Resolution Timer instance
3736 * @param Timer This parameter can be one of the following values:
3737 * @arg @ref LL_HRTIM_TIMER_MASTER
3738 * @arg @ref LL_HRTIM_TIMER_A
3739 * @arg @ref LL_HRTIM_TIMER_B
3740 * @arg @ref LL_HRTIM_TIMER_C
3741 * @arg @ref LL_HRTIM_TIMER_D
3742 * @arg @ref LL_HRTIM_TIMER_E
3743 * @arg @ref LL_HRTIM_TIMER_F
3744 * @param Prescaler This parameter can be one of the following values:
3745 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
3746 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
3747 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
3748 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
3749 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
3750 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
3751 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
3752 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
3753 * @retval None
3754 */
LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)3755 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
3756 {
3757 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3758 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3759 MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
3760 }
3761
3762 /**
3763 * @brief Get the timer clock prescaler ratio
3764 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
3765 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
3766 * @param HRTIMx High Resolution Timer instance
3767 * @param Timer This parameter can be one of the following values:
3768 * @arg @ref LL_HRTIM_TIMER_MASTER
3769 * @arg @ref LL_HRTIM_TIMER_A
3770 * @arg @ref LL_HRTIM_TIMER_B
3771 * @arg @ref LL_HRTIM_TIMER_C
3772 * @arg @ref LL_HRTIM_TIMER_D
3773 * @arg @ref LL_HRTIM_TIMER_E
3774 * @arg @ref LL_HRTIM_TIMER_F
3775 * @retval Prescaler Returned value can be one of the following values:
3776 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
3777 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
3778 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
3779 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
3780 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
3781 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
3782 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
3783 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
3784 */
LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3785 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3786 {
3787 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3788 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3789 return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
3790 }
3791
3792 /**
3793 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
3794 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
3795 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
3796 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
3797 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
3798 * @param HRTIMx High Resolution Timer instance
3799 * @param Timer This parameter can be one of the following values:
3800 * @arg @ref LL_HRTIM_TIMER_MASTER
3801 * @arg @ref LL_HRTIM_TIMER_A
3802 * @arg @ref LL_HRTIM_TIMER_B
3803 * @arg @ref LL_HRTIM_TIMER_C
3804 * @arg @ref LL_HRTIM_TIMER_D
3805 * @arg @ref LL_HRTIM_TIMER_E
3806 * @arg @ref LL_HRTIM_TIMER_F
3807 * @param Mode This parameter can be one of the following values:
3808 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
3809 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
3810 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
3811 * @retval None
3812 */
LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)3813 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
3814 {
3815 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3816 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3817 MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
3818 }
3819
3820 /**
3821 * @brief Get the counter operating mode mode
3822 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
3823 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
3824 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
3825 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
3826 * @param HRTIMx High Resolution Timer instance
3827 * @param Timer This parameter can be one of the following values:
3828 * @arg @ref LL_HRTIM_TIMER_MASTER
3829 * @arg @ref LL_HRTIM_TIMER_A
3830 * @arg @ref LL_HRTIM_TIMER_B
3831 * @arg @ref LL_HRTIM_TIMER_C
3832 * @arg @ref LL_HRTIM_TIMER_D
3833 * @arg @ref LL_HRTIM_TIMER_E
3834 * @arg @ref LL_HRTIM_TIMER_F
3835 * @retval Mode Returned value can be one of the following values:
3836 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
3837 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
3838 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
3839 */
LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3840 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3841 {
3842 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3843 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3844 return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
3845 }
3846
3847 /**
3848 * @brief Enable the half duty-cycle mode.
3849 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
3850 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
3851 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
3852 * active register is automatically updated with HRTIM_MPER/2
3853 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
3854 * @param HRTIMx High Resolution Timer instance
3855 * @param Timer This parameter can be one of the following values:
3856 * @arg @ref LL_HRTIM_TIMER_MASTER
3857 * @arg @ref LL_HRTIM_TIMER_A
3858 * @arg @ref LL_HRTIM_TIMER_B
3859 * @arg @ref LL_HRTIM_TIMER_C
3860 * @arg @ref LL_HRTIM_TIMER_D
3861 * @arg @ref LL_HRTIM_TIMER_E
3862 * @arg @ref LL_HRTIM_TIMER_F
3863 * @retval None
3864 */
LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3865 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3866 {
3867 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3868 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3869 SET_BIT(*pReg, HRTIM_MCR_HALF);
3870 }
3871
3872 /**
3873 * @brief Disable the half duty-cycle mode.
3874 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
3875 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
3876 * @param HRTIMx High Resolution Timer instance
3877 * @param Timer This parameter can be one of the following values:
3878 * @arg @ref LL_HRTIM_TIMER_MASTER
3879 * @arg @ref LL_HRTIM_TIMER_A
3880 * @arg @ref LL_HRTIM_TIMER_B
3881 * @arg @ref LL_HRTIM_TIMER_C
3882 * @arg @ref LL_HRTIM_TIMER_D
3883 * @arg @ref LL_HRTIM_TIMER_E
3884 * @arg @ref LL_HRTIM_TIMER_F
3885 * @retval None
3886 */
LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3887 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3888 {
3889 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3890 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3891 CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
3892 CLEAR_BIT(*pReg, HRTIM_MCR_INTLVD << REG_SHIFT_TAB_INTLVD[iTimer]);
3893 }
3894
3895 /**
3896 * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
3897 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
3898 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
3899 * @param HRTIMx High Resolution Timer instance
3900 * @param Timer This parameter can be one of the following values:
3901 * @arg @ref LL_HRTIM_TIMER_MASTER
3902 * @arg @ref LL_HRTIM_TIMER_A
3903 * @arg @ref LL_HRTIM_TIMER_B
3904 * @arg @ref LL_HRTIM_TIMER_C
3905 * @arg @ref LL_HRTIM_TIMER_D
3906 * @arg @ref LL_HRTIM_TIMER_E
3907 * @arg @ref LL_HRTIM_TIMER_F
3908 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
3909 */
LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3910 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3911 {
3912 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3913 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3914
3915 return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
3916 }
3917
3918 /**
3919 * @brief Enable the Re-Syncronisation Update.
3920 * @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
3921 * or from a software update (TxSWU bit) is taken into account on the following reset/roll-over.
3922 * @note LL_HRTIM_ForceUpdate must be called prior programming the syncrhonization mode to force
3923 * immediate update of the slave timer registers.
3924 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_EnableResyncUpdate
3925 * @param HRTIMx High Resolution Timer instance
3926 * @param Timer This parameter can be one of the following values:
3927 * @arg @ref LL_HRTIM_TIMER_A
3928 * @arg @ref LL_HRTIM_TIMER_B
3929 * @arg @ref LL_HRTIM_TIMER_C
3930 * @arg @ref LL_HRTIM_TIMER_D
3931 * @arg @ref LL_HRTIM_TIMER_E
3932 * @arg @ref LL_HRTIM_TIMER_F
3933 * @retval None
3934 */
LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3935 __STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3936 {
3937 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3938 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3939 REG_OFFSET_TAB_TIMER[iTimer]));
3940 SET_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
3941 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3942 }
3943
3944 /**
3945 * @brief Disable the Re-Syncronisation Update.
3946 * @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
3947 * or from a software update (TxSWU bit) is taken into account immediately.
3948 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_DisableResyncUpdate
3949 * @param HRTIMx High Resolution Timer instance
3950 * @param Timer This parameter can be one of the following values:
3951 * @arg @ref LL_HRTIM_TIMER_A
3952 * @arg @ref LL_HRTIM_TIMER_B
3953 * @arg @ref LL_HRTIM_TIMER_C
3954 * @arg @ref LL_HRTIM_TIMER_D
3955 * @arg @ref LL_HRTIM_TIMER_E
3956 * @arg @ref LL_HRTIM_TIMER_F
3957 * @retval None
3958 */
LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3959 __STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3960 {
3961 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3962 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3963 REG_OFFSET_TAB_TIMER[iTimer]));
3964
3965 CLEAR_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
3966 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3967 }
3968
3969 /**
3970 * @brief Indicate whether the Re-Syncronisation Update is enabled.
3971 * @note This bit specifies whether update source coming outside
3972 * from the timing unit must be synchronized
3973 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_IsEnabledResyncUpdate
3974 * @param HRTIMx High Resolution Timer instance
3975 * @param Timer This parameter can be one of the following values:
3976 * @arg @ref LL_HRTIM_TIMER_A
3977 * @arg @ref LL_HRTIM_TIMER_B
3978 * @arg @ref LL_HRTIM_TIMER_C
3979 * @arg @ref LL_HRTIM_TIMER_D
3980 * @arg @ref LL_HRTIM_TIMER_E
3981 * @arg @ref LL_HRTIM_TIMER_F
3982 * @retval State of RSYNC bit in HRTIM_TIMxCR register (1 or 0).
3983 */
LL_HRTIM_TIM_IsEnabledResyncUpdate(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3984 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3985 {
3986 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3987 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3988 REG_OFFSET_TAB_TIMER[iTimer]));
3989
3990 return ((READ_BIT(*pReg, HRTIM_TIMCR_RSYNCU) == (HRTIM_TIMCR_RSYNCU)) ? 1UL : 0UL);
3991 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3992 }
3993
3994 /**
3995 * @note Interleaved mode complements the Half mode and helps the implementation of interleaved topologies.
3996 * @note When interleaved mode is enabled, the content of the compare registers is overridden.
3997 * @rmtoll MCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
3998 * MCR INTLVD LL_HRTIM_TIM_SetInterleavedMode\n
3999 * TIMxCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
4000 * TIMxCR INTLVD LL_HRTIM_TIM_SetInterleavedMode
4001 * @param HRTIMx High Resolution Timer instance
4002 * @param Timer This parameter can be one of the following values:
4003 * @arg @ref LL_HRTIM_TIMER_MASTER
4004 * @arg @ref LL_HRTIM_TIMER_A
4005 * @arg @ref LL_HRTIM_TIMER_B
4006 * @arg @ref LL_HRTIM_TIMER_C
4007 * @arg @ref LL_HRTIM_TIMER_D
4008 * @arg @ref LL_HRTIM_TIMER_E
4009 * @arg @ref LL_HRTIM_TIMER_F
4010 * @param Mode This parameter can be one of the following values:
4011 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
4012 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
4013 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
4014 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
4015 * @retval None
4016 */
LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)4017 __STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
4018 {
4019 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4020 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4021
4022 MODIFY_REG(*pReg, REG_MASK_TAB_INTLVD[iTimer],
4023 ((Mode & HRTIM_MCR_HALF) | ((Mode & HRTIM_MCR_INTLVD) << REG_SHIFT_TAB_INTLVD[iTimer])));
4024 }
4025
4026 /**
4027 * @brief get the Interleaved configuration.
4028 * @rmtoll MCR INTLVD LL_HRTIM_TIM_GetInterleavedMode\n
4029 * TIMxCR INTLVD LL_HRTIM_TIM_GetInterleavedMode
4030 * @note The interleaved Mode is Triple or Quad if HALF bit is disabled
4031 * the interleaved Mode is dual if HALF bit is set,
4032
4033 * HRTIM_MCMP1R (or HRTIM_CMP1xR) active register is automatically updated
4034 * with HRTIM_MPER/2 or HRTIM_MPER/4
4035 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
4036
4037 * @param HRTIMx High Resolution Timer instance
4038 * @param Timer This parameter can be one of the following values:
4039 * @arg @ref LL_HRTIM_TIMER_MASTER
4040 * @arg @ref LL_HRTIM_TIMER_A
4041 * @arg @ref LL_HRTIM_TIMER_B
4042 * @arg @ref LL_HRTIM_TIMER_C
4043 * @arg @ref LL_HRTIM_TIMER_D
4044 * @arg @ref LL_HRTIM_TIMER_E
4045 * @arg @ref LL_HRTIM_TIMER_F
4046 * @retval This parameter can be one of the following values:
4047 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
4048 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
4049 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
4050 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
4051 */
LL_HRTIM_TIM_GetInterleavedMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4052 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4053 {
4054 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4055 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4056
4057 uint32_t Mode = READ_BIT(*pReg, (REG_MASK_TAB_INTLVD[iTimer]));
4058 return ((Mode & HRTIM_MCR_HALF) | ((Mode >> REG_SHIFT_TAB_INTLVD[iTimer]) & HRTIM_MCR_INTLVD));
4059 }
4060
4061 /**
4062 * @brief Enable the timer start when receiving a synchronization input event.
4063 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
4064 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
4065 * @param HRTIMx High Resolution Timer instance
4066 * @param Timer This parameter can be one of the following values:
4067 * @arg @ref LL_HRTIM_TIMER_MASTER
4068 * @arg @ref LL_HRTIM_TIMER_A
4069 * @arg @ref LL_HRTIM_TIMER_B
4070 * @arg @ref LL_HRTIM_TIMER_C
4071 * @arg @ref LL_HRTIM_TIMER_D
4072 * @arg @ref LL_HRTIM_TIMER_E
4073 * @arg @ref LL_HRTIM_TIMER_F
4074 * @retval None
4075 */
LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4076 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4077 {
4078 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4079 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4080 SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
4081 }
4082
4083 /**
4084 * @brief Disable the timer start when receiving a synchronization input event.
4085 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
4086 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
4087 * @param HRTIMx High Resolution Timer instance
4088 * @param Timer This parameter can be one of the following values:
4089 * @arg @ref LL_HRTIM_TIMER_MASTER
4090 * @arg @ref LL_HRTIM_TIMER_A
4091 * @arg @ref LL_HRTIM_TIMER_B
4092 * @arg @ref LL_HRTIM_TIMER_C
4093 * @arg @ref LL_HRTIM_TIMER_D
4094 * @arg @ref LL_HRTIM_TIMER_E
4095 * @arg @ref LL_HRTIM_TIMER_F
4096 * @retval None
4097 */
LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4098 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4099 {
4100 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4101 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4102 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
4103 }
4104
4105 /**
4106 * @brief Indicate whether the timer start when receiving a synchronization input event.
4107 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
4108 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
4109 * @param HRTIMx High Resolution Timer instance
4110 * @param Timer This parameter can be one of the following values:
4111 * @arg @ref LL_HRTIM_TIMER_MASTER
4112 * @arg @ref LL_HRTIM_TIMER_A
4113 * @arg @ref LL_HRTIM_TIMER_B
4114 * @arg @ref LL_HRTIM_TIMER_C
4115 * @arg @ref LL_HRTIM_TIMER_D
4116 * @arg @ref LL_HRTIM_TIMER_E
4117 * @arg @ref LL_HRTIM_TIMER_F
4118 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
4119 */
LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4120 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4121 {
4122 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4123 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4124
4125 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
4126 }
4127
4128 /**
4129 * @brief Enable the timer reset when receiving a synchronization input event.
4130 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
4131 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
4132 * @param HRTIMx High Resolution Timer instance
4133 * @param Timer This parameter can be one of the following values:
4134 * @arg @ref LL_HRTIM_TIMER_MASTER
4135 * @arg @ref LL_HRTIM_TIMER_A
4136 * @arg @ref LL_HRTIM_TIMER_B
4137 * @arg @ref LL_HRTIM_TIMER_C
4138 * @arg @ref LL_HRTIM_TIMER_D
4139 * @arg @ref LL_HRTIM_TIMER_E
4140 * @arg @ref LL_HRTIM_TIMER_F
4141 * @retval None
4142 */
LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4143 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4144 {
4145 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4146 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4147 SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
4148 }
4149
4150 /**
4151 * @brief Disable the timer reset when receiving a synchronization input event.
4152 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
4153 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
4154 * @param HRTIMx High Resolution Timer instance
4155 * @param Timer This parameter can be one of the following values:
4156 * @arg @ref LL_HRTIM_TIMER_MASTER
4157 * @arg @ref LL_HRTIM_TIMER_A
4158 * @arg @ref LL_HRTIM_TIMER_B
4159 * @arg @ref LL_HRTIM_TIMER_C
4160 * @arg @ref LL_HRTIM_TIMER_D
4161 * @arg @ref LL_HRTIM_TIMER_E
4162 * @arg @ref LL_HRTIM_TIMER_F
4163 * @retval None
4164 */
LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4165 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4166 {
4167 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4168 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4169 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
4170 }
4171
4172 /**
4173 * @brief Indicate whether the timer reset when receiving a synchronization input event.
4174 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
4175 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
4176 * @param HRTIMx High Resolution Timer instance
4177 * @param Timer This parameter can be one of the following values:
4178 * @arg @ref LL_HRTIM_TIMER_MASTER
4179 * @arg @ref LL_HRTIM_TIMER_A
4180 * @arg @ref LL_HRTIM_TIMER_B
4181 * @arg @ref LL_HRTIM_TIMER_C
4182 * @arg @ref LL_HRTIM_TIMER_D
4183 * @arg @ref LL_HRTIM_TIMER_E
4184 * @arg @ref LL_HRTIM_TIMER_F
4185 * @retval None
4186 */
LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4187 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4188 {
4189 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4190 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4191
4192 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
4193 }
4194
4195 /**
4196 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
4197 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
4198 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
4199 * @param HRTIMx High Resolution Timer instance
4200 * @param Timer This parameter can be one of the following values:
4201 * @arg @ref LL_HRTIM_TIMER_MASTER
4202 * @arg @ref LL_HRTIM_TIMER_A
4203 * @arg @ref LL_HRTIM_TIMER_B
4204 * @arg @ref LL_HRTIM_TIMER_C
4205 * @arg @ref LL_HRTIM_TIMER_D
4206 * @arg @ref LL_HRTIM_TIMER_E
4207 * @arg @ref LL_HRTIM_TIMER_F
4208 * @param DACTrig This parameter can be one of the following values:
4209 * @arg @ref LL_HRTIM_DACTRIG_NONE
4210 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
4211 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
4212 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
4213 * @retval None
4214 */
LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DACTrig)4215 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
4216 {
4217 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4218 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4219 MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
4220 }
4221
4222 /**
4223 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
4224 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
4225 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
4226 * @param HRTIMx High Resolution Timer instance
4227 * @param Timer This parameter can be one of the following values:
4228 * @arg @ref LL_HRTIM_TIMER_MASTER
4229 * @arg @ref LL_HRTIM_TIMER_A
4230 * @arg @ref LL_HRTIM_TIMER_B
4231 * @arg @ref LL_HRTIM_TIMER_C
4232 * @arg @ref LL_HRTIM_TIMER_D
4233 * @arg @ref LL_HRTIM_TIMER_E
4234 * @arg @ref LL_HRTIM_TIMER_F
4235 * @retval DACTrig Returned value can be one of the following values:
4236 * @arg @ref LL_HRTIM_DACTRIG_NONE
4237 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
4238 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
4239 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
4240 */
LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4241 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4242 {
4243 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4244 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4245 return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
4246 }
4247
4248 /**
4249 * @brief Enable the timer registers preload mechanism.
4250 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
4251 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
4252 * @note When the preload mode is enabled, accessed registers are shadow registers.
4253 * Their content is transferred into the active register after an update request,
4254 * either software or synchronized with an event.
4255 * @param HRTIMx High Resolution Timer instance
4256 * @param Timer This parameter can be one of the following values:
4257 * @arg @ref LL_HRTIM_TIMER_MASTER
4258 * @arg @ref LL_HRTIM_TIMER_A
4259 * @arg @ref LL_HRTIM_TIMER_B
4260 * @arg @ref LL_HRTIM_TIMER_C
4261 * @arg @ref LL_HRTIM_TIMER_D
4262 * @arg @ref LL_HRTIM_TIMER_E
4263 * @arg @ref LL_HRTIM_TIMER_F
4264 * @retval None
4265 */
LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4266 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4267 {
4268 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4269 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4270 SET_BIT(*pReg, HRTIM_MCR_PREEN);
4271 }
4272
4273 /**
4274 * @brief Disable the timer registers preload mechanism.
4275 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
4276 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
4277 * @param HRTIMx High Resolution Timer instance
4278 * @param Timer This parameter can be one of the following values:
4279 * @arg @ref LL_HRTIM_TIMER_MASTER
4280 * @arg @ref LL_HRTIM_TIMER_A
4281 * @arg @ref LL_HRTIM_TIMER_B
4282 * @arg @ref LL_HRTIM_TIMER_C
4283 * @arg @ref LL_HRTIM_TIMER_D
4284 * @arg @ref LL_HRTIM_TIMER_E
4285 * @arg @ref LL_HRTIM_TIMER_F
4286 * @retval None
4287 */
LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4288 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4289 {
4290 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4291 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4292 CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
4293 }
4294
4295 /**
4296 * @brief Indicate whether the timer registers preload mechanism is enabled.
4297 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
4298 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
4299 * @param HRTIMx High Resolution Timer instance
4300 * @param Timer This parameter can be one of the following values:
4301 * @arg @ref LL_HRTIM_TIMER_MASTER
4302 * @arg @ref LL_HRTIM_TIMER_A
4303 * @arg @ref LL_HRTIM_TIMER_B
4304 * @arg @ref LL_HRTIM_TIMER_C
4305 * @arg @ref LL_HRTIM_TIMER_D
4306 * @arg @ref LL_HRTIM_TIMER_E
4307 * @arg @ref LL_HRTIM_TIMER_F
4308 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
4309 */
LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4310 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4311 {
4312 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4313 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4314
4315 return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
4316 }
4317
4318 /**
4319 * @brief Set the timer register update trigger.
4320 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
4321 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
4322 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
4323 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
4324 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
4325 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
4326 * TIMxCR TFU LL_HRTIM_TIM_SetUpdateTrig\n
4327 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
4328 * @param HRTIMx High Resolution Timer instance
4329 * @param Timer This parameter can be one of the following values:
4330 * @arg @ref LL_HRTIM_TIMER_MASTER
4331 * @arg @ref LL_HRTIM_TIMER_A
4332 * @arg @ref LL_HRTIM_TIMER_B
4333 * @arg @ref LL_HRTIM_TIMER_C
4334 * @arg @ref LL_HRTIM_TIMER_D
4335 * @arg @ref LL_HRTIM_TIMER_E
4336 * @arg @ref LL_HRTIM_TIMER_F
4337 * @param UpdateTrig This parameter can be one of the following values:
4338 *
4339 * For the master timer this parameter can be one of the following values:
4340 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4341 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4342 *
4343 * For timer A..F this parameter can be:
4344 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4345 * or a combination of the following values:
4346 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
4347 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
4348 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
4349 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
4350 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
4351 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
4352 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
4353 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4354 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
4355 * @retval None
4356 */
LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateTrig)4357 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
4358 {
4359 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4360 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4361 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
4362 }
4363
4364 /**
4365 * @brief Get the timer register update trigger.
4366 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
4367 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
4368 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
4369 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
4370 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
4371 * TIMxCR TFU LL_HRTIM_TIM_GetUpdateTrig\n
4372 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
4373 * @param HRTIMx High Resolution Timer instance
4374 * @param Timer This parameter can be one of the following values:
4375 * @arg @ref LL_HRTIM_TIMER_MASTER
4376 * @arg @ref LL_HRTIM_TIMER_A
4377 * @arg @ref LL_HRTIM_TIMER_B
4378 * @arg @ref LL_HRTIM_TIMER_C
4379 * @arg @ref LL_HRTIM_TIMER_D
4380 * @arg @ref LL_HRTIM_TIMER_E
4381 * @arg @ref LL_HRTIM_TIMER_F
4382 * @retval UpdateTrig Returned value can be one of the following values:
4383 *
4384 * For the master timer this parameter can be one of the following values:
4385 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4386 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4387 *
4388 * For timer A..F this parameter can be:
4389 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4390 * or a combination of the following values:
4391 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
4392 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
4393 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
4394 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
4395 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
4396 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
4397 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
4398 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4399 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
4400 */
LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4401 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4402 {
4403 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4404 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4405 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
4406 }
4407
4408 /**
4409 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
4410 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
4411 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
4412 * @param HRTIMx High Resolution Timer instance
4413 * @param Timer This parameter can be one of the following values:
4414 * @arg @ref LL_HRTIM_TIMER_MASTER
4415 * @arg @ref LL_HRTIM_TIMER_A
4416 * @arg @ref LL_HRTIM_TIMER_B
4417 * @arg @ref LL_HRTIM_TIMER_C
4418 * @arg @ref LL_HRTIM_TIMER_D
4419 * @arg @ref LL_HRTIM_TIMER_E
4420 * @arg @ref LL_HRTIM_TIMER_F
4421 * @param UpdateGating This parameter can be one of the following values:
4422 *
4423 * For the master timer this parameter can be one of the following values:
4424 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4425 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4426 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4427 *
4428 * For the timer A..F this parameter can be one of the following values:
4429 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4430 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4431 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4432 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
4433 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
4434 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
4435 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
4436 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
4437 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
4438 * @retval None
4439 */
LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateGating)4440 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
4441 {
4442 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4443 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4444 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
4445 }
4446
4447 /**
4448 * @brief Get the timer registers update condition.
4449 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
4450 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
4451 * @param HRTIMx High Resolution Timer instance
4452 * @param Timer This parameter can be one of the following values:
4453 * @arg @ref LL_HRTIM_TIMER_MASTER
4454 * @arg @ref LL_HRTIM_TIMER_A
4455 * @arg @ref LL_HRTIM_TIMER_B
4456 * @arg @ref LL_HRTIM_TIMER_C
4457 * @arg @ref LL_HRTIM_TIMER_D
4458 * @arg @ref LL_HRTIM_TIMER_E
4459 * @arg @ref LL_HRTIM_TIMER_F
4460 * @retval UpdateGating Returned value can be one of the following values:
4461 *
4462 * For the master timer this parameter can be one of the following values:
4463 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4464 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4465 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4466 *
4467 * For the timer A..F this parameter can be one of the following values:
4468 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4469 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4470 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4471 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
4472 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
4473 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
4474 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
4475 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
4476 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
4477 */
LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4478 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4479 {
4480 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4481 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4482 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
4483 }
4484
4485 /**
4486 * @brief Enable the push-pull mode.
4487 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
4488 * @param HRTIMx High Resolution Timer instance
4489 * @param Timer This parameter can be one of the following values:
4490 * @arg @ref LL_HRTIM_TIMER_A
4491 * @arg @ref LL_HRTIM_TIMER_B
4492 * @arg @ref LL_HRTIM_TIMER_C
4493 * @arg @ref LL_HRTIM_TIMER_D
4494 * @arg @ref LL_HRTIM_TIMER_E
4495 * @arg @ref LL_HRTIM_TIMER_F
4496 * @retval None
4497 */
LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4498 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4499 {
4500 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4501 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4502 REG_OFFSET_TAB_TIMER[iTimer]));
4503 SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
4504 }
4505
4506 /**
4507 * @brief Disable the push-pull mode.
4508 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
4509 * @param HRTIMx High Resolution Timer instance
4510 * @param Timer This parameter can be one of the following values:
4511 * @arg @ref LL_HRTIM_TIMER_A
4512 * @arg @ref LL_HRTIM_TIMER_B
4513 * @arg @ref LL_HRTIM_TIMER_C
4514 * @arg @ref LL_HRTIM_TIMER_D
4515 * @arg @ref LL_HRTIM_TIMER_E
4516 * @arg @ref LL_HRTIM_TIMER_F
4517 * @retval None
4518 */
LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4519 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4520 {
4521 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4522 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4523 REG_OFFSET_TAB_TIMER[iTimer]));
4524 CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
4525 }
4526
4527 /**
4528 * @brief Indicate whether the push-pull mode is enabled.
4529 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
4530 * @param HRTIMx High Resolution Timer instance
4531 * @param Timer This parameter can be one of the following values:
4532 * @arg @ref LL_HRTIM_TIMER_A
4533 * @arg @ref LL_HRTIM_TIMER_B
4534 * @arg @ref LL_HRTIM_TIMER_C
4535 * @arg @ref LL_HRTIM_TIMER_D
4536 * @arg @ref LL_HRTIM_TIMER_E
4537 * @arg @ref LL_HRTIM_TIMER_F
4538 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
4539 */
LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4540 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4541 {
4542 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4543 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4544 REG_OFFSET_TAB_TIMER[iTimer]));
4545 return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
4546 }
4547
4548 /**
4549 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
4550 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
4551 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
4552 * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
4553 * @param HRTIMx High Resolution Timer instance
4554 * @param Timer This parameter can be one of the following values:
4555 * @arg @ref LL_HRTIM_TIMER_A
4556 * @arg @ref LL_HRTIM_TIMER_B
4557 * @arg @ref LL_HRTIM_TIMER_C
4558 * @arg @ref LL_HRTIM_TIMER_D
4559 * @arg @ref LL_HRTIM_TIMER_E
4560 * @arg @ref LL_HRTIM_TIMER_F
4561 * @param CompareUnit This parameter can be one of the following values:
4562 * @arg @ref LL_HRTIM_COMPAREUNIT_2
4563 * @arg @ref LL_HRTIM_COMPAREUNIT_4
4564 * @param Mode This parameter can be one of the following values:
4565 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
4566 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
4567 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
4568 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
4569 * @retval None
4570 */
LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit,uint32_t Mode)4571 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
4572 uint32_t Mode)
4573 {
4574 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4575 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4576 REG_OFFSET_TAB_TIMER[iTimer]));
4577 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
4578 MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
4579 }
4580
4581 /**
4582 * @brief Get the functioning mode of the compare unit.
4583 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
4584 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
4585 * @param HRTIMx High Resolution Timer instance
4586 * @param Timer This parameter can be one of the following values:
4587 * @arg @ref LL_HRTIM_TIMER_A
4588 * @arg @ref LL_HRTIM_TIMER_B
4589 * @arg @ref LL_HRTIM_TIMER_C
4590 * @arg @ref LL_HRTIM_TIMER_D
4591 * @arg @ref LL_HRTIM_TIMER_E
4592 * @arg @ref LL_HRTIM_TIMER_F
4593 * @param CompareUnit This parameter can be one of the following values:
4594 * @arg @ref LL_HRTIM_COMPAREUNIT_2
4595 * @arg @ref LL_HRTIM_COMPAREUNIT_4
4596 * @retval Mode Returned value can be one of the following values:
4597 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
4598 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
4599 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
4600 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
4601 */
LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit)4602 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
4603 {
4604 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4605 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4606 REG_OFFSET_TAB_TIMER[iTimer]));
4607 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
4608 return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
4609 }
4610
4611 /**
4612 * @brief Set the timer counter value.
4613 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
4614 * CNTxR CNTx LL_HRTIM_TIM_SetCounter
4615 * @note This function can only be called when the timer is stopped.
4616 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
4617 * significant bits of the counter are not significant. They cannot be
4618 * written and return 0 when read.
4619 * @note The timer behavior is not guaranteed if the counter value is set above
4620 * the period.
4621 * @param HRTIMx High Resolution Timer instance
4622 * @param Timer This parameter can be one of the following values:
4623 * @arg @ref LL_HRTIM_TIMER_MASTER
4624 * @arg @ref LL_HRTIM_TIMER_A
4625 * @arg @ref LL_HRTIM_TIMER_B
4626 * @arg @ref LL_HRTIM_TIMER_C
4627 * @arg @ref LL_HRTIM_TIMER_D
4628 * @arg @ref LL_HRTIM_TIMER_E
4629 * @arg @ref LL_HRTIM_TIMER_F
4630 * @param Counter Value between 0 and 0xFFFF
4631 * @retval None
4632 */
LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Counter)4633 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
4634 {
4635 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4636 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
4637 REG_OFFSET_TAB_TIMER[iTimer]));
4638 MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
4639 }
4640
4641 /**
4642 * @brief Get actual timer counter value.
4643 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
4644 * CNTxR CNTx LL_HRTIM_TIM_GetCounter
4645 * @param HRTIMx High Resolution Timer instance
4646 * @param Timer This parameter can be one of the following values:
4647 * @arg @ref LL_HRTIM_TIMER_MASTER
4648 * @arg @ref LL_HRTIM_TIMER_A
4649 * @arg @ref LL_HRTIM_TIMER_B
4650 * @arg @ref LL_HRTIM_TIMER_C
4651 * @arg @ref LL_HRTIM_TIMER_D
4652 * @arg @ref LL_HRTIM_TIMER_E
4653 * @arg @ref LL_HRTIM_TIMER_F
4654 * @retval Counter Value between 0 and 0xFFFF
4655 */
LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4656 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4657 {
4658 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4659 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
4660 REG_OFFSET_TAB_TIMER[iTimer]));
4661 return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
4662 }
4663
4664 /**
4665 * @brief Set the timer period value.
4666 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
4667 * PERxR PERx LL_HRTIM_TIM_SetPeriod
4668 * @param HRTIMx High Resolution Timer instance
4669 * @param Timer This parameter can be one of the following values:
4670 * @arg @ref LL_HRTIM_TIMER_MASTER
4671 * @arg @ref LL_HRTIM_TIMER_A
4672 * @arg @ref LL_HRTIM_TIMER_B
4673 * @arg @ref LL_HRTIM_TIMER_C
4674 * @arg @ref LL_HRTIM_TIMER_D
4675 * @arg @ref LL_HRTIM_TIMER_E
4676 * @arg @ref LL_HRTIM_TIMER_F
4677 * @param Period Value between 0 and 0xFFFF
4678 * @retval None
4679 */
LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Period)4680 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
4681 {
4682 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4683 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
4684 REG_OFFSET_TAB_TIMER[iTimer]));
4685 MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
4686 }
4687
4688 /**
4689 * @brief Get actual timer period value.
4690 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
4691 * PERxR PERx LL_HRTIM_TIM_GetPeriod
4692 * @param HRTIMx High Resolution Timer instance
4693 * @param Timer This parameter can be one of the following values:
4694 * @arg @ref LL_HRTIM_TIMER_MASTER
4695 * @arg @ref LL_HRTIM_TIMER_A
4696 * @arg @ref LL_HRTIM_TIMER_B
4697 * @arg @ref LL_HRTIM_TIMER_C
4698 * @arg @ref LL_HRTIM_TIMER_D
4699 * @arg @ref LL_HRTIM_TIMER_E
4700 * @arg @ref LL_HRTIM_TIMER_F
4701 * @retval Period Value between 0 and 0xFFFF
4702 */
LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4703 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4704 {
4705 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4706 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
4707 REG_OFFSET_TAB_TIMER[iTimer]));
4708 return (READ_BIT(*pReg, HRTIM_MPER_MPER));
4709 }
4710
4711 /**
4712 * @brief Set the timer repetition period value.
4713 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
4714 * REPxR REPx LL_HRTIM_TIM_SetRepetition
4715 * @param HRTIMx High Resolution Timer instance
4716 * @param Timer This parameter can be one of the following values:
4717 * @arg @ref LL_HRTIM_TIMER_MASTER
4718 * @arg @ref LL_HRTIM_TIMER_A
4719 * @arg @ref LL_HRTIM_TIMER_B
4720 * @arg @ref LL_HRTIM_TIMER_C
4721 * @arg @ref LL_HRTIM_TIMER_D
4722 * @arg @ref LL_HRTIM_TIMER_E
4723 * @arg @ref LL_HRTIM_TIMER_F
4724 * @param Repetition Value between 0 and 0xFF
4725 * @retval None
4726 */
LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Repetition)4727 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
4728 {
4729 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4730 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
4731 REG_OFFSET_TAB_TIMER[iTimer]));
4732 MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
4733 }
4734
4735 /**
4736 * @brief Get actual timer repetition period value.
4737 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
4738 * REPxR REPx LL_HRTIM_TIM_GetRepetition
4739 * @param HRTIMx High Resolution Timer instance
4740 * @param Timer This parameter can be one of the following values:
4741 * @arg @ref LL_HRTIM_TIMER_MASTER
4742 * @arg @ref LL_HRTIM_TIMER_A
4743 * @arg @ref LL_HRTIM_TIMER_B
4744 * @arg @ref LL_HRTIM_TIMER_C
4745 * @arg @ref LL_HRTIM_TIMER_D
4746 * @arg @ref LL_HRTIM_TIMER_E
4747 * @arg @ref LL_HRTIM_TIMER_F
4748 * @retval Repetition Value between 0 and 0xFF
4749 */
LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4750 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4751 {
4752 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4753 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
4754 REG_OFFSET_TAB_TIMER[iTimer]));
4755 return (READ_BIT(*pReg, HRTIM_MREP_MREP));
4756 }
4757
4758 /**
4759 * @brief Set the compare value of the compare unit 1.
4760 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
4761 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
4762 * @param HRTIMx High Resolution Timer instance
4763 * @param Timer This parameter can be one of the following values:
4764 * @arg @ref LL_HRTIM_TIMER_MASTER
4765 * @arg @ref LL_HRTIM_TIMER_A
4766 * @arg @ref LL_HRTIM_TIMER_B
4767 * @arg @ref LL_HRTIM_TIMER_C
4768 * @arg @ref LL_HRTIM_TIMER_D
4769 * @arg @ref LL_HRTIM_TIMER_E
4770 * @arg @ref LL_HRTIM_TIMER_F
4771 * @param CompareValue Compare value must be above or equal to 3
4772 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4773 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4774 * @retval None
4775 */
LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4776 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4777 {
4778 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4779 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
4780 REG_OFFSET_TAB_TIMER[iTimer]));
4781 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
4782 }
4783
4784 /**
4785 * @brief Get actual compare value of the compare unit 1.
4786 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
4787 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
4788 * @param HRTIMx High Resolution Timer instance
4789 * @param Timer This parameter can be one of the following values:
4790 * @arg @ref LL_HRTIM_TIMER_MASTER
4791 * @arg @ref LL_HRTIM_TIMER_A
4792 * @arg @ref LL_HRTIM_TIMER_B
4793 * @arg @ref LL_HRTIM_TIMER_C
4794 * @arg @ref LL_HRTIM_TIMER_D
4795 * @arg @ref LL_HRTIM_TIMER_E
4796 * @arg @ref LL_HRTIM_TIMER_F
4797 * @retval CompareValue Compare value must be above or equal to 3
4798 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4799 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4800 */
LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4801 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4802 {
4803 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4804 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
4805 REG_OFFSET_TAB_TIMER[iTimer]));
4806 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
4807 }
4808
4809 /**
4810 * @brief Set the compare value of the compare unit 2.
4811 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
4812 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
4813 * @param HRTIMx High Resolution Timer instance
4814 * @param Timer This parameter can be one of the following values:
4815 * @arg @ref LL_HRTIM_TIMER_MASTER
4816 * @arg @ref LL_HRTIM_TIMER_A
4817 * @arg @ref LL_HRTIM_TIMER_B
4818 * @arg @ref LL_HRTIM_TIMER_C
4819 * @arg @ref LL_HRTIM_TIMER_D
4820 * @arg @ref LL_HRTIM_TIMER_E
4821 * @arg @ref LL_HRTIM_TIMER_F
4822 * @param CompareValue Compare value must be above or equal to 3
4823 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4824 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4825 * @retval None
4826 */
LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4827 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4828 {
4829 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4830 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
4831 REG_OFFSET_TAB_TIMER[iTimer]));
4832 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
4833 }
4834
4835 /**
4836 * @brief Get actual compare value of the compare unit 2.
4837 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
4838 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
4839 * @param HRTIMx High Resolution Timer instance
4840 * @param Timer This parameter can be one of the following values:
4841 * @arg @ref LL_HRTIM_TIMER_MASTER
4842 * @arg @ref LL_HRTIM_TIMER_A
4843 * @arg @ref LL_HRTIM_TIMER_B
4844 * @arg @ref LL_HRTIM_TIMER_C
4845 * @arg @ref LL_HRTIM_TIMER_D
4846 * @arg @ref LL_HRTIM_TIMER_E
4847 * @arg @ref LL_HRTIM_TIMER_F
4848 * @retval CompareValue Compare value must be above or equal to 3
4849 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4850 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4851 */
LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4852 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4853 {
4854 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4855 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
4856 REG_OFFSET_TAB_TIMER[iTimer]));
4857 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
4858 }
4859
4860 /**
4861 * @brief Set the compare value of the compare unit 3.
4862 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
4863 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
4864 * @param HRTIMx High Resolution Timer instance
4865 * @param Timer This parameter can be one of the following values:
4866 * @arg @ref LL_HRTIM_TIMER_MASTER
4867 * @arg @ref LL_HRTIM_TIMER_A
4868 * @arg @ref LL_HRTIM_TIMER_B
4869 * @arg @ref LL_HRTIM_TIMER_C
4870 * @arg @ref LL_HRTIM_TIMER_D
4871 * @arg @ref LL_HRTIM_TIMER_E
4872 * @arg @ref LL_HRTIM_TIMER_F
4873 * @param CompareValue Compare value must be above or equal to 3
4874 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4875 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4876 * @retval None
4877 */
LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4878 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4879 {
4880 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4881 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
4882 REG_OFFSET_TAB_TIMER[iTimer]));
4883 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
4884 }
4885
4886 /**
4887 * @brief Get actual compare value of the compare unit 3.
4888 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
4889 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
4890 * @param HRTIMx High Resolution Timer instance
4891 * @param Timer This parameter can be one of the following values:
4892 * @arg @ref LL_HRTIM_TIMER_MASTER
4893 * @arg @ref LL_HRTIM_TIMER_A
4894 * @arg @ref LL_HRTIM_TIMER_B
4895 * @arg @ref LL_HRTIM_TIMER_C
4896 * @arg @ref LL_HRTIM_TIMER_D
4897 * @arg @ref LL_HRTIM_TIMER_E
4898 * @arg @ref LL_HRTIM_TIMER_F
4899 * @retval CompareValue Compare value must be above or equal to 3
4900 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4901 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4902 */
LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4903 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4904 {
4905 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4906 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
4907 REG_OFFSET_TAB_TIMER[iTimer]));
4908 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
4909 }
4910
4911 /**
4912 * @brief Set the compare value of the compare unit 4.
4913 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
4914 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
4915 * @param HRTIMx High Resolution Timer instance
4916 * @param Timer This parameter can be one of the following values:
4917 * @arg @ref LL_HRTIM_TIMER_MASTER
4918 * @arg @ref LL_HRTIM_TIMER_A
4919 * @arg @ref LL_HRTIM_TIMER_B
4920 * @arg @ref LL_HRTIM_TIMER_C
4921 * @arg @ref LL_HRTIM_TIMER_D
4922 * @arg @ref LL_HRTIM_TIMER_E
4923 * @arg @ref LL_HRTIM_TIMER_F
4924 * @param CompareValue Compare value must be above or equal to 3
4925 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4926 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4927 * @retval None
4928 */
LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4929 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4930 {
4931 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4932 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
4933 REG_OFFSET_TAB_TIMER[iTimer]));
4934 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
4935 }
4936
4937 /**
4938 * @brief Get actual compare value of the compare unit 4.
4939 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
4940 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
4941 * @param HRTIMx High Resolution Timer instance
4942 * @param Timer This parameter can be one of the following values:
4943 * @arg @ref LL_HRTIM_TIMER_MASTER
4944 * @arg @ref LL_HRTIM_TIMER_A
4945 * @arg @ref LL_HRTIM_TIMER_B
4946 * @arg @ref LL_HRTIM_TIMER_C
4947 * @arg @ref LL_HRTIM_TIMER_D
4948 * @arg @ref LL_HRTIM_TIMER_E
4949 * @arg @ref LL_HRTIM_TIMER_F
4950 * @retval CompareValue Compare value must be above or equal to 3
4951 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4952 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4953 */
LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4954 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4955 {
4956 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4957 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
4958 REG_OFFSET_TAB_TIMER[iTimer]));
4959 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
4960 }
4961
4962 /**
4963 * @brief Set the reset trigger of a timer counter.
4964 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
4965 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
4966 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
4967 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
4968 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
4969 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
4970 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
4971 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
4972 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
4973 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
4974 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
4975 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
4976 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
4977 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
4978 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
4979 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
4980 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
4981 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
4982 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
4983 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
4984 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
4985 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
4986 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
4987 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
4988 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
4989 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
4990 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
4991 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
4992 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
4993 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig\n
4994 * RSTxR TIMFCMP1 LL_HRTIM_TIM_SetResetTrig\n
4995 * RSTxR TIMFCMP2 LL_HRTIM_TIM_SetResetTrig
4996 * @note The reset of the timer counter can be triggered by up to 30 events
4997 * that can be selected among the following sources:
4998 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
4999 * @arg The master timer: Reset and Compare 1..4 (5 events).
5000 * @arg The external events EXTEVNT1..10 (10 events).
5001 * @arg All other timing units (e.g. Timer B..F for timer A): Compare 1, 2 and 4 (12 events).
5002 * @param HRTIMx High Resolution Timer instance
5003 * @param Timer This parameter can be one of the following values:
5004 * @arg @ref LL_HRTIM_TIMER_A
5005 * @arg @ref LL_HRTIM_TIMER_B
5006 * @arg @ref LL_HRTIM_TIMER_C
5007 * @arg @ref LL_HRTIM_TIMER_D
5008 * @arg @ref LL_HRTIM_TIMER_E
5009 * @arg @ref LL_HRTIM_TIMER_F
5010 * @param ResetTrig This parameter can be a combination of the following values:
5011 * @arg @ref LL_HRTIM_RESETTRIG_NONE
5012 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
5013 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
5014 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
5015 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
5016 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
5017 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
5018 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
5019 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
5020 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
5021 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
5022 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
5023 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
5024 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
5025 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
5026 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
5027 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
5028 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
5029 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
5030 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
5031 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
5032 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
5033 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
5034 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
5035 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
5036 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
5037 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
5038 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
5039 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
5040 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
5041 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
5042 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
5043 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
5044 * @retval None
5045 */
LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t ResetTrig)5046 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
5047 {
5048 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5049 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
5050 REG_OFFSET_TAB_TIMER[iTimer]));
5051 WRITE_REG(*pReg, ResetTrig);
5052 }
5053
5054 /**
5055 * @brief Get actual reset trigger of a timer counter.
5056 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
5057 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
5058 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
5059 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
5060 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
5061 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
5062 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
5063 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
5064 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
5065 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
5066 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
5067 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
5068 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
5069 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
5070 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
5071 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
5072 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
5073 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
5074 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
5075 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
5076 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
5077 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
5078 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
5079 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
5080 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
5081 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
5082 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
5083 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
5084 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
5085 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig\n
5086 * RSTxR TIMFCMP1 LL_HRTIM_TIM_GetResetTrig\n
5087 * RSTxR TIMFCMP2 LL_HRTIM_TIM_GetResetTrig
5088 * @param HRTIMx High Resolution Timer instance
5089 * @param Timer This parameter can be one of the following values:
5090 * @arg @ref LL_HRTIM_TIMER_A
5091 * @arg @ref LL_HRTIM_TIMER_B
5092 * @arg @ref LL_HRTIM_TIMER_C
5093 * @arg @ref LL_HRTIM_TIMER_D
5094 * @arg @ref LL_HRTIM_TIMER_E
5095 * @arg @ref LL_HRTIM_TIMER_F
5096 * @retval ResetTrig Returned value can be one of the following values:
5097 * @arg @ref LL_HRTIM_RESETTRIG_NONE
5098 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
5099 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
5100 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
5101 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
5102 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
5103 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
5104 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
5105 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
5106 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
5107 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
5108 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
5109 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
5110 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
5111 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
5112 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
5113 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
5114 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
5115 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
5116 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
5117 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
5118 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
5119 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
5120 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
5121 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
5122 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
5123 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
5124 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
5125 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
5126 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
5127 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
5128 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
5129 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
5130 */
LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5131 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5132 {
5133 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5134 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
5135 REG_OFFSET_TAB_TIMER[iTimer]));
5136 return (READ_REG(*pReg));
5137 }
5138
5139 /**
5140 * @brief Get captured value for capture unit 1.
5141 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
5142 * @param HRTIMx High Resolution Timer instance
5143 * @param Timer This parameter can be one of the following values:
5144 * @arg @ref LL_HRTIM_TIMER_A
5145 * @arg @ref LL_HRTIM_TIMER_B
5146 * @arg @ref LL_HRTIM_TIMER_C
5147 * @arg @ref LL_HRTIM_TIMER_D
5148 * @arg @ref LL_HRTIM_TIMER_E
5149 * @arg @ref LL_HRTIM_TIMER_F
5150 * @retval Captured value
5151 */
LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5152 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5153 {
5154 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5155 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
5156 REG_OFFSET_TAB_TIMER[iTimer]));
5157 return (READ_REG(*pReg));
5158 }
5159
5160 /**
5161 * @brief Get the counting direction when capture 1 event occurred.
5162 * @rmtoll CPT1xR DIR LL_HRTIM_TIM_GetCapture1Direction
5163 * @param HRTIMx High Resolution Timer instance
5164 * @param Timer This parameter can be one of the following values:
5165 * @arg @ref LL_HRTIM_TIMER_A
5166 * @arg @ref LL_HRTIM_TIMER_B
5167 * @arg @ref LL_HRTIM_TIMER_C
5168 * @arg @ref LL_HRTIM_TIMER_D
5169 * @arg @ref LL_HRTIM_TIMER_E
5170 * @arg @ref LL_HRTIM_TIMER_F
5171 * @retval Filter This parameter can be one of the following values:
5172 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
5173 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
5174 */
LL_HRTIM_TIM_GetCapture1Direction(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5175 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5176 {
5177 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5178 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
5179 REG_OFFSET_TAB_TIMER[iTimer]));
5180 return ((READ_BIT(*pReg, HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
5181 }
5182
5183 /**
5184 * @brief Get captured value for capture unit 2.
5185 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
5186 * @param HRTIMx High Resolution Timer instance
5187 * @param Timer This parameter can be one of the following values:
5188 * @arg @ref LL_HRTIM_TIMER_A
5189 * @arg @ref LL_HRTIM_TIMER_B
5190 * @arg @ref LL_HRTIM_TIMER_C
5191 * @arg @ref LL_HRTIM_TIMER_D
5192 * @arg @ref LL_HRTIM_TIMER_E
5193 * @arg @ref LL_HRTIM_TIMER_F
5194 * @retval Captured value
5195 */
LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5196 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5197 {
5198 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5199 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
5200 REG_OFFSET_TAB_TIMER[iTimer]));
5201 return (READ_REG(*pReg));
5202 }
5203
5204 /**
5205 * @brief Get the counting direction when capture 2 event occurred.
5206 * @rmtoll CPT2xR DIR LL_HRTIM_TIM_GetCapture2Direction
5207 * @param HRTIMx High Resolution Timer instance
5208 * @param Timer This parameter can be one of the following values:
5209 * @arg @ref LL_HRTIM_TIMER_A
5210 * @arg @ref LL_HRTIM_TIMER_B
5211 * @arg @ref LL_HRTIM_TIMER_C
5212 * @arg @ref LL_HRTIM_TIMER_D
5213 * @arg @ref LL_HRTIM_TIMER_E
5214 * @arg @ref LL_HRTIM_TIMER_F
5215 * @retval Filter This parameter can be one of the following values:
5216 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
5217 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
5218 */
LL_HRTIM_TIM_GetCapture2Direction(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5219 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5220 {
5221 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5222 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
5223 REG_OFFSET_TAB_TIMER[iTimer]));
5224 return ((READ_BIT(*pReg, HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
5225 }
5226
5227 /**
5228 * @brief Set the trigger of a capture unit for a given timer.
5229 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
5230 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
5231 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
5232 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
5233 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
5234 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
5235 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
5236 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
5237 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
5238 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
5239 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
5240 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
5241 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
5242 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
5243 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5244 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5245 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
5246 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
5247 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5248 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5249 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
5250 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
5251 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5252 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5253 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
5254 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
5255 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5256 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5257 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
5258 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
5259 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5260 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5261 * CPT1xCR TF1SET LL_HRTIM_TIM_SetCaptureTrig\n
5262 * CPT1xCR TF1RST LL_HRTIM_TIM_SetCaptureTrig\n
5263 * CPT1xCR TFCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5264 * CPT1xCR TFCMP2 LL_HRTIM_TIM_SetCaptureTrig
5265 * @param HRTIMx High Resolution Timer instance
5266 * @param Timer This parameter can be one of the following values:
5267 * @arg @ref LL_HRTIM_TIMER_A
5268 * @arg @ref LL_HRTIM_TIMER_B
5269 * @arg @ref LL_HRTIM_TIMER_C
5270 * @arg @ref LL_HRTIM_TIMER_D
5271 * @arg @ref LL_HRTIM_TIMER_E
5272 * @arg @ref LL_HRTIM_TIMER_F
5273 * @param CaptureUnit This parameter can be one of the following values:
5274 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
5275 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
5276 * @param CaptureTrig This parameter can be a combination of the following values:
5277 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
5278 * @arg @ref LL_HRTIM_CAPTURETRIG_SW
5279 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
5280 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
5281 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
5282 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
5283 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
5284 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
5285 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
5286 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
5287 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
5288 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
5289 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
5290 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
5291 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
5292 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
5293 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
5294 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
5295 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
5296 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
5297 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
5298 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
5299 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
5300 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
5301 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
5302 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
5303 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
5304 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
5305 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
5306 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
5307 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
5308 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
5309 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
5310 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
5311 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
5312 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
5313 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
5314 * @retval None
5315 */
LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit,uint64_t CaptureTrig)5316 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
5317 uint64_t CaptureTrig)
5318 {
5319 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5320 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
5321 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
5322
5323 uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU);
5324 uint32_t cfg2 = (uint32_t)((CaptureTrig & 0xFFFFF00F00000000U) >> 32U);
5325
5326 cfg2 = (cfg2 & REG_MASK_TAB_CPT[iTimer]) | ((cfg2 & 0x0000000FU) << (REG_SHIFT_TAB_CPT[iTimer]));
5327
5328 WRITE_REG(*pReg, (cfg1 | cfg2));
5329
5330 }
5331
5332 /**
5333 * @brief Get actual trigger of a capture unit for a given timer.
5334 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
5335 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
5336 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
5337 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
5338 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
5339 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
5340 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
5341 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
5342 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
5343 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
5344 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
5345 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
5346 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
5347 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
5348 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5349 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5350 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
5351 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
5352 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5353 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5354 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
5355 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
5356 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5357 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5358 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
5359 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
5360 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5361 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5362 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
5363 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
5364 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5365 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5366 * CPT1xCR TF1SET LL_HRTIM_TIM_GetCaptureTrig\n
5367 * CPT1xCR TF1RST LL_HRTIM_TIM_GetCaptureTrig\n
5368 * CPT1xCR TFCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5369 * CPT1xCR TFCMP2 LL_HRTIM_TIM_GetCaptureTrig
5370 * @param HRTIMx High Resolution Timer instance
5371 * @param Timer This parameter can be one of the following values:
5372 * @arg @ref LL_HRTIM_TIMER_A
5373 * @arg @ref LL_HRTIM_TIMER_B
5374 * @arg @ref LL_HRTIM_TIMER_C
5375 * @arg @ref LL_HRTIM_TIMER_D
5376 * @arg @ref LL_HRTIM_TIMER_E
5377 * @arg @ref LL_HRTIM_TIMER_F
5378 * @param CaptureUnit This parameter can be one of the following values:
5379 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
5380 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
5381 * @retval CaptureTrig This parameter can be a combination of the following values:
5382 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
5383 * @arg @ref LL_HRTIM_CAPTURETRIG_SW
5384 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
5385 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
5386 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
5387 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
5388 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
5389 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
5390 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
5391 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
5392 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
5393 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
5394 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
5395 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
5396 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
5397 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
5398 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
5399 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
5400 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
5401 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
5402 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
5403 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
5404 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
5405 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
5406 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
5407 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
5408 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
5409 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
5410 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
5411 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
5412 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
5413 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
5414 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
5415 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
5416 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
5417 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
5418 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
5419 */
LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit)5420 __STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
5421 {
5422 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5423 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
5424 (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U)));
5425
5426 uint64_t cfg;
5427 uint32_t CaptureTrig = READ_REG(*pReg);
5428
5429 cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer])));
5430
5431 return ((uint64_t)(((uint64_t)CaptureTrig & (uint64_t)0x00000FFFU) | (uint64_t)((cfg) << 32U)));
5432 }
5433
5434 /**
5435 * @brief Enable deadtime insertion for a given timer.
5436 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
5437 * @param HRTIMx High Resolution Timer instance
5438 * @param Timer This parameter can be one of the following values:
5439 * @arg @ref LL_HRTIM_TIMER_A
5440 * @arg @ref LL_HRTIM_TIMER_B
5441 * @arg @ref LL_HRTIM_TIMER_C
5442 * @arg @ref LL_HRTIM_TIMER_D
5443 * @arg @ref LL_HRTIM_TIMER_E
5444 * @arg @ref LL_HRTIM_TIMER_F
5445 * @retval None
5446 */
LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5447 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5448 {
5449 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5450 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5451 REG_OFFSET_TAB_TIMER[iTimer]));
5452 SET_BIT(*pReg, HRTIM_OUTR_DTEN);
5453 }
5454
5455 /**
5456 * @brief Disable deadtime insertion for a given timer.
5457 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
5458 * @param HRTIMx High Resolution Timer instance
5459 * @param Timer This parameter can be one of the following values:
5460 * @arg @ref LL_HRTIM_TIMER_A
5461 * @arg @ref LL_HRTIM_TIMER_B
5462 * @arg @ref LL_HRTIM_TIMER_C
5463 * @arg @ref LL_HRTIM_TIMER_D
5464 * @arg @ref LL_HRTIM_TIMER_E
5465 * @arg @ref LL_HRTIM_TIMER_F
5466 * @retval None
5467 */
LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5468 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5469 {
5470 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5471 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5472 REG_OFFSET_TAB_TIMER[iTimer]));
5473 CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
5474 }
5475
5476 /**
5477 * @brief Indicate whether deadtime insertion is enabled for a given timer.
5478 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
5479 * @param HRTIMx High Resolution Timer instance
5480 * @param Timer This parameter can be one of the following values:
5481 * @arg @ref LL_HRTIM_TIMER_A
5482 * @arg @ref LL_HRTIM_TIMER_B
5483 * @arg @ref LL_HRTIM_TIMER_C
5484 * @arg @ref LL_HRTIM_TIMER_D
5485 * @arg @ref LL_HRTIM_TIMER_E
5486 * @arg @ref LL_HRTIM_TIMER_F
5487 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
5488 */
LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5489 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5490 {
5491 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5492 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5493 REG_OFFSET_TAB_TIMER[iTimer]));
5494
5495 return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
5496 }
5497
5498 /**
5499 * @brief Set the delayed protection (DLYPRT) mode.
5500 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
5501 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
5502 * @note This function must be called prior enabling the delayed protection
5503 * @note Balanced Idle mode is only available in push-pull mode
5504 * @param HRTIMx High Resolution Timer instance
5505 * @param Timer This parameter can be one of the following values:
5506 * @arg @ref LL_HRTIM_TIMER_A
5507 * @arg @ref LL_HRTIM_TIMER_B
5508 * @arg @ref LL_HRTIM_TIMER_C
5509 * @arg @ref LL_HRTIM_TIMER_D
5510 * @arg @ref LL_HRTIM_TIMER_E
5511 * @arg @ref LL_HRTIM_TIMER_F
5512 * @param DLYPRTMode Delayed protection (DLYPRT) mode
5513 *
5514 * For timers A, B and C this parameter can be one of the following values:
5515 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
5516 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
5517 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
5518 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
5519 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
5520 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
5521 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
5522 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
5523 *
5524 * For timers D, E and F this parameter can be one of the following values:
5525 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
5526 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
5527 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
5528 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
5529 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
5530 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
5531 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
5532 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
5533 * @retval None
5534 */
LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DLYPRTMode)5535 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
5536 {
5537 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5538 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5539 REG_OFFSET_TAB_TIMER[iTimer]));
5540 MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
5541 }
5542
5543 /**
5544 * @brief Get the delayed protection (DLYPRT) mode.
5545 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
5546 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
5547 * @param HRTIMx High Resolution Timer instance
5548 * @param Timer This parameter can be one of the following values:
5549 * @arg @ref LL_HRTIM_TIMER_A
5550 * @arg @ref LL_HRTIM_TIMER_B
5551 * @arg @ref LL_HRTIM_TIMER_C
5552 * @arg @ref LL_HRTIM_TIMER_D
5553 * @arg @ref LL_HRTIM_TIMER_E
5554 * @arg @ref LL_HRTIM_TIMER_F
5555 * @retval DLYPRTMode Delayed protection (DLYPRT) mode
5556 *
5557 * For timers A, B and C this parameter can be one of the following values:
5558 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
5559 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
5560 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
5561 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
5562 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
5563 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
5564 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
5565 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
5566 *
5567 * For timers D, E and F this parameter can be one of the following values:
5568 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
5569 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
5570 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
5571 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
5572 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
5573 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
5574 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
5575 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
5576 */
LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5577 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5578 {
5579 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5580 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5581 REG_OFFSET_TAB_TIMER[iTimer]));
5582 return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
5583 }
5584
5585 /**
5586 * @brief Enable delayed protection (DLYPRT) for a given timer.
5587 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
5588 * @note This function must not be called once the concerned timer is enabled
5589 * @param HRTIMx High Resolution Timer instance
5590 * @param Timer This parameter can be one of the following values:
5591 * @arg @ref LL_HRTIM_TIMER_A
5592 * @arg @ref LL_HRTIM_TIMER_B
5593 * @arg @ref LL_HRTIM_TIMER_C
5594 * @arg @ref LL_HRTIM_TIMER_D
5595 * @arg @ref LL_HRTIM_TIMER_E
5596 * @arg @ref LL_HRTIM_TIMER_F
5597 * @retval None
5598 */
LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5599 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5600 {
5601 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5602 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5603 REG_OFFSET_TAB_TIMER[iTimer]));
5604 SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
5605 }
5606
5607 /**
5608 * @brief Disable delayed protection (DLYPRT) for a given timer.
5609 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
5610 * @note This function must not be called once the concerned timer is enabled
5611 * @param HRTIMx High Resolution Timer instance
5612 * @param Timer This parameter can be one of the following values:
5613 * @arg @ref LL_HRTIM_TIMER_A
5614 * @arg @ref LL_HRTIM_TIMER_B
5615 * @arg @ref LL_HRTIM_TIMER_C
5616 * @arg @ref LL_HRTIM_TIMER_D
5617 * @arg @ref LL_HRTIM_TIMER_E
5618 * @arg @ref LL_HRTIM_TIMER_F
5619 * @retval None
5620 */
LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5621 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5622 {
5623 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5624 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5625 REG_OFFSET_TAB_TIMER[iTimer]));
5626 CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
5627 }
5628
5629 /**
5630 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
5631 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
5632 * @param HRTIMx High Resolution Timer instance
5633 * @param Timer This parameter can be one of the following values:
5634 * @arg @ref LL_HRTIM_TIMER_A
5635 * @arg @ref LL_HRTIM_TIMER_B
5636 * @arg @ref LL_HRTIM_TIMER_C
5637 * @arg @ref LL_HRTIM_TIMER_D
5638 * @arg @ref LL_HRTIM_TIMER_E
5639 * @arg @ref LL_HRTIM_TIMER_F
5640 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
5641 */
LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5642 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5643 {
5644 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5645 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5646 REG_OFFSET_TAB_TIMER[iTimer]));
5647 return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
5648 }
5649
5650 /**
5651 * @brief Enable the Balanced Idle Automatic Resume (BIAR) for a given timer.
5652 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_EnableBIAR
5653 * @note This function must not be called once the concerned timer is enabled
5654 * @param HRTIMx High Resolution Timer instance
5655 * @param Timer This parameter can be one of the following values:
5656 * @arg @ref LL_HRTIM_TIMER_A
5657 * @arg @ref LL_HRTIM_TIMER_B
5658 * @arg @ref LL_HRTIM_TIMER_C
5659 * @arg @ref LL_HRTIM_TIMER_D
5660 * @arg @ref LL_HRTIM_TIMER_E
5661 * @arg @ref LL_HRTIM_TIMER_F
5662 * @retval None
5663 */
LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5664 __STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5665 {
5666 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5667 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5668 REG_OFFSET_TAB_TIMER[iTimer]));
5669 SET_BIT(*pReg, HRTIM_OUTR_BIAR);
5670 }
5671
5672 /**
5673 * @brief Disable the Balanced Idle Automatic Resume (BIAR) for a given timer.
5674 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_DisableBIAR
5675 * @note This function must not be called once the concerned timer is enabled
5676 * @param HRTIMx High Resolution Timer instance
5677 * @param Timer This parameter can be one of the following values:
5678 * @arg @ref LL_HRTIM_TIMER_A
5679 * @arg @ref LL_HRTIM_TIMER_B
5680 * @arg @ref LL_HRTIM_TIMER_C
5681 * @arg @ref LL_HRTIM_TIMER_D
5682 * @arg @ref LL_HRTIM_TIMER_E
5683 * @arg @ref LL_HRTIM_TIMER_F
5684 * @retval None
5685 */
LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5686 __STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5687 {
5688 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5689 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) +
5690 REG_OFFSET_TAB_TIMER[iTimer]));
5691 CLEAR_BIT(*pReg, HRTIM_OUTR_BIAR);
5692 }
5693
5694 /**
5695 * @brief Indicate whether the Balanced Idle Automatic Resume (BIAR) is enabled for a given timer.
5696 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_IsEnabledBIAR
5697 * @param HRTIMx High Resolution Timer instance
5698 * @param Timer This parameter can be one of the following values:
5699 * @arg @ref LL_HRTIM_TIMER_A
5700 * @arg @ref LL_HRTIM_TIMER_B
5701 * @arg @ref LL_HRTIM_TIMER_C
5702 * @arg @ref LL_HRTIM_TIMER_D
5703 * @arg @ref LL_HRTIM_TIMER_E
5704 * @arg @ref LL_HRTIM_TIMER_F
5705 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
5706 */
LL_HRTIM_TIM_IsEnabledBIAR(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5707 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5708 {
5709 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5710 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5711 REG_OFFSET_TAB_TIMER[iTimer]));
5712
5713 return ((READ_BIT(*pReg, HRTIM_OUTR_BIAR) == (HRTIM_OUTR_BIAR)) ? 1UL : 0UL);
5714 }
5715
5716 /**
5717 * @brief Enable the fault channel(s) for a given timer.
5718 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
5719 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
5720 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
5721 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
5722 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault\n
5723 * FLTxR FLT6EN LL_HRTIM_TIM_EnableFault
5724 * @param HRTIMx High Resolution Timer instance
5725 * @param Timer This parameter can be one of the following values:
5726 * @arg @ref LL_HRTIM_TIMER_A
5727 * @arg @ref LL_HRTIM_TIMER_B
5728 * @arg @ref LL_HRTIM_TIMER_C
5729 * @arg @ref LL_HRTIM_TIMER_D
5730 * @arg @ref LL_HRTIM_TIMER_E
5731 * @arg @ref LL_HRTIM_TIMER_F
5732 * @param Faults This parameter can be a combination of the following values:
5733 * @arg @ref LL_HRTIM_FAULT_1
5734 * @arg @ref LL_HRTIM_FAULT_2
5735 * @arg @ref LL_HRTIM_FAULT_3
5736 * @arg @ref LL_HRTIM_FAULT_4
5737 * @arg @ref LL_HRTIM_FAULT_5
5738 * @arg @ref LL_HRTIM_FAULT_6
5739 * @retval None
5740 */
LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)5741 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
5742 {
5743 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5744 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5745 REG_OFFSET_TAB_TIMER[iTimer]));
5746 SET_BIT(*pReg, Faults);
5747 }
5748
5749 /**
5750 * @brief Disable the fault channel(s) for a given timer.
5751 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
5752 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
5753 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
5754 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
5755 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault\n
5756 * FLTxR FLT6EN LL_HRTIM_TIM_DisableFault
5757 * @param HRTIMx High Resolution Timer instance
5758 * @param Timer This parameter can be one of the following values:
5759 * @arg @ref LL_HRTIM_TIMER_A
5760 * @arg @ref LL_HRTIM_TIMER_B
5761 * @arg @ref LL_HRTIM_TIMER_C
5762 * @arg @ref LL_HRTIM_TIMER_D
5763 * @arg @ref LL_HRTIM_TIMER_E
5764 * @arg @ref LL_HRTIM_TIMER_F
5765 * @param Faults This parameter can be a combination of the following values:
5766 * @arg @ref LL_HRTIM_FAULT_1
5767 * @arg @ref LL_HRTIM_FAULT_2
5768 * @arg @ref LL_HRTIM_FAULT_3
5769 * @arg @ref LL_HRTIM_FAULT_4
5770 * @arg @ref LL_HRTIM_FAULT_5
5771 * @arg @ref LL_HRTIM_FAULT_6
5772 * @retval None
5773 */
LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)5774 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
5775 {
5776 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5777 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5778 REG_OFFSET_TAB_TIMER[iTimer]));
5779 CLEAR_BIT(*pReg, Faults);
5780 }
5781
5782 /**
5783 * @brief Indicate whether the fault channel is enabled for a given timer.
5784 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
5785 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
5786 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
5787 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
5788 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault\n
5789 * FLTxR FLT6EN LL_HRTIM_TIM_IsEnabledFault
5790 * @param HRTIMx High Resolution Timer instance
5791 * @param Timer This parameter can be one of the following values:
5792 * @arg @ref LL_HRTIM_TIMER_A
5793 * @arg @ref LL_HRTIM_TIMER_B
5794 * @arg @ref LL_HRTIM_TIMER_C
5795 * @arg @ref LL_HRTIM_TIMER_D
5796 * @arg @ref LL_HRTIM_TIMER_E
5797 * @arg @ref LL_HRTIM_TIMER_F
5798 * @param Fault This parameter can be one of the following values:
5799 * @arg @ref LL_HRTIM_FAULT_1
5800 * @arg @ref LL_HRTIM_FAULT_2
5801 * @arg @ref LL_HRTIM_FAULT_3
5802 * @arg @ref LL_HRTIM_FAULT_4
5803 * @arg @ref LL_HRTIM_FAULT_5
5804 * @arg @ref LL_HRTIM_FAULT_6
5805 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
5806 */
LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Fault)5807 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
5808 {
5809 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5810 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5811 REG_OFFSET_TAB_TIMER[iTimer]));
5812
5813 return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
5814 }
5815
5816 /**
5817 * @brief Lock the fault conditioning set-up for a given timer.
5818 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
5819 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
5820 * @param HRTIMx High Resolution Timer instance
5821 * @param Timer This parameter can be one of the following values:
5822 * @arg @ref LL_HRTIM_TIMER_A
5823 * @arg @ref LL_HRTIM_TIMER_B
5824 * @arg @ref LL_HRTIM_TIMER_C
5825 * @arg @ref LL_HRTIM_TIMER_D
5826 * @arg @ref LL_HRTIM_TIMER_E
5827 * @arg @ref LL_HRTIM_TIMER_F
5828 * @retval None
5829 */
LL_HRTIM_TIM_LockFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5830 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5831 {
5832 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5833 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5834 REG_OFFSET_TAB_TIMER[iTimer]));
5835 SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
5836 }
5837
5838 /**
5839 * @brief Define how the timer behaves during a burst mode operation.
5840 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
5841 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
5842 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
5843 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
5844 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
5845 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption\n
5846 * BMCR TFBM LL_HRTIM_TIM_SetBurstModeOption
5847 * @note This function must not be called when the burst mode is enabled
5848 * @param HRTIMx High Resolution Timer instance
5849 * @param Timer This parameter can be one of the following values:
5850 * @arg @ref LL_HRTIM_TIMER_MASTER
5851 * @arg @ref LL_HRTIM_TIMER_A
5852 * @arg @ref LL_HRTIM_TIMER_B
5853 * @arg @ref LL_HRTIM_TIMER_C
5854 * @arg @ref LL_HRTIM_TIMER_D
5855 * @arg @ref LL_HRTIM_TIMER_E
5856 * @arg @ref LL_HRTIM_TIMER_F
5857 * @param BurtsModeOption This parameter can be one of the following values:
5858 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
5859 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
5860 * @retval None
5861 */
LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t BurtsModeOption)5862 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
5863 {
5864 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
5865 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
5866 }
5867
5868 /**
5869 * @brief Retrieve how the timer behaves during a burst mode operation.
5870 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
5871 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
5872 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
5873 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
5874 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
5875 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption\n
5876 * BMCR TFBM LL_HRTIM_TIM_GetBurstModeOption
5877 * @param HRTIMx High Resolution Timer instance
5878 * @param Timer This parameter can be one of the following values:
5879 * @arg @ref LL_HRTIM_TIMER_MASTER
5880 * @arg @ref LL_HRTIM_TIMER_A
5881 * @arg @ref LL_HRTIM_TIMER_B
5882 * @arg @ref LL_HRTIM_TIMER_C
5883 * @arg @ref LL_HRTIM_TIMER_D
5884 * @arg @ref LL_HRTIM_TIMER_E
5885 * @arg @ref LL_HRTIM_TIMER_F
5886 * @retval BurtsMode This parameter can be one of the following values:
5887 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
5888 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
5889 */
LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5890 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5891 {
5892 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
5893 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
5894 }
5895
5896 /**
5897 * @brief Program which registers are to be written by Burst DMA transfers.
5898 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
5899 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
5900 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
5901 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
5902 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
5903 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
5904 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
5905 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
5906 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
5907 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
5908 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
5909 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
5910 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
5911 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
5912 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
5913 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
5914 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
5915 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
5916 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
5917 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
5918 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
5919 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
5920 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
5921 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
5922 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
5923 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
5924 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
5925 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
5926 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
5927 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
5928 * @param HRTIMx High Resolution Timer instance
5929 * @param Timer This parameter can be one of the following values:
5930 * @arg @ref LL_HRTIM_TIMER_MASTER
5931 * @arg @ref LL_HRTIM_TIMER_A
5932 * @arg @ref LL_HRTIM_TIMER_B
5933 * @arg @ref LL_HRTIM_TIMER_C
5934 * @arg @ref LL_HRTIM_TIMER_D
5935 * @arg @ref LL_HRTIM_TIMER_E
5936 * @arg @ref LL_HRTIM_TIMER_F
5937 * @param Registers Registers to be updated by the DMA request
5938 *
5939 * For Master timer this parameter can be can be a combination of the following values:
5940 * @arg @ref LL_HRTIM_BURSTDMA_NONE
5941 * @arg @ref LL_HRTIM_BURSTDMA_MCR
5942 * @arg @ref LL_HRTIM_BURSTDMA_MICR
5943 * @arg @ref LL_HRTIM_BURSTDMA_MDIER
5944 * @arg @ref LL_HRTIM_BURSTDMA_MCNT
5945 * @arg @ref LL_HRTIM_BURSTDMA_MPER
5946 * @arg @ref LL_HRTIM_BURSTDMA_MREP
5947 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
5948 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
5949 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
5950 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
5951 *
5952 * For Timers A..F this parameter can be can be a combination of the following values:
5953 * @arg @ref LL_HRTIM_BURSTDMA_NONE
5954 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
5955 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
5956 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
5957 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
5958 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
5959 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
5960 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
5961 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
5962 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
5963 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
5964 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
5965 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
5966 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
5967 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
5968 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
5969 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
5970 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
5971 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
5972 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
5973 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
5974 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
5975 * @arg @ref LL_HRTIM_BURSTDMA_CR2
5976 * @arg @ref LL_HRTIM_BURSTDMA_EEFR3
5977 * @retval None
5978 */
LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Registers)5979 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
5980 {
5981 const uint8_t REG_OFFSET_TAB_BDTUPR[] =
5982 {
5983 0x00U, /* BDMUPR ; offset = 0x000 */
5984 0x04U, /* BDAUPR ; offset = 0x05C */
5985 0x08U, /* BDBUPR ; offset = 0x060 */
5986 0x0CU, /* BDCUPR ; offset = 0x064 */
5987 0x10U, /* BDDUPR ; offset = 0x068 */
5988 0x14U, /* BDEUPR ; offset = 0x06C */
5989 0x1CU /* BDFUPR ; offset = 0x074 */
5990 };
5991
5992 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
5993 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer]));
5994 WRITE_REG(*pReg, Registers);
5995 }
5996
5997 /**
5998 * @brief Indicate on which output the signal is currently applied.
5999 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
6000 * @note Only significant when the timer operates in push-pull mode.
6001 * @param HRTIMx High Resolution Timer instance
6002 * @param Timer This parameter can be one of the following values:
6003 * @arg @ref LL_HRTIM_TIMER_A
6004 * @arg @ref LL_HRTIM_TIMER_B
6005 * @arg @ref LL_HRTIM_TIMER_C
6006 * @arg @ref LL_HRTIM_TIMER_D
6007 * @arg @ref LL_HRTIM_TIMER_E
6008 * @arg @ref LL_HRTIM_TIMER_F
6009 * @retval CPPSTAT This parameter can be one of the following values:
6010 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
6011 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
6012 */
LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6013 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6014 {
6015 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
6016 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
6017 REG_OFFSET_TAB_TIMER[iTimer]));
6018 return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
6019 }
6020
6021 /**
6022 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
6023 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
6024 * @param HRTIMx High Resolution Timer instance
6025 * @param Timer This parameter can be one of the following values:
6026 * @arg @ref LL_HRTIM_TIMER_A
6027 * @arg @ref LL_HRTIM_TIMER_B
6028 * @arg @ref LL_HRTIM_TIMER_C
6029 * @arg @ref LL_HRTIM_TIMER_D
6030 * @arg @ref LL_HRTIM_TIMER_E
6031 * @arg @ref LL_HRTIM_TIMER_F
6032 * @retval IPPSTAT This parameter can be one of the following values:
6033 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
6034 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
6035 */
LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6036 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6037 {
6038 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
6039 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
6040 REG_OFFSET_TAB_TIMER[iTimer]));
6041 return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
6042 }
6043
6044 /**
6045 * @brief Set the event filter for a given timer.
6046 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
6047 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
6048 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
6049 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
6050 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
6051 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
6052 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
6053 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
6054 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
6055 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
6056 * @note This function must not be called when the timer counter is enabled.
6057 * @param HRTIMx High Resolution Timer instance
6058 * @param Timer This parameter can be one of the following values:
6059 * @arg @ref LL_HRTIM_TIMER_A
6060 * @arg @ref LL_HRTIM_TIMER_B
6061 * @arg @ref LL_HRTIM_TIMER_C
6062 * @arg @ref LL_HRTIM_TIMER_D
6063 * @arg @ref LL_HRTIM_TIMER_E
6064 * @arg @ref LL_HRTIM_TIMER_F
6065 * @param Event This parameter can be one of the following values:
6066 * @arg @ref LL_HRTIM_EVENT_1
6067 * @arg @ref LL_HRTIM_EVENT_2
6068 * @arg @ref LL_HRTIM_EVENT_3
6069 * @arg @ref LL_HRTIM_EVENT_4
6070 * @arg @ref LL_HRTIM_EVENT_5
6071 * @arg @ref LL_HRTIM_EVENT_6
6072 * @arg @ref LL_HRTIM_EVENT_7
6073 * @arg @ref LL_HRTIM_EVENT_8
6074 * @arg @ref LL_HRTIM_EVENT_9
6075 * @arg @ref LL_HRTIM_EVENT_10
6076 * @param Filter This parameter can be one of the following values:
6077 * @arg @ref LL_HRTIM_EEFLTR_NONE
6078 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
6079 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
6080 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
6081 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
6082 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
6083 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
6084 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
6085 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
6086 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
6087 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
6088 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
6089 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
6090 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
6091 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
6092 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
6093 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
6094 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
6095 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
6096 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
6097 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
6098 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
6099 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
6100 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
6101 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
6102 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
6103 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
6104 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
6105 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
6106 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
6107 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
6108 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
6109 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
6110 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
6111 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
6112 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
6113 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
6114 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
6115 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
6116 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
6117 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
6118 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
6119 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
6120 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
6121 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
6122 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
6123 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
6124 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
6125 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
6126 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
6127 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
6128 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
6129 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
6130 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
6131 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
6132 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
6133
6134 * @retval None
6135 */
LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t Filter)6136 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
6137 {
6138 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6139 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6140 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6141 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6142 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
6143 }
6144
6145 /**
6146 * @brief Get actual event filter settings for a given timer.
6147 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
6148 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
6149 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
6150 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
6151 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
6152 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
6153 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
6154 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
6155 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
6156 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
6157 * @param HRTIMx High Resolution Timer instance
6158 * @param Timer This parameter can be one of the following values:
6159 * @arg @ref LL_HRTIM_TIMER_A
6160 * @arg @ref LL_HRTIM_TIMER_B
6161 * @arg @ref LL_HRTIM_TIMER_C
6162 * @arg @ref LL_HRTIM_TIMER_D
6163 * @arg @ref LL_HRTIM_TIMER_E
6164 * @arg @ref LL_HRTIM_TIMER_F
6165 * @param Event This parameter can be one of the following values:
6166 * @arg @ref LL_HRTIM_EVENT_1
6167 * @arg @ref LL_HRTIM_EVENT_2
6168 * @arg @ref LL_HRTIM_EVENT_3
6169 * @arg @ref LL_HRTIM_EVENT_4
6170 * @arg @ref LL_HRTIM_EVENT_5
6171 * @arg @ref LL_HRTIM_EVENT_6
6172 * @arg @ref LL_HRTIM_EVENT_7
6173 * @arg @ref LL_HRTIM_EVENT_8
6174 * @arg @ref LL_HRTIM_EVENT_9
6175 * @arg @ref LL_HRTIM_EVENT_10
6176 * @retval Filter This parameter can be one of the following values:
6177 * @arg @ref LL_HRTIM_EEFLTR_NONE
6178 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
6179 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
6180 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
6181 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
6182 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
6183 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
6184 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
6185 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
6186 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
6187 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
6188 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
6189 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
6190 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
6191 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
6192 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
6193 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
6194 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
6195 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
6196 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
6197 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
6198 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
6199 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
6200 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
6201 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
6202 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
6203 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
6204 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
6205 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
6206 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
6207 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
6208 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
6209 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
6210 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
6211 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
6212 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
6213 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
6214 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
6215 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
6216 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
6217 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
6218 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
6219 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
6220 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
6221 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
6222 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
6223 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
6224 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
6225 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
6226 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
6227 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
6228 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
6229 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
6230 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
6231 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
6232 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
6233 */
LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)6234 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
6235 {
6236 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6237 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6238 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6239 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6240 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
6241 }
6242
6243 /**
6244 * @brief Enable or disable event latch mechanism for a given timer.
6245 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6246 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6247 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6248 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6249 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6250 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6251 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6252 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6253 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6254 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
6255 * @note This function must not be called when the timer counter is enabled.
6256 * @param HRTIMx High Resolution Timer instance
6257 * @param Timer This parameter can be one of the following values:
6258 * @arg @ref LL_HRTIM_TIMER_A
6259 * @arg @ref LL_HRTIM_TIMER_B
6260 * @arg @ref LL_HRTIM_TIMER_C
6261 * @arg @ref LL_HRTIM_TIMER_D
6262 * @arg @ref LL_HRTIM_TIMER_E
6263 * @arg @ref LL_HRTIM_TIMER_F
6264 * @param Event This parameter can be one of the following values:
6265 * @arg @ref LL_HRTIM_EVENT_1
6266 * @arg @ref LL_HRTIM_EVENT_2
6267 * @arg @ref LL_HRTIM_EVENT_3
6268 * @arg @ref LL_HRTIM_EVENT_4
6269 * @arg @ref LL_HRTIM_EVENT_5
6270 * @arg @ref LL_HRTIM_EVENT_6
6271 * @arg @ref LL_HRTIM_EVENT_7
6272 * @arg @ref LL_HRTIM_EVENT_8
6273 * @arg @ref LL_HRTIM_EVENT_9
6274 * @arg @ref LL_HRTIM_EVENT_10
6275 * @param LatchStatus This parameter can be one of the following values:
6276 * @arg @ref LL_HRTIM_EELATCH_DISABLED
6277 * @arg @ref LL_HRTIM_EELATCH_ENABLED
6278 * @retval None
6279 */
LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t LatchStatus)6280 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
6281 uint32_t LatchStatus)
6282 {
6283 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6284 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6285 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6286 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6287 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
6288 }
6289
6290 /**
6291 * @brief Get actual event latch status for a given timer.
6292 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6293 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6294 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6295 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6296 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6297 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6298 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6299 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6300 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6301 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
6302 * @param HRTIMx High Resolution Timer instance
6303 * @param Timer This parameter can be one of the following values:
6304 * @arg @ref LL_HRTIM_TIMER_A
6305 * @arg @ref LL_HRTIM_TIMER_B
6306 * @arg @ref LL_HRTIM_TIMER_C
6307 * @arg @ref LL_HRTIM_TIMER_D
6308 * @arg @ref LL_HRTIM_TIMER_E
6309 * @arg @ref LL_HRTIM_TIMER_F
6310 * @param Event This parameter can be one of the following values:
6311 * @arg @ref LL_HRTIM_EVENT_1
6312 * @arg @ref LL_HRTIM_EVENT_2
6313 * @arg @ref LL_HRTIM_EVENT_3
6314 * @arg @ref LL_HRTIM_EVENT_4
6315 * @arg @ref LL_HRTIM_EVENT_5
6316 * @arg @ref LL_HRTIM_EVENT_6
6317 * @arg @ref LL_HRTIM_EVENT_7
6318 * @arg @ref LL_HRTIM_EVENT_8
6319 * @arg @ref LL_HRTIM_EVENT_9
6320 * @arg @ref LL_HRTIM_EVENT_10
6321 * @retval LatchStatus This parameter can be one of the following values:
6322 * @arg @ref LL_HRTIM_EELATCH_DISABLED
6323 * @arg @ref LL_HRTIM_EELATCH_ENABLED
6324 */
LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)6325 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
6326 {
6327 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6328 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6329 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6330 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6331 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
6332 }
6333
6334 /**
6335 * @brief Select the Trigger-Half operating mode for a given timer.
6336 * @note This bitfield defines whether the compare 2 register
6337 * @note is behaving in standard mode (compare match issued as soon as counter equal compare)
6338 * @note or in triggered-half mode
6339 * @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_SetTriggeredHalfMode
6340 * @param HRTIMx High Resolution Timer instance
6341 * @param Timer This parameter can be one of the following values:
6342 * @arg @ref LL_HRTIM_TIMER_A
6343 * @arg @ref LL_HRTIM_TIMER_B
6344 * @arg @ref LL_HRTIM_TIMER_C
6345 * @arg @ref LL_HRTIM_TIMER_D
6346 * @arg @ref LL_HRTIM_TIMER_E
6347 * @arg @ref LL_HRTIM_TIMER_F
6348 * @param Mode This parameter can be one of the following values:
6349 * @arg @ref LL_HRTIM_TRIGHALF_ENABLED
6350 * @arg @ref LL_HRTIM_TRIGHALF_DISABLED
6351 * @retval None
6352 */
LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6353 __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6354 {
6355 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6356 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6357 REG_OFFSET_TAB_TIMER[iTimer]));
6358 MODIFY_REG(* pReg, HRTIM_TIMCR2_TRGHLF, Mode);
6359 }
6360
6361 /**
6362 * @brief Get the Trigger-Half operating mode for a given timer.
6363 * @note This bitfield reports whether the compare 2 register
6364 * @note is behaving in standard mode (compare match issued as soon as counter equal compare)
6365 * @note or in triggered-half mode
6366 * @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_GetTriggeredHalfMode
6367 * @param HRTIMx High Resolution Timer instance
6368 * @param Timer This parameter can be one of the following values:
6369 * @arg @ref LL_HRTIM_TIMER_A
6370 * @arg @ref LL_HRTIM_TIMER_B
6371 * @arg @ref LL_HRTIM_TIMER_C
6372 * @arg @ref LL_HRTIM_TIMER_D
6373 * @arg @ref LL_HRTIM_TIMER_E
6374 * @arg @ref LL_HRTIM_TIMER_F
6375 * @retval Mode This parameter can be one of the following values:
6376 * @arg @ref LL_HRTIM_TRIGHALF_ENABLED
6377 * @arg @ref LL_HRTIM_TRIGHALF_DISABLED
6378 */
LL_HRTIM_TIM_GetTriggeredHalfMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6379 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6380 {
6381 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6382 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6383 REG_OFFSET_TAB_TIMER[iTimer]));
6384 return (READ_BIT(* pReg, HRTIM_TIMCR2_TRGHLF));
6385 }
6386
6387 /**
6388 * @brief Select the compare 1 operating mode.
6389 * @note This bit defines the compare 1 operating mode:
6390 * @note 0: the compare 1 event is generated when the counter is equal to the compare value
6391 * @note 1: the compare 1 event is generated when the counter is greater than the compare value
6392 * @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_SetComp1Mode
6393 * @param HRTIMx High Resolution Timer instance
6394 * @param Timer This parameter can be one of the following values:
6395 * @arg @ref LL_HRTIM_TIMER_A
6396 * @arg @ref LL_HRTIM_TIMER_B
6397 * @arg @ref LL_HRTIM_TIMER_C
6398 * @arg @ref LL_HRTIM_TIMER_D
6399 * @arg @ref LL_HRTIM_TIMER_E
6400 * @arg @ref LL_HRTIM_TIMER_F
6401 * @param Mode This parameter can be one of the following values:
6402 * @arg @ref LL_HRTIM_GTCMP1_EQUAL
6403 * @arg @ref LL_HRTIM_GTCMP1_GREATER
6404 * @retval None
6405 */
LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6406 __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6407 {
6408 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6409 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6410 REG_OFFSET_TAB_TIMER[iTimer]));
6411 MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP1, Mode);
6412 }
6413
6414 /**
6415 * @brief Get the selected compare 1 operating mode.
6416 * @note This bit reports the compare 1 operating mode:
6417 * @note 0: the compare 1 event is generated when the counter is equal to the compare value
6418 * @note 1: the compare 1 event is generated when the counter is greater than the compare value
6419 * @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_GetComp1Mode
6420 * @param HRTIMx High Resolution Timer instance
6421 * @param Timer This parameter can be one of the following values:
6422 * @arg @ref LL_HRTIM_TIMER_A
6423 * @arg @ref LL_HRTIM_TIMER_B
6424 * @arg @ref LL_HRTIM_TIMER_C
6425 * @arg @ref LL_HRTIM_TIMER_D
6426 * @arg @ref LL_HRTIM_TIMER_E
6427 * @arg @ref LL_HRTIM_TIMER_F
6428 * @retval Mode This parameter can be one of the following values:
6429 * @arg @ref LL_HRTIM_GTCMP1_EQUAL
6430 * @arg @ref LL_HRTIM_GTCMP1_GREATER
6431 */
LL_HRTIM_TIM_GetComp1Mode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6432 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6433 {
6434 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6435 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6436 REG_OFFSET_TAB_TIMER[iTimer]));
6437 return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP1));
6438 }
6439
6440 /**
6441 * @brief Select the compare 3 operating mode.
6442 * @note This bit defines the compare 3 operating mode:
6443 * @note 0: the compare 3 event is generated when the counter is equal to the compare value
6444 * @note 1: the compare 3 event is generated when the counter is greater than the compare value
6445 * @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_SetComp3Mode
6446 * @param HRTIMx High Resolution Timer instance
6447 * @param Timer This parameter can be one of the following values:
6448 * @arg @ref LL_HRTIM_TIMER_A
6449 * @arg @ref LL_HRTIM_TIMER_B
6450 * @arg @ref LL_HRTIM_TIMER_C
6451 * @arg @ref LL_HRTIM_TIMER_D
6452 * @arg @ref LL_HRTIM_TIMER_E
6453 * @arg @ref LL_HRTIM_TIMER_F
6454 * @param Mode This parameter can be one of the following values:
6455 * @arg @ref LL_HRTIM_GTCMP3_EQUAL
6456 * @arg @ref LL_HRTIM_GTCMP3_GREATER
6457 * @retval None
6458 */
LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6459 __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6460 {
6461 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6462 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6463 REG_OFFSET_TAB_TIMER[iTimer]));
6464 MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP3, (Mode));
6465 }
6466
6467 /**
6468 * @brief Get the selected compare 3 operating mode.
6469 * @note This bit reports the compare 3 operating mode:
6470 * @note 0: the compare 3 event is generated when the counter is equal to the compare value
6471 * @note 1: the compare 3 event is generated when the counter is greater than the compare value
6472 * @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_GetComp1Mode
6473 * @param HRTIMx High Resolution Timer instance
6474 * @param Timer This parameter can be one of the following values:
6475 * @arg @ref LL_HRTIM_TIMER_A
6476 * @arg @ref LL_HRTIM_TIMER_B
6477 * @arg @ref LL_HRTIM_TIMER_C
6478 * @arg @ref LL_HRTIM_TIMER_D
6479 * @arg @ref LL_HRTIM_TIMER_E
6480 * @arg @ref LL_HRTIM_TIMER_F
6481 * @retval Mode This parameter can be one of the following values:
6482 * @arg @ref LL_HRTIM_GTCMP3_EQUAL
6483 * @arg @ref LL_HRTIM_GTCMP3_GREATER
6484 */
LL_HRTIM_TIM_GetComp3Mode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6485 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6486 {
6487 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6488 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) +
6489 REG_OFFSET_TAB_TIMER[iTimer]));
6490 return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP3));
6491 }
6492
6493 /**
6494 * @brief Select the roll-over mode.
6495 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6496 * @note Only concerns the Roll-over event with the following destinations: Update trigger, IRQ
6497 * and DMA requests, repetition counter decrement and External Event filtering.
6498 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_SetRollOverMode
6499 * @param HRTIMx High Resolution Timer instance
6500 * @param Timer This parameter can be one of the following values:
6501 * @arg @ref LL_HRTIM_TIMER_A
6502 * @arg @ref LL_HRTIM_TIMER_B
6503 * @arg @ref LL_HRTIM_TIMER_C
6504 * @arg @ref LL_HRTIM_TIMER_D
6505 * @arg @ref LL_HRTIM_TIMER_E
6506 * @arg @ref LL_HRTIM_TIMER_F
6507 * @param Mode This parameter can be one of the following values:
6508 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6509 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6510 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6511 * @retval None
6512 */
LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6513 __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6514 {
6515 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6516 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6517 REG_OFFSET_TAB_TIMER[iTimer]));
6518 MODIFY_REG(* pReg, HRTIM_TIMCR2_ROM, (Mode << HRTIM_TIMCR2_ROM_Pos));
6519 }
6520
6521 /**
6522 * @brief Get selected the roll-over mode.
6523 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetRollOverMode
6524 * @param HRTIMx High Resolution Timer instance
6525 * @param Timer This parameter can be one of the following values:
6526 * @arg @ref LL_HRTIM_TIMER_A
6527 * @arg @ref LL_HRTIM_TIMER_B
6528 * @arg @ref LL_HRTIM_TIMER_C
6529 * @arg @ref LL_HRTIM_TIMER_D
6530 * @arg @ref LL_HRTIM_TIMER_E
6531 * @arg @ref LL_HRTIM_TIMER_F
6532 * @retval Mode returned value can be one of the following values:
6533 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6534 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6535 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6536 */
LL_HRTIM_TIM_GetRollOverMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6537 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6538 {
6539 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6540 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6541 REG_OFFSET_TAB_TIMER[iTimer]));
6542 return (READ_BIT(*pReg, HRTIM_TIMCR2_ROM) >> HRTIM_TIMCR2_ROM_Pos);
6543 }
6544
6545 /**
6546 * @brief Select Fault and Event roll-over mode.
6547 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6548 * @note only concerns the Roll-over event used by the Fault and Event counters.
6549 * @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_SetFaultEventRollOverMode
6550 * @param HRTIMx High Resolution Timer instance
6551 * @param Timer This parameter can be one of the following values:
6552 * @arg @ref LL_HRTIM_TIMER_A
6553 * @arg @ref LL_HRTIM_TIMER_B
6554 * @arg @ref LL_HRTIM_TIMER_C
6555 * @arg @ref LL_HRTIM_TIMER_D
6556 * @arg @ref LL_HRTIM_TIMER_E
6557 * @arg @ref LL_HRTIM_TIMER_F
6558 * @param Mode This parameter can be one of the following values:
6559 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6560 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6561 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6562 * @retval None
6563 */
LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6564 __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6565 {
6566 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6567 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6568 REG_OFFSET_TAB_TIMER[iTimer]));
6569 MODIFY_REG(* pReg, HRTIM_TIMCR2_FEROM, (Mode << HRTIM_TIMCR2_FEROM_Pos));
6570 }
6571
6572 /**
6573 * @brief Get selected Fault and Event role-over mode.
6574 * @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_GetFaultEventRollOverMode
6575 * @param HRTIMx High Resolution Timer instance
6576 * @param Timer This parameter can be one of the following values:
6577 * @arg @ref LL_HRTIM_TIMER_A
6578 * @arg @ref LL_HRTIM_TIMER_B
6579 * @arg @ref LL_HRTIM_TIMER_C
6580 * @arg @ref LL_HRTIM_TIMER_D
6581 * @arg @ref LL_HRTIM_TIMER_E
6582 * @arg @ref LL_HRTIM_TIMER_F
6583 * @retval Mode returned value can be one of the following values:
6584 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6585 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6586 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6587 */
LL_HRTIM_TIM_GetFaultEventRollOverMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6588 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6589 {
6590 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6591 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6592 REG_OFFSET_TAB_TIMER[iTimer]));
6593 return (READ_BIT(*pReg, HRTIM_TIMCR2_FEROM) >> HRTIM_TIMCR2_FEROM_Pos);
6594 }
6595
6596 /**
6597 * @brief Select the Burst mode roll-over mode.
6598 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6599 * @note Only concerns the Roll-over event used in the Burst mode controller, as clock as as burst mode trigger.
6600 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetBMRollOverMode
6601 * @param HRTIMx High Resolution Timer instance
6602 * @param Timer This parameter can be one of the following values:
6603 * @arg @ref LL_HRTIM_TIMER_A
6604 * @arg @ref LL_HRTIM_TIMER_B
6605 * @arg @ref LL_HRTIM_TIMER_C
6606 * @arg @ref LL_HRTIM_TIMER_D
6607 * @arg @ref LL_HRTIM_TIMER_E
6608 * @arg @ref LL_HRTIM_TIMER_F
6609 * @param Mode This parameter can be one of the following values:
6610 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6611 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6612 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6613 * @retval None
6614 */
LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6615 __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6616 {
6617 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6618 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6619 REG_OFFSET_TAB_TIMER[iTimer]));
6620 MODIFY_REG(* pReg, HRTIM_TIMCR2_BMROM, (Mode << HRTIM_TIMCR2_BMROM_Pos));
6621 }
6622
6623 /**
6624 * @brief Get selected Burst mode roll-over mode.
6625 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetBMRollOverMode
6626 * @param HRTIMx High Resolution Timer instance
6627 * @param Timer This parameter can be one of the following values:
6628 * @arg @ref LL_HRTIM_TIMER_A
6629 * @arg @ref LL_HRTIM_TIMER_B
6630 * @arg @ref LL_HRTIM_TIMER_C
6631 * @arg @ref LL_HRTIM_TIMER_D
6632 * @arg @ref LL_HRTIM_TIMER_E
6633 * @arg @ref LL_HRTIM_TIMER_F
6634 * @retval Mode returned value can be one of the following values:
6635 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6636 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6637 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6638 */
LL_HRTIM_TIM_GetBMRollOverMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6639 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6640 {
6641 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6642 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6643 REG_OFFSET_TAB_TIMER[iTimer]));
6644 return (READ_BIT(*pReg, HRTIM_TIMCR2_BMROM) >> HRTIM_TIMCR2_BMROM_Pos);
6645 }
6646
6647 /**
6648 * @brief Select the ADC roll-over mode.
6649 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6650 * @note Only concerns the Roll-over event used to trigger the ADC.
6651 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetADCRollOverMode
6652 * @param HRTIMx High Resolution Timer instance
6653 * @param Timer This parameter can be one of the following values:
6654 * @arg @ref LL_HRTIM_TIMER_A
6655 * @arg @ref LL_HRTIM_TIMER_B
6656 * @arg @ref LL_HRTIM_TIMER_C
6657 * @arg @ref LL_HRTIM_TIMER_D
6658 * @arg @ref LL_HRTIM_TIMER_E
6659 * @arg @ref LL_HRTIM_TIMER_F
6660 * @param Mode This parameter can be one of the following values:
6661 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6662 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6663 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6664 * @retval None
6665 */
LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6666 __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6667 {
6668 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6669 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6670 REG_OFFSET_TAB_TIMER[iTimer]));
6671 MODIFY_REG(* pReg, HRTIM_TIMCR2_ADROM, (Mode << HRTIM_TIMCR2_ADROM_Pos));
6672 }
6673
6674 /**
6675 * @brief Get selected ADC roll-over mode.
6676 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_GetADCRollOverMode
6677 * @param HRTIMx High Resolution Timer instance
6678 * @param Timer This parameter can be one of the following values:
6679 * @arg @ref LL_HRTIM_TIMER_A
6680 * @arg @ref LL_HRTIM_TIMER_B
6681 * @arg @ref LL_HRTIM_TIMER_C
6682 * @arg @ref LL_HRTIM_TIMER_D
6683 * @arg @ref LL_HRTIM_TIMER_E
6684 * @arg @ref LL_HRTIM_TIMER_F
6685 * @retval Mode returned value can be one of the following values:
6686 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6687 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6688 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6689 */
LL_HRTIM_TIM_GetADCRollOverMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6690 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6691 {
6692 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6693 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6694 REG_OFFSET_TAB_TIMER[iTimer]));
6695 return (READ_BIT(*pReg, HRTIM_TIMCR2_ADROM) >> HRTIM_TIMCR2_ADROM_Pos);
6696 }
6697
6698 /**
6699 * @brief Select the ADC roll-over mode.
6700 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6701 * @note Only concerns concerns the Roll-over event which sets and/or resets the outputs,
6702 * as per HRTIM_SETxyR and HRTIM_RSTxyR settings (see function @ref LL_HRTIM_OUT_SetOutputSetSrc()
6703 * and function @ref LL_HRTIM_OUT_SetOutputResetSrc() respectively).
6704 * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_SetOutputRollOverMode
6705 * @param HRTIMx High Resolution Timer instance
6706 * @param Timer This parameter can be one of the following values:
6707 * @arg @ref LL_HRTIM_TIMER_A
6708 * @arg @ref LL_HRTIM_TIMER_B
6709 * @arg @ref LL_HRTIM_TIMER_C
6710 * @arg @ref LL_HRTIM_TIMER_D
6711 * @arg @ref LL_HRTIM_TIMER_E
6712 * @arg @ref LL_HRTIM_TIMER_F
6713 * @param Mode This parameter can be one of the following values:
6714 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6715 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6716 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6717 * @retval None
6718 */
LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6719 __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6720 {
6721 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6722 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6723 REG_OFFSET_TAB_TIMER[iTimer]));
6724 MODIFY_REG(* pReg, HRTIM_TIMCR2_OUTROM, (Mode << HRTIM_TIMCR2_OUTROM_Pos));
6725 }
6726
6727 /**
6728 * @brief Get selected ADC roll-over mode.
6729 * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_GetOutputRollOverMode
6730 * @param HRTIMx High Resolution Timer instance
6731 * @param Timer This parameter can be one of the following values:
6732 * @arg @ref LL_HRTIM_TIMER_A
6733 * @arg @ref LL_HRTIM_TIMER_B
6734 * @arg @ref LL_HRTIM_TIMER_C
6735 * @arg @ref LL_HRTIM_TIMER_D
6736 * @arg @ref LL_HRTIM_TIMER_E
6737 * @arg @ref LL_HRTIM_TIMER_F
6738 * @retval Mode returned value can be one of the following values:
6739 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6740 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6741 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6742 */
LL_HRTIM_TIM_GetOutputRollOverMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6743 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6744 {
6745 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6746 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6747 REG_OFFSET_TAB_TIMER[iTimer]));
6748 return (READ_BIT(*pReg, HRTIM_TIMCR2_OUTROM) >> HRTIM_TIMCR2_OUTROM_Pos);
6749 }
6750
6751 /**
6752 * @brief Select the counting mode.
6753 * @note The up-down counting mode is available for both continuous and single-shot
6754 * (retriggerable and nonretriggerable) operating modes
6755 * (see function @ref LL_HRTIM_TIM_SetCounterMode()).
6756 * @note The counter roll-over event is defined differently in-up-down counting mode to
6757 * support various operating condition.
6758 * See @ref LL_HRTIM_TIM_SetCounterMode()
6759 * @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_SetCountingMode
6760 * @param HRTIMx High Resolution Timer instance
6761 * @param Timer This parameter can be one of the following values:
6762 * @arg @ref LL_HRTIM_TIMER_A
6763 * @arg @ref LL_HRTIM_TIMER_B
6764 * @arg @ref LL_HRTIM_TIMER_C
6765 * @arg @ref LL_HRTIM_TIMER_D
6766 * @arg @ref LL_HRTIM_TIMER_E
6767 * @arg @ref LL_HRTIM_TIMER_F
6768 * @param Mode This parameter can be one of the following values:
6769 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
6770 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
6771 * @retval None
6772 */
LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6773 __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6774 {
6775 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6776 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6777 REG_OFFSET_TAB_TIMER[iTimer]));
6778 MODIFY_REG(* pReg, HRTIM_TIMCR2_UDM, Mode);
6779 }
6780
6781 /**
6782 * @brief Get selected counting mode.
6783 * @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_GetCountingMode
6784 * @param HRTIMx High Resolution Timer instance
6785 * @param Timer This parameter can be one of the following values:
6786 * @arg @ref LL_HRTIM_TIMER_A
6787 * @arg @ref LL_HRTIM_TIMER_B
6788 * @arg @ref LL_HRTIM_TIMER_C
6789 * @arg @ref LL_HRTIM_TIMER_D
6790 * @arg @ref LL_HRTIM_TIMER_E
6791 * @arg @ref LL_HRTIM_TIMER_F
6792 * @retval Mode returned value can be one of the following values:
6793 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
6794 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
6795 * @retval None
6796 */
LL_HRTIM_TIM_GetCountingMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6797 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6798 {
6799 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6800 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6801 REG_OFFSET_TAB_TIMER[iTimer]));
6802 return (READ_BIT(*pReg, HRTIM_TIMCR2_UDM));
6803 }
6804
6805 /**
6806 * @brief Select Dual Channel DAC Reset trigger.
6807 * @note Significant only when Dual channel DAC trigger is enabled
6808 * (see function @ref LL_HRTIM_TIM_EnableDualDacTrigger()).
6809 * @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_SetDualDacResetTrigger
6810 * @param HRTIMx High Resolution Timer instance
6811 * @param Timer This parameter can be one of the following values:
6812 * @arg @ref LL_HRTIM_TIMER_A
6813 * @arg @ref LL_HRTIM_TIMER_B
6814 * @arg @ref LL_HRTIM_TIMER_C
6815 * @arg @ref LL_HRTIM_TIMER_D
6816 * @arg @ref LL_HRTIM_TIMER_E
6817 * @arg @ref LL_HRTIM_TIMER_F
6818 * @param Mode This parameter can be one of the following values:
6819 * @arg @ref LL_HRTIM_DCDR_COUNTER
6820 * @arg @ref LL_HRTIM_DCDR_OUT1SET
6821 * @retval None
6822 */
LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6823 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6824 {
6825 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6826 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6827 REG_OFFSET_TAB_TIMER[iTimer]));
6828 MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDR, Mode);
6829 }
6830
6831 /**
6832 * @brief Get selected Dual Channel DAC Reset trigger.
6833 * @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_GetDualDacResetTrigger
6834 * @param HRTIMx High Resolution Timer instance
6835 * @param Timer This parameter can be one of the following values:
6836 * @arg @ref LL_HRTIM_TIMER_A
6837 * @arg @ref LL_HRTIM_TIMER_B
6838 * @arg @ref LL_HRTIM_TIMER_C
6839 * @arg @ref LL_HRTIM_TIMER_D
6840 * @arg @ref LL_HRTIM_TIMER_E
6841 * @arg @ref LL_HRTIM_TIMER_F
6842 * @retval Trigger returned value can be one of the following values:
6843 * @arg @ref LL_HRTIM_DCDR_COUNTER
6844 * @arg @ref LL_HRTIM_DCDR_OUT1SET
6845 */
LL_HRTIM_TIM_GetDualDacResetTrigger(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6846 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6847 {
6848 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6849 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6850 REG_OFFSET_TAB_TIMER[iTimer]));
6851 return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDR));
6852 }
6853
6854 /**
6855 * @brief Select Dual Channel DAC Reset trigger.
6856 * @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_SetDualDacStepTrigger
6857 * @param HRTIMx High Resolution Timer instance
6858 * @param Timer This parameter can be one of the following values:
6859 * @arg @ref LL_HRTIM_TIMER_A
6860 * @arg @ref LL_HRTIM_TIMER_B
6861 * @arg @ref LL_HRTIM_TIMER_C
6862 * @arg @ref LL_HRTIM_TIMER_D
6863 * @arg @ref LL_HRTIM_TIMER_E
6864 * @arg @ref LL_HRTIM_TIMER_F
6865 * @param Mode This parameter can be one of the following values:
6866 * @arg @ref LL_HRTIM_DCDS_CMP2
6867 * @arg @ref LL_HRTIM_DCDS_OUT1RST
6868 * @retval None
6869 */
LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6870 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6871 {
6872 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6873 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6874 REG_OFFSET_TAB_TIMER[iTimer]));
6875 MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDS, Mode);
6876 }
6877
6878 /**
6879 * @brief Get selected Dual Channel DAC Reset trigger.
6880 * @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_GetDualDacStepTrigger
6881 * @param HRTIMx High Resolution Timer instance
6882 * @param Timer This parameter can be one of the following values:
6883 * @arg @ref LL_HRTIM_TIMER_A
6884 * @arg @ref LL_HRTIM_TIMER_B
6885 * @arg @ref LL_HRTIM_TIMER_C
6886 * @arg @ref LL_HRTIM_TIMER_D
6887 * @arg @ref LL_HRTIM_TIMER_E
6888 * @arg @ref LL_HRTIM_TIMER_F
6889 * @retval Trigger returned value can be one of the following values:
6890 * @arg @ref LL_HRTIM_DCDS_CMP2
6891 * @arg @ref LL_HRTIM_DCDS_OUT1RST
6892 */
LL_HRTIM_TIM_GetDualDacStepTrigger(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6893 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6894 {
6895 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6896 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6897 REG_OFFSET_TAB_TIMER[iTimer]));
6898 return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDS));
6899 }
6900
6901 /**
6902 * @brief Enable Dual Channel DAC trigger.
6903 * @note Only significant when balanced Idle mode is enabled (see function @ref LL_HRTIM_TIM_SetDLYPRTMode()).
6904 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_EnableDualDacTrigger
6905 * @param HRTIMx High Resolution Timer instance
6906 * @param Timer This parameter can be one of the following values:
6907 * @arg @ref LL_HRTIM_TIMER_A
6908 * @arg @ref LL_HRTIM_TIMER_B
6909 * @arg @ref LL_HRTIM_TIMER_C
6910 * @arg @ref LL_HRTIM_TIMER_D
6911 * @arg @ref LL_HRTIM_TIMER_E
6912 * @arg @ref LL_HRTIM_TIMER_F
6913 * @retval None
6914 */
LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6915 __STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6916 {
6917 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6918 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6919 REG_OFFSET_TAB_TIMER[iTimer]));
6920 SET_BIT(* pReg, HRTIM_TIMCR2_DCDE);
6921 }
6922
6923 /**
6924 * @brief Disable Dual Channel DAC trigger.
6925 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_DisableDualDacTrigger
6926 * @param HRTIMx High Resolution Timer instance
6927 * @param Timer This parameter can be one of the following values:
6928 * @arg @ref LL_HRTIM_TIMER_A
6929 * @arg @ref LL_HRTIM_TIMER_B
6930 * @arg @ref LL_HRTIM_TIMER_C
6931 * @arg @ref LL_HRTIM_TIMER_D
6932 * @arg @ref LL_HRTIM_TIMER_E
6933 * @arg @ref LL_HRTIM_TIMER_F
6934 * @retval None
6935 */
LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6936 __STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6937 {
6938 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6939 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6940 REG_OFFSET_TAB_TIMER[iTimer]));
6941 CLEAR_BIT(* pReg, HRTIM_TIMCR2_DCDE);
6942 }
6943
6944 /**
6945 * @brief Indicate whether Dual Channel DAC trigger is enabled for a given timer.
6946 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_IsEnabledDualDacTrigger
6947 * @param HRTIMx High Resolution Timer instance
6948 * @param Timer This parameter can be one of the following values:
6949 * @arg @ref LL_HRTIM_TIMER_A
6950 * @arg @ref LL_HRTIM_TIMER_B
6951 * @arg @ref LL_HRTIM_TIMER_C
6952 * @arg @ref LL_HRTIM_TIMER_D
6953 * @arg @ref LL_HRTIM_TIMER_E
6954 * @arg @ref LL_HRTIM_TIMER_F
6955 * @retval State of DCDE bit in HRTIM_TIMxCR2 register (1 or 0).
6956 */
LL_HRTIM_TIM_IsEnabledDualDacTrigger(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)6957 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6958 {
6959 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6960 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6961 REG_OFFSET_TAB_TIMER[iTimer]));
6962
6963 return ((READ_BIT(* pReg, HRTIM_TIMCR2_DCDE) == (HRTIM_TIMCR2_DCDE)) ? 1UL : 0UL);
6964 }
6965
6966
6967 /**
6968 * @brief Set the external event counter threshold.
6969 * @note The external event is propagated to the timer only if the number
6970 * of active edges is greater than the external event counter threshold.
6971 * @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_SetEventCounterThreshold\n
6972 * EEFxR3 EEVACNT LL_HRTIM_TIM_SetEventCounterThreshold
6973 * @param HRTIMx High Resolution Timer instance
6974 * @param Timer This parameter can be one of the following values:
6975 * @arg @ref LL_HRTIM_TIMER_A
6976 * @arg @ref LL_HRTIM_TIMER_B
6977 * @arg @ref LL_HRTIM_TIMER_C
6978 * @arg @ref LL_HRTIM_TIMER_D
6979 * @arg @ref LL_HRTIM_TIMER_E
6980 * @arg @ref LL_HRTIM_TIMER_F
6981 * @param EventCounter This parameter can be one of the following values:
6982 * @arg @ref LL_HRTIM_EE_COUNTER_A
6983 * @arg @ref LL_HRTIM_EE_COUNTER_B
6984 * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=63
6985 * @retval None
6986 */
LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Threshold)6987 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
6988 uint32_t Threshold)
6989 {
6990 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6991 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
6992
6993 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVACNT << EventCounter), Threshold << (HRTIM_EEFR3_EEVACNT_Pos + EventCounter));
6994 }
6995
6996 /**
6997 * @brief Get the programmed external event counter threshold.
6998 * @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_GetEventCounterThreshold\n
6999 * EEFxR3 EEVACNT LL_HRTIM_TIM_GetEventCounterThreshold
7000 * @param HRTIMx High Resolution Timer instance
7001 * @param Timer This parameter can be one of the following values:
7002 * @arg @ref LL_HRTIM_TIMER_A
7003 * @arg @ref LL_HRTIM_TIMER_B
7004 * @arg @ref LL_HRTIM_TIMER_C
7005 * @arg @ref LL_HRTIM_TIMER_D
7006 * @arg @ref LL_HRTIM_TIMER_E
7007 * @arg @ref LL_HRTIM_TIMER_F
7008 * @param EventCounter This parameter can be one of the following values:
7009 * @arg @ref LL_HRTIM_EE_COUNTER_A
7010 * @arg @ref LL_HRTIM_EE_COUNTER_B
7011 * @retval Threshold Value between Min_Data=0 and Max_Data=63
7012 */
LL_HRTIM_TIM_GetEventCounterThreshold(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7013 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7014 uint32_t EventCounter)
7015 {
7016 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7017 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7018
7019 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACNT) << EventCounter)) >> ((HRTIM_EEFR3_EEVACNT_Pos + EventCounter))) ;
7020 }
7021
7022 /**
7023 * @brief Select the external event counter source.
7024 * @note External event counting is only valid for edge-sensitive
7025 * external events (See function LL_HRTIM_EE_Config() and function
7026 * LL_HRTIM_EE_SetSensitivity()).
7027 * @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_SetEventCounterSource\n
7028 * EEFxR3 EEVASEL LL_HRTIM_TIM_SetEventCounterSource
7029 * @param HRTIMx High Resolution Timer instance
7030 * @param Timer This parameter can be one of the following values:
7031 * @arg @ref LL_HRTIM_TIMER_A
7032 * @arg @ref LL_HRTIM_TIMER_B
7033 * @arg @ref LL_HRTIM_TIMER_C
7034 * @arg @ref LL_HRTIM_TIMER_D
7035 * @arg @ref LL_HRTIM_TIMER_E
7036 * @arg @ref LL_HRTIM_TIMER_F
7037 * @param EventCounter This parameter can be one of the following values:
7038 * @arg @ref LL_HRTIM_EE_COUNTER_A
7039 * @arg @ref LL_HRTIM_EE_COUNTER_B
7040 * @param Event This parameter can be one of the following values:
7041 * @arg @ref LL_HRTIM_EVENT_1
7042 * @arg @ref LL_HRTIM_EVENT_2
7043 * @arg @ref LL_HRTIM_EVENT_3
7044 * @arg @ref LL_HRTIM_EVENT_4
7045 * @arg @ref LL_HRTIM_EVENT_5
7046 * @arg @ref LL_HRTIM_EVENT_6
7047 * @arg @ref LL_HRTIM_EVENT_7
7048 * @arg @ref LL_HRTIM_EVENT_8
7049 * @arg @ref LL_HRTIM_EVENT_9
7050 * @arg @ref LL_HRTIM_EVENT_10
7051 * @retval None
7052 */
LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Event)7053 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
7054 uint32_t Event)
7055 {
7056 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7057 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7058 uint32_t iEvent = (uint32_t)(POSITION_VAL(Event));
7059
7060 /* register SEL value is 0 if LL_HRTIM_EVENT_1, 1 if LL_HRTIM_EVENT_1, etc
7061 and 9 if LL_HRTIM_EVENT_10 */
7062 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVASEL << EventCounter), iEvent << (HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
7063 }
7064
7065 /**
7066 * @brief get the selected external event counter source.
7067 * LL_HRTIM_EE_SetSensitivity()).
7068 * @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_GetEventCounterSource\n
7069 * EEFxR3 EEVASEL LL_HRTIM_TIM_GetEventCounterSource
7070 * @param HRTIMx High Resolution Timer instance
7071 * @param Timer This parameter can be one of the following values:
7072 * @arg @ref LL_HRTIM_TIMER_A
7073 * @arg @ref LL_HRTIM_TIMER_B
7074 * @arg @ref LL_HRTIM_TIMER_C
7075 * @arg @ref LL_HRTIM_TIMER_D
7076 * @arg @ref LL_HRTIM_TIMER_E
7077 * @arg @ref LL_HRTIM_TIMER_F
7078 * @param EventCounter This parameter can be one of the following values:
7079 * @arg @ref LL_HRTIM_EE_COUNTER_A
7080 * @arg @ref LL_HRTIM_EE_COUNTER_B
7081 * @retval Event This parameter can be one of the following values:
7082 * @arg @ref LL_HRTIM_EVENT_1
7083 * @arg @ref LL_HRTIM_EVENT_2
7084 * @arg @ref LL_HRTIM_EVENT_3
7085 * @arg @ref LL_HRTIM_EVENT_4
7086 * @arg @ref LL_HRTIM_EVENT_5
7087 * @arg @ref LL_HRTIM_EVENT_6
7088 * @arg @ref LL_HRTIM_EVENT_7
7089 * @arg @ref LL_HRTIM_EVENT_8
7090 * @arg @ref LL_HRTIM_EVENT_9
7091 * @arg @ref LL_HRTIM_EVENT_10
7092 */
LL_HRTIM_TIM_GetEventCounterSource(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7093 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7094 uint32_t EventCounter)
7095 {
7096 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7097 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7098
7099 uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
7100
7101 /* returned value is 0 if SEL is LL_HRTIM_EVENT_1, 1 if SEL is LL_HRTIM_EVENT_1, etc
7102 and 9 if SEL is LL_HRTIM_EVENT_10 */
7103 return ((uint32_t)0x1U << iEvent) ;
7104 }
7105
7106 /**
7107 * @brief Select the external event counter reset mode.
7108 * @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_SetEventCounterResetMode\n
7109 * EEFxR3 EEVARSTM LL_HRTIM_TIM_SetEventCounterResetMode
7110 * @param HRTIMx High Resolution Timer instance
7111 * @param Timer This parameter can be one of the following values:
7112 * @arg @ref LL_HRTIM_TIMER_A
7113 * @arg @ref LL_HRTIM_TIMER_B
7114 * @arg @ref LL_HRTIM_TIMER_C
7115 * @arg @ref LL_HRTIM_TIMER_D
7116 * @arg @ref LL_HRTIM_TIMER_E
7117 * @arg @ref LL_HRTIM_TIMER_F
7118 * @param EventCounter This parameter can be one of the following values:
7119 * @arg @ref LL_HRTIM_EE_COUNTER_A
7120 * @arg @ref LL_HRTIM_EE_COUNTER_B
7121 * @param Mode This parameter can be one of the following values:
7122 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
7123 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
7124 * @retval None
7125 */
LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Mode)7126 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
7127 uint32_t Mode)
7128 {
7129 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7130 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7131
7132 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVARSTM << (EventCounter)), Mode << (EventCounter));
7133 }
7134
7135 /**
7136 * @brief Get selected external event counter reset mode.
7137 * @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_GetEventCounterResetMode\n
7138 * EEFxR3 EEVARSTM LL_HRTIM_TIM_GetEventCounterResetMode
7139 * @param HRTIMx High Resolution Timer instance
7140 * @param Timer This parameter can be one of the following values:
7141 * @arg @ref LL_HRTIM_TIMER_A
7142 * @arg @ref LL_HRTIM_TIMER_B
7143 * @arg @ref LL_HRTIM_TIMER_C
7144 * @arg @ref LL_HRTIM_TIMER_D
7145 * @arg @ref LL_HRTIM_TIMER_E
7146 * @arg @ref LL_HRTIM_TIMER_F
7147 * @param EventCounter This parameter can be one of the following values:
7148 * @arg @ref LL_HRTIM_EE_COUNTER_A
7149 * @arg @ref LL_HRTIM_EE_COUNTER_B
7150 * @retval Mode This parameter can be one of the following values:
7151 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
7152 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
7153 */
LL_HRTIM_TIM_GetEventCounterResetMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7154 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7155 uint32_t EventCounter)
7156 {
7157 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7158 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7159
7160 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVARSTM) << (EventCounter))) >> (EventCounter)) ;
7161 }
7162
7163 /**
7164 * @brief Reset the external event counter.
7165 * @rmtoll EEFxR3 EEVACRES LL_HRTIM_TIM_ResetEventCounter\n
7166 * EEFxR3 EEVBCRES LL_HRTIM_TIM_ResetEventCounter
7167 * @param HRTIMx High Resolution Timer instance
7168 * @param Timer This parameter can be one of the following values:
7169 * @arg @ref LL_HRTIM_TIMER_A
7170 * @arg @ref LL_HRTIM_TIMER_B
7171 * @arg @ref LL_HRTIM_TIMER_C
7172 * @arg @ref LL_HRTIM_TIMER_D
7173 * @arg @ref LL_HRTIM_TIMER_E
7174 * @arg @ref LL_HRTIM_TIMER_F
7175 * @param EventCounter This parameter can be one of the following values:
7176 * @arg @ref LL_HRTIM_EE_COUNTER_A
7177 * @arg @ref LL_HRTIM_EE_COUNTER_B
7178 * @retval None
7179 */
LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7180 __STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7181 {
7182 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7183 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7184
7185 SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACRES) << EventCounter);
7186 }
7187
7188 /**
7189 * @brief Enable the external event counter.
7190 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_EnableEventCounter\n
7191 * EEFxR3 EEVBCE LL_HRTIM_TIM_EnableEventCounter
7192 * @param HRTIMx High Resolution Timer instance
7193 * @param Timer This parameter can be one of the following values:
7194 * @arg @ref LL_HRTIM_TIMER_A
7195 * @arg @ref LL_HRTIM_TIMER_B
7196 * @arg @ref LL_HRTIM_TIMER_C
7197 * @arg @ref LL_HRTIM_TIMER_D
7198 * @arg @ref LL_HRTIM_TIMER_E
7199 * @arg @ref LL_HRTIM_TIMER_F
7200 * @param EventCounter This parameter can be one of the following values:
7201 * @arg @ref LL_HRTIM_EE_COUNTER_A
7202 * @arg @ref LL_HRTIM_EE_COUNTER_B
7203 * @retval None
7204 */
LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7205 __STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7206 {
7207 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7208 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7209
7210 SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
7211 }
7212
7213 /**
7214 * @brief Disable the external event counter.
7215 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_DisableEventCounter\n
7216 * EEFxR3 EEVBCE LL_HRTIM_TIM_DisableEventCounter
7217 * @param HRTIMx High Resolution Timer instance
7218 * @param Timer This parameter can be one of the following values:
7219 * @arg @ref LL_HRTIM_TIMER_A
7220 * @arg @ref LL_HRTIM_TIMER_B
7221 * @arg @ref LL_HRTIM_TIMER_C
7222 * @arg @ref LL_HRTIM_TIMER_D
7223 * @arg @ref LL_HRTIM_TIMER_E
7224 * @arg @ref LL_HRTIM_TIMER_F
7225 * @param EventCounter This parameter can be one of the following values:
7226 * @arg @ref LL_HRTIM_EE_COUNTER_A
7227 * @arg @ref LL_HRTIM_EE_COUNTER_B
7228 * @retval None
7229 */
LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7230 __STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7231 {
7232 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7233 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7234
7235 CLEAR_BIT(*pReg, (HRTIM_EEFR3_EEVACE << EventCounter));
7236 }
7237
7238
7239 /**
7240 * @brief Indicate whether the external event counter is enabled for a given timer.
7241 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_IsEnabledEventCounter\n
7242 * EEFxR3 EEVBCE LL_HRTIM_TIM_IsEnabledEventCounter
7243 * @param HRTIMx High Resolution Timer instance
7244 * @param Timer This parameter can be one of the following values:
7245 * @arg @ref LL_HRTIM_TIMER_A
7246 * @arg @ref LL_HRTIM_TIMER_B
7247 * @arg @ref LL_HRTIM_TIMER_C
7248 * @arg @ref LL_HRTIM_TIMER_D
7249 * @arg @ref LL_HRTIM_TIMER_E
7250 * @arg @ref LL_HRTIM_TIMER_F
7251 * @param EventCounter This parameter can be one of the following values:
7252 * @arg @ref LL_HRTIM_EE_COUNTER_A
7253 * @arg @ref LL_HRTIM_EE_COUNTER_B
7254 * @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0).
7255 */
LL_HRTIM_TIM_IsEnabledEventCounter(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7256 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7257 uint32_t EventCounter)
7258 {
7259 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7260 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7261
7262 uint32_t temp; /* MISRAC-2012 compliance */
7263 temp = READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
7264
7265 return ((temp == ((uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter)) ? 1UL : 0UL);
7266 }
7267
7268 /**
7269 * @}
7270 */
7271
7272 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
7273 * @{
7274 */
7275
7276 /**
7277 * @brief Configure the dead time insertion feature for a given timer.
7278 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
7279 * DTxR SDTF LL_HRTIM_DT_Config\n
7280 * DTxR SDRT LL_HRTIM_DT_Config
7281 * @param HRTIMx High Resolution Timer instance
7282 * @param Timer This parameter can be one of the following values:
7283 * @arg @ref LL_HRTIM_TIMER_A
7284 * @arg @ref LL_HRTIM_TIMER_B
7285 * @arg @ref LL_HRTIM_TIMER_C
7286 * @arg @ref LL_HRTIM_TIMER_D
7287 * @arg @ref LL_HRTIM_TIMER_E
7288 * @arg @ref LL_HRTIM_TIMER_F
7289 * @param Configuration This parameter must be a combination of all the following values:
7290 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
7291 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
7292 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
7293 * @retval None
7294 */
LL_HRTIM_DT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)7295 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
7296 {
7297 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7298 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7299 REG_OFFSET_TAB_TIMER[iTimer]));
7300 MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
7301 }
7302
7303 /**
7304 * @brief Set the deadtime prescaler value.
7305 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
7306 * @param HRTIMx High Resolution Timer instance
7307 * @param Timer This parameter can be one of the following values:
7308 * @arg @ref LL_HRTIM_TIMER_A
7309 * @arg @ref LL_HRTIM_TIMER_B
7310 * @arg @ref LL_HRTIM_TIMER_C
7311 * @arg @ref LL_HRTIM_TIMER_D
7312 * @arg @ref LL_HRTIM_TIMER_E
7313 * @arg @ref LL_HRTIM_TIMER_F
7314 * @param Prescaler This parameter can be one of the following values:
7315 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
7316 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
7317 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
7318 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
7319 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
7320 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
7321 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
7322 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
7323 * @retval None
7324 */
LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)7325 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
7326 {
7327 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7328 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7329 REG_OFFSET_TAB_TIMER[iTimer]));
7330 MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
7331 }
7332
7333 /**
7334 * @brief Get actual deadtime prescaler value.
7335 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
7336 * @param HRTIMx High Resolution Timer instance
7337 * @param Timer This parameter can be one of the following values:
7338 * @arg @ref LL_HRTIM_TIMER_A
7339 * @arg @ref LL_HRTIM_TIMER_B
7340 * @arg @ref LL_HRTIM_TIMER_C
7341 * @arg @ref LL_HRTIM_TIMER_D
7342 * @arg @ref LL_HRTIM_TIMER_E
7343 * @arg @ref LL_HRTIM_TIMER_F
7344 * @retval Prescaler This parameter can be one of the following values:
7345 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
7346 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
7347 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
7348 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
7349 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
7350 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
7351 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
7352 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
7353 */
LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7354 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7355 {
7356 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7357 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7358 REG_OFFSET_TAB_TIMER[iTimer]));
7359 return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
7360 }
7361
7362 /**
7363 * @brief Set the deadtime rising value.
7364 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
7365 * @param HRTIMx High Resolution Timer instance
7366 * @param Timer This parameter can be one of the following values:
7367 * @arg @ref LL_HRTIM_TIMER_A
7368 * @arg @ref LL_HRTIM_TIMER_B
7369 * @arg @ref LL_HRTIM_TIMER_C
7370 * @arg @ref LL_HRTIM_TIMER_D
7371 * @arg @ref LL_HRTIM_TIMER_E
7372 * @arg @ref LL_HRTIM_TIMER_F
7373 * @param RisingValue Value between 0 and 0x1FF
7374 * @retval None
7375 */
LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingValue)7376 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
7377 {
7378 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7379 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7380 REG_OFFSET_TAB_TIMER[iTimer]));
7381 MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
7382 }
7383
7384 /**
7385 * @brief Get actual deadtime rising value.
7386 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
7387 * @param HRTIMx High Resolution Timer instance
7388 * @param Timer This parameter can be one of the following values:
7389 * @arg @ref LL_HRTIM_TIMER_A
7390 * @arg @ref LL_HRTIM_TIMER_B
7391 * @arg @ref LL_HRTIM_TIMER_C
7392 * @arg @ref LL_HRTIM_TIMER_D
7393 * @arg @ref LL_HRTIM_TIMER_E
7394 * @arg @ref LL_HRTIM_TIMER_F
7395 * @retval RisingValue Value between 0 and 0x1FF
7396 */
LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7397 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7398 {
7399 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7400 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7401 REG_OFFSET_TAB_TIMER[iTimer]));
7402 return (READ_BIT(*pReg, HRTIM_DTR_DTR));
7403 }
7404
7405 /**
7406 * @brief Set the deadtime sign on rising edge.
7407 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
7408 * @param HRTIMx High Resolution Timer instance
7409 * @param Timer This parameter can be one of the following values:
7410 * @arg @ref LL_HRTIM_TIMER_A
7411 * @arg @ref LL_HRTIM_TIMER_B
7412 * @arg @ref LL_HRTIM_TIMER_C
7413 * @arg @ref LL_HRTIM_TIMER_D
7414 * @arg @ref LL_HRTIM_TIMER_E
7415 * @arg @ref LL_HRTIM_TIMER_F
7416 * @param RisingSign This parameter can be one of the following values:
7417 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
7418 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
7419 * @retval None
7420 */
LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingSign)7421 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
7422 {
7423 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7424 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7425 REG_OFFSET_TAB_TIMER[iTimer]));
7426 MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
7427 }
7428
7429 /**
7430 * @brief Get actual deadtime sign on rising edge.
7431 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
7432 * @param HRTIMx High Resolution Timer instance
7433 * @param Timer This parameter can be one of the following values:
7434 * @arg @ref LL_HRTIM_TIMER_A
7435 * @arg @ref LL_HRTIM_TIMER_B
7436 * @arg @ref LL_HRTIM_TIMER_C
7437 * @arg @ref LL_HRTIM_TIMER_D
7438 * @arg @ref LL_HRTIM_TIMER_E
7439 * @arg @ref LL_HRTIM_TIMER_F
7440 * @retval RisingSign This parameter can be one of the following values:
7441 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
7442 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
7443 */
LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7444 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7445 {
7446 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7447 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7448 REG_OFFSET_TAB_TIMER[iTimer]));
7449 return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
7450 }
7451
7452 /**
7453 * @brief Set the deadime falling value.
7454 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
7455 * @param HRTIMx High Resolution Timer instance
7456 * @param Timer This parameter can be one of the following values:
7457 * @arg @ref LL_HRTIM_TIMER_A
7458 * @arg @ref LL_HRTIM_TIMER_B
7459 * @arg @ref LL_HRTIM_TIMER_C
7460 * @arg @ref LL_HRTIM_TIMER_D
7461 * @arg @ref LL_HRTIM_TIMER_E
7462 * @arg @ref LL_HRTIM_TIMER_F
7463 * @param FallingValue Value between 0 and 0x1FF
7464 * @retval None
7465 */
LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingValue)7466 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
7467 {
7468 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7469 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7470 REG_OFFSET_TAB_TIMER[iTimer]));
7471 MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
7472 }
7473
7474 /**
7475 * @brief Get actual deadtime falling value
7476 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
7477 * @param HRTIMx High Resolution Timer instance
7478 * @param Timer This parameter can be one of the following values:
7479 * @arg @ref LL_HRTIM_TIMER_A
7480 * @arg @ref LL_HRTIM_TIMER_B
7481 * @arg @ref LL_HRTIM_TIMER_C
7482 * @arg @ref LL_HRTIM_TIMER_D
7483 * @arg @ref LL_HRTIM_TIMER_E
7484 * @arg @ref LL_HRTIM_TIMER_F
7485 * @retval FallingValue Value between 0 and 0x1FF
7486 */
LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7487 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7488 {
7489 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7490 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7491 REG_OFFSET_TAB_TIMER[iTimer]));
7492 return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
7493 }
7494
7495 /**
7496 * @brief Set the deadtime sign on falling edge.
7497 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
7498 * @param HRTIMx High Resolution Timer instance
7499 * @param Timer This parameter can be one of the following values:
7500 * @arg @ref LL_HRTIM_TIMER_A
7501 * @arg @ref LL_HRTIM_TIMER_B
7502 * @arg @ref LL_HRTIM_TIMER_C
7503 * @arg @ref LL_HRTIM_TIMER_D
7504 * @arg @ref LL_HRTIM_TIMER_E
7505 * @arg @ref LL_HRTIM_TIMER_F
7506 * @param FallingSign This parameter can be one of the following values:
7507 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
7508 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
7509 * @retval None
7510 */
LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingSign)7511 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
7512 {
7513 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7514 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7515 REG_OFFSET_TAB_TIMER[iTimer]));
7516 MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
7517 }
7518
7519 /**
7520 * @brief Get actual deadtime sign on falling edge.
7521 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
7522 * @param HRTIMx High Resolution Timer instance
7523 * @param Timer This parameter can be one of the following values:
7524 * @arg @ref LL_HRTIM_TIMER_A
7525 * @arg @ref LL_HRTIM_TIMER_B
7526 * @arg @ref LL_HRTIM_TIMER_C
7527 * @arg @ref LL_HRTIM_TIMER_D
7528 * @arg @ref LL_HRTIM_TIMER_E
7529 * @arg @ref LL_HRTIM_TIMER_F
7530 * @retval FallingSign This parameter can be one of the following values:
7531 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
7532 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
7533 */
LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7534 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7535 {
7536 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7537 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7538 REG_OFFSET_TAB_TIMER[iTimer]));
7539 return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
7540 }
7541
7542 /**
7543 * @brief Lock the deadtime value and sign on rising edge.
7544 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
7545 * @param HRTIMx High Resolution Timer instance
7546 * @param Timer This parameter can be one of the following values:
7547 * @arg @ref LL_HRTIM_TIMER_A
7548 * @arg @ref LL_HRTIM_TIMER_B
7549 * @arg @ref LL_HRTIM_TIMER_C
7550 * @arg @ref LL_HRTIM_TIMER_D
7551 * @arg @ref LL_HRTIM_TIMER_E
7552 * @arg @ref LL_HRTIM_TIMER_F
7553 * @retval None
7554 */
LL_HRTIM_DT_LockRising(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7555 __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7556 {
7557 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7558 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7559 REG_OFFSET_TAB_TIMER[iTimer]));
7560 SET_BIT(*pReg, HRTIM_DTR_DTRLK);
7561 }
7562
7563 /**
7564 * @brief Lock the deadtime sign on rising edge.
7565 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
7566 * @param HRTIMx High Resolution Timer instance
7567 * @param Timer This parameter can be one of the following values:
7568 * @arg @ref LL_HRTIM_TIMER_A
7569 * @arg @ref LL_HRTIM_TIMER_B
7570 * @arg @ref LL_HRTIM_TIMER_C
7571 * @arg @ref LL_HRTIM_TIMER_D
7572 * @arg @ref LL_HRTIM_TIMER_E
7573 * @arg @ref LL_HRTIM_TIMER_F
7574 * @retval None
7575 */
LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7576 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7577 {
7578 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7579 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7580 REG_OFFSET_TAB_TIMER[iTimer]));
7581 SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
7582 }
7583
7584 /**
7585 * @brief Lock the deadtime value and sign on falling edge.
7586 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
7587 * @param HRTIMx High Resolution Timer instance
7588 * @param Timer This parameter can be one of the following values:
7589 * @arg @ref LL_HRTIM_TIMER_A
7590 * @arg @ref LL_HRTIM_TIMER_B
7591 * @arg @ref LL_HRTIM_TIMER_C
7592 * @arg @ref LL_HRTIM_TIMER_D
7593 * @arg @ref LL_HRTIM_TIMER_E
7594 * @arg @ref LL_HRTIM_TIMER_F
7595 * @retval None
7596 */
LL_HRTIM_DT_LockFalling(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7597 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7598 {
7599 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7600 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7601 REG_OFFSET_TAB_TIMER[iTimer]));
7602 SET_BIT(*pReg, HRTIM_DTR_DTFLK);
7603 }
7604
7605 /**
7606 * @brief Lock the deadtime sign on falling edge.
7607 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
7608 * @param HRTIMx High Resolution Timer instance
7609 * @param Timer This parameter can be one of the following values:
7610 * @arg @ref LL_HRTIM_TIMER_A
7611 * @arg @ref LL_HRTIM_TIMER_B
7612 * @arg @ref LL_HRTIM_TIMER_C
7613 * @arg @ref LL_HRTIM_TIMER_D
7614 * @arg @ref LL_HRTIM_TIMER_E
7615 * @arg @ref LL_HRTIM_TIMER_F
7616 * @retval None
7617 */
LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7618 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7619 {
7620 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7621 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7622 REG_OFFSET_TAB_TIMER[iTimer]));
7623 SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
7624 }
7625
7626 /**
7627 * @}
7628 */
7629
7630 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
7631 * @{
7632 */
7633
7634 /**
7635 * @brief Configure the chopper stage for a given timer.
7636 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
7637 * CHPxR CARDTY LL_HRTIM_CHP_Config\n
7638 * CHPxR STRTPW LL_HRTIM_CHP_Config
7639 * @note This function must not be called if the chopper mode is already
7640 * enabled for one of the timer outputs.
7641 * @param HRTIMx High Resolution Timer instance
7642 * @param Timer This parameter can be one of the following values:
7643 * @arg @ref LL_HRTIM_TIMER_A
7644 * @arg @ref LL_HRTIM_TIMER_B
7645 * @arg @ref LL_HRTIM_TIMER_C
7646 * @arg @ref LL_HRTIM_TIMER_D
7647 * @arg @ref LL_HRTIM_TIMER_E
7648 * @arg @ref LL_HRTIM_TIMER_F
7649 * @param Configuration This parameter must be a combination of all the following values:
7650 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
7651 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
7652 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
7653 * @retval None
7654 */
LL_HRTIM_CHP_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)7655 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
7656 {
7657 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7658 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7659 REG_OFFSET_TAB_TIMER[iTimer]));
7660 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
7661 }
7662
7663 /**
7664 * @brief Set prescaler determining the carrier frequency to be added on top
7665 * of the timer output signals when chopper mode is enabled.
7666 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
7667 * @note This function must not be called if the chopper mode is already
7668 * enabled for one of the timer outputs.
7669 * @param HRTIMx High Resolution Timer instance
7670 * @param Timer This parameter can be one of the following values:
7671 * @arg @ref LL_HRTIM_TIMER_A
7672 * @arg @ref LL_HRTIM_TIMER_B
7673 * @arg @ref LL_HRTIM_TIMER_C
7674 * @arg @ref LL_HRTIM_TIMER_D
7675 * @arg @ref LL_HRTIM_TIMER_E
7676 * @arg @ref LL_HRTIM_TIMER_F
7677 * @param Prescaler This parameter can be one of the following values:
7678 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
7679 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
7680 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
7681 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
7682 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
7683 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
7684 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
7685 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
7686 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
7687 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
7688 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
7689 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
7690 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
7691 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
7692 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
7693 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
7694 * @retval None
7695 */
LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)7696 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
7697 {
7698 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7699 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7700 REG_OFFSET_TAB_TIMER[iTimer]));
7701 MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
7702 }
7703
7704 /**
7705 * @brief Get actual chopper stage prescaler value.
7706 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
7707 * @param HRTIMx High Resolution Timer instance
7708 * @param Timer This parameter can be one of the following values:
7709 * @arg @ref LL_HRTIM_TIMER_A
7710 * @arg @ref LL_HRTIM_TIMER_B
7711 * @arg @ref LL_HRTIM_TIMER_C
7712 * @arg @ref LL_HRTIM_TIMER_D
7713 * @arg @ref LL_HRTIM_TIMER_E
7714 * @arg @ref LL_HRTIM_TIMER_F
7715 * @retval Prescaler This parameter can be one of the following values:
7716 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
7717 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
7718 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
7719 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
7720 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
7721 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
7722 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
7723 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
7724 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
7725 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
7726 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
7727 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
7728 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
7729 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
7730 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
7731 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
7732 */
LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7733 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7734 {
7735 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7736 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7737 REG_OFFSET_TAB_TIMER[iTimer]));
7738 return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
7739 }
7740
7741 /**
7742 * @brief Set the chopper duty cycle.
7743 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
7744 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
7745 * @note This function must not be called if the chopper mode is already
7746 * enabled for one of the timer outputs.
7747 * @param HRTIMx High Resolution Timer instance
7748 * @param Timer This parameter can be one of the following values:
7749 * @arg @ref LL_HRTIM_TIMER_A
7750 * @arg @ref LL_HRTIM_TIMER_B
7751 * @arg @ref LL_HRTIM_TIMER_C
7752 * @arg @ref LL_HRTIM_TIMER_D
7753 * @arg @ref LL_HRTIM_TIMER_E
7754 * @arg @ref LL_HRTIM_TIMER_F
7755 * @param DutyCycle This parameter can be one of the following values:
7756 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
7757 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
7758 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
7759 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
7760 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
7761 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
7762 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
7763 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
7764 * @retval None
7765 */
LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DutyCycle)7766 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
7767 {
7768 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7769 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7770 REG_OFFSET_TAB_TIMER[iTimer]));
7771 MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
7772 }
7773
7774 /**
7775 * @brief Get actual chopper duty cycle.
7776 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
7777 * @param HRTIMx High Resolution Timer instance
7778 * @param Timer This parameter can be one of the following values:
7779 * @arg @ref LL_HRTIM_TIMER_A
7780 * @arg @ref LL_HRTIM_TIMER_B
7781 * @arg @ref LL_HRTIM_TIMER_C
7782 * @arg @ref LL_HRTIM_TIMER_D
7783 * @arg @ref LL_HRTIM_TIMER_E
7784 * @arg @ref LL_HRTIM_TIMER_F
7785 * @retval DutyCycle This parameter can be one of the following values:
7786 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
7787 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
7788 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
7789 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
7790 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
7791 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
7792 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
7793 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
7794 */
LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7795 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7796 {
7797 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7798 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7799 REG_OFFSET_TAB_TIMER[iTimer]));
7800 return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
7801 }
7802
7803 /**
7804 * @brief Set the start pulse width.
7805 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
7806 * @note This function must not be called if the chopper mode is already
7807 * enabled for one of the timer outputs.
7808 * @param HRTIMx High Resolution Timer instance
7809 * @param Timer This parameter can be one of the following values:
7810 * @arg @ref LL_HRTIM_TIMER_A
7811 * @arg @ref LL_HRTIM_TIMER_B
7812 * @arg @ref LL_HRTIM_TIMER_C
7813 * @arg @ref LL_HRTIM_TIMER_D
7814 * @arg @ref LL_HRTIM_TIMER_E
7815 * @arg @ref LL_HRTIM_TIMER_F
7816 * @param PulseWidth This parameter can be one of the following values:
7817 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
7818 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
7819 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
7820 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
7821 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
7822 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
7823 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
7824 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
7825 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
7826 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
7827 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
7828 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
7829 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
7830 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
7831 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
7832 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
7833 * @retval None
7834 */
LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t PulseWidth)7835 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
7836 {
7837 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7838 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7839 REG_OFFSET_TAB_TIMER[iTimer]));
7840 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
7841 }
7842
7843 /**
7844 * @brief Get actual start pulse width.
7845 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
7846 * @param HRTIMx High Resolution Timer instance
7847 * @param Timer This parameter can be one of the following values:
7848 * @arg @ref LL_HRTIM_TIMER_A
7849 * @arg @ref LL_HRTIM_TIMER_B
7850 * @arg @ref LL_HRTIM_TIMER_C
7851 * @arg @ref LL_HRTIM_TIMER_D
7852 * @arg @ref LL_HRTIM_TIMER_E
7853 * @arg @ref LL_HRTIM_TIMER_F
7854 * @retval PulseWidth This parameter can be one of the following values:
7855 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
7856 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
7857 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
7858 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
7859 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
7860 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
7861 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
7862 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
7863 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
7864 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
7865 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
7866 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
7867 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
7868 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
7869 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
7870 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
7871 */
LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7872 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7873 {
7874 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7875 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7876 REG_OFFSET_TAB_TIMER[iTimer]));
7877 return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
7878 }
7879
7880 /**
7881 * @}
7882 */
7883
7884 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
7885 * @{
7886 */
7887
7888 /**
7889 * @brief Set the timer output set source.
7890 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
7891 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
7892 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
7893 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7894 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7895 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7896 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7897 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
7898 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7899 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7900 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7901 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7902 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7903 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7904 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7905 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7906 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7907 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7908 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7909 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7910 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7911 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7912 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7913 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7914 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7915 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7916 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7917 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7918 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7919 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7920 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
7921 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
7922 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
7923 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
7924 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
7925 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7926 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7927 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7928 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7929 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
7930 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7931 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7932 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7933 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7934 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7935 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7936 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7937 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7938 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7939 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7940 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7941 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7942 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7943 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7944 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7945 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7946 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7947 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7948 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7949 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7950 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7951 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7952 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
7953 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
7954 * @param HRTIMx High Resolution Timer instance
7955 * @param Output This parameter can be one of the following values:
7956 * @arg @ref LL_HRTIM_OUTPUT_TA1
7957 * @arg @ref LL_HRTIM_OUTPUT_TA2
7958 * @arg @ref LL_HRTIM_OUTPUT_TB1
7959 * @arg @ref LL_HRTIM_OUTPUT_TB2
7960 * @arg @ref LL_HRTIM_OUTPUT_TC1
7961 * @arg @ref LL_HRTIM_OUTPUT_TC2
7962 * @arg @ref LL_HRTIM_OUTPUT_TD1
7963 * @arg @ref LL_HRTIM_OUTPUT_TD2
7964 * @arg @ref LL_HRTIM_OUTPUT_TE1
7965 * @arg @ref LL_HRTIM_OUTPUT_TE2
7966 * @arg @ref LL_HRTIM_OUTPUT_TF1
7967 * @arg @ref LL_HRTIM_OUTPUT_TF2
7968 * @param SetSrc This parameter can be a combination of the following values:
7969 * @arg @ref LL_HRTIM_OUTPUTSET_NONE
7970 * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
7971 * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
7972 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
7973 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
7974 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
7975 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
7976 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
7977 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
7978 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
7979 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
7980 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
7981 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
7982 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
7983 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
7984 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
7985 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
7986 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
7987 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
7988 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
7989 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
7990 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
7991 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
7992 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
7993 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
7994 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
7995 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
7996 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
7997 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
7998 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
7999 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
8000 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
8001 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
8002 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
8003 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
8004 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
8005 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
8006 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
8007 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
8008 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
8009 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
8010 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
8011 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
8012 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
8013 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
8014 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
8015 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
8016 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
8017 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
8018 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
8019 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
8020 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
8021 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
8022 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
8023 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
8024 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
8025 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
8026 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
8027 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
8028 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
8029 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
8030 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
8031 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
8032 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
8033 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
8034 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
8035 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
8036 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
8037 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
8038 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
8039 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
8040 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
8041 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
8042 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
8043 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
8044 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
8045 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
8046 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8047 * @retval None
8048 */
LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t SetSrc)8049 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
8050 {
8051 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8052 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
8053 REG_OFFSET_TAB_SETxR[iOutput]));
8054 WRITE_REG(*pReg, SetSrc);
8055 }
8056
8057 /**
8058 * @brief Get the timer output set source.
8059 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
8060 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
8061 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
8062 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8063 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8064 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8065 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8066 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
8067 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8068 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8069 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8070 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8071 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8072 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8073 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8074 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8075 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8076 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8077 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8078 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8079 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8080 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8081 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8082 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8083 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8084 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8085 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8086 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8087 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8088 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8089 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
8090 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
8091 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
8092 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
8093 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
8094 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8095 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8096 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8097 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8098 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
8099 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8100 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8101 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8102 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8103 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8104 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8105 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8106 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8107 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8108 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8109 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8110 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8111 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8112 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8113 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8114 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8115 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8116 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8117 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8118 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8119 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8120 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8121 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
8122 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
8123 * @param HRTIMx High Resolution Timer instance
8124 * @param Output This parameter can be one of the following values:
8125 * @arg @ref LL_HRTIM_OUTPUT_TA1
8126 * @arg @ref LL_HRTIM_OUTPUT_TA2
8127 * @arg @ref LL_HRTIM_OUTPUT_TB1
8128 * @arg @ref LL_HRTIM_OUTPUT_TB2
8129 * @arg @ref LL_HRTIM_OUTPUT_TC1
8130 * @arg @ref LL_HRTIM_OUTPUT_TC2
8131 * @arg @ref LL_HRTIM_OUTPUT_TD1
8132 * @arg @ref LL_HRTIM_OUTPUT_TD2
8133 * @arg @ref LL_HRTIM_OUTPUT_TE1
8134 * @arg @ref LL_HRTIM_OUTPUT_TE2
8135 * @arg @ref LL_HRTIM_OUTPUT_TF1
8136 * @arg @ref LL_HRTIM_OUTPUT_TF2
8137 * @retval SetSrc This parameter can be a combination of the following values:
8138 * @arg @ref LL_HRTIM_OUTPUTSET_NONE
8139 * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
8140 * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
8141 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
8142 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
8143 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
8144 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
8145 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
8146 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
8147 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
8148 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
8149 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
8150 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
8151 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
8152 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
8153 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
8154 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
8155 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
8156 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
8157 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
8158 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
8159 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
8160 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
8161 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
8162 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
8163 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
8164 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
8165 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
8166 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
8167 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
8168 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
8169 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
8170 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
8171 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
8172 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
8173 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
8174 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
8175 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
8176 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
8177 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
8178 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
8179 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
8180 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
8181 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
8182 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
8183 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
8184 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
8185 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
8186 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
8187 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
8188 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
8189 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
8190 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
8191 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
8192 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
8193 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
8194 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
8195 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
8196 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
8197 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
8198 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
8199 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
8200 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
8201 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
8202 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
8203 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
8204 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
8205 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
8206 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
8207 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
8208 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
8209 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
8210 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
8211 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
8212 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
8213 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
8214 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
8215 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8216 */
LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Output)8217 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
8218 {
8219 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8220 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
8221 REG_OFFSET_TAB_SETxR[iOutput]));
8222 return (uint32_t) READ_REG(*pReg);
8223 }
8224
8225 /**
8226 * @brief Set the timer output reset source.
8227 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
8228 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
8229 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
8230 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8231 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8232 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8233 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8234 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
8235 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8236 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8237 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8238 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8239 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8240 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8241 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8242 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8243 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8244 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8245 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8246 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8247 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8248 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8249 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8250 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8251 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8252 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8253 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8254 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8255 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8256 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8257 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
8258 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
8259 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
8260 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
8261 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
8262 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8263 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8264 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8265 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8266 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
8267 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8268 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8269 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8270 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8271 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8272 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8273 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8274 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8275 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8276 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8277 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8278 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8279 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8280 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8281 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8282 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8283 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8284 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8285 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8286 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8287 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8288 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8289 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
8290 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
8291 * @param HRTIMx High Resolution Timer instance
8292 * @param Output This parameter can be one of the following values:
8293 * @arg @ref LL_HRTIM_OUTPUT_TA1
8294 * @arg @ref LL_HRTIM_OUTPUT_TA2
8295 * @arg @ref LL_HRTIM_OUTPUT_TB1
8296 * @arg @ref LL_HRTIM_OUTPUT_TB2
8297 * @arg @ref LL_HRTIM_OUTPUT_TC1
8298 * @arg @ref LL_HRTIM_OUTPUT_TC2
8299 * @arg @ref LL_HRTIM_OUTPUT_TD1
8300 * @arg @ref LL_HRTIM_OUTPUT_TD2
8301 * @arg @ref LL_HRTIM_OUTPUT_TE1
8302 * @arg @ref LL_HRTIM_OUTPUT_TE2
8303 * @arg @ref LL_HRTIM_OUTPUT_TF1
8304 * @arg @ref LL_HRTIM_OUTPUT_TF2
8305 * @param ResetSrc This parameter can be a combination of the following values:
8306 * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
8307 * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
8308 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
8309 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
8310 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
8311 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
8312 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
8313 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
8314 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
8315 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
8316 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
8317 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
8318 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
8319 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
8320 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
8321 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
8322 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
8323 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
8324 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
8325 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
8326 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
8327 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
8328 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
8329 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
8330 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
8331 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
8332 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
8333 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
8334 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
8335 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
8336 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
8337 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
8338 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
8339 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
8340 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
8341 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
8342 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
8343 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
8344 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
8345 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
8346 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
8347 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
8348 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
8349 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
8350 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
8351 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
8352 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
8353 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
8354 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
8355 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
8356 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
8357 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
8358 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
8359 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
8360 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
8361 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
8362 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
8363 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
8364 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
8365 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
8366 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
8367 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
8368 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
8369 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
8370 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
8371 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
8372 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
8373 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
8374 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
8375 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
8376 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
8377 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
8378 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
8379 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
8380 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
8381 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
8382 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
8383 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8384 * @retval None
8385 */
LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ResetSrc)8386 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
8387 {
8388 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8389 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
8390 REG_OFFSET_TAB_SETxR[iOutput]));
8391 WRITE_REG(*pReg, ResetSrc);
8392 }
8393
8394 /**
8395 * @brief Get the timer output set source.
8396 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
8397 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
8398 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
8399 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8400 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8401 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8402 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8403 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
8404 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8405 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8406 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8407 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8408 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8409 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8410 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8411 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8412 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8413 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8414 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8415 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8416 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8417 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8418 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8419 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8420 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8421 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8422 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8423 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8424 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8425 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8426 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
8427 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
8428 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
8429 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
8430 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
8431 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8432 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8433 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8434 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8435 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
8436 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8437 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8438 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8439 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8440 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8441 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8442 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8443 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8444 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8445 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8446 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8447 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8448 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8449 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8450 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8451 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8452 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8453 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8454 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8455 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8456 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8457 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8458 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
8459 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
8460 * @param HRTIMx High Resolution Timer instance
8461 * @param Output This parameter can be one of the following values:
8462 * @arg @ref LL_HRTIM_OUTPUT_TA1
8463 * @arg @ref LL_HRTIM_OUTPUT_TA2
8464 * @arg @ref LL_HRTIM_OUTPUT_TB1
8465 * @arg @ref LL_HRTIM_OUTPUT_TB2
8466 * @arg @ref LL_HRTIM_OUTPUT_TC1
8467 * @arg @ref LL_HRTIM_OUTPUT_TC2
8468 * @arg @ref LL_HRTIM_OUTPUT_TD1
8469 * @arg @ref LL_HRTIM_OUTPUT_TD2
8470 * @arg @ref LL_HRTIM_OUTPUT_TE1
8471 * @arg @ref LL_HRTIM_OUTPUT_TE2
8472 * @arg @ref LL_HRTIM_OUTPUT_TF1
8473 * @arg @ref LL_HRTIM_OUTPUT_TF2
8474 * @retval ResetSrc This parameter can be a combination of the following values:
8475 * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
8476 * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
8477 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
8478 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
8479 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
8480 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
8481 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
8482 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
8483 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
8484 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
8485 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
8486 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
8487 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
8488 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
8489 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
8490 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
8491 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
8492 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
8493 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
8494 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
8495 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
8496 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
8497 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
8498 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
8499 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
8500 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
8501 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
8502 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
8503 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
8504 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
8505 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
8506 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
8507 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
8508 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
8509 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
8510 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
8511 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
8512 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
8513 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
8514 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
8515 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
8516 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
8517 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
8518 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
8519 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
8520 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
8521 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
8522 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
8523 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
8524 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
8525 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
8526 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
8527 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
8528 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
8529 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
8530 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
8531 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
8532 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
8533 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
8534 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
8535 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
8536 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
8537 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
8538 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
8539 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
8540 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
8541 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
8542 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
8543 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
8544 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
8545 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
8546 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
8547 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
8548 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
8549 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
8550 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
8551 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
8552 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8553 */
LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Output)8554 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
8555 {
8556 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8557 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
8558 REG_OFFSET_TAB_SETxR[iOutput]));
8559 return (uint32_t) READ_REG(*pReg);
8560 }
8561
8562 /**
8563 * @brief Configure a timer output.
8564 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
8565 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
8566 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
8567 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
8568 * OUTxR CHP1 LL_HRTIM_OUT_Config\n
8569 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
8570 * OUTxR POL2 LL_HRTIM_OUT_Config\n
8571 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
8572 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
8573 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
8574 * OUTxR CHP2 LL_HRTIM_OUT_Config\n
8575 * OUTxR DIDL2 LL_HRTIM_OUT_Config
8576 * @param HRTIMx High Resolution Timer instance
8577 * @param Output This parameter can be one of the following values:
8578 * @arg @ref LL_HRTIM_OUTPUT_TA1
8579 * @arg @ref LL_HRTIM_OUTPUT_TA2
8580 * @arg @ref LL_HRTIM_OUTPUT_TB1
8581 * @arg @ref LL_HRTIM_OUTPUT_TB2
8582 * @arg @ref LL_HRTIM_OUTPUT_TC1
8583 * @arg @ref LL_HRTIM_OUTPUT_TC2
8584 * @arg @ref LL_HRTIM_OUTPUT_TD1
8585 * @arg @ref LL_HRTIM_OUTPUT_TD2
8586 * @arg @ref LL_HRTIM_OUTPUT_TE1
8587 * @arg @ref LL_HRTIM_OUTPUT_TE2
8588 * @arg @ref LL_HRTIM_OUTPUT_TF1
8589 * @arg @ref LL_HRTIM_OUTPUT_TF2
8590 * @param Configuration This parameter must be a combination of all the following values:
8591 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8592 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8593 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8594 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8595 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8596 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8597 * @retval None
8598 */
LL_HRTIM_OUT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Configuration)8599 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
8600 {
8601 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8602 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8603 REG_OFFSET_TAB_OUTxR[iOutput]));
8604 MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
8605 (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
8606 }
8607
8608 /**
8609 * @brief Set the polarity of a timer output.
8610 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
8611 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
8612 * @param HRTIMx High Resolution Timer instance
8613 * @param Output This parameter can be one of the following values:
8614 * @arg @ref LL_HRTIM_OUTPUT_TA1
8615 * @arg @ref LL_HRTIM_OUTPUT_TA2
8616 * @arg @ref LL_HRTIM_OUTPUT_TB1
8617 * @arg @ref LL_HRTIM_OUTPUT_TB2
8618 * @arg @ref LL_HRTIM_OUTPUT_TC1
8619 * @arg @ref LL_HRTIM_OUTPUT_TC2
8620 * @arg @ref LL_HRTIM_OUTPUT_TD1
8621 * @arg @ref LL_HRTIM_OUTPUT_TD2
8622 * @arg @ref LL_HRTIM_OUTPUT_TE1
8623 * @arg @ref LL_HRTIM_OUTPUT_TE2
8624 * @arg @ref LL_HRTIM_OUTPUT_TF1
8625 * @arg @ref LL_HRTIM_OUTPUT_TF2
8626 * @param Polarity This parameter can be one of the following values:
8627 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
8628 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8629 * @retval None
8630 */
LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Polarity)8631 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
8632 {
8633 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8634 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8635 REG_OFFSET_TAB_OUTxR[iOutput]));
8636 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
8637 }
8638
8639 /**
8640 * @brief Get actual polarity of the timer output.
8641 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
8642 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
8643 * @param HRTIMx High Resolution Timer instance
8644 * @param Output This parameter can be one of the following values:
8645 * @arg @ref LL_HRTIM_OUTPUT_TA1
8646 * @arg @ref LL_HRTIM_OUTPUT_TA2
8647 * @arg @ref LL_HRTIM_OUTPUT_TB1
8648 * @arg @ref LL_HRTIM_OUTPUT_TB2
8649 * @arg @ref LL_HRTIM_OUTPUT_TC1
8650 * @arg @ref LL_HRTIM_OUTPUT_TC2
8651 * @arg @ref LL_HRTIM_OUTPUT_TD1
8652 * @arg @ref LL_HRTIM_OUTPUT_TD2
8653 * @arg @ref LL_HRTIM_OUTPUT_TE1
8654 * @arg @ref LL_HRTIM_OUTPUT_TE2
8655 * @arg @ref LL_HRTIM_OUTPUT_TF1
8656 * @arg @ref LL_HRTIM_OUTPUT_TF2
8657 * @retval Polarity This parameter can be one of the following values:
8658 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
8659 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8660 */
LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Output)8661 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
8662 {
8663 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8664 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8665 REG_OFFSET_TAB_OUTxR[iOutput]));
8666 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8667 }
8668
8669 /**
8670 * @brief Set the output IDLE mode.
8671 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
8672 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
8673 * @note This function must not be called when the burst mode is active
8674 * @param HRTIMx High Resolution Timer instance
8675 * @param Output This parameter can be one of the following values:
8676 * @arg @ref LL_HRTIM_OUTPUT_TA1
8677 * @arg @ref LL_HRTIM_OUTPUT_TA2
8678 * @arg @ref LL_HRTIM_OUTPUT_TB1
8679 * @arg @ref LL_HRTIM_OUTPUT_TB2
8680 * @arg @ref LL_HRTIM_OUTPUT_TC1
8681 * @arg @ref LL_HRTIM_OUTPUT_TC2
8682 * @arg @ref LL_HRTIM_OUTPUT_TD1
8683 * @arg @ref LL_HRTIM_OUTPUT_TD2
8684 * @arg @ref LL_HRTIM_OUTPUT_TE1
8685 * @arg @ref LL_HRTIM_OUTPUT_TE2
8686 * @arg @ref LL_HRTIM_OUTPUT_TF1
8687 * @arg @ref LL_HRTIM_OUTPUT_TF2
8688 * @param IdleMode This parameter can be one of the following values:
8689 * @arg @ref LL_HRTIM_OUT_NO_IDLE
8690 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8691 * @retval None
8692 */
LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleMode)8693 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
8694 {
8695 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8696 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8697 REG_OFFSET_TAB_OUTxR[iOutput]));
8698 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
8699 }
8700
8701 /**
8702 * @brief Get actual output IDLE mode.
8703 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
8704 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
8705 * @param HRTIMx High Resolution Timer instance
8706 * @param Output This parameter can be one of the following values:
8707 * @arg @ref LL_HRTIM_OUTPUT_TA1
8708 * @arg @ref LL_HRTIM_OUTPUT_TA2
8709 * @arg @ref LL_HRTIM_OUTPUT_TB1
8710 * @arg @ref LL_HRTIM_OUTPUT_TB2
8711 * @arg @ref LL_HRTIM_OUTPUT_TC1
8712 * @arg @ref LL_HRTIM_OUTPUT_TC2
8713 * @arg @ref LL_HRTIM_OUTPUT_TD1
8714 * @arg @ref LL_HRTIM_OUTPUT_TD2
8715 * @arg @ref LL_HRTIM_OUTPUT_TE1
8716 * @arg @ref LL_HRTIM_OUTPUT_TE2
8717 * @arg @ref LL_HRTIM_OUTPUT_TF1
8718 * @arg @ref LL_HRTIM_OUTPUT_TF2
8719 * @retval IdleMode This parameter can be one of the following values:
8720 * @arg @ref LL_HRTIM_OUT_NO_IDLE
8721 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8722 */
LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)8723 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
8724 {
8725 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8726 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8727 REG_OFFSET_TAB_OUTxR[iOutput]));
8728 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8729 }
8730
8731 /**
8732 * @brief Set the output IDLE level.
8733 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
8734 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
8735 * @note This function must be called prior enabling the timer.
8736 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
8737 * @param HRTIMx High Resolution Timer instance
8738 * @param Output This parameter can be one of the following values:
8739 * @arg @ref LL_HRTIM_OUTPUT_TA1
8740 * @arg @ref LL_HRTIM_OUTPUT_TA2
8741 * @arg @ref LL_HRTIM_OUTPUT_TB1
8742 * @arg @ref LL_HRTIM_OUTPUT_TB2
8743 * @arg @ref LL_HRTIM_OUTPUT_TC1
8744 * @arg @ref LL_HRTIM_OUTPUT_TC2
8745 * @arg @ref LL_HRTIM_OUTPUT_TD1
8746 * @arg @ref LL_HRTIM_OUTPUT_TD2
8747 * @arg @ref LL_HRTIM_OUTPUT_TE1
8748 * @arg @ref LL_HRTIM_OUTPUT_TE2
8749 * @arg @ref LL_HRTIM_OUTPUT_TF1
8750 * @arg @ref LL_HRTIM_OUTPUT_TF2
8751 * @param IdleLevel This parameter can be one of the following values:
8752 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
8753 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8754 * @retval None
8755 */
LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleLevel)8756 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
8757 {
8758 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8759 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8760 REG_OFFSET_TAB_OUTxR[iOutput]));
8761 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
8762 }
8763
8764 /**
8765 * @brief Get actual output IDLE level.
8766 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
8767 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
8768 * @param HRTIMx High Resolution Timer instance
8769 * @param Output This parameter can be one of the following values:
8770 * @arg @ref LL_HRTIM_OUTPUT_TA1
8771 * @arg @ref LL_HRTIM_OUTPUT_TA2
8772 * @arg @ref LL_HRTIM_OUTPUT_TB1
8773 * @arg @ref LL_HRTIM_OUTPUT_TB2
8774 * @arg @ref LL_HRTIM_OUTPUT_TC1
8775 * @arg @ref LL_HRTIM_OUTPUT_TC2
8776 * @arg @ref LL_HRTIM_OUTPUT_TD1
8777 * @arg @ref LL_HRTIM_OUTPUT_TD2
8778 * @arg @ref LL_HRTIM_OUTPUT_TE1
8779 * @arg @ref LL_HRTIM_OUTPUT_TE2
8780 * @arg @ref LL_HRTIM_OUTPUT_TF1
8781 * @arg @ref LL_HRTIM_OUTPUT_TF2
8782 * @retval IdleLevel This parameter can be one of the following values:
8783 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
8784 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8785 */
LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef * HRTIMx,uint32_t Output)8786 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
8787 {
8788 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8789 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8790 REG_OFFSET_TAB_OUTxR[iOutput]));
8791 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8792 }
8793
8794 /**
8795 * @brief Set the output FAULT state.
8796 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
8797 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
8798 * @note This function must not called when the timer is enabled and a fault
8799 * channel is enabled at timer level.
8800 * @param HRTIMx High Resolution Timer instance
8801 * @param Output This parameter can be one of the following values:
8802 * @arg @ref LL_HRTIM_OUTPUT_TA1
8803 * @arg @ref LL_HRTIM_OUTPUT_TA2
8804 * @arg @ref LL_HRTIM_OUTPUT_TB1
8805 * @arg @ref LL_HRTIM_OUTPUT_TB2
8806 * @arg @ref LL_HRTIM_OUTPUT_TC1
8807 * @arg @ref LL_HRTIM_OUTPUT_TC2
8808 * @arg @ref LL_HRTIM_OUTPUT_TD1
8809 * @arg @ref LL_HRTIM_OUTPUT_TD2
8810 * @arg @ref LL_HRTIM_OUTPUT_TE1
8811 * @arg @ref LL_HRTIM_OUTPUT_TE2
8812 * @arg @ref LL_HRTIM_OUTPUT_TF1
8813 * @arg @ref LL_HRTIM_OUTPUT_TF2
8814 * @param FaultState This parameter can be one of the following values:
8815 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
8816 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
8817 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
8818 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8819 * @retval None
8820 */
LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t FaultState)8821 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
8822 {
8823 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8824 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8825 REG_OFFSET_TAB_OUTxR[iOutput]));
8826 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
8827 }
8828
8829 /**
8830 * @brief Get actual FAULT state.
8831 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
8832 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
8833 * @param HRTIMx High Resolution Timer instance
8834 * @param Output This parameter can be one of the following values:
8835 * @arg @ref LL_HRTIM_OUTPUT_TA1
8836 * @arg @ref LL_HRTIM_OUTPUT_TA2
8837 * @arg @ref LL_HRTIM_OUTPUT_TB1
8838 * @arg @ref LL_HRTIM_OUTPUT_TB2
8839 * @arg @ref LL_HRTIM_OUTPUT_TC1
8840 * @arg @ref LL_HRTIM_OUTPUT_TC2
8841 * @arg @ref LL_HRTIM_OUTPUT_TD1
8842 * @arg @ref LL_HRTIM_OUTPUT_TD2
8843 * @arg @ref LL_HRTIM_OUTPUT_TE1
8844 * @arg @ref LL_HRTIM_OUTPUT_TE2
8845 * @arg @ref LL_HRTIM_OUTPUT_TF1
8846 * @arg @ref LL_HRTIM_OUTPUT_TF2
8847 * @retval FaultState This parameter can be one of the following values:
8848 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
8849 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
8850 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
8851 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8852 */
LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef * HRTIMx,uint32_t Output)8853 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
8854 {
8855 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8856 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8857 REG_OFFSET_TAB_OUTxR[iOutput]));
8858 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8859 }
8860
8861 /**
8862 * @brief Set the output chopper mode.
8863 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
8864 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
8865 * @note This function must not called when the timer is enabled.
8866 * @param HRTIMx High Resolution Timer instance
8867 * @param Output This parameter can be one of the following values:
8868 * @arg @ref LL_HRTIM_OUTPUT_TA1
8869 * @arg @ref LL_HRTIM_OUTPUT_TA2
8870 * @arg @ref LL_HRTIM_OUTPUT_TB1
8871 * @arg @ref LL_HRTIM_OUTPUT_TB2
8872 * @arg @ref LL_HRTIM_OUTPUT_TC1
8873 * @arg @ref LL_HRTIM_OUTPUT_TC2
8874 * @arg @ref LL_HRTIM_OUTPUT_TD1
8875 * @arg @ref LL_HRTIM_OUTPUT_TD2
8876 * @arg @ref LL_HRTIM_OUTPUT_TE1
8877 * @arg @ref LL_HRTIM_OUTPUT_TE2
8878 * @arg @ref LL_HRTIM_OUTPUT_TF1
8879 * @arg @ref LL_HRTIM_OUTPUT_TF2
8880 * @param ChopperMode This parameter can be one of the following values:
8881 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
8882 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8883 * @retval None
8884 */
LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ChopperMode)8885 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
8886 {
8887 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8888 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8889 REG_OFFSET_TAB_OUTxR[iOutput]));
8890 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
8891 }
8892
8893 /**
8894 * @brief Get actual output chopper mode
8895 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
8896 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
8897 * @param HRTIMx High Resolution Timer instance
8898 * @param Output This parameter can be one of the following values:
8899 * @arg @ref LL_HRTIM_OUTPUT_TA1
8900 * @arg @ref LL_HRTIM_OUTPUT_TA2
8901 * @arg @ref LL_HRTIM_OUTPUT_TB1
8902 * @arg @ref LL_HRTIM_OUTPUT_TB2
8903 * @arg @ref LL_HRTIM_OUTPUT_TC1
8904 * @arg @ref LL_HRTIM_OUTPUT_TC2
8905 * @arg @ref LL_HRTIM_OUTPUT_TD1
8906 * @arg @ref LL_HRTIM_OUTPUT_TD2
8907 * @arg @ref LL_HRTIM_OUTPUT_TE1
8908 * @arg @ref LL_HRTIM_OUTPUT_TE2
8909 * @arg @ref LL_HRTIM_OUTPUT_TF1
8910 * @arg @ref LL_HRTIM_OUTPUT_TF2
8911 * @retval ChopperMode This parameter can be one of the following values:
8912 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
8913 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8914 */
LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)8915 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
8916 {
8917 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8918 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8919 REG_OFFSET_TAB_OUTxR[iOutput]));
8920 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8921 }
8922
8923 /**
8924 * @brief Set the output burst mode entry mode.
8925 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
8926 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
8927 * @note This function must not called when the timer is enabled.
8928 * @param HRTIMx High Resolution Timer instance
8929 * @param Output This parameter can be one of the following values:
8930 * @arg @ref LL_HRTIM_OUTPUT_TA1
8931 * @arg @ref LL_HRTIM_OUTPUT_TA2
8932 * @arg @ref LL_HRTIM_OUTPUT_TB1
8933 * @arg @ref LL_HRTIM_OUTPUT_TB2
8934 * @arg @ref LL_HRTIM_OUTPUT_TC1
8935 * @arg @ref LL_HRTIM_OUTPUT_TC2
8936 * @arg @ref LL_HRTIM_OUTPUT_TD1
8937 * @arg @ref LL_HRTIM_OUTPUT_TD2
8938 * @arg @ref LL_HRTIM_OUTPUT_TE1
8939 * @arg @ref LL_HRTIM_OUTPUT_TE2
8940 * @arg @ref LL_HRTIM_OUTPUT_TF1
8941 * @arg @ref LL_HRTIM_OUTPUT_TF2
8942 * @param BMEntryMode This parameter can be one of the following values:
8943 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
8944 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8945 * @retval None
8946 */
LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t BMEntryMode)8947 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
8948 {
8949 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8950 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8951 REG_OFFSET_TAB_OUTxR[iOutput]));
8952 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
8953 }
8954
8955 /**
8956 * @brief Get actual output burst mode entry mode.
8957 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
8958 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
8959 * @param HRTIMx High Resolution Timer instance
8960 * @param Output This parameter can be one of the following values:
8961 * @arg @ref LL_HRTIM_OUTPUT_TA1
8962 * @arg @ref LL_HRTIM_OUTPUT_TA2
8963 * @arg @ref LL_HRTIM_OUTPUT_TB1
8964 * @arg @ref LL_HRTIM_OUTPUT_TB2
8965 * @arg @ref LL_HRTIM_OUTPUT_TC1
8966 * @arg @ref LL_HRTIM_OUTPUT_TC2
8967 * @arg @ref LL_HRTIM_OUTPUT_TD1
8968 * @arg @ref LL_HRTIM_OUTPUT_TD2
8969 * @arg @ref LL_HRTIM_OUTPUT_TE1
8970 * @arg @ref LL_HRTIM_OUTPUT_TE2
8971 * @arg @ref LL_HRTIM_OUTPUT_TF1
8972 * @arg @ref LL_HRTIM_OUTPUT_TF2
8973 * @retval BMEntryMode This parameter can be one of the following values:
8974 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
8975 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8976 */
LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)8977 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
8978 {
8979 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8980 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8981 REG_OFFSET_TAB_OUTxR[iOutput]));
8982 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8983 }
8984
8985 /**
8986 * @brief Get the level (active or inactive) of the designated output when the
8987 * delayed protection was triggered.
8988 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
8989 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
8990 * @param HRTIMx High Resolution Timer instance
8991 * @param Output This parameter can be one of the following values:
8992 * @arg @ref LL_HRTIM_OUTPUT_TA1
8993 * @arg @ref LL_HRTIM_OUTPUT_TA2
8994 * @arg @ref LL_HRTIM_OUTPUT_TB1
8995 * @arg @ref LL_HRTIM_OUTPUT_TB2
8996 * @arg @ref LL_HRTIM_OUTPUT_TC1
8997 * @arg @ref LL_HRTIM_OUTPUT_TC2
8998 * @arg @ref LL_HRTIM_OUTPUT_TD1
8999 * @arg @ref LL_HRTIM_OUTPUT_TD2
9000 * @arg @ref LL_HRTIM_OUTPUT_TE1
9001 * @arg @ref LL_HRTIM_OUTPUT_TE2
9002 * @arg @ref LL_HRTIM_OUTPUT_TF1
9003 * @arg @ref LL_HRTIM_OUTPUT_TF2
9004 * @retval OutputLevel This parameter can be one of the following values:
9005 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9006 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9007 */
LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Output)9008 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
9009 {
9010 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9011 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
9012 REG_OFFSET_TAB_OUTxR[iOutput]));
9013 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
9014 HRTIM_TIMISR_O1STAT_Pos);
9015 }
9016
9017 /**
9018 * @brief Force the timer output to its active or inactive level.
9019 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
9020 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
9021 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
9022 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
9023 * @param HRTIMx High Resolution Timer instance
9024 * @param Output This parameter can be one of the following values:
9025 * @arg @ref LL_HRTIM_OUTPUT_TA1
9026 * @arg @ref LL_HRTIM_OUTPUT_TA2
9027 * @arg @ref LL_HRTIM_OUTPUT_TB1
9028 * @arg @ref LL_HRTIM_OUTPUT_TB2
9029 * @arg @ref LL_HRTIM_OUTPUT_TC1
9030 * @arg @ref LL_HRTIM_OUTPUT_TC2
9031 * @arg @ref LL_HRTIM_OUTPUT_TD1
9032 * @arg @ref LL_HRTIM_OUTPUT_TD2
9033 * @arg @ref LL_HRTIM_OUTPUT_TE1
9034 * @arg @ref LL_HRTIM_OUTPUT_TE2
9035 * @arg @ref LL_HRTIM_OUTPUT_TF1
9036 * @arg @ref LL_HRTIM_OUTPUT_TF2
9037 * @param OutputLevel This parameter can be one of the following values:
9038 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9039 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9040 * @retval None
9041 */
LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t OutputLevel)9042 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
9043 {
9044 const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
9045 {
9046 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
9047 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
9048 };
9049
9050 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9051 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
9052 REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
9053 SET_BIT(*pReg, HRTIM_SET1R_SST);
9054 }
9055
9056 /**
9057 * @brief Get actual output level, before the output stage (chopper, polarity).
9058 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
9059 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
9060 * @param HRTIMx High Resolution Timer instance
9061 * @param Output This parameter can be one of the following values:
9062 * @arg @ref LL_HRTIM_OUTPUT_TA1
9063 * @arg @ref LL_HRTIM_OUTPUT_TA2
9064 * @arg @ref LL_HRTIM_OUTPUT_TB1
9065 * @arg @ref LL_HRTIM_OUTPUT_TB2
9066 * @arg @ref LL_HRTIM_OUTPUT_TC1
9067 * @arg @ref LL_HRTIM_OUTPUT_TC2
9068 * @arg @ref LL_HRTIM_OUTPUT_TD1
9069 * @arg @ref LL_HRTIM_OUTPUT_TD2
9070 * @arg @ref LL_HRTIM_OUTPUT_TE1
9071 * @arg @ref LL_HRTIM_OUTPUT_TE2
9072 * @arg @ref LL_HRTIM_OUTPUT_TF1
9073 * @arg @ref LL_HRTIM_OUTPUT_TF2
9074 * @retval OutputLevel This parameter can be one of the following values:
9075 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9076 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9077 */
LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef * HRTIMx,uint32_t Output)9078 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
9079 {
9080 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9081 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
9082 REG_OFFSET_TAB_OUTxR[iOutput]));
9083 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
9084 HRTIM_TIMISR_O1CPY_Pos);
9085 }
9086
9087 /**
9088 * @}
9089 */
9090
9091 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
9092 * @{
9093 */
9094
9095 /**
9096 * @brief Configure external event conditioning.
9097 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
9098 * EECR1 EE1POL LL_HRTIM_EE_Config\n
9099 * EECR1 EE1SNS LL_HRTIM_EE_Config\n
9100 * EECR1 EE1FAST LL_HRTIM_EE_Config\n
9101 * EECR1 EE2SRC LL_HRTIM_EE_Config\n
9102 * EECR1 EE2POL LL_HRTIM_EE_Config\n
9103 * EECR1 EE2SNS LL_HRTIM_EE_Config\n
9104 * EECR1 EE2FAST LL_HRTIM_EE_Config\n
9105 * EECR1 EE3SRC LL_HRTIM_EE_Config\n
9106 * EECR1 EE3POL LL_HRTIM_EE_Config\n
9107 * EECR1 EE3SNS LL_HRTIM_EE_Config\n
9108 * EECR1 EE3FAST LL_HRTIM_EE_Config\n
9109 * EECR1 EE4SRC LL_HRTIM_EE_Config\n
9110 * EECR1 EE4POL LL_HRTIM_EE_Config\n
9111 * EECR1 EE4SNS LL_HRTIM_EE_Config\n
9112 * EECR1 EE4FAST LL_HRTIM_EE_Config\n
9113 * EECR1 EE5SRC LL_HRTIM_EE_Config\n
9114 * EECR1 EE5POL LL_HRTIM_EE_Config\n
9115 * EECR1 EE5SNS LL_HRTIM_EE_Config\n
9116 * EECR1 EE5FAST LL_HRTIM_EE_Config\n
9117 * EECR2 EE6SRC LL_HRTIM_EE_Config\n
9118 * EECR2 EE6POL LL_HRTIM_EE_Config\n
9119 * EECR2 EE6SNS LL_HRTIM_EE_Config\n
9120 * EECR2 EE6FAST LL_HRTIM_EE_Config\n
9121 * EECR2 EE7SRC LL_HRTIM_EE_Config\n
9122 * EECR2 EE7POL LL_HRTIM_EE_Config\n
9123 * EECR2 EE7SNS LL_HRTIM_EE_Config\n
9124 * EECR2 EE7FAST LL_HRTIM_EE_Config\n
9125 * EECR2 EE8SRC LL_HRTIM_EE_Config\n
9126 * EECR2 EE8POL LL_HRTIM_EE_Config\n
9127 * EECR2 EE8SNS LL_HRTIM_EE_Config\n
9128 * EECR2 EE8FAST LL_HRTIM_EE_Config\n
9129 * EECR2 EE9SRC LL_HRTIM_EE_Config\n
9130 * EECR2 EE9POL LL_HRTIM_EE_Config\n
9131 * EECR2 EE9SNS LL_HRTIM_EE_Config\n
9132 * EECR2 EE9FAST LL_HRTIM_EE_Config\n
9133 * EECR2 EE10SRC LL_HRTIM_EE_Config\n
9134 * EECR2 EE10POL LL_HRTIM_EE_Config\n
9135 * EECR2 EE10SNS LL_HRTIM_EE_Config\n
9136 * EECR2 EE10FAST LL_HRTIM_EE_Config
9137 * @note This function must not be called when the timer counter is enabled.
9138 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
9139 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
9140 * @param HRTIMx High Resolution Timer instance
9141 * @param Event This parameter can be one of the following values:
9142 * @arg @ref LL_HRTIM_EVENT_1
9143 * @arg @ref LL_HRTIM_EVENT_2
9144 * @arg @ref LL_HRTIM_EVENT_3
9145 * @arg @ref LL_HRTIM_EVENT_4
9146 * @arg @ref LL_HRTIM_EVENT_5
9147 * @arg @ref LL_HRTIM_EVENT_6
9148 * @arg @ref LL_HRTIM_EVENT_7
9149 * @arg @ref LL_HRTIM_EVENT_8
9150 * @arg @ref LL_HRTIM_EVENT_9
9151 * @arg @ref LL_HRTIM_EVENT_10
9152 * @param Configuration This parameter must be a combination of all the following values:
9153 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
9154 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
9155 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9156 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
9157 * @retval None
9158 */
LL_HRTIM_EE_Config(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Configuration)9159 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
9160 {
9161 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9162 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9163 REG_OFFSET_TAB_EECR[iEvent]));
9164 MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
9165 (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
9166 }
9167
9168 /**
9169 * @brief Set the external event source.
9170 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
9171 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
9172 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
9173 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
9174 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
9175 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
9176 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
9177 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
9178 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
9179 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
9180 * @param HRTIMx High Resolution Timer instance
9181 * @param Event This parameter can be one of the following values:
9182 * @arg @ref LL_HRTIM_EVENT_1
9183 * @arg @ref LL_HRTIM_EVENT_2
9184 * @arg @ref LL_HRTIM_EVENT_3
9185 * @arg @ref LL_HRTIM_EVENT_4
9186 * @arg @ref LL_HRTIM_EVENT_5
9187 * @arg @ref LL_HRTIM_EVENT_6
9188 * @arg @ref LL_HRTIM_EVENT_7
9189 * @arg @ref LL_HRTIM_EVENT_8
9190 * @arg @ref LL_HRTIM_EVENT_9
9191 * @arg @ref LL_HRTIM_EVENT_10
9192 * @param Src This parameter can be one of the following values:
9193 * @arg External event source 1
9194 * @arg External event source 2
9195 * @arg External event source 3
9196 * @arg External event source 4
9197 * @retval None
9198 */
LL_HRTIM_EE_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Src)9199 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
9200 {
9201 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9202 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9203 REG_OFFSET_TAB_EECR[iEvent]));
9204 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
9205 }
9206
9207 /**
9208 * @brief Get actual external event source.
9209 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
9210 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
9211 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
9212 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
9213 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
9214 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
9215 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
9216 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
9217 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
9218 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
9219 * @param HRTIMx High Resolution Timer instance
9220 * @param Event This parameter can be one of the following values:
9221 * @arg @ref LL_HRTIM_EVENT_1
9222 * @arg @ref LL_HRTIM_EVENT_2
9223 * @arg @ref LL_HRTIM_EVENT_3
9224 * @arg @ref LL_HRTIM_EVENT_4
9225 * @arg @ref LL_HRTIM_EVENT_5
9226 * @arg @ref LL_HRTIM_EVENT_6
9227 * @arg @ref LL_HRTIM_EVENT_7
9228 * @arg @ref LL_HRTIM_EVENT_8
9229 * @arg @ref LL_HRTIM_EVENT_9
9230 * @arg @ref LL_HRTIM_EVENT_10
9231 * @retval EventSrc This parameter can be one of the following values:
9232 * @arg External event source 1
9233 * @arg External event source 2
9234 * @arg External event source 3
9235 * @arg External event source 4
9236 */
LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Event)9237 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
9238 {
9239 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9240 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9241 REG_OFFSET_TAB_EECR[iEvent]));
9242 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9243 }
9244
9245 /**
9246 * @brief Set the polarity of an external event.
9247 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
9248 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
9249 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
9250 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
9251 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
9252 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
9253 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
9254 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
9255 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
9256 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
9257 * @note This function must not be called when the timer counter is enabled.
9258 * @note Event polarity is only significant when event detection is level-sensitive.
9259 * @param HRTIMx High Resolution Timer instance
9260 * @param Event This parameter can be one of the following values:
9261 * @arg @ref LL_HRTIM_EVENT_1
9262 * @arg @ref LL_HRTIM_EVENT_2
9263 * @arg @ref LL_HRTIM_EVENT_3
9264 * @arg @ref LL_HRTIM_EVENT_4
9265 * @arg @ref LL_HRTIM_EVENT_5
9266 * @arg @ref LL_HRTIM_EVENT_6
9267 * @arg @ref LL_HRTIM_EVENT_7
9268 * @arg @ref LL_HRTIM_EVENT_8
9269 * @arg @ref LL_HRTIM_EVENT_9
9270 * @arg @ref LL_HRTIM_EVENT_10
9271 * @param Polarity This parameter can be one of the following values:
9272 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
9273 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
9274 * @retval None
9275 */
LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Polarity)9276 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
9277 {
9278 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9279 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9280 REG_OFFSET_TAB_EECR[iEvent]));
9281 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
9282 }
9283
9284 /**
9285 * @brief Get actual polarity setting of an external event.
9286 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
9287 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
9288 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
9289 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
9290 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
9291 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
9292 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
9293 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
9294 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
9295 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
9296 * @param HRTIMx High Resolution Timer instance
9297 * @param Event This parameter can be one of the following values:
9298 * @arg @ref LL_HRTIM_EVENT_1
9299 * @arg @ref LL_HRTIM_EVENT_2
9300 * @arg @ref LL_HRTIM_EVENT_3
9301 * @arg @ref LL_HRTIM_EVENT_4
9302 * @arg @ref LL_HRTIM_EVENT_5
9303 * @arg @ref LL_HRTIM_EVENT_6
9304 * @arg @ref LL_HRTIM_EVENT_7
9305 * @arg @ref LL_HRTIM_EVENT_8
9306 * @arg @ref LL_HRTIM_EVENT_9
9307 * @arg @ref LL_HRTIM_EVENT_10
9308 * @retval Polarity This parameter can be one of the following values:
9309 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
9310 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
9311 */
LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Event)9312 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
9313 {
9314 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9315 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9316 REG_OFFSET_TAB_EECR[iEvent]));
9317 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9318 }
9319
9320 /**
9321 * @brief Set the sensitivity of an external event.
9322 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
9323 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
9324 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
9325 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
9326 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
9327 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
9328 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
9329 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
9330 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
9331 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
9332 * @param HRTIMx High Resolution Timer instance
9333 * @param Event This parameter can be one of the following values:
9334 * @arg @ref LL_HRTIM_EVENT_1
9335 * @arg @ref LL_HRTIM_EVENT_2
9336 * @arg @ref LL_HRTIM_EVENT_3
9337 * @arg @ref LL_HRTIM_EVENT_4
9338 * @arg @ref LL_HRTIM_EVENT_5
9339 * @arg @ref LL_HRTIM_EVENT_6
9340 * @arg @ref LL_HRTIM_EVENT_7
9341 * @arg @ref LL_HRTIM_EVENT_8
9342 * @arg @ref LL_HRTIM_EVENT_9
9343 * @arg @ref LL_HRTIM_EVENT_10
9344 * @param Sensitivity This parameter can be one of the following values:
9345 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
9346 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
9347 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
9348 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9349 * @retval None
9350 */
9351
LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Sensitivity)9352 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
9353 {
9354 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9355 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9356 REG_OFFSET_TAB_EECR[iEvent]));
9357 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
9358 }
9359
9360 /**
9361 * @brief Get actual sensitivity setting of an external event.
9362 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
9363 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
9364 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
9365 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
9366 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
9367 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
9368 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
9369 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
9370 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
9371 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
9372 * @param HRTIMx High Resolution Timer instance
9373 * @param Event This parameter can be one of the following values:
9374 * @arg @ref LL_HRTIM_EVENT_1
9375 * @arg @ref LL_HRTIM_EVENT_2
9376 * @arg @ref LL_HRTIM_EVENT_3
9377 * @arg @ref LL_HRTIM_EVENT_4
9378 * @arg @ref LL_HRTIM_EVENT_5
9379 * @arg @ref LL_HRTIM_EVENT_6
9380 * @arg @ref LL_HRTIM_EVENT_7
9381 * @arg @ref LL_HRTIM_EVENT_8
9382 * @arg @ref LL_HRTIM_EVENT_9
9383 * @arg @ref LL_HRTIM_EVENT_10
9384 * @retval Polarity This parameter can be one of the following values:
9385 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
9386 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
9387 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
9388 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9389 */
LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef * HRTIMx,uint32_t Event)9390 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
9391 {
9392 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9393 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9394 REG_OFFSET_TAB_EECR[iEvent]));
9395 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9396 }
9397
9398 /**
9399 * @brief Set the fast mode of an external event.
9400 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
9401 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
9402 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
9403 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
9404 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
9405 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
9406 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
9407 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
9408 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
9409 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
9410 * @note This function must not be called when the timer counter is enabled.
9411 * @param HRTIMx High Resolution Timer instance
9412 * @param Event This parameter can be one of the following values:
9413 * @arg @ref LL_HRTIM_EVENT_1
9414 * @arg @ref LL_HRTIM_EVENT_2
9415 * @arg @ref LL_HRTIM_EVENT_3
9416 * @arg @ref LL_HRTIM_EVENT_4
9417 * @arg @ref LL_HRTIM_EVENT_5
9418 * @param FastMode This parameter can be one of the following values:
9419 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
9420 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
9421 * @retval None
9422 */
LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t FastMode)9423 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
9424 {
9425 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9426 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9427 REG_OFFSET_TAB_EECR[iEvent]));
9428 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
9429 }
9430
9431 /**
9432 * @brief Get actual fast mode setting of an external event.
9433 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
9434 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
9435 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
9436 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
9437 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
9438 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
9439 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
9440 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
9441 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
9442 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
9443 * @param HRTIMx High Resolution Timer instance
9444 * @param Event This parameter can be one of the following values:
9445 * @arg @ref LL_HRTIM_EVENT_1
9446 * @arg @ref LL_HRTIM_EVENT_2
9447 * @arg @ref LL_HRTIM_EVENT_3
9448 * @arg @ref LL_HRTIM_EVENT_4
9449 * @arg @ref LL_HRTIM_EVENT_5
9450 * @retval FastMode This parameter can be one of the following values:
9451 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
9452 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
9453 */
LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef * HRTIMx,uint32_t Event)9454 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
9455 {
9456 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9457 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9458 REG_OFFSET_TAB_EECR[iEvent]));
9459 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9460 }
9461
9462 /**
9463 * @brief Set the digital noise filter of a external event.
9464 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
9465 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
9466 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
9467 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
9468 * EECR3 EE10F LL_HRTIM_EE_SetFilter
9469 * @param HRTIMx High Resolution Timer instance
9470 * @param Event This parameter can be one of the following values:
9471 * @arg @ref LL_HRTIM_EVENT_6
9472 * @arg @ref LL_HRTIM_EVENT_7
9473 * @arg @ref LL_HRTIM_EVENT_8
9474 * @arg @ref LL_HRTIM_EVENT_9
9475 * @arg @ref LL_HRTIM_EVENT_10
9476 * @param Filter This parameter can be one of the following values:
9477 * @arg @ref LL_HRTIM_EE_FILTER_NONE
9478 * @arg @ref LL_HRTIM_EE_FILTER_1
9479 * @arg @ref LL_HRTIM_EE_FILTER_2
9480 * @arg @ref LL_HRTIM_EE_FILTER_3
9481 * @arg @ref LL_HRTIM_EE_FILTER_4
9482 * @arg @ref LL_HRTIM_EE_FILTER_5
9483 * @arg @ref LL_HRTIM_EE_FILTER_6
9484 * @arg @ref LL_HRTIM_EE_FILTER_7
9485 * @arg @ref LL_HRTIM_EE_FILTER_8
9486 * @arg @ref LL_HRTIM_EE_FILTER_9
9487 * @arg @ref LL_HRTIM_EE_FILTER_10
9488 * @arg @ref LL_HRTIM_EE_FILTER_11
9489 * @arg @ref LL_HRTIM_EE_FILTER_12
9490 * @arg @ref LL_HRTIM_EE_FILTER_13
9491 * @arg @ref LL_HRTIM_EE_FILTER_14
9492 * @arg @ref LL_HRTIM_EE_FILTER_15
9493 * @retval None
9494 */
LL_HRTIM_EE_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Filter)9495 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
9496 {
9497 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9498 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
9499 (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
9500 }
9501
9502 /**
9503 * @brief Get actual digital noise filter setting of a external event.
9504 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
9505 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
9506 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
9507 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
9508 * EECR3 EE10F LL_HRTIM_EE_GetFilter
9509 * @param HRTIMx High Resolution Timer instance
9510 * @param Event This parameter can be one of the following values:
9511 * @arg @ref LL_HRTIM_EVENT_6
9512 * @arg @ref LL_HRTIM_EVENT_7
9513 * @arg @ref LL_HRTIM_EVENT_8
9514 * @arg @ref LL_HRTIM_EVENT_9
9515 * @arg @ref LL_HRTIM_EVENT_10
9516 * @retval Filter This parameter can be one of the following values:
9517 * @arg @ref LL_HRTIM_EE_FILTER_NONE
9518 * @arg @ref LL_HRTIM_EE_FILTER_1
9519 * @arg @ref LL_HRTIM_EE_FILTER_2
9520 * @arg @ref LL_HRTIM_EE_FILTER_3
9521 * @arg @ref LL_HRTIM_EE_FILTER_4
9522 * @arg @ref LL_HRTIM_EE_FILTER_5
9523 * @arg @ref LL_HRTIM_EE_FILTER_6
9524 * @arg @ref LL_HRTIM_EE_FILTER_7
9525 * @arg @ref LL_HRTIM_EE_FILTER_8
9526 * @arg @ref LL_HRTIM_EE_FILTER_9
9527 * @arg @ref LL_HRTIM_EE_FILTER_10
9528 * @arg @ref LL_HRTIM_EE_FILTER_11
9529 * @arg @ref LL_HRTIM_EE_FILTER_12
9530 * @arg @ref LL_HRTIM_EE_FILTER_13
9531 * @arg @ref LL_HRTIM_EE_FILTER_14
9532 * @arg @ref LL_HRTIM_EE_FILTER_15
9533 */
LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Event)9534 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
9535 {
9536 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
9537 return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
9538 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9539 }
9540
9541 /**
9542 * @brief Set the external event prescaler.
9543 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
9544 * @param HRTIMx High Resolution Timer instance
9545 * @param Prescaler This parameter can be one of the following values:
9546 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
9547 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
9548 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
9549 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
9550 * @retval None
9551 */
9552
LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)9553 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
9554 {
9555 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
9556 }
9557
9558 /**
9559 * @brief Get actual external event prescaler setting.
9560 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
9561 * @param HRTIMx High Resolution Timer instance
9562 * @retval Prescaler This parameter can be one of the following values:
9563 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
9564 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
9565 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
9566 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
9567 */
9568
LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef * HRTIMx)9569 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
9570 {
9571 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
9572 }
9573
9574 /**
9575 * @}
9576 */
9577
9578 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
9579 * @{
9580 */
9581 /**
9582 * @brief Configure fault signal conditioning Polarity and Source.
9583 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
9584 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
9585 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
9586 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
9587 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
9588 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
9589 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
9590 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
9591 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
9592 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config\n
9593 * FLTINR2 FLT6P LL_HRTIM_FLT_Config\n
9594 * FLTINR2 FLT6SRC LL_HRTIM_FLT_Config
9595 * @note This function must not be called when the fault channel is enabled.
9596 * @param HRTIMx High Resolution Timer instance
9597 * @param Fault This parameter can be one of the following values:
9598 * @arg @ref LL_HRTIM_FAULT_1
9599 * @arg @ref LL_HRTIM_FAULT_2
9600 * @arg @ref LL_HRTIM_FAULT_3
9601 * @arg @ref LL_HRTIM_FAULT_4
9602 * @arg @ref LL_HRTIM_FAULT_5
9603 * @arg @ref LL_HRTIM_FAULT_6
9604 * @param Configuration This parameter must be a combination of all the following values:
9605 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_EEVINPUT
9606 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
9607 * @retval None
9608 */
LL_HRTIM_FLT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Configuration)9609 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
9610 {
9611 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9612 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9613 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9614
9615 uint64_t cfg;
9616 uint64_t mask;
9617
9618 cfg = ((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_CONFIG_MASK) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9619 (((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
9620
9621 mask = ((uint64_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9622 ((uint64_t)(HRTIM_FLT_SRC_1_MASK) << 32U); /* this for SouRCe bit 1 */
9623
9624 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9625 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9626
9627 }
9628
9629 /**
9630 * @brief Set the source of a fault signal.
9631 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
9632 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
9633 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
9634 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
9635 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc\n
9636 * FLTINR2 FLT6SRC LL_HRTIM_FLT_SetSrc
9637 * @note This function must not be called when the fault channel is enabled.
9638 * @param HRTIMx High Resolution Timer instance
9639 * @param Fault This parameter can be one of the following values:
9640 * @arg @ref LL_HRTIM_FAULT_1
9641 * @arg @ref LL_HRTIM_FAULT_2
9642 * @arg @ref LL_HRTIM_FAULT_3
9643 * @arg @ref LL_HRTIM_FAULT_4
9644 * @arg @ref LL_HRTIM_FAULT_5
9645 * @arg @ref LL_HRTIM_FAULT_6
9646 * @param Src This parameter can be one of the following values:
9647 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
9648 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
9649 * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
9650 * @retval None
9651 */
LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Src)9652 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
9653 {
9654 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9655 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9656 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9657
9658 uint64_t cfg = ((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 bit */
9659 (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
9660 uint64_t mask = ((uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */
9661 (((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */
9662
9663 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9664 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9665 }
9666
9667 /**
9668 * @brief Get actual source of a fault signal.
9669 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
9670 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
9671 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
9672 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
9673 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc\n
9674 * FLTINR2 FLT6SRC LL_HRTIM_FLT_GetSrc
9675 * @param HRTIMx High Resolution Timer instance
9676 * @param Fault This parameter can be one of the following values:
9677 * @arg @ref LL_HRTIM_FAULT_1
9678 * @arg @ref LL_HRTIM_FAULT_2
9679 * @arg @ref LL_HRTIM_FAULT_3
9680 * @arg @ref LL_HRTIM_FAULT_4
9681 * @arg @ref LL_HRTIM_FAULT_5
9682 * @arg @ref LL_HRTIM_FAULT_6
9683 * @retval Source This parameter can be one of the following values:
9684 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
9685 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
9686 * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
9687 */
LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)9688 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9689 {
9690 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9691 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9692 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9693
9694 uint64_t Src0;
9695 uint32_t Src1;
9696 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9697
9698 /* this for SouRCe bit 1 */
9699 Src1 = READ_BIT(*pReg2, HRTIM_FLT_SRC_1_MASK) >> REG_SHIFT_TAB_FLTx[iFault] ;
9700 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT6SRC_0));
9701 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT4SRC_0));
9702
9703 /* this for SouRCe bit 0 */
9704 Src0 = (uint64_t)temp1 << 32U;
9705 Src0 |= (uint64_t)temp2;
9706 Src0 = (Src0 >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9707
9708 return ((uint32_t)(Src0 | Src1));
9709 }
9710
9711 /**
9712 * @brief Set the polarity of a fault signal.
9713 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
9714 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
9715 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
9716 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
9717 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity\n
9718 * FLTINR2 FLT6P LL_HRTIM_FLT_SetPolarity
9719 * @note This function must not be called when the fault channel is enabled.
9720 * @param HRTIMx High Resolution Timer instance
9721 * @param Fault This parameter can be one of the following values:
9722 * @arg @ref LL_HRTIM_FAULT_1
9723 * @arg @ref LL_HRTIM_FAULT_2
9724 * @arg @ref LL_HRTIM_FAULT_3
9725 * @arg @ref LL_HRTIM_FAULT_4
9726 * @arg @ref LL_HRTIM_FAULT_5
9727 * @arg @ref LL_HRTIM_FAULT_6
9728 * @param Polarity This parameter can be one of the following values:
9729 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
9730 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
9731 * @retval None
9732 */
LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Polarity)9733 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
9734 {
9735 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9736 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9737 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9738
9739 uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(HRTIM_FLTINR1_FLT1P)) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9740 uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1P) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9741
9742 /* for Polarity bit */
9743 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9744 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9745 }
9746
9747 /**
9748 * @brief Get actual polarity of a fault signal.
9749 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
9750 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
9751 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
9752 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
9753 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity\n
9754 * FLTINR2 FLT6P LL_HRTIM_FLT_GetPolarity
9755 * @param HRTIMx High Resolution Timer instance
9756 * @param Fault This parameter can be one of the following values:
9757 * @arg @ref LL_HRTIM_FAULT_1
9758 * @arg @ref LL_HRTIM_FAULT_2
9759 * @arg @ref LL_HRTIM_FAULT_3
9760 * @arg @ref LL_HRTIM_FAULT_4
9761 * @arg @ref LL_HRTIM_FAULT_5
9762 * @arg @ref LL_HRTIM_FAULT_6
9763 * @retval Polarity This parameter can be one of the following values:
9764 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
9765 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
9766 */
LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)9767 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9768 {
9769 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9770 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9771 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9772 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9773 uint64_t cfg;
9774
9775 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT6P));
9776 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT4P));
9777
9778 cfg = (uint64_t)temp1 << 32 ;
9779 cfg |= (uint64_t)temp2;
9780 cfg = (cfg >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9781
9782 return (uint32_t)(cfg);
9783
9784 }
9785
9786 /**
9787 * @brief Set the digital noise filter of a fault signal.
9788 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
9789 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
9790 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
9791 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
9792 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter\n
9793 * FLTINR2 FLT6F LL_HRTIM_FLT_SetFilter
9794 * @note This function must not be called when the fault channel is enabled.
9795 * @param HRTIMx High Resolution Timer instance
9796 * @param Fault This parameter can be one of the following values:
9797 * @arg @ref LL_HRTIM_FAULT_1
9798 * @arg @ref LL_HRTIM_FAULT_2
9799 * @arg @ref LL_HRTIM_FAULT_3
9800 * @arg @ref LL_HRTIM_FAULT_4
9801 * @arg @ref LL_HRTIM_FAULT_5
9802 * @arg @ref LL_HRTIM_FAULT_6
9803 * @param Filter This parameter can be one of the following values:
9804 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
9805 * @arg @ref LL_HRTIM_FLT_FILTER_1
9806 * @arg @ref LL_HRTIM_FLT_FILTER_2
9807 * @arg @ref LL_HRTIM_FLT_FILTER_3
9808 * @arg @ref LL_HRTIM_FLT_FILTER_4
9809 * @arg @ref LL_HRTIM_FLT_FILTER_5
9810 * @arg @ref LL_HRTIM_FLT_FILTER_6
9811 * @arg @ref LL_HRTIM_FLT_FILTER_7
9812 * @arg @ref LL_HRTIM_FLT_FILTER_8
9813 * @arg @ref LL_HRTIM_FLT_FILTER_9
9814 * @arg @ref LL_HRTIM_FLT_FILTER_10
9815 * @arg @ref LL_HRTIM_FLT_FILTER_11
9816 * @arg @ref LL_HRTIM_FLT_FILTER_12
9817 * @arg @ref LL_HRTIM_FLT_FILTER_13
9818 * @arg @ref LL_HRTIM_FLT_FILTER_14
9819 * @arg @ref LL_HRTIM_FLT_FILTER_15
9820 * @retval None
9821 */
LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Filter)9822 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
9823 {
9824 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9825 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9826 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9827
9828 uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for filter bits */
9829 uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9830
9831 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(flt));
9832 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(flt >> 32U));
9833 }
9834
9835 /**
9836 * @brief Get actual digital noise filter setting of a fault signal.
9837 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
9838 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
9839 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
9840 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
9841 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter\n
9842 * FLTINR2 FLT6F LL_HRTIM_FLT_GetFilter
9843 * @param HRTIMx High Resolution Timer instance
9844 * @param Fault This parameter can be one of the following values:
9845 * @arg @ref LL_HRTIM_FAULT_1
9846 * @arg @ref LL_HRTIM_FAULT_2
9847 * @arg @ref LL_HRTIM_FAULT_3
9848 * @arg @ref LL_HRTIM_FAULT_4
9849 * @arg @ref LL_HRTIM_FAULT_5
9850 * @arg @ref LL_HRTIM_FAULT_6
9851 * @retval Filter This parameter can be one of the following values:
9852 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
9853 * @arg @ref LL_HRTIM_FLT_FILTER_1
9854 * @arg @ref LL_HRTIM_FLT_FILTER_2
9855 * @arg @ref LL_HRTIM_FLT_FILTER_3
9856 * @arg @ref LL_HRTIM_FLT_FILTER_4
9857 * @arg @ref LL_HRTIM_FLT_FILTER_5
9858 * @arg @ref LL_HRTIM_FLT_FILTER_6
9859 * @arg @ref LL_HRTIM_FLT_FILTER_7
9860 * @arg @ref LL_HRTIM_FLT_FILTER_8
9861 * @arg @ref LL_HRTIM_FLT_FILTER_9
9862 * @arg @ref LL_HRTIM_FLT_FILTER_10
9863 * @arg @ref LL_HRTIM_FLT_FILTER_11
9864 * @arg @ref LL_HRTIM_FLT_FILTER_12
9865 * @arg @ref LL_HRTIM_FLT_FILTER_13
9866 * @arg @ref LL_HRTIM_FLT_FILTER_14
9867 * @arg @ref LL_HRTIM_FLT_FILTER_15
9868 */
LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)9869 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9870 {
9871 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9872 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9873 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9874 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9875 uint64_t flt;
9876 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT6F));
9877 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT4F));
9878
9879 flt = (uint64_t)temp1 << 32U;
9880 flt |= (uint64_t)temp2;
9881 flt = (flt >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9882
9883 return (uint32_t)(flt);
9884
9885 }
9886
9887 /**
9888 * @brief Set the fault circuitry prescaler.
9889 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
9890 * @param HRTIMx High Resolution Timer instance
9891 * @param Prescaler This parameter can be one of the following values:
9892 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
9893 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
9894 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
9895 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
9896 * @retval None
9897 */
LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)9898 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
9899 {
9900 MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
9901 }
9902
9903 /**
9904 * @brief Get actual fault circuitry prescaler setting.
9905 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
9906 * @param HRTIMx High Resolution Timer instance
9907 * @retval Prescaler This parameter can be one of the following values:
9908 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
9909 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
9910 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
9911 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
9912 */
LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef * HRTIMx)9913 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
9914 {
9915 return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
9916 }
9917
9918 /**
9919 * @brief Lock the fault signal conditioning settings.
9920 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
9921 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
9922 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
9923 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
9924 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock\n
9925 * FLTINR2 FLT6LCK LL_HRTIM_FLT_Lock
9926 * @param HRTIMx High Resolution Timer instance
9927 * @param Fault This parameter can be one of the following values:
9928 * @arg @ref LL_HRTIM_FAULT_1
9929 * @arg @ref LL_HRTIM_FAULT_2
9930 * @arg @ref LL_HRTIM_FAULT_3
9931 * @arg @ref LL_HRTIM_FAULT_4
9932 * @arg @ref LL_HRTIM_FAULT_5
9933 * @arg @ref LL_HRTIM_FAULT_6
9934 * @retval None
9935 */
LL_HRTIM_FLT_Lock(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9936 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9937 {
9938 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9939 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9940 REG_OFFSET_TAB_FLTINR[iFault]));
9941 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
9942 }
9943
9944 /**
9945 * @brief Enable the fault circuitry for the designated fault input.
9946 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
9947 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
9948 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
9949 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
9950 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable\n
9951 * FLTINR2 FLT6E LL_HRTIM_FLT_Enable
9952 * @param HRTIMx High Resolution Timer instance
9953 * @param Fault This parameter can be one of the following values:
9954 * @arg @ref LL_HRTIM_FAULT_1
9955 * @arg @ref LL_HRTIM_FAULT_2
9956 * @arg @ref LL_HRTIM_FAULT_3
9957 * @arg @ref LL_HRTIM_FAULT_4
9958 * @arg @ref LL_HRTIM_FAULT_5
9959 * @arg @ref LL_HRTIM_FAULT_6
9960 * @retval None
9961 */
LL_HRTIM_FLT_Enable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9962 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9963 {
9964 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9965 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9966 REG_OFFSET_TAB_FLTINR[iFault]));
9967 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
9968 }
9969
9970 /**
9971 * @brief Disable the fault circuitry for for the designated fault input.
9972 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
9973 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
9974 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
9975 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
9976 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable\n
9977 * FLTINR2 FLT6E LL_HRTIM_FLT_Disable
9978 * @param HRTIMx High Resolution Timer instance
9979 * @param Fault This parameter can be one of the following values:
9980 * @arg @ref LL_HRTIM_FAULT_1
9981 * @arg @ref LL_HRTIM_FAULT_2
9982 * @arg @ref LL_HRTIM_FAULT_3
9983 * @arg @ref LL_HRTIM_FAULT_4
9984 * @arg @ref LL_HRTIM_FAULT_5
9985 * @arg @ref LL_HRTIM_FAULT_6
9986 * @retval None
9987 */
LL_HRTIM_FLT_Disable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9988 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9989 {
9990 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9991 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9992 REG_OFFSET_TAB_FLTINR[iFault]));
9993 CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
9994
9995 }
9996
9997 /**
9998 * @brief Indicate whether the fault circuitry is enabled for a given fault input.
9999 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
10000 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
10001 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
10002 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
10003 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled\n
10004 * FLTINR2 FLT6E LL_HRTIM_FLT_IsEnabled
10005 * @param HRTIMx High Resolution Timer instance
10006 * @param Fault This parameter can be one of the following values:
10007 * @arg @ref LL_HRTIM_FAULT_1
10008 * @arg @ref LL_HRTIM_FAULT_2
10009 * @arg @ref LL_HRTIM_FAULT_3
10010 * @arg @ref LL_HRTIM_FAULT_4
10011 * @arg @ref LL_HRTIM_FAULT_5
10012 * @arg @ref LL_HRTIM_FAULT_6
10013 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
10014 */
LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)10015 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10016 {
10017 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10018 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
10019 REG_OFFSET_TAB_FLTINR[iFault]));
10020 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
10021 (HRTIM_FLTINR1_FLT1E)) ? 1UL : 0UL);
10022 }
10023
10024 /**
10025 * @brief Enable the Blanking of the fault circuitry for the designated fault input.
10026 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_EnableBlanking\n
10027 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_EnableBlanking\n
10028 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_EnableBlanking\n
10029 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_EnableBlanking\n
10030 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_EnableBlanking\n
10031 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_EnableBlanking
10032 * @param HRTIMx High Resolution Timer instance
10033 * @param Fault This parameter can be one of the following values:
10034 * @arg @ref LL_HRTIM_FAULT_1
10035 * @arg @ref LL_HRTIM_FAULT_2
10036 * @arg @ref LL_HRTIM_FAULT_3
10037 * @arg @ref LL_HRTIM_FAULT_4
10038 * @arg @ref LL_HRTIM_FAULT_5
10039 * @arg @ref LL_HRTIM_FAULT_6
10040 * @retval None
10041 */
LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10042 __STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10043 {
10044 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10045 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10046 REG_OFFSET_TAB_FLTINR[iFault]));
10047 SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]);
10048 }
10049
10050 /**
10051 * @brief Disable the Blanking of the fault circuitry for the designated fault input.
10052 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_DisableBlanking\n
10053 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_DisableBlanking\n
10054 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_DisableBlanking\n
10055 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_DisableBlanking\n
10056 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_DisableBlanking\n
10057 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_DisableBlanking
10058 * @param HRTIMx High Resolution Timer instance
10059 * @param Fault This parameter can be one of the following values:
10060 * @arg @ref LL_HRTIM_FAULT_1
10061 * @arg @ref LL_HRTIM_FAULT_2
10062 * @arg @ref LL_HRTIM_FAULT_3
10063 * @arg @ref LL_HRTIM_FAULT_4
10064 * @arg @ref LL_HRTIM_FAULT_5
10065 * @arg @ref LL_HRTIM_FAULT_6
10066 * @retval None
10067 */
LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10068 __STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10069 {
10070 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10071 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10072 REG_OFFSET_TAB_FLTINR[iFault]));
10073 CLEAR_BIT(*pReg, (HRTIM_FLTINR3_FLT1BLKE << REG_SHIFT_TAB_FLTxE[iFault]));
10074 }
10075
10076 /**
10077 * @brief Indicate whether the Blanking of the fault circuitry is enabled for a given fault input.
10078 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10079 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10080 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10081 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10082 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10083 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_IsEnabledBlanking
10084 * @param HRTIMx High Resolution Timer instance
10085 * @param Fault This parameter can be one of the following values:
10086 * @arg @ref LL_HRTIM_FAULT_1
10087 * @arg @ref LL_HRTIM_FAULT_2
10088 * @arg @ref LL_HRTIM_FAULT_3
10089 * @arg @ref LL_HRTIM_FAULT_4
10090 * @arg @ref LL_HRTIM_FAULT_5
10091 * @arg @ref LL_HRTIM_FAULT_6
10092 * @retval State of FLTxBLKE bit in HRTIM_FLTINRx register (1 or 0).
10093 */
LL_HRTIM_FLT_IsEnabledBlanking(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)10094 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10095 {
10096 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10097 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10098 REG_OFFSET_TAB_FLTINR[iFault]));
10099 uint32_t temp; /* MISRAC-2012 compliance */
10100 temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault];
10101
10102 return ((temp == (HRTIM_FLTINR3_FLT1BLKE)) ? 1UL : 0UL);
10103 }
10104
10105 /**
10106 * @brief Set the Blanking Source of the fault circuitry for a given fault input.
10107 * @note Fault inputs can be temporary disabled to blank spurious fault events.
10108 * @note This function allows for selection amongst 2 possible blanking sources.
10109 * @note Events triggering blanking window start and blanking window end depend
10110 * on both the selected blanking source and the fault input.
10111 * @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10112 * FLTINR3 FLT2BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10113 * FLTINR3 FLT3BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10114 * FLTINR3 FLT4BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10115 * FLTINR4 FLT5BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10116 * FLTINR4 FLT6BLKS LL_HRTIM_FLT_SetBlankingSrc
10117 * @param HRTIMx High Resolution Timer instance
10118 * @param Fault This parameter can be one of the following values:
10119 * @arg @ref LL_HRTIM_FAULT_1
10120 * @arg @ref LL_HRTIM_FAULT_2
10121 * @arg @ref LL_HRTIM_FAULT_3
10122 * @arg @ref LL_HRTIM_FAULT_4
10123 * @arg @ref LL_HRTIM_FAULT_5
10124 * @arg @ref LL_HRTIM_FAULT_6
10125 * @param Source parameter can be one of the following values:
10126 * @arg @ref LL_HRTIM_FLT_BLANKING_RSTALIGNED
10127 * @arg @ref LL_HRTIM_FLT_BLANKING_MOVING
10128 * @retval None
10129 */
LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Source)10130 __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Source)
10131 {
10132 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10133 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10134 REG_OFFSET_TAB_FLTINR[iFault]));
10135 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault]));
10136
10137 }
10138
10139 /**
10140 * @brief Get the Blanking Source of the fault circuitry is enabled for a given fault input.
10141 * @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10142 * FLTINR3 FLT2BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10143 * FLTINR3 FLT3BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10144 * FLTINR3 FLT4BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10145 * FLTINR4 FLT5BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10146 * FLTINR4 FLT6BLKS LL_HRTIM_FLT_GetBlankingSrc
10147 * @param HRTIMx High Resolution Timer instance
10148 * @param Fault This parameter can be one of the following values:
10149 * @arg @ref LL_HRTIM_FAULT_1
10150 * @arg @ref LL_HRTIM_FAULT_2
10151 * @arg @ref LL_HRTIM_FAULT_3
10152 * @arg @ref LL_HRTIM_FAULT_4
10153 * @arg @ref LL_HRTIM_FAULT_5
10154 * @arg @ref LL_HRTIM_FAULT_6
10155 */
LL_HRTIM_FLT_GetBlankingSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)10156 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10157 {
10158 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10159 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10160 REG_OFFSET_TAB_FLTINR[iFault]));
10161 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]));
10162 }
10163
10164 /**
10165 * @brief Set the Counter threshold value of a fault counter.
10166 * @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_SetCounterThreshold\n
10167 * FLTINR3 FLT2CNT LL_HRTIM_FLT_SetCounterThreshold\n
10168 * FLTINR3 FLT3CNT LL_HRTIM_FLT_SetCounterThreshold\n
10169 * FLTINR3 FLT4CNT LL_HRTIM_FLT_SetCounterThreshold\n
10170 * FLTINR4 FLT5CNT LL_HRTIM_FLT_SetCounterThreshold\n
10171 * FLTINR4 FLT6CNT LL_HRTIM_FLT_SetCounterThreshold
10172 * @note This function must not be called when the fault channel is enabled.
10173 * @param HRTIMx High Resolution Timer instance
10174 * @param Fault This parameter can be one of the following values:
10175 * @arg @ref LL_HRTIM_FAULT_1
10176 * @arg @ref LL_HRTIM_FAULT_2
10177 * @arg @ref LL_HRTIM_FAULT_3
10178 * @arg @ref LL_HRTIM_FAULT_4
10179 * @arg @ref LL_HRTIM_FAULT_5
10180 * @arg @ref LL_HRTIM_FAULT_6
10181 * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10182 * @retval None
10183 */
LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Threshold)10184 __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Threshold)
10185 {
10186 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10187 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10188 REG_OFFSET_TAB_FLTINR[iFault]));
10189 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxCNT[iFault]));
10190 }
10191
10192 /**
10193 * @brief Get actual the Counter threshold value of a fault counter.
10194 * @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_GetCounterThreshold\n
10195 * FLTINR3 FLT2CNT LL_HRTIM_FLT_GetCounterThreshold\n
10196 * FLTINR3 FLT3CNT LL_HRTIM_FLT_GetCounterThreshold\n
10197 * FLTINR3 FLT4CNT LL_HRTIM_FLT_GetCounterThreshold\n
10198 * FLTINR4 FLT5CNT LL_HRTIM_FLT_GetCounterThreshold\n
10199 * FLTINR4 FLT6CNT LL_HRTIM_FLT_GetCounterThreshold
10200 * @param HRTIMx High Resolution Timer instance
10201 * @param Fault This parameter can be one of the following values:
10202 * @arg @ref LL_HRTIM_FAULT_1
10203 * @arg @ref LL_HRTIM_FAULT_2
10204 * @arg @ref LL_HRTIM_FAULT_3
10205 * @arg @ref LL_HRTIM_FAULT_4
10206 * @arg @ref LL_HRTIM_FAULT_5
10207 * @arg @ref LL_HRTIM_FAULT_6
10208 * @retval Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10209 */
LL_HRTIM_FLT_GetCounterThreshold(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)10210 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10211 {
10212 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10213 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10214 REG_OFFSET_TAB_FLTINR[iFault]));
10215 return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxCNT[iFault]);
10216 }
10217
10218 /**
10219 * @brief Set the mode of reset of a fault counter to 'always reset'.
10220 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_SetResetMode\n
10221 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_SetResetMode\n
10222 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_SetResetMode\n
10223 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_SetResetMode\n
10224 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_SetResetMode\n
10225 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_SetResetMode
10226 * @param HRTIMx High Resolution Timer instance
10227 * @param Fault This parameter can be one of the following values:
10228 * @arg @ref LL_HRTIM_FAULT_1
10229 * @arg @ref LL_HRTIM_FAULT_2
10230 * @arg @ref LL_HRTIM_FAULT_3
10231 * @arg @ref LL_HRTIM_FAULT_4
10232 * @arg @ref LL_HRTIM_FAULT_5
10233 * @arg @ref LL_HRTIM_FAULT_6
10234 * @param Mode This parameter can be one of the following values:
10235 * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10236 * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10237 * @retval None
10238 */
LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Mode)10239 __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Mode)
10240 {
10241 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10242 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10243 REG_OFFSET_TAB_FLTINR[iFault]));
10244 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]);
10245
10246 }
10247
10248 /**
10249 * @brief Get the mode of reset of a fault counter to 'reset on event'.
10250 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_GetResetMode\n
10251 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_GetResetMode\n
10252 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_GetResetMode\n
10253 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_GetResetMode\n
10254 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_GetResetMode\n
10255 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_GetResetMode
10256 * @param HRTIMx High Resolution Timer instance
10257 * @param Fault This parameter can be one of the following values:
10258 * @arg @ref LL_HRTIM_FAULT_1
10259 * @arg @ref LL_HRTIM_FAULT_2
10260 * @arg @ref LL_HRTIM_FAULT_3
10261 * @arg @ref LL_HRTIM_FAULT_4
10262 * @arg @ref LL_HRTIM_FAULT_5
10263 * @arg @ref LL_HRTIM_FAULT_6
10264 * @retval Mode This parameter can be one of the following values:
10265 * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10266 * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10267 */
LL_HRTIM_FLT_GetResetMode(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)10268 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10269 {
10270 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10271 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10272 REG_OFFSET_TAB_FLTINR[iFault]));
10273 return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]);
10274 }
10275
10276 /**
10277 * @brief Reset the fault counter for a fault circuitry
10278 * @rmtoll FLTINR3 FLT1CRES LL_HRTIM_FLT_ResetCounter\n
10279 * FLTINR3 FLT2CRES LL_HRTIM_FLT_ResetCounter\n
10280 * FLTINR3 FLT3CRES LL_HRTIM_FLT_ResetCounter\n
10281 * FLTINR3 FLT4CRES LL_HRTIM_FLT_ResetCounter\n
10282 * FLTINR4 FLT5CRES LL_HRTIM_FLT_ResetCounter\n
10283 * FLTINR4 FLT6CRES LL_HRTIM_FLT_ResetCounter
10284 * @param HRTIMx High Resolution Timer instance
10285 * @param Fault This parameter can be one of the following values:
10286 * @arg @ref LL_HRTIM_FAULT_1
10287 * @arg @ref LL_HRTIM_FAULT_2
10288 * @arg @ref LL_HRTIM_FAULT_3
10289 * @arg @ref LL_HRTIM_FAULT_4
10290 * @arg @ref LL_HRTIM_FAULT_5
10291 * @arg @ref LL_HRTIM_FAULT_6
10292 * @retval None
10293 */
LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10294 __STATIC_INLINE void LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10295 {
10296 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10297 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10298 REG_OFFSET_TAB_FLTINR[iFault]));
10299 SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CRES) << REG_SHIFT_TAB_FLTxE[iFault]);
10300
10301 }
10302
10303 /**
10304 * @}
10305 */
10306
10307 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
10308 * @{
10309 */
10310
10311 /**
10312 * @brief Configure the burst mode controller.
10313 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
10314 * BMCR BMCLK LL_HRTIM_BM_Config\n
10315 * BMCR BMPRSC LL_HRTIM_BM_Config
10316 * @param HRTIMx High Resolution Timer instance
10317 * @param Configuration This parameter must be a combination of all the following values:
10318 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
10319 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10320 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
10321 * @retval None
10322 */
LL_HRTIM_BM_Config(HRTIM_TypeDef * HRTIMx,uint32_t Configuration)10323 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
10324 {
10325 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
10326 }
10327
10328 /**
10329 * @brief Set the burst mode controller operating mode.
10330 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
10331 * @param HRTIMx High Resolution Timer instance
10332 * @param Mode This parameter can be one of the following values:
10333 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10334 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10335 * @retval None
10336 */
LL_HRTIM_BM_SetMode(HRTIM_TypeDef * HRTIMx,uint32_t Mode)10337 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
10338 {
10339 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
10340 }
10341
10342 /**
10343 * @brief Get actual burst mode controller operating mode.
10344 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
10345 * @param HRTIMx High Resolution Timer instance
10346 * @retval Mode This parameter can be one of the following values:
10347 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10348 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10349 */
LL_HRTIM_BM_GetMode(const HRTIM_TypeDef * HRTIMx)10350 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx)
10351 {
10352 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
10353 }
10354
10355 /**
10356 * @brief Set the burst mode controller clock source.
10357 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
10358 * @param HRTIMx High Resolution Timer instance
10359 * @param ClockSrc This parameter can be one of the following values:
10360 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10361 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10362 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10363 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10364 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10365 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10366 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10367 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10368 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10369 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10370 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10371 * @retval None
10372 */
LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef * HRTIMx,uint32_t ClockSrc)10373 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
10374 {
10375 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
10376 }
10377
10378 /**
10379 * @brief Get actual burst mode controller clock source.
10380 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
10381 * @param HRTIMx High Resolution Timer instance
10382 * @retval ClockSrc This parameter can be one of the following values:
10383 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10384 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10385 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10386 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10387 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10388 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10389 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10390 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10391 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10392 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10393 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10394 * @retval ClockSrc This parameter can be one of the following values:
10395 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10396 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10397 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10398 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10399 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10400 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10401 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10402 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10403 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10404 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10405 */
LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef * HRTIMx)10406 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx)
10407 {
10408 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
10409 }
10410
10411 /**
10412 * @brief Set the burst mode controller prescaler.
10413 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
10414 * @param HRTIMx High Resolution Timer instance
10415 * @param Prescaler This parameter can be one of the following values:
10416 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10417 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10418 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10419 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10420 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10421 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10422 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10423 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10424 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10425 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10426 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10427 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10428 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10429 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10430 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10431 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10432 * @retval None
10433 */
LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)10434 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
10435 {
10436 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
10437 }
10438
10439 /**
10440 * @brief Get actual burst mode controller prescaler setting.
10441 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
10442 * @param HRTIMx High Resolution Timer instance
10443 * @retval Prescaler This parameter can be one of the following values:
10444 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10445 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10446 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10447 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10448 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10449 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10450 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10451 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10452 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10453 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10454 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10455 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10456 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10457 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10458 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10459 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10460 */
LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef * HRTIMx)10461 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
10462 {
10463 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
10464 }
10465
10466 /**
10467 * @brief Enable burst mode compare and period registers preload.
10468 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
10469 * @param HRTIMx High Resolution Timer instance
10470 * @retval None
10471 */
LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef * HRTIMx)10472 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
10473 {
10474 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10475 }
10476
10477 /**
10478 * @brief Disable burst mode compare and period registers preload.
10479 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
10480 * @param HRTIMx High Resolution Timer instance
10481 * @retval None
10482 */
LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef * HRTIMx)10483 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
10484 {
10485 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10486 }
10487
10488 /**
10489 * @brief Indicate whether burst mode compare and period registers are preloaded.
10490 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
10491 * @param HRTIMx High Resolution Timer instance
10492 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
10493 */
LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef * HRTIMx)10494 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx)
10495 {
10496 uint32_t temp; /* MISRAC-2012 compliance */
10497 temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10498
10499 return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
10500 }
10501
10502 /**
10503 * @brief Set the burst mode controller trigger
10504 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
10505 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
10506 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
10507 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
10508 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
10509 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
10510 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
10511 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
10512 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
10513 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
10514 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
10515 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
10516 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
10517 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
10518 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
10519 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
10520 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
10521 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
10522 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
10523 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
10524 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
10525 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
10526 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
10527 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
10528 * BMTRGR TFREP LL_HRTIM_BM_SetTrig\n
10529 * BMTRGR TFRST LL_HRTIM_BM_SetTrig\n
10530 * BMTRGR TFCMP1 LL_HRTIM_BM_SetTrig\n
10531 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
10532 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
10533 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
10534 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
10535 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
10536 * @param HRTIMx High Resolution Timer instance
10537 * @param Trig This parameter can be a combination of the following values:
10538 * @arg @ref LL_HRTIM_BM_TRIG_NONE
10539 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10540 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10541 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10542 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10543 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10544 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10545 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10546 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10547 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10548 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10549 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10550 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10551 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10552 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10553 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10554 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10555 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10556 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10557 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10558 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10559 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10560 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10561 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10562 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10563 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10564 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10565 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10566 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10567 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10568 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10569 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10570 * @retval None
10571 */
LL_HRTIM_BM_SetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Trig)10572 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
10573 {
10574 WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
10575 }
10576
10577 /**
10578 * @brief Get actual burst mode controller trigger.
10579 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
10580 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
10581 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
10582 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
10583 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
10584 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
10585 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
10586 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
10587 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
10588 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
10589 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
10590 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
10591 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
10592 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
10593 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
10594 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
10595 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
10596 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
10597 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
10598 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
10599 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
10600 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
10601 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
10602 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
10603 * BMTRGR TFREP LL_HRTIM_BM_GetTrig\n
10604 * BMTRGR TFRST LL_HRTIM_BM_GetTrig\n
10605 * BMTRGR TFCMP1 LL_HRTIM_BM_GetTrig\n
10606 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
10607 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
10608 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
10609 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
10610 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
10611 * @param HRTIMx High Resolution Timer instance
10612 * @retval Trig This parameter can be a combination of the following values:
10613 * @arg @ref LL_HRTIM_BM_TRIG_NONE
10614 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10615 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10616 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10617 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10618 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10619 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10620 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10621 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10622 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10623 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10624 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10625 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10626 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10627 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10628 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10629 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10630 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10631 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10632 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10633 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10634 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10635 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10636 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10637 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10638 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10639 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10640 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10641 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10642 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10643 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10644 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10645 */
LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef * HRTIMx)10646 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx)
10647 {
10648 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
10649 }
10650
10651 /**
10652 * @brief Set the burst mode controller compare value.
10653 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
10654 * @param HRTIMx High Resolution Timer instance
10655 * @param CompareValue Compare value must be above or equal to 3
10656 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10657 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10658 * @retval None
10659 */
LL_HRTIM_BM_SetCompare(HRTIM_TypeDef * HRTIMx,uint32_t CompareValue)10660 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
10661 {
10662 WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
10663 }
10664
10665 /**
10666 * @brief Get actual burst mode controller compare value.
10667 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
10668 * @param HRTIMx High Resolution Timer instance
10669 * @retval CompareValue Compare value must be above or equal to 3
10670 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10671 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10672 */
LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef * HRTIMx)10673 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx)
10674 {
10675 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
10676 }
10677
10678 /**
10679 * @brief Set the burst mode controller period.
10680 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
10681 * @param HRTIMx High Resolution Timer instance
10682 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
10683 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10684 * The maximum value is 0x0000 FFDF.
10685 * @retval None
10686 */
LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Period)10687 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
10688 {
10689 WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
10690 }
10691
10692 /**
10693 * @brief Get actual burst mode controller period.
10694 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
10695 * @param HRTIMx High Resolution Timer instance
10696 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
10697 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10698 * The maximum value is 0x0000 FFDF.
10699 */
LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef * HRTIMx)10700 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx)
10701 {
10702 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
10703 }
10704
10705 /**
10706 * @brief Enable the burst mode controller
10707 * @rmtoll BMCR BME LL_HRTIM_BM_Enable
10708 * @param HRTIMx High Resolution Timer instance
10709 * @retval None
10710 */
LL_HRTIM_BM_Enable(HRTIM_TypeDef * HRTIMx)10711 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
10712 {
10713 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
10714 }
10715
10716 /**
10717 * @brief Disable the burst mode controller
10718 * @rmtoll BMCR BME LL_HRTIM_BM_Disable
10719 * @param HRTIMx High Resolution Timer instance
10720 * @retval None
10721 */
LL_HRTIM_BM_Disable(HRTIM_TypeDef * HRTIMx)10722 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
10723 {
10724 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
10725 }
10726
10727 /**
10728 * @brief Indicate whether the burst mode controller is enabled.
10729 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
10730 * @param HRTIMx High Resolution Timer instance
10731 * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
10732 */
LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef * HRTIMx)10733 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx)
10734 {
10735 return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
10736 }
10737
10738 /**
10739 * @brief Trigger the burst operation (software trigger)
10740 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
10741 * @param HRTIMx High Resolution Timer instance
10742 * @retval None
10743 */
LL_HRTIM_BM_Start(HRTIM_TypeDef * HRTIMx)10744 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
10745 {
10746 SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
10747 }
10748
10749 /**
10750 * @brief Stop the burst mode operation.
10751 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
10752 * @note Causes a burst mode early termination.
10753 * @param HRTIMx High Resolution Timer instance
10754 * @retval None
10755 */
LL_HRTIM_BM_Stop(HRTIM_TypeDef * HRTIMx)10756 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
10757 {
10758 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
10759 }
10760
10761 /**
10762 * @brief Get actual burst mode status
10763 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
10764 * @param HRTIMx High Resolution Timer instance
10765 * @retval Status This parameter can be one of the following values:
10766 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
10767 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
10768 */
LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef * HRTIMx)10769 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx)
10770 {
10771 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
10772 }
10773
10774 /**
10775 * @}
10776 */
10777
10778 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
10779 * @{
10780 */
10781
10782 /**
10783 * @brief Clear the Fault 1 interrupt flag.
10784 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
10785 * @param HRTIMx High Resolution Timer instance
10786 * @retval None
10787 */
LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef * HRTIMx)10788 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
10789 {
10790 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
10791 }
10792
10793 /**
10794 * @brief Indicate whether Fault 1 interrupt occurred.
10795 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
10796 * @param HRTIMx High Resolution Timer instance
10797 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
10798 */
LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef * HRTIMx)10799 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx)
10800 {
10801 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
10802 }
10803
10804 /**
10805 * @brief Clear the Fault 2 interrupt flag.
10806 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
10807 * @param HRTIMx High Resolution Timer instance
10808 * @retval None
10809 */
LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef * HRTIMx)10810 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
10811 {
10812 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
10813 }
10814
10815 /**
10816 * @brief Indicate whether Fault 2 interrupt occurred.
10817 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
10818 * @param HRTIMx High Resolution Timer instance
10819 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
10820 */
LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef * HRTIMx)10821 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx)
10822 {
10823 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
10824 }
10825
10826 /**
10827 * @brief Clear the Fault 3 interrupt flag.
10828 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
10829 * @param HRTIMx High Resolution Timer instance
10830 * @retval None
10831 */
LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef * HRTIMx)10832 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
10833 {
10834 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
10835 }
10836
10837 /**
10838 * @brief Indicate whether Fault 3 interrupt occurred.
10839 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
10840 * @param HRTIMx High Resolution Timer instance
10841 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
10842 */
LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef * HRTIMx)10843 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx)
10844 {
10845 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
10846 }
10847
10848 /**
10849 * @brief Clear the Fault 4 interrupt flag.
10850 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
10851 * @param HRTIMx High Resolution Timer instance
10852 * @retval None
10853 */
LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef * HRTIMx)10854 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
10855 {
10856 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
10857 }
10858
10859 /**
10860 * @brief Indicate whether Fault 4 interrupt occurred.
10861 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
10862 * @param HRTIMx High Resolution Timer instance
10863 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
10864 */
LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef * HRTIMx)10865 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx)
10866 {
10867 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
10868 }
10869
10870 /**
10871 * @brief Clear the Fault 5 interrupt flag.
10872 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
10873 * @param HRTIMx High Resolution Timer instance
10874 * @retval None
10875 */
LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef * HRTIMx)10876 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
10877 {
10878 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
10879 }
10880
10881 /**
10882 * @brief Indicate whether Fault 5 interrupt occurred.
10883 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
10884 * @param HRTIMx High Resolution Timer instance
10885 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
10886 */
LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef * HRTIMx)10887 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx)
10888 {
10889 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
10890 }
10891
10892 /**
10893 * @brief Clear the Fault 6 interrupt flag.
10894 * @rmtoll ICR FLT6C LL_HRTIM_ClearFlag_FLT6
10895 * @param HRTIMx High Resolution Timer instance
10896 * @retval None
10897 */
LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef * HRTIMx)10898 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef *HRTIMx)
10899 {
10900 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT6C);
10901 }
10902
10903 /**
10904 * @brief Indicate whether Fault 6 interrupt occurred.
10905 * @rmtoll ICR FLT6 LL_HRTIM_IsActiveFlag_FLT6
10906 * @param HRTIMx High Resolution Timer instance
10907 * @retval State of FLT6 bit in HRTIM_ISR register (1 or 0).
10908 */
LL_HRTIM_IsActiveFlag_FLT6(const HRTIM_TypeDef * HRTIMx)10909 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT6(const HRTIM_TypeDef *HRTIMx)
10910 {
10911 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT6) == (HRTIM_ISR_FLT6)) ? 1UL : 0UL);
10912 }
10913
10914 /**
10915 * @brief Clear the System Fault interrupt flag.
10916 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
10917 * @param HRTIMx High Resolution Timer instance
10918 * @retval None
10919 */
LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef * HRTIMx)10920 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
10921 {
10922 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
10923 }
10924
10925 /**
10926 * @brief Indicate whether System Fault interrupt occurred.
10927 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
10928 * @param HRTIMx High Resolution Timer instance
10929 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
10930 */
LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef * HRTIMx)10931 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx)
10932 {
10933 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
10934 }
10935
10936 /**
10937 * @brief Clear the DLL ready interrupt flag.
10938 * @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
10939 * @param HRTIMx High Resolution Timer instance
10940 * @retval None
10941 */
LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef * HRTIMx)10942 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
10943 {
10944 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
10945 }
10946
10947 /**
10948 * @brief Indicate whether DLL ready interrupt occurred.
10949 * @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
10950 * @param HRTIMx High Resolution Timer instance
10951 * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
10952 */
LL_HRTIM_IsActiveFlag_DLLRDY(const HRTIM_TypeDef * HRTIMx)10953 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(const HRTIM_TypeDef *HRTIMx)
10954 {
10955 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL);
10956 }
10957
10958 /**
10959 * @brief Clear the Burst Mode period interrupt flag.
10960 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
10961 * @param HRTIMx High Resolution Timer instance
10962 * @retval None
10963 */
LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef * HRTIMx)10964 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
10965 {
10966 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
10967 }
10968
10969 /**
10970 * @brief Indicate whether Burst Mode period interrupt occurred.
10971 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
10972 * @param HRTIMx High Resolution Timer instance
10973 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
10974 */
LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef * HRTIMx)10975 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx)
10976 {
10977 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
10978 }
10979
10980 /**
10981 * @brief Clear the Synchronization Input interrupt flag.
10982 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
10983 * @param HRTIMx High Resolution Timer instance
10984 * @retval None
10985 */
LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef * HRTIMx)10986 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
10987 {
10988 SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
10989 }
10990
10991 /**
10992 * @brief Indicate whether the Synchronization Input interrupt occurred.
10993 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
10994 * @param HRTIMx High Resolution Timer instance
10995 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
10996 */
LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef * HRTIMx)10997 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx)
10998 {
10999 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
11000 }
11001
11002 /**
11003 * @brief Clear the update interrupt flag for a given timer (including the master timer) .
11004 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
11005 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
11006 * @param HRTIMx High Resolution Timer instance
11007 * @param Timer This parameter can be one of the following values:
11008 * @arg @ref LL_HRTIM_TIMER_MASTER
11009 * @arg @ref LL_HRTIM_TIMER_A
11010 * @arg @ref LL_HRTIM_TIMER_B
11011 * @arg @ref LL_HRTIM_TIMER_C
11012 * @arg @ref LL_HRTIM_TIMER_D
11013 * @arg @ref LL_HRTIM_TIMER_E
11014 * @arg @ref LL_HRTIM_TIMER_F
11015 * @retval None
11016 */
LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11017 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11018 {
11019 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11020 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11021 REG_OFFSET_TAB_TIMER[iTimer]));
11022 SET_BIT(*pReg, HRTIM_MICR_MUPD);
11023 }
11024
11025 /**
11026 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
11027 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
11028 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
11029 * @param HRTIMx High Resolution Timer instance
11030 * @param Timer This parameter can be one of the following values:
11031 * @arg @ref LL_HRTIM_TIMER_MASTER
11032 * @arg @ref LL_HRTIM_TIMER_A
11033 * @arg @ref LL_HRTIM_TIMER_B
11034 * @arg @ref LL_HRTIM_TIMER_C
11035 * @arg @ref LL_HRTIM_TIMER_D
11036 * @arg @ref LL_HRTIM_TIMER_E
11037 * @arg @ref LL_HRTIM_TIMER_F
11038 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11039 */
LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11040 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11041 {
11042 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11043 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11044 REG_OFFSET_TAB_TIMER[iTimer]));
11045
11046 return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
11047 }
11048
11049 /**
11050 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
11051 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
11052 * TIMxICR REPC LL_HRTIM_ClearFlag_REP
11053 * @param HRTIMx High Resolution Timer instance
11054 * @param Timer This parameter can be one of the following values:
11055 * @arg @ref LL_HRTIM_TIMER_MASTER
11056 * @arg @ref LL_HRTIM_TIMER_A
11057 * @arg @ref LL_HRTIM_TIMER_B
11058 * @arg @ref LL_HRTIM_TIMER_C
11059 * @arg @ref LL_HRTIM_TIMER_D
11060 * @arg @ref LL_HRTIM_TIMER_E
11061 * @arg @ref LL_HRTIM_TIMER_F
11062 * @retval None
11063 */
LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11064 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11065 {
11066 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11067 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11068 REG_OFFSET_TAB_TIMER[iTimer]));
11069 SET_BIT(*pReg, HRTIM_MICR_MREP);
11070
11071 }
11072
11073 /**
11074 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
11075 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
11076 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
11077 * @param HRTIMx High Resolution Timer instance
11078 * @param Timer This parameter can be one of the following values:
11079 * @arg @ref LL_HRTIM_TIMER_MASTER
11080 * @arg @ref LL_HRTIM_TIMER_A
11081 * @arg @ref LL_HRTIM_TIMER_B
11082 * @arg @ref LL_HRTIM_TIMER_C
11083 * @arg @ref LL_HRTIM_TIMER_D
11084 * @arg @ref LL_HRTIM_TIMER_E
11085 * @arg @ref LL_HRTIM_TIMER_F
11086 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11087 */
LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11088 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11089 {
11090 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11091 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11092 REG_OFFSET_TAB_TIMER[iTimer]));
11093
11094 return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
11095 }
11096
11097 /**
11098 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
11099 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
11100 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
11101 * @param HRTIMx High Resolution Timer instance
11102 * @param Timer This parameter can be one of the following values:
11103 * @arg @ref LL_HRTIM_TIMER_MASTER
11104 * @arg @ref LL_HRTIM_TIMER_A
11105 * @arg @ref LL_HRTIM_TIMER_B
11106 * @arg @ref LL_HRTIM_TIMER_C
11107 * @arg @ref LL_HRTIM_TIMER_D
11108 * @arg @ref LL_HRTIM_TIMER_E
11109 * @arg @ref LL_HRTIM_TIMER_F
11110 * @retval None
11111 */
LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11112 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11113 {
11114 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11115 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11116 REG_OFFSET_TAB_TIMER[iTimer]));
11117 SET_BIT(*pReg, HRTIM_MICR_MCMP1);
11118 }
11119
11120 /**
11121 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
11122 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
11123 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
11124 * @param HRTIMx High Resolution Timer instance
11125 * @param Timer This parameter can be one of the following values:
11126 * @arg @ref LL_HRTIM_TIMER_MASTER
11127 * @arg @ref LL_HRTIM_TIMER_A
11128 * @arg @ref LL_HRTIM_TIMER_B
11129 * @arg @ref LL_HRTIM_TIMER_C
11130 * @arg @ref LL_HRTIM_TIMER_D
11131 * @arg @ref LL_HRTIM_TIMER_E
11132 * @arg @ref LL_HRTIM_TIMER_F
11133 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11134 */
LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11135 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11136 {
11137 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11138 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11139 REG_OFFSET_TAB_TIMER[iTimer]));
11140
11141 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
11142 }
11143
11144 /**
11145 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
11146 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
11147 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
11148 * @param HRTIMx High Resolution Timer instance
11149 * @param Timer This parameter can be one of the following values:
11150 * @arg @ref LL_HRTIM_TIMER_MASTER
11151 * @arg @ref LL_HRTIM_TIMER_A
11152 * @arg @ref LL_HRTIM_TIMER_B
11153 * @arg @ref LL_HRTIM_TIMER_C
11154 * @arg @ref LL_HRTIM_TIMER_D
11155 * @arg @ref LL_HRTIM_TIMER_E
11156 * @arg @ref LL_HRTIM_TIMER_F
11157 * @retval None
11158 */
LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11159 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11160 {
11161 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11162 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11163 REG_OFFSET_TAB_TIMER[iTimer]));
11164 SET_BIT(*pReg, HRTIM_MICR_MCMP2);
11165 }
11166
11167 /**
11168 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
11169 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
11170 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
11171 * @param HRTIMx High Resolution Timer instance
11172 * @param Timer This parameter can be one of the following values:
11173 * @arg @ref LL_HRTIM_TIMER_MASTER
11174 * @arg @ref LL_HRTIM_TIMER_A
11175 * @arg @ref LL_HRTIM_TIMER_B
11176 * @arg @ref LL_HRTIM_TIMER_C
11177 * @arg @ref LL_HRTIM_TIMER_D
11178 * @arg @ref LL_HRTIM_TIMER_E
11179 * @arg @ref LL_HRTIM_TIMER_F
11180 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11181 */
LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11182 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11183 {
11184 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11185 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11186 REG_OFFSET_TAB_TIMER[iTimer]));
11187
11188 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
11189 }
11190
11191 /**
11192 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
11193 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
11194 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
11195 * @param HRTIMx High Resolution Timer instance
11196 * @param Timer This parameter can be one of the following values:
11197 * @arg @ref LL_HRTIM_TIMER_MASTER
11198 * @arg @ref LL_HRTIM_TIMER_A
11199 * @arg @ref LL_HRTIM_TIMER_B
11200 * @arg @ref LL_HRTIM_TIMER_C
11201 * @arg @ref LL_HRTIM_TIMER_D
11202 * @arg @ref LL_HRTIM_TIMER_E
11203 * @arg @ref LL_HRTIM_TIMER_F
11204 * @retval None
11205 */
LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11206 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11207 {
11208 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11209 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11210 REG_OFFSET_TAB_TIMER[iTimer]));
11211 SET_BIT(*pReg, HRTIM_MICR_MCMP3);
11212 }
11213
11214 /**
11215 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
11216 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
11217 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
11218 * @param HRTIMx High Resolution Timer instance
11219 * @param Timer This parameter can be one of the following values:
11220 * @arg @ref LL_HRTIM_TIMER_MASTER
11221 * @arg @ref LL_HRTIM_TIMER_A
11222 * @arg @ref LL_HRTIM_TIMER_B
11223 * @arg @ref LL_HRTIM_TIMER_C
11224 * @arg @ref LL_HRTIM_TIMER_D
11225 * @arg @ref LL_HRTIM_TIMER_E
11226 * @arg @ref LL_HRTIM_TIMER_F
11227 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11228 */
LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11229 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11230 {
11231 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11232 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11233 REG_OFFSET_TAB_TIMER[iTimer]));
11234
11235 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
11236 }
11237
11238 /**
11239 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
11240 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
11241 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
11242 * @param HRTIMx High Resolution Timer instance
11243 * @param Timer This parameter can be one of the following values:
11244 * @arg @ref LL_HRTIM_TIMER_MASTER
11245 * @arg @ref LL_HRTIM_TIMER_A
11246 * @arg @ref LL_HRTIM_TIMER_B
11247 * @arg @ref LL_HRTIM_TIMER_C
11248 * @arg @ref LL_HRTIM_TIMER_D
11249 * @arg @ref LL_HRTIM_TIMER_E
11250 * @arg @ref LL_HRTIM_TIMER_F
11251 * @retval None
11252 */
LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11253 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11254 {
11255 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11256 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11257 REG_OFFSET_TAB_TIMER[iTimer]));
11258 SET_BIT(*pReg, HRTIM_MICR_MCMP4);
11259 }
11260
11261 /**
11262 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
11263 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
11264 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
11265 * @param HRTIMx High Resolution Timer instance
11266 * @param Timer This parameter can be one of the following values:
11267 * @arg @ref LL_HRTIM_TIMER_MASTER
11268 * @arg @ref LL_HRTIM_TIMER_A
11269 * @arg @ref LL_HRTIM_TIMER_B
11270 * @arg @ref LL_HRTIM_TIMER_C
11271 * @arg @ref LL_HRTIM_TIMER_D
11272 * @arg @ref LL_HRTIM_TIMER_E
11273 * @arg @ref LL_HRTIM_TIMER_F
11274 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11275 */
LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11276 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11277 {
11278 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11279 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11280 REG_OFFSET_TAB_TIMER[iTimer]));
11281
11282 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
11283 }
11284
11285 /**
11286 * @brief Clear the capture 1 interrupt flag for a given timer.
11287 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
11288 * @param HRTIMx High Resolution Timer instance
11289 * @param Timer This parameter can be one of the following values:
11290 * @arg @ref LL_HRTIM_TIMER_A
11291 * @arg @ref LL_HRTIM_TIMER_B
11292 * @arg @ref LL_HRTIM_TIMER_C
11293 * @arg @ref LL_HRTIM_TIMER_D
11294 * @arg @ref LL_HRTIM_TIMER_E
11295 * @arg @ref LL_HRTIM_TIMER_F
11296 * @retval None
11297 */
LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11298 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11299 {
11300 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11301 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11302 REG_OFFSET_TAB_TIMER[iTimer]));
11303 SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
11304 }
11305
11306 /**
11307 * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
11308 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
11309 * @param HRTIMx High Resolution Timer instance
11310 * @param Timer This parameter can be one of the following values:
11311 * @arg @ref LL_HRTIM_TIMER_A
11312 * @arg @ref LL_HRTIM_TIMER_B
11313 * @arg @ref LL_HRTIM_TIMER_C
11314 * @arg @ref LL_HRTIM_TIMER_D
11315 * @arg @ref LL_HRTIM_TIMER_E
11316 * @arg @ref LL_HRTIM_TIMER_F
11317 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
11318 */
LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11319 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11320 {
11321 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11322 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11323 REG_OFFSET_TAB_TIMER[iTimer]));
11324
11325 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
11326 }
11327
11328 /**
11329 * @brief Clear the capture 2 interrupt flag for a given timer.
11330 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
11331 * @param HRTIMx High Resolution Timer instance
11332 * @param Timer This parameter can be one of the following values:
11333 * @arg @ref LL_HRTIM_TIMER_A
11334 * @arg @ref LL_HRTIM_TIMER_B
11335 * @arg @ref LL_HRTIM_TIMER_C
11336 * @arg @ref LL_HRTIM_TIMER_D
11337 * @arg @ref LL_HRTIM_TIMER_E
11338 * @arg @ref LL_HRTIM_TIMER_F
11339 * @retval None
11340 */
LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11341 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11342 {
11343 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11344 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11345 REG_OFFSET_TAB_TIMER[iTimer]));
11346 SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
11347 }
11348
11349 /**
11350 * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
11351 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
11352 * @param HRTIMx High Resolution Timer instance
11353 * @param Timer This parameter can be one of the following values:
11354 * @arg @ref LL_HRTIM_TIMER_A
11355 * @arg @ref LL_HRTIM_TIMER_B
11356 * @arg @ref LL_HRTIM_TIMER_C
11357 * @arg @ref LL_HRTIM_TIMER_D
11358 * @arg @ref LL_HRTIM_TIMER_E
11359 * @arg @ref LL_HRTIM_TIMER_F
11360 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
11361 */
LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11362 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11363 {
11364 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11365 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11366 REG_OFFSET_TAB_TIMER[iTimer]));
11367
11368 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
11369 }
11370
11371 /**
11372 * @brief Clear the output 1 set interrupt flag for a given timer.
11373 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
11374 * @param HRTIMx High Resolution Timer instance
11375 * @param Timer This parameter can be one of the following values:
11376 * @arg @ref LL_HRTIM_TIMER_A
11377 * @arg @ref LL_HRTIM_TIMER_B
11378 * @arg @ref LL_HRTIM_TIMER_C
11379 * @arg @ref LL_HRTIM_TIMER_D
11380 * @arg @ref LL_HRTIM_TIMER_E
11381 * @arg @ref LL_HRTIM_TIMER_F
11382 * @retval None
11383 */
LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11384 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11385 {
11386 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11387 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11388 REG_OFFSET_TAB_TIMER[iTimer]));
11389 SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
11390 }
11391
11392 /**
11393 * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
11394 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
11395 * @param HRTIMx High Resolution Timer instance
11396 * @param Timer This parameter can be one of the following values:
11397 * @arg @ref LL_HRTIM_TIMER_A
11398 * @arg @ref LL_HRTIM_TIMER_B
11399 * @arg @ref LL_HRTIM_TIMER_C
11400 * @arg @ref LL_HRTIM_TIMER_D
11401 * @arg @ref LL_HRTIM_TIMER_E
11402 * @arg @ref LL_HRTIM_TIMER_F
11403 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
11404 */
LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11405 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11406 {
11407 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11408 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11409 REG_OFFSET_TAB_TIMER[iTimer]));
11410
11411 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
11412 }
11413
11414 /**
11415 * @brief Clear the output 1 reset interrupt flag for a given timer.
11416 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
11417 * @param HRTIMx High Resolution Timer instance
11418 * @param Timer This parameter can be one of the following values:
11419 * @arg @ref LL_HRTIM_TIMER_A
11420 * @arg @ref LL_HRTIM_TIMER_B
11421 * @arg @ref LL_HRTIM_TIMER_C
11422 * @arg @ref LL_HRTIM_TIMER_D
11423 * @arg @ref LL_HRTIM_TIMER_E
11424 * @arg @ref LL_HRTIM_TIMER_F
11425 * @retval None
11426 */
LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11427 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11428 {
11429 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11430 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11431 REG_OFFSET_TAB_TIMER[iTimer]));
11432 SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
11433 }
11434
11435 /**
11436 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
11437 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
11438 * @param HRTIMx High Resolution Timer instance
11439 * @param Timer This parameter can be one of the following values:
11440 * @arg @ref LL_HRTIM_TIMER_A
11441 * @arg @ref LL_HRTIM_TIMER_B
11442 * @arg @ref LL_HRTIM_TIMER_C
11443 * @arg @ref LL_HRTIM_TIMER_D
11444 * @arg @ref LL_HRTIM_TIMER_E
11445 * @arg @ref LL_HRTIM_TIMER_F
11446 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
11447 */
LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11448 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11449 {
11450 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11451 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11452 REG_OFFSET_TAB_TIMER[iTimer]));
11453
11454 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
11455 }
11456
11457 /**
11458 * @brief Clear the output 2 set interrupt flag for a given timer.
11459 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
11460 * @param HRTIMx High Resolution Timer instance
11461 * @param Timer This parameter can be one of the following values:
11462 * @arg @ref LL_HRTIM_TIMER_A
11463 * @arg @ref LL_HRTIM_TIMER_B
11464 * @arg @ref LL_HRTIM_TIMER_C
11465 * @arg @ref LL_HRTIM_TIMER_D
11466 * @arg @ref LL_HRTIM_TIMER_E
11467 * @arg @ref LL_HRTIM_TIMER_F
11468 * @retval None
11469 */
LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11470 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11471 {
11472 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11473 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11474 REG_OFFSET_TAB_TIMER[iTimer]));
11475 SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
11476 }
11477
11478 /**
11479 * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
11480 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
11481 * @param HRTIMx High Resolution Timer instance
11482 * @param Timer This parameter can be one of the following values:
11483 * @arg @ref LL_HRTIM_TIMER_A
11484 * @arg @ref LL_HRTIM_TIMER_B
11485 * @arg @ref LL_HRTIM_TIMER_C
11486 * @arg @ref LL_HRTIM_TIMER_D
11487 * @arg @ref LL_HRTIM_TIMER_E
11488 * @arg @ref LL_HRTIM_TIMER_F
11489 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
11490 */
LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11491 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11492 {
11493 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11494 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11495 REG_OFFSET_TAB_TIMER[iTimer]));
11496
11497 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
11498 }
11499
11500 /**
11501 * @brief Clear the output 2reset interrupt flag for a given timer.
11502 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
11503 * @param HRTIMx High Resolution Timer instance
11504 * @param Timer This parameter can be one of the following values:
11505 * @arg @ref LL_HRTIM_TIMER_A
11506 * @arg @ref LL_HRTIM_TIMER_B
11507 * @arg @ref LL_HRTIM_TIMER_C
11508 * @arg @ref LL_HRTIM_TIMER_D
11509 * @arg @ref LL_HRTIM_TIMER_E
11510 * @arg @ref LL_HRTIM_TIMER_F
11511 * @retval None
11512 */
LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11513 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11514 {
11515 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11516 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11517 REG_OFFSET_TAB_TIMER[iTimer]));
11518 SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
11519 }
11520
11521 /**
11522 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
11523 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
11524 * @param HRTIMx High Resolution Timer instance
11525 * @param Timer This parameter can be one of the following values:
11526 * @arg @ref LL_HRTIM_TIMER_A
11527 * @arg @ref LL_HRTIM_TIMER_B
11528 * @arg @ref LL_HRTIM_TIMER_C
11529 * @arg @ref LL_HRTIM_TIMER_D
11530 * @arg @ref LL_HRTIM_TIMER_E
11531 * @arg @ref LL_HRTIM_TIMER_F
11532 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
11533 */
LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11534 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11535 {
11536 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11537 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11538 REG_OFFSET_TAB_TIMER[iTimer]));
11539
11540 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
11541 }
11542
11543 /**
11544 * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
11545 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
11546 * @param HRTIMx High Resolution Timer instance
11547 * @param Timer This parameter can be one of the following values:
11548 * @arg @ref LL_HRTIM_TIMER_A
11549 * @arg @ref LL_HRTIM_TIMER_B
11550 * @arg @ref LL_HRTIM_TIMER_C
11551 * @arg @ref LL_HRTIM_TIMER_D
11552 * @arg @ref LL_HRTIM_TIMER_E
11553 * @arg @ref LL_HRTIM_TIMER_F
11554 * @retval None
11555 */
LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11556 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11557 {
11558 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11559 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11560 REG_OFFSET_TAB_TIMER[iTimer]));
11561 SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
11562 }
11563
11564 /**
11565 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
11566 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
11567 * @param HRTIMx High Resolution Timer instance
11568 * @param Timer This parameter can be one of the following values:
11569 * @arg @ref LL_HRTIM_TIMER_A
11570 * @arg @ref LL_HRTIM_TIMER_B
11571 * @arg @ref LL_HRTIM_TIMER_C
11572 * @arg @ref LL_HRTIM_TIMER_D
11573 * @arg @ref LL_HRTIM_TIMER_E
11574 * @arg @ref LL_HRTIM_TIMER_F
11575 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
11576 */
LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11577 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11578 {
11579 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11580 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11581 REG_OFFSET_TAB_TIMER[iTimer]));
11582
11583 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
11584 }
11585
11586 /**
11587 * @brief Clear the delayed protection interrupt flag for a given timer.
11588 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
11589 * @param HRTIMx High Resolution Timer instance
11590 * @param Timer This parameter can be one of the following values:
11591 * @arg @ref LL_HRTIM_TIMER_A
11592 * @arg @ref LL_HRTIM_TIMER_B
11593 * @arg @ref LL_HRTIM_TIMER_C
11594 * @arg @ref LL_HRTIM_TIMER_D
11595 * @arg @ref LL_HRTIM_TIMER_E
11596 * @arg @ref LL_HRTIM_TIMER_F
11597 * @retval None
11598 */
LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11599 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11600 {
11601 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11602 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11603 REG_OFFSET_TAB_TIMER[iTimer]));
11604 SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
11605 }
11606
11607 /**
11608 * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
11609 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
11610 * @param HRTIMx High Resolution Timer instance
11611 * @param Timer This parameter can be one of the following values:
11612 * @arg @ref LL_HRTIM_TIMER_A
11613 * @arg @ref LL_HRTIM_TIMER_B
11614 * @arg @ref LL_HRTIM_TIMER_C
11615 * @arg @ref LL_HRTIM_TIMER_D
11616 * @arg @ref LL_HRTIM_TIMER_E
11617 * @arg @ref LL_HRTIM_TIMER_F
11618 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
11619 */
LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)11620 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11621 {
11622 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11623 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11624 REG_OFFSET_TAB_TIMER[iTimer]));
11625
11626 return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
11627 }
11628
11629 /**
11630 * @}
11631 */
11632
11633 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
11634 * @{
11635 */
11636
11637 /**
11638 * @brief Enable the fault 1 interrupt.
11639 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
11640 * @param HRTIMx High Resolution Timer instance
11641 * @retval None
11642 */
LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef * HRTIMx)11643 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
11644 {
11645 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
11646 }
11647
11648 /**
11649 * @brief Disable the fault 1 interrupt.
11650 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
11651 * @param HRTIMx High Resolution Timer instance
11652 * @retval None
11653 */
LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef * HRTIMx)11654 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
11655 {
11656 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
11657 }
11658
11659 /**
11660 * @brief Indicate whether the fault 1 interrupt is enabled.
11661 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
11662 * @param HRTIMx High Resolution Timer instance
11663 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
11664 */
LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef * HRTIMx)11665 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx)
11666 {
11667 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
11668 }
11669
11670 /**
11671 * @brief Enable the fault 2 interrupt.
11672 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
11673 * @param HRTIMx High Resolution Timer instance
11674 * @retval None
11675 */
LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef * HRTIMx)11676 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
11677 {
11678 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
11679 }
11680
11681 /**
11682 * @brief Disable the fault 2 interrupt.
11683 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
11684 * @param HRTIMx High Resolution Timer instance
11685 * @retval None
11686 */
LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef * HRTIMx)11687 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
11688 {
11689 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
11690 }
11691
11692 /**
11693 * @brief Indicate whether the fault 2 interrupt is enabled.
11694 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
11695 * @param HRTIMx High Resolution Timer instance
11696 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
11697 */
LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef * HRTIMx)11698 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx)
11699 {
11700 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
11701 }
11702
11703 /**
11704 * @brief Enable the fault 3 interrupt.
11705 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
11706 * @param HRTIMx High Resolution Timer instance
11707 * @retval None
11708 */
LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef * HRTIMx)11709 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
11710 {
11711 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
11712 }
11713
11714 /**
11715 * @brief Disable the fault 3 interrupt.
11716 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
11717 * @param HRTIMx High Resolution Timer instance
11718 * @retval None
11719 */
LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef * HRTIMx)11720 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
11721 {
11722 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
11723 }
11724
11725 /**
11726 * @brief Indicate whether the fault 3 interrupt is enabled.
11727 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
11728 * @param HRTIMx High Resolution Timer instance
11729 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
11730 */
LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef * HRTIMx)11731 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx)
11732 {
11733 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
11734 }
11735
11736 /**
11737 * @brief Enable the fault 4 interrupt.
11738 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
11739 * @param HRTIMx High Resolution Timer instance
11740 * @retval None
11741 */
LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef * HRTIMx)11742 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
11743 {
11744 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
11745 }
11746
11747 /**
11748 * @brief Disable the fault 4 interrupt.
11749 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
11750 * @param HRTIMx High Resolution Timer instance
11751 * @retval None
11752 */
LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef * HRTIMx)11753 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
11754 {
11755 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
11756 }
11757
11758 /**
11759 * @brief Indicate whether the fault 4 interrupt is enabled.
11760 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
11761 * @param HRTIMx High Resolution Timer instance
11762 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
11763 */
LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef * HRTIMx)11764 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx)
11765 {
11766 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
11767 }
11768
11769 /**
11770 * @brief Enable the fault 5 interrupt.
11771 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
11772 * @param HRTIMx High Resolution Timer instance
11773 * @retval None
11774 */
LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef * HRTIMx)11775 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
11776 {
11777 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
11778 }
11779
11780 /**
11781 * @brief Disable the fault 5 interrupt.
11782 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
11783 * @param HRTIMx High Resolution Timer instance
11784 * @retval None
11785 */
LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef * HRTIMx)11786 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
11787 {
11788 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
11789 }
11790
11791 /**
11792 * @brief Indicate whether the fault 5 interrupt is enabled.
11793 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
11794 * @param HRTIMx High Resolution Timer instance
11795 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
11796 */
LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef * HRTIMx)11797 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx)
11798 {
11799 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
11800 }
11801
11802 /**
11803 * @brief Enable the fault 6 interrupt.
11804 * @rmtoll IER FLT6IE LL_HRTIM_EnableIT_FLT6
11805 * @param HRTIMx High Resolution Timer instance
11806 * @retval None
11807 */
LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef * HRTIMx)11808 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef *HRTIMx)
11809 {
11810 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
11811 }
11812
11813 /**
11814 * @brief Disable the fault 6 interrupt.
11815 * @rmtoll IER FLT6IE LL_HRTIM_DisableIT_FLT6
11816 * @param HRTIMx High Resolution Timer instance
11817 * @retval None
11818 */
LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef * HRTIMx)11819 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef *HRTIMx)
11820 {
11821 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
11822 }
11823
11824 /**
11825 * @brief Indicate whether the fault 6 interrupt is enabled.
11826 * @rmtoll IER FLT6IE LL_HRTIM_IsEnabledIT_FLT6
11827 * @param HRTIMx High Resolution Timer instance
11828 * @retval State of FLT6IE bit in HRTIM_IER register (1 or 0).
11829 */
LL_HRTIM_IsEnabledIT_FLT6(const HRTIM_TypeDef * HRTIMx)11830 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT6(const HRTIM_TypeDef *HRTIMx)
11831 {
11832 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6) == (HRTIM_IER_FLT6)) ? 1UL : 0UL);
11833 }
11834
11835 /**
11836 * @brief Enable the system fault interrupt.
11837 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
11838 * @param HRTIMx High Resolution Timer instance
11839 * @retval None
11840 */
LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)11841 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11842 {
11843 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
11844 }
11845
11846 /**
11847 * @brief Disable the system fault interrupt.
11848 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
11849 * @param HRTIMx High Resolution Timer instance
11850 * @retval None
11851 */
LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)11852 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11853 {
11854 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
11855 }
11856
11857 /**
11858 * @brief Indicate whether the system fault interrupt is enabled.
11859 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
11860 * @param HRTIMx High Resolution Timer instance
11861 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
11862 */
LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef * HRTIMx)11863 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx)
11864 {
11865 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
11866 }
11867
11868 /**
11869 * @brief Enable the DLL ready interrupt.
11870 * @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
11871 * @param HRTIMx High Resolution Timer instance
11872 * @retval None
11873 */
LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef * HRTIMx)11874 __STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11875 {
11876 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
11877 }
11878
11879 /**
11880 * @brief Disable the DLL ready interrupt.
11881 * @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
11882 * @param HRTIMx High Resolution Timer instance
11883 * @retval None
11884 */
LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef * HRTIMx)11885 __STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11886 {
11887 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
11888 }
11889
11890 /**
11891 * @brief Indicate whether the DLL ready interrupt is enabled.
11892 * @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
11893 * @param HRTIMx High Resolution Timer instance
11894 * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
11895 */
LL_HRTIM_IsEnabledIT_DLLRDY(const HRTIM_TypeDef * HRTIMx)11896 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(const HRTIM_TypeDef *HRTIMx)
11897 {
11898 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL);
11899 }
11900
11901 /**
11902 * @brief Enable the burst mode period interrupt.
11903 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
11904 * @param HRTIMx High Resolution Timer instance
11905 * @retval None
11906 */
LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef * HRTIMx)11907 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
11908 {
11909 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
11910 }
11911
11912 /**
11913 * @brief Disable the burst mode period interrupt.
11914 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
11915 * @param HRTIMx High Resolution Timer instance
11916 * @retval None
11917 */
LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef * HRTIMx)11918 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
11919 {
11920 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
11921 }
11922
11923 /**
11924 * @brief Indicate whether the burst mode period interrupt is enabled.
11925 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
11926 * @param HRTIMx High Resolution Timer instance
11927 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
11928 */
LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef * HRTIMx)11929 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx)
11930 {
11931 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
11932 }
11933
11934 /**
11935 * @brief Enable the synchronization input interrupt.
11936 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
11937 * @param HRTIMx High Resolution Timer instance
11938 * @retval None
11939 */
LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef * HRTIMx)11940 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
11941 {
11942 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
11943 }
11944
11945 /**
11946 * @brief Disable the synchronization input interrupt.
11947 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
11948 * @param HRTIMx High Resolution Timer instance
11949 * @retval None
11950 */
LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef * HRTIMx)11951 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
11952 {
11953 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
11954 }
11955
11956 /**
11957 * @brief Indicate whether the synchronization input interrupt is enabled.
11958 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
11959 * @param HRTIMx High Resolution Timer instance
11960 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
11961 */
LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef * HRTIMx)11962 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx)
11963 {
11964 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
11965 }
11966
11967 /**
11968 * @brief Enable the update interrupt for a given timer.
11969 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
11970 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
11971 * @param HRTIMx High Resolution Timer instance
11972 * @param Timer This parameter can be one of the following values:
11973 * @arg @ref LL_HRTIM_TIMER_MASTER
11974 * @arg @ref LL_HRTIM_TIMER_A
11975 * @arg @ref LL_HRTIM_TIMER_B
11976 * @arg @ref LL_HRTIM_TIMER_C
11977 * @arg @ref LL_HRTIM_TIMER_D
11978 * @arg @ref LL_HRTIM_TIMER_E
11979 * @arg @ref LL_HRTIM_TIMER_F
11980 * @retval None
11981 */
LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11982 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11983 {
11984 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11985 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
11986 REG_OFFSET_TAB_TIMER[iTimer]));
11987 SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
11988 }
11989
11990 /**
11991 * @brief Disable the update interrupt for a given timer.
11992 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
11993 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
11994 * @param HRTIMx High Resolution Timer instance
11995 * @param Timer This parameter can be one of the following values:
11996 * @arg @ref LL_HRTIM_TIMER_MASTER
11997 * @arg @ref LL_HRTIM_TIMER_A
11998 * @arg @ref LL_HRTIM_TIMER_B
11999 * @arg @ref LL_HRTIM_TIMER_C
12000 * @arg @ref LL_HRTIM_TIMER_D
12001 * @arg @ref LL_HRTIM_TIMER_E
12002 * @arg @ref LL_HRTIM_TIMER_F
12003 * @retval None
12004 */
LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12005 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12006 {
12007 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12008 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12009 REG_OFFSET_TAB_TIMER[iTimer]));
12010 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
12011 }
12012
12013 /**
12014 * @brief Indicate whether the update interrupt is enabled for a given timer.
12015 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
12016 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
12017 * @param HRTIMx High Resolution Timer instance
12018 * @param Timer This parameter can be one of the following values:
12019 * @arg @ref LL_HRTIM_TIMER_MASTER
12020 * @arg @ref LL_HRTIM_TIMER_A
12021 * @arg @ref LL_HRTIM_TIMER_B
12022 * @arg @ref LL_HRTIM_TIMER_C
12023 * @arg @ref LL_HRTIM_TIMER_D
12024 * @arg @ref LL_HRTIM_TIMER_E
12025 * @arg @ref LL_HRTIM_TIMER_F
12026 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12027 */
LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12028 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12029 {
12030 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12031 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12032 REG_OFFSET_TAB_TIMER[iTimer]));
12033
12034 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
12035 }
12036
12037 /**
12038 * @brief Enable the repetition interrupt for a given timer.
12039 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
12040 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
12041 * @param HRTIMx High Resolution Timer instance
12042 * @param Timer This parameter can be one of the following values:
12043 * @arg @ref LL_HRTIM_TIMER_MASTER
12044 * @arg @ref LL_HRTIM_TIMER_A
12045 * @arg @ref LL_HRTIM_TIMER_B
12046 * @arg @ref LL_HRTIM_TIMER_C
12047 * @arg @ref LL_HRTIM_TIMER_D
12048 * @arg @ref LL_HRTIM_TIMER_E
12049 * @arg @ref LL_HRTIM_TIMER_F
12050 * @retval None
12051 */
LL_HRTIM_EnableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12052 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12053 {
12054 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12055 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12056 REG_OFFSET_TAB_TIMER[iTimer]));
12057 SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
12058 }
12059
12060 /**
12061 * @brief Disable the repetition interrupt for a given timer.
12062 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
12063 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
12064 * @param HRTIMx High Resolution Timer instance
12065 * @param Timer This parameter can be one of the following values:
12066 * @arg @ref LL_HRTIM_TIMER_MASTER
12067 * @arg @ref LL_HRTIM_TIMER_A
12068 * @arg @ref LL_HRTIM_TIMER_B
12069 * @arg @ref LL_HRTIM_TIMER_C
12070 * @arg @ref LL_HRTIM_TIMER_D
12071 * @arg @ref LL_HRTIM_TIMER_E
12072 * @arg @ref LL_HRTIM_TIMER_F
12073 * @retval None
12074 */
LL_HRTIM_DisableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12075 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12076 {
12077 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12078 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12079 REG_OFFSET_TAB_TIMER[iTimer]));
12080 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
12081 }
12082
12083 /**
12084 * @brief Indicate whether the repetition interrupt is enabled for a given timer.
12085 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
12086 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
12087 * @param HRTIMx High Resolution Timer instance
12088 * @param Timer This parameter can be one of the following values:
12089 * @arg @ref LL_HRTIM_TIMER_MASTER
12090 * @arg @ref LL_HRTIM_TIMER_A
12091 * @arg @ref LL_HRTIM_TIMER_B
12092 * @arg @ref LL_HRTIM_TIMER_C
12093 * @arg @ref LL_HRTIM_TIMER_D
12094 * @arg @ref LL_HRTIM_TIMER_E
12095 * @arg @ref LL_HRTIM_TIMER_F
12096 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12097 */
LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12098 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12099 {
12100 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12101 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12102 REG_OFFSET_TAB_TIMER[iTimer]));
12103
12104 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
12105 }
12106
12107 /**
12108 * @brief Enable the compare 1 interrupt for a given timer.
12109 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
12110 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
12111 * @param HRTIMx High Resolution Timer instance
12112 * @param Timer This parameter can be one of the following values:
12113 * @arg @ref LL_HRTIM_TIMER_MASTER
12114 * @arg @ref LL_HRTIM_TIMER_A
12115 * @arg @ref LL_HRTIM_TIMER_B
12116 * @arg @ref LL_HRTIM_TIMER_C
12117 * @arg @ref LL_HRTIM_TIMER_D
12118 * @arg @ref LL_HRTIM_TIMER_E
12119 * @arg @ref LL_HRTIM_TIMER_F
12120 * @retval None
12121 */
LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12122 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12123 {
12124 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12125 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12126 REG_OFFSET_TAB_TIMER[iTimer]));
12127 SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
12128 }
12129
12130 /**
12131 * @brief Disable the compare 1 interrupt for a given timer.
12132 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
12133 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
12134 * @param HRTIMx High Resolution Timer instance
12135 * @param Timer This parameter can be one of the following values:
12136 * @arg @ref LL_HRTIM_TIMER_MASTER
12137 * @arg @ref LL_HRTIM_TIMER_A
12138 * @arg @ref LL_HRTIM_TIMER_B
12139 * @arg @ref LL_HRTIM_TIMER_C
12140 * @arg @ref LL_HRTIM_TIMER_D
12141 * @arg @ref LL_HRTIM_TIMER_E
12142 * @arg @ref LL_HRTIM_TIMER_F
12143 * @retval None
12144 */
LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12145 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12146 {
12147 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12148 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12149 REG_OFFSET_TAB_TIMER[iTimer]));
12150 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
12151 }
12152
12153 /**
12154 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
12155 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
12156 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
12157 * @param HRTIMx High Resolution Timer instance
12158 * @param Timer This parameter can be one of the following values:
12159 * @arg @ref LL_HRTIM_TIMER_MASTER
12160 * @arg @ref LL_HRTIM_TIMER_A
12161 * @arg @ref LL_HRTIM_TIMER_B
12162 * @arg @ref LL_HRTIM_TIMER_C
12163 * @arg @ref LL_HRTIM_TIMER_D
12164 * @arg @ref LL_HRTIM_TIMER_E
12165 * @arg @ref LL_HRTIM_TIMER_F
12166 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12167 */
LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12168 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12169 {
12170 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12171 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12172 REG_OFFSET_TAB_TIMER[iTimer]));
12173
12174 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
12175 }
12176
12177 /**
12178 * @brief Enable the compare 2 interrupt for a given timer.
12179 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
12180 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
12181 * @param HRTIMx High Resolution Timer instance
12182 * @param Timer This parameter can be one of the following values:
12183 * @arg @ref LL_HRTIM_TIMER_MASTER
12184 * @arg @ref LL_HRTIM_TIMER_A
12185 * @arg @ref LL_HRTIM_TIMER_B
12186 * @arg @ref LL_HRTIM_TIMER_C
12187 * @arg @ref LL_HRTIM_TIMER_D
12188 * @arg @ref LL_HRTIM_TIMER_E
12189 * @arg @ref LL_HRTIM_TIMER_F
12190 * @retval None
12191 */
LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12192 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12193 {
12194 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12195 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12196 REG_OFFSET_TAB_TIMER[iTimer]));
12197 SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
12198 }
12199
12200 /**
12201 * @brief Disable the compare 2 interrupt for a given timer.
12202 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
12203 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
12204 * @param HRTIMx High Resolution Timer instance
12205 * @param Timer This parameter can be one of the following values:
12206 * @arg @ref LL_HRTIM_TIMER_MASTER
12207 * @arg @ref LL_HRTIM_TIMER_A
12208 * @arg @ref LL_HRTIM_TIMER_B
12209 * @arg @ref LL_HRTIM_TIMER_C
12210 * @arg @ref LL_HRTIM_TIMER_D
12211 * @arg @ref LL_HRTIM_TIMER_E
12212 * @arg @ref LL_HRTIM_TIMER_F
12213 * @retval None
12214 */
LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12215 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12216 {
12217 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12218 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12219 REG_OFFSET_TAB_TIMER[iTimer]));
12220 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
12221 }
12222
12223 /**
12224 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
12225 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
12226 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
12227 * @param HRTIMx High Resolution Timer instance
12228 * @param Timer This parameter can be one of the following values:
12229 * @arg @ref LL_HRTIM_TIMER_MASTER
12230 * @arg @ref LL_HRTIM_TIMER_A
12231 * @arg @ref LL_HRTIM_TIMER_B
12232 * @arg @ref LL_HRTIM_TIMER_C
12233 * @arg @ref LL_HRTIM_TIMER_D
12234 * @arg @ref LL_HRTIM_TIMER_E
12235 * @arg @ref LL_HRTIM_TIMER_F
12236 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12237 */
LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12238 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12239 {
12240 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12241 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12242 REG_OFFSET_TAB_TIMER[iTimer]));
12243
12244 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
12245 }
12246
12247 /**
12248 * @brief Enable the compare 3 interrupt for a given timer.
12249 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
12250 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
12251 * @param HRTIMx High Resolution Timer instance
12252 * @param Timer This parameter can be one of the following values:
12253 * @arg @ref LL_HRTIM_TIMER_MASTER
12254 * @arg @ref LL_HRTIM_TIMER_A
12255 * @arg @ref LL_HRTIM_TIMER_B
12256 * @arg @ref LL_HRTIM_TIMER_C
12257 * @arg @ref LL_HRTIM_TIMER_D
12258 * @arg @ref LL_HRTIM_TIMER_E
12259 * @arg @ref LL_HRTIM_TIMER_F
12260 * @retval None
12261 */
LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12262 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12263 {
12264 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12265 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12266 REG_OFFSET_TAB_TIMER[iTimer]));
12267 SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
12268 }
12269
12270 /**
12271 * @brief Disable the compare 3 interrupt for a given timer.
12272 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
12273 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
12274 * @param HRTIMx High Resolution Timer instance
12275 * @param Timer This parameter can be one of the following values:
12276 * @arg @ref LL_HRTIM_TIMER_MASTER
12277 * @arg @ref LL_HRTIM_TIMER_A
12278 * @arg @ref LL_HRTIM_TIMER_B
12279 * @arg @ref LL_HRTIM_TIMER_C
12280 * @arg @ref LL_HRTIM_TIMER_D
12281 * @arg @ref LL_HRTIM_TIMER_E
12282 * @arg @ref LL_HRTIM_TIMER_F
12283 * @retval None
12284 */
LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12285 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12286 {
12287 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12288 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12289 REG_OFFSET_TAB_TIMER[iTimer]));
12290 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
12291 }
12292
12293 /**
12294 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
12295 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
12296 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
12297 * @param HRTIMx High Resolution Timer instance
12298 * @param Timer This parameter can be one of the following values:
12299 * @arg @ref LL_HRTIM_TIMER_MASTER
12300 * @arg @ref LL_HRTIM_TIMER_A
12301 * @arg @ref LL_HRTIM_TIMER_B
12302 * @arg @ref LL_HRTIM_TIMER_C
12303 * @arg @ref LL_HRTIM_TIMER_D
12304 * @arg @ref LL_HRTIM_TIMER_E
12305 * @arg @ref LL_HRTIM_TIMER_F
12306 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12307 */
LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12308 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12309 {
12310 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12311 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12312 REG_OFFSET_TAB_TIMER[iTimer]));
12313
12314 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
12315 }
12316
12317 /**
12318 * @brief Enable the compare 4 interrupt for a given timer.
12319 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
12320 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
12321 * @param HRTIMx High Resolution Timer instance
12322 * @param Timer This parameter can be one of the following values:
12323 * @arg @ref LL_HRTIM_TIMER_MASTER
12324 * @arg @ref LL_HRTIM_TIMER_A
12325 * @arg @ref LL_HRTIM_TIMER_B
12326 * @arg @ref LL_HRTIM_TIMER_C
12327 * @arg @ref LL_HRTIM_TIMER_D
12328 * @arg @ref LL_HRTIM_TIMER_E
12329 * @arg @ref LL_HRTIM_TIMER_F
12330 * @retval None
12331 */
LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12332 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12333 {
12334 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12335 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12336 REG_OFFSET_TAB_TIMER[iTimer]));
12337 SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
12338 }
12339
12340 /**
12341 * @brief Disable the compare 4 interrupt for a given timer.
12342 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
12343 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
12344 * @param HRTIMx High Resolution Timer instance
12345 * @param Timer This parameter can be one of the following values:
12346 * @arg @ref LL_HRTIM_TIMER_MASTER
12347 * @arg @ref LL_HRTIM_TIMER_A
12348 * @arg @ref LL_HRTIM_TIMER_B
12349 * @arg @ref LL_HRTIM_TIMER_C
12350 * @arg @ref LL_HRTIM_TIMER_D
12351 * @arg @ref LL_HRTIM_TIMER_E
12352 * @arg @ref LL_HRTIM_TIMER_F
12353 * @retval None
12354 */
LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12355 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12356 {
12357 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12358 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12359 REG_OFFSET_TAB_TIMER[iTimer]));
12360 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
12361 }
12362
12363 /**
12364 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
12365 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
12366 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
12367 * @param HRTIMx High Resolution Timer instance
12368 * @param Timer This parameter can be one of the following values:
12369 * @arg @ref LL_HRTIM_TIMER_MASTER
12370 * @arg @ref LL_HRTIM_TIMER_A
12371 * @arg @ref LL_HRTIM_TIMER_B
12372 * @arg @ref LL_HRTIM_TIMER_C
12373 * @arg @ref LL_HRTIM_TIMER_D
12374 * @arg @ref LL_HRTIM_TIMER_E
12375 * @arg @ref LL_HRTIM_TIMER_F
12376 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12377 */
LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12378 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12379 {
12380 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12381 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12382 REG_OFFSET_TAB_TIMER[iTimer]));
12383
12384 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
12385 }
12386
12387 /**
12388 * @brief Enable the capture 1 interrupt for a given timer.
12389 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
12390 * @param HRTIMx High Resolution Timer instance
12391 * @param Timer This parameter can be one of the following values:
12392 * @arg @ref LL_HRTIM_TIMER_A
12393 * @arg @ref LL_HRTIM_TIMER_B
12394 * @arg @ref LL_HRTIM_TIMER_C
12395 * @arg @ref LL_HRTIM_TIMER_D
12396 * @arg @ref LL_HRTIM_TIMER_E
12397 * @arg @ref LL_HRTIM_TIMER_F
12398 * @retval None
12399 */
LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12400 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12401 {
12402 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12403 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12404 REG_OFFSET_TAB_TIMER[iTimer]));
12405 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
12406 }
12407
12408 /**
12409 * @brief Enable the capture 1 interrupt for a given timer.
12410 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
12411 * @param HRTIMx High Resolution Timer instance
12412 * @param Timer This parameter can be one of the following values:
12413 * @arg @ref LL_HRTIM_TIMER_A
12414 * @arg @ref LL_HRTIM_TIMER_B
12415 * @arg @ref LL_HRTIM_TIMER_C
12416 * @arg @ref LL_HRTIM_TIMER_D
12417 * @arg @ref LL_HRTIM_TIMER_E
12418 * @arg @ref LL_HRTIM_TIMER_F
12419 * @retval None
12420 */
LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12421 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12422 {
12423 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12424 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12425 REG_OFFSET_TAB_TIMER[iTimer]));
12426 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
12427 }
12428
12429 /**
12430 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
12431 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
12432 * @param HRTIMx High Resolution Timer instance
12433 * @param Timer This parameter can be one of the following values:
12434 * @arg @ref LL_HRTIM_TIMER_A
12435 * @arg @ref LL_HRTIM_TIMER_B
12436 * @arg @ref LL_HRTIM_TIMER_C
12437 * @arg @ref LL_HRTIM_TIMER_D
12438 * @arg @ref LL_HRTIM_TIMER_E
12439 * @arg @ref LL_HRTIM_TIMER_F
12440 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
12441 */
LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12442 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12443 {
12444 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12445 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12446 REG_OFFSET_TAB_TIMER[iTimer]));
12447
12448 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
12449 }
12450
12451 /**
12452 * @brief Enable the capture 2 interrupt for a given timer.
12453 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
12454 * @param HRTIMx High Resolution Timer instance
12455 * @param Timer This parameter can be one of the following values:
12456 * @arg @ref LL_HRTIM_TIMER_A
12457 * @arg @ref LL_HRTIM_TIMER_B
12458 * @arg @ref LL_HRTIM_TIMER_C
12459 * @arg @ref LL_HRTIM_TIMER_D
12460 * @arg @ref LL_HRTIM_TIMER_E
12461 * @arg @ref LL_HRTIM_TIMER_F
12462 * @retval None
12463 */
LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12464 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12465 {
12466 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12467 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12468 REG_OFFSET_TAB_TIMER[iTimer]));
12469 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
12470 }
12471
12472 /**
12473 * @brief Enable the capture 2 interrupt for a given timer.
12474 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
12475 * @param HRTIMx High Resolution Timer instance
12476 * @param Timer This parameter can be one of the following values:
12477 * @arg @ref LL_HRTIM_TIMER_A
12478 * @arg @ref LL_HRTIM_TIMER_B
12479 * @arg @ref LL_HRTIM_TIMER_C
12480 * @arg @ref LL_HRTIM_TIMER_D
12481 * @arg @ref LL_HRTIM_TIMER_E
12482 * @arg @ref LL_HRTIM_TIMER_F
12483 * @retval None
12484 */
LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12485 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12486 {
12487 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12488 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12489 REG_OFFSET_TAB_TIMER[iTimer]));
12490 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
12491 }
12492
12493 /**
12494 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
12495 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
12496 * @param HRTIMx High Resolution Timer instance
12497 * @param Timer This parameter can be one of the following values:
12498 * @arg @ref LL_HRTIM_TIMER_A
12499 * @arg @ref LL_HRTIM_TIMER_B
12500 * @arg @ref LL_HRTIM_TIMER_C
12501 * @arg @ref LL_HRTIM_TIMER_D
12502 * @arg @ref LL_HRTIM_TIMER_E
12503 * @arg @ref LL_HRTIM_TIMER_F
12504 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
12505 */
LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12506 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12507 {
12508 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12509 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12510 REG_OFFSET_TAB_TIMER[iTimer]));
12511
12512 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
12513 }
12514
12515 /**
12516 * @brief Enable the output 1 set interrupt for a given timer.
12517 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
12518 * @param HRTIMx High Resolution Timer instance
12519 * @param Timer This parameter can be one of the following values:
12520 * @arg @ref LL_HRTIM_TIMER_A
12521 * @arg @ref LL_HRTIM_TIMER_B
12522 * @arg @ref LL_HRTIM_TIMER_C
12523 * @arg @ref LL_HRTIM_TIMER_D
12524 * @arg @ref LL_HRTIM_TIMER_E
12525 * @arg @ref LL_HRTIM_TIMER_F
12526 * @retval None
12527 */
LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12528 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12529 {
12530 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12531 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12532 REG_OFFSET_TAB_TIMER[iTimer]));
12533 SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
12534 }
12535
12536 /**
12537 * @brief Disable the output 1 set interrupt for a given timer.
12538 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
12539 * @param HRTIMx High Resolution Timer instance
12540 * @param Timer This parameter can be one of the following values:
12541 * @arg @ref LL_HRTIM_TIMER_A
12542 * @arg @ref LL_HRTIM_TIMER_B
12543 * @arg @ref LL_HRTIM_TIMER_C
12544 * @arg @ref LL_HRTIM_TIMER_D
12545 * @arg @ref LL_HRTIM_TIMER_E
12546 * @arg @ref LL_HRTIM_TIMER_F
12547 * @retval None
12548 */
LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12549 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12550 {
12551 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12552 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12553 REG_OFFSET_TAB_TIMER[iTimer]));
12554 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
12555 }
12556
12557 /**
12558 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
12559 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
12560 * @param HRTIMx High Resolution Timer instance
12561 * @param Timer This parameter can be one of the following values:
12562 * @arg @ref LL_HRTIM_TIMER_A
12563 * @arg @ref LL_HRTIM_TIMER_B
12564 * @arg @ref LL_HRTIM_TIMER_C
12565 * @arg @ref LL_HRTIM_TIMER_D
12566 * @arg @ref LL_HRTIM_TIMER_E
12567 * @arg @ref LL_HRTIM_TIMER_F
12568 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12569 */
LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12570 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12571 {
12572 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12573 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12574 REG_OFFSET_TAB_TIMER[iTimer]));
12575
12576 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
12577 }
12578
12579 /**
12580 * @brief Enable the output 1 reset interrupt for a given timer.
12581 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
12582 * @param HRTIMx High Resolution Timer instance
12583 * @param Timer This parameter can be one of the following values:
12584 * @arg @ref LL_HRTIM_TIMER_A
12585 * @arg @ref LL_HRTIM_TIMER_B
12586 * @arg @ref LL_HRTIM_TIMER_C
12587 * @arg @ref LL_HRTIM_TIMER_D
12588 * @arg @ref LL_HRTIM_TIMER_E
12589 * @arg @ref LL_HRTIM_TIMER_F
12590 * @retval None
12591 */
LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12592 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12593 {
12594 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12595 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12596 REG_OFFSET_TAB_TIMER[iTimer]));
12597 SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
12598 }
12599
12600 /**
12601 * @brief Disable the output 1 reset interrupt for a given timer.
12602 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
12603 * @param HRTIMx High Resolution Timer instance
12604 * @param Timer This parameter can be one of the following values:
12605 * @arg @ref LL_HRTIM_TIMER_A
12606 * @arg @ref LL_HRTIM_TIMER_B
12607 * @arg @ref LL_HRTIM_TIMER_C
12608 * @arg @ref LL_HRTIM_TIMER_D
12609 * @arg @ref LL_HRTIM_TIMER_E
12610 * @arg @ref LL_HRTIM_TIMER_F
12611 * @retval None
12612 */
LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12613 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12614 {
12615 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12616 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12617 REG_OFFSET_TAB_TIMER[iTimer]));
12618 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
12619 }
12620
12621 /**
12622 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
12623 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
12624 * @param HRTIMx High Resolution Timer instance
12625 * @param Timer This parameter can be one of the following values:
12626 * @arg @ref LL_HRTIM_TIMER_A
12627 * @arg @ref LL_HRTIM_TIMER_B
12628 * @arg @ref LL_HRTIM_TIMER_C
12629 * @arg @ref LL_HRTIM_TIMER_D
12630 * @arg @ref LL_HRTIM_TIMER_E
12631 * @arg @ref LL_HRTIM_TIMER_F
12632 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12633 */
LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12634 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12635 {
12636 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12637 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12638 REG_OFFSET_TAB_TIMER[iTimer]));
12639
12640 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
12641 }
12642
12643 /**
12644 * @brief Enable the output 2 set interrupt for a given timer.
12645 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
12646 * @param HRTIMx High Resolution Timer instance
12647 * @param Timer This parameter can be one of the following values:
12648 * @arg @ref LL_HRTIM_TIMER_A
12649 * @arg @ref LL_HRTIM_TIMER_B
12650 * @arg @ref LL_HRTIM_TIMER_C
12651 * @arg @ref LL_HRTIM_TIMER_D
12652 * @arg @ref LL_HRTIM_TIMER_E
12653 * @arg @ref LL_HRTIM_TIMER_F
12654 * @retval None
12655 */
LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12656 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12657 {
12658 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12659 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12660 REG_OFFSET_TAB_TIMER[iTimer]));
12661 SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
12662 }
12663
12664 /**
12665 * @brief Disable the output 2 set interrupt for a given timer.
12666 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
12667 * @param HRTIMx High Resolution Timer instance
12668 * @param Timer This parameter can be one of the following values:
12669 * @arg @ref LL_HRTIM_TIMER_A
12670 * @arg @ref LL_HRTIM_TIMER_B
12671 * @arg @ref LL_HRTIM_TIMER_C
12672 * @arg @ref LL_HRTIM_TIMER_D
12673 * @arg @ref LL_HRTIM_TIMER_E
12674 * @arg @ref LL_HRTIM_TIMER_F
12675 * @retval None
12676 */
LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12677 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12678 {
12679 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12680 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12681 REG_OFFSET_TAB_TIMER[iTimer]));
12682 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
12683 }
12684
12685 /**
12686 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
12687 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
12688 * @param HRTIMx High Resolution Timer instance
12689 * @param Timer This parameter can be one of the following values:
12690 * @arg @ref LL_HRTIM_TIMER_A
12691 * @arg @ref LL_HRTIM_TIMER_B
12692 * @arg @ref LL_HRTIM_TIMER_C
12693 * @arg @ref LL_HRTIM_TIMER_D
12694 * @arg @ref LL_HRTIM_TIMER_E
12695 * @arg @ref LL_HRTIM_TIMER_F
12696 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12697 */
LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12698 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12699 {
12700 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12701 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12702 REG_OFFSET_TAB_TIMER[iTimer]));
12703
12704 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
12705 }
12706
12707 /**
12708 * @brief Enable the output 2 reset interrupt for a given timer.
12709 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
12710 * @param HRTIMx High Resolution Timer instance
12711 * @param Timer This parameter can be one of the following values:
12712 * @arg @ref LL_HRTIM_TIMER_A
12713 * @arg @ref LL_HRTIM_TIMER_B
12714 * @arg @ref LL_HRTIM_TIMER_C
12715 * @arg @ref LL_HRTIM_TIMER_D
12716 * @arg @ref LL_HRTIM_TIMER_E
12717 * @arg @ref LL_HRTIM_TIMER_F
12718 * @retval None
12719 */
LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12720 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12721 {
12722 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12723 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12724 REG_OFFSET_TAB_TIMER[iTimer]));
12725 SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
12726 }
12727
12728 /**
12729 * @brief Disable the output 2 reset interrupt for a given timer.
12730 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
12731 * @param HRTIMx High Resolution Timer instance
12732 * @param Timer This parameter can be one of the following values:
12733 * @arg @ref LL_HRTIM_TIMER_A
12734 * @arg @ref LL_HRTIM_TIMER_B
12735 * @arg @ref LL_HRTIM_TIMER_C
12736 * @arg @ref LL_HRTIM_TIMER_D
12737 * @arg @ref LL_HRTIM_TIMER_E
12738 * @arg @ref LL_HRTIM_TIMER_F
12739 * @retval None
12740 */
LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12741 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12742 {
12743 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12744 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12745 REG_OFFSET_TAB_TIMER[iTimer]));
12746 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
12747 }
12748
12749 /**
12750 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
12751 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
12752 * @param HRTIMx High Resolution Timer instance
12753 * @param Timer This parameter can be one of the following values:
12754 * @arg @ref LL_HRTIM_TIMER_A
12755 * @arg @ref LL_HRTIM_TIMER_B
12756 * @arg @ref LL_HRTIM_TIMER_C
12757 * @arg @ref LL_HRTIM_TIMER_D
12758 * @arg @ref LL_HRTIM_TIMER_E
12759 * @arg @ref LL_HRTIM_TIMER_F
12760 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12761 */
LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12762 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12763 {
12764 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12765 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12766 REG_OFFSET_TAB_TIMER[iTimer]));
12767
12768 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
12769 }
12770
12771 /**
12772 * @brief Enable the reset/roll-over interrupt for a given timer.
12773 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
12774 * @param HRTIMx High Resolution Timer instance
12775 * @param Timer This parameter can be one of the following values:
12776 * @arg @ref LL_HRTIM_TIMER_A
12777 * @arg @ref LL_HRTIM_TIMER_B
12778 * @arg @ref LL_HRTIM_TIMER_C
12779 * @arg @ref LL_HRTIM_TIMER_D
12780 * @arg @ref LL_HRTIM_TIMER_E
12781 * @arg @ref LL_HRTIM_TIMER_F
12782 * @retval None
12783 */
LL_HRTIM_EnableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12784 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12785 {
12786 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12787 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12788 REG_OFFSET_TAB_TIMER[iTimer]));
12789 SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
12790 }
12791
12792 /**
12793 * @brief Disable the reset/roll-over interrupt for a given timer.
12794 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
12795 * @param HRTIMx High Resolution Timer instance
12796 * @param Timer This parameter can be one of the following values:
12797 * @arg @ref LL_HRTIM_TIMER_A
12798 * @arg @ref LL_HRTIM_TIMER_B
12799 * @arg @ref LL_HRTIM_TIMER_C
12800 * @arg @ref LL_HRTIM_TIMER_D
12801 * @arg @ref LL_HRTIM_TIMER_E
12802 * @arg @ref LL_HRTIM_TIMER_F
12803 * @retval None
12804 */
LL_HRTIM_DisableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12805 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12806 {
12807 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12808 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12809 REG_OFFSET_TAB_TIMER[iTimer]));
12810 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
12811 }
12812
12813 /**
12814 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
12815 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
12816 * @param HRTIMx High Resolution Timer instance
12817 * @param Timer This parameter can be one of the following values:
12818 * @arg @ref LL_HRTIM_TIMER_A
12819 * @arg @ref LL_HRTIM_TIMER_B
12820 * @arg @ref LL_HRTIM_TIMER_C
12821 * @arg @ref LL_HRTIM_TIMER_D
12822 * @arg @ref LL_HRTIM_TIMER_E
12823 * @arg @ref LL_HRTIM_TIMER_F
12824 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
12825 */
LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12826 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12827 {
12828 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12829 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12830 REG_OFFSET_TAB_TIMER[iTimer]));
12831
12832 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
12833 }
12834
12835 /**
12836 * @brief Enable the delayed protection interrupt for a given timer.
12837 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
12838 * @param HRTIMx High Resolution Timer instance
12839 * @param Timer This parameter can be one of the following values:
12840 * @arg @ref LL_HRTIM_TIMER_A
12841 * @arg @ref LL_HRTIM_TIMER_B
12842 * @arg @ref LL_HRTIM_TIMER_C
12843 * @arg @ref LL_HRTIM_TIMER_D
12844 * @arg @ref LL_HRTIM_TIMER_E
12845 * @arg @ref LL_HRTIM_TIMER_F
12846 * @retval None
12847 */
LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12848 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12849 {
12850 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12851 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12852 REG_OFFSET_TAB_TIMER[iTimer]));
12853 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
12854 }
12855
12856 /**
12857 * @brief Disable the delayed protection interrupt for a given timer.
12858 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
12859 * @param HRTIMx High Resolution Timer instance
12860 * @param Timer This parameter can be one of the following values:
12861 * @arg @ref LL_HRTIM_TIMER_A
12862 * @arg @ref LL_HRTIM_TIMER_B
12863 * @arg @ref LL_HRTIM_TIMER_C
12864 * @arg @ref LL_HRTIM_TIMER_D
12865 * @arg @ref LL_HRTIM_TIMER_E
12866 * @arg @ref LL_HRTIM_TIMER_F
12867 * @retval None
12868 */
LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12869 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12870 {
12871 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12872 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12873 REG_OFFSET_TAB_TIMER[iTimer]));
12874 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
12875 }
12876
12877 /**
12878 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
12879 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
12880 * @param HRTIMx High Resolution Timer instance
12881 * @param Timer This parameter can be one of the following values:
12882 * @arg @ref LL_HRTIM_TIMER_A
12883 * @arg @ref LL_HRTIM_TIMER_B
12884 * @arg @ref LL_HRTIM_TIMER_C
12885 * @arg @ref LL_HRTIM_TIMER_D
12886 * @arg @ref LL_HRTIM_TIMER_E
12887 * @arg @ref LL_HRTIM_TIMER_F
12888 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
12889 */
LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)12890 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12891 {
12892 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12893 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12894 REG_OFFSET_TAB_TIMER[iTimer]));
12895
12896 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
12897 }
12898
12899 /**
12900 * @}
12901 */
12902
12903 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
12904 * @{
12905 */
12906
12907 /**
12908 * @brief Enable the synchronization input DMA request.
12909 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
12910 * @param HRTIMx High Resolution Timer instance
12911 * @retval None
12912 */
LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)12913 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12914 {
12915 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
12916 }
12917
12918 /**
12919 * @brief Disable the synchronization input DMA request
12920 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
12921 * @param HRTIMx High Resolution Timer instance
12922 * @retval None
12923 */
LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)12924 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12925 {
12926 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
12927 }
12928
12929 /**
12930 * @brief Indicate whether the synchronization input DMA request is enabled.
12931 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
12932 * @param HRTIMx High Resolution Timer instance
12933 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
12934 */
LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef * HRTIMx)12935 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx)
12936 {
12937 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
12938 }
12939
12940 /**
12941 * @brief Enable the update DMA request for a given timer.
12942 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
12943 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
12944 * @param HRTIMx High Resolution Timer instance
12945 * @param Timer This parameter can be one of the following values:
12946 * @arg @ref LL_HRTIM_TIMER_MASTER
12947 * @arg @ref LL_HRTIM_TIMER_A
12948 * @arg @ref LL_HRTIM_TIMER_B
12949 * @arg @ref LL_HRTIM_TIMER_C
12950 * @arg @ref LL_HRTIM_TIMER_D
12951 * @arg @ref LL_HRTIM_TIMER_E
12952 * @arg @ref LL_HRTIM_TIMER_F
12953 * @retval None
12954 */
LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12955 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12956 {
12957 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12958 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12959 REG_OFFSET_TAB_TIMER[iTimer]));
12960 SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
12961 }
12962
12963 /**
12964 * @brief Disable the update DMA request for a given timer.
12965 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
12966 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
12967 * @param HRTIMx High Resolution Timer instance
12968 * @param Timer This parameter can be one of the following values:
12969 * @arg @ref LL_HRTIM_TIMER_MASTER
12970 * @arg @ref LL_HRTIM_TIMER_A
12971 * @arg @ref LL_HRTIM_TIMER_B
12972 * @arg @ref LL_HRTIM_TIMER_C
12973 * @arg @ref LL_HRTIM_TIMER_D
12974 * @arg @ref LL_HRTIM_TIMER_E
12975 * @arg @ref LL_HRTIM_TIMER_F
12976 * @retval None
12977 */
LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12978 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12979 {
12980 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12981 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12982 REG_OFFSET_TAB_TIMER[iTimer]));
12983 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
12984 }
12985
12986 /**
12987 * @brief Indicate whether the update DMA request is enabled for a given timer.
12988 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
12989 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
12990 * @param HRTIMx High Resolution Timer instance
12991 * @param Timer This parameter can be one of the following values:
12992 * @arg @ref LL_HRTIM_TIMER_MASTER
12993 * @arg @ref LL_HRTIM_TIMER_A
12994 * @arg @ref LL_HRTIM_TIMER_B
12995 * @arg @ref LL_HRTIM_TIMER_C
12996 * @arg @ref LL_HRTIM_TIMER_D
12997 * @arg @ref LL_HRTIM_TIMER_E
12998 * @arg @ref LL_HRTIM_TIMER_F
12999 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13000 */
LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13001 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13002 {
13003 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13004 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13005 REG_OFFSET_TAB_TIMER[iTimer]));
13006
13007 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
13008 }
13009
13010 /**
13011 * @brief Enable the repetition DMA request for a given timer.
13012 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
13013 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
13014 * @param HRTIMx High Resolution Timer instance
13015 * @param Timer This parameter can be one of the following values:
13016 * @arg @ref LL_HRTIM_TIMER_MASTER
13017 * @arg @ref LL_HRTIM_TIMER_A
13018 * @arg @ref LL_HRTIM_TIMER_B
13019 * @arg @ref LL_HRTIM_TIMER_C
13020 * @arg @ref LL_HRTIM_TIMER_D
13021 * @arg @ref LL_HRTIM_TIMER_E
13022 * @arg @ref LL_HRTIM_TIMER_F
13023 * @retval None
13024 */
LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13025 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13026 {
13027 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13028 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13029 REG_OFFSET_TAB_TIMER[iTimer]));
13030 SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
13031 }
13032
13033 /**
13034 * @brief Disable the repetition DMA request for a given timer.
13035 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
13036 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
13037 * @param HRTIMx High Resolution Timer instance
13038 * @param Timer This parameter can be one of the following values:
13039 * @arg @ref LL_HRTIM_TIMER_MASTER
13040 * @arg @ref LL_HRTIM_TIMER_A
13041 * @arg @ref LL_HRTIM_TIMER_B
13042 * @arg @ref LL_HRTIM_TIMER_C
13043 * @arg @ref LL_HRTIM_TIMER_D
13044 * @arg @ref LL_HRTIM_TIMER_E
13045 * @arg @ref LL_HRTIM_TIMER_F
13046 * @retval None
13047 */
LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13048 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13049 {
13050 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13051 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13052 REG_OFFSET_TAB_TIMER[iTimer]));
13053 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
13054 }
13055
13056 /**
13057 * @brief Indicate whether the repetition DMA request is enabled for a given timer.
13058 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
13059 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
13060 * @param HRTIMx High Resolution Timer instance
13061 * @param Timer This parameter can be one of the following values:
13062 * @arg @ref LL_HRTIM_TIMER_MASTER
13063 * @arg @ref LL_HRTIM_TIMER_A
13064 * @arg @ref LL_HRTIM_TIMER_B
13065 * @arg @ref LL_HRTIM_TIMER_C
13066 * @arg @ref LL_HRTIM_TIMER_D
13067 * @arg @ref LL_HRTIM_TIMER_E
13068 * @arg @ref LL_HRTIM_TIMER_F
13069 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13070 */
LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13071 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13072 {
13073 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13074 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13075 REG_OFFSET_TAB_TIMER[iTimer]));
13076
13077 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
13078 }
13079
13080 /**
13081 * @brief Enable the compare 1 DMA request for a given timer.
13082 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
13083 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
13084 * @param HRTIMx High Resolution Timer instance
13085 * @param Timer This parameter can be one of the following values:
13086 * @arg @ref LL_HRTIM_TIMER_MASTER
13087 * @arg @ref LL_HRTIM_TIMER_A
13088 * @arg @ref LL_HRTIM_TIMER_B
13089 * @arg @ref LL_HRTIM_TIMER_C
13090 * @arg @ref LL_HRTIM_TIMER_D
13091 * @arg @ref LL_HRTIM_TIMER_E
13092 * @arg @ref LL_HRTIM_TIMER_F
13093 * @retval None
13094 */
LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13095 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13096 {
13097 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13098 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13099 REG_OFFSET_TAB_TIMER[iTimer]));
13100 SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
13101 }
13102
13103 /**
13104 * @brief Disable the compare 1 DMA request for a given timer.
13105 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
13106 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
13107 * @param HRTIMx High Resolution Timer instance
13108 * @param Timer This parameter can be one of the following values:
13109 * @arg @ref LL_HRTIM_TIMER_MASTER
13110 * @arg @ref LL_HRTIM_TIMER_A
13111 * @arg @ref LL_HRTIM_TIMER_B
13112 * @arg @ref LL_HRTIM_TIMER_C
13113 * @arg @ref LL_HRTIM_TIMER_D
13114 * @arg @ref LL_HRTIM_TIMER_E
13115 * @arg @ref LL_HRTIM_TIMER_F
13116 * @retval None
13117 */
LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13118 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13119 {
13120 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13121 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13122 REG_OFFSET_TAB_TIMER[iTimer]));
13123 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
13124 }
13125
13126 /**
13127 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
13128 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
13129 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
13130 * @param HRTIMx High Resolution Timer instance
13131 * @param Timer This parameter can be one of the following values:
13132 * @arg @ref LL_HRTIM_TIMER_MASTER
13133 * @arg @ref LL_HRTIM_TIMER_A
13134 * @arg @ref LL_HRTIM_TIMER_B
13135 * @arg @ref LL_HRTIM_TIMER_C
13136 * @arg @ref LL_HRTIM_TIMER_D
13137 * @arg @ref LL_HRTIM_TIMER_E
13138 * @arg @ref LL_HRTIM_TIMER_F
13139 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13140 */
LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13141 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13142 {
13143 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13144 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13145 REG_OFFSET_TAB_TIMER[iTimer]));
13146
13147 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
13148 }
13149
13150 /**
13151 * @brief Enable the compare 2 DMA request for a given timer.
13152 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
13153 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
13154 * @param HRTIMx High Resolution Timer instance
13155 * @param Timer This parameter can be one of the following values:
13156 * @arg @ref LL_HRTIM_TIMER_MASTER
13157 * @arg @ref LL_HRTIM_TIMER_A
13158 * @arg @ref LL_HRTIM_TIMER_B
13159 * @arg @ref LL_HRTIM_TIMER_C
13160 * @arg @ref LL_HRTIM_TIMER_D
13161 * @arg @ref LL_HRTIM_TIMER_E
13162 * @arg @ref LL_HRTIM_TIMER_F
13163 * @retval None
13164 */
LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13165 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13166 {
13167 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13168 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13169 REG_OFFSET_TAB_TIMER[iTimer]));
13170 SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
13171 }
13172
13173 /**
13174 * @brief Disable the compare 2 DMA request for a given timer.
13175 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
13176 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
13177 * @param HRTIMx High Resolution Timer instance
13178 * @param Timer This parameter can be one of the following values:
13179 * @arg @ref LL_HRTIM_TIMER_MASTER
13180 * @arg @ref LL_HRTIM_TIMER_A
13181 * @arg @ref LL_HRTIM_TIMER_B
13182 * @arg @ref LL_HRTIM_TIMER_C
13183 * @arg @ref LL_HRTIM_TIMER_D
13184 * @arg @ref LL_HRTIM_TIMER_E
13185 * @arg @ref LL_HRTIM_TIMER_F
13186 * @retval None
13187 */
LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13188 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13189 {
13190 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13191 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13192 REG_OFFSET_TAB_TIMER[iTimer]));
13193 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
13194 }
13195
13196 /**
13197 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
13198 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
13199 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
13200 * @param HRTIMx High Resolution Timer instance
13201 * @param Timer This parameter can be one of the following values:
13202 * @arg @ref LL_HRTIM_TIMER_MASTER
13203 * @arg @ref LL_HRTIM_TIMER_A
13204 * @arg @ref LL_HRTIM_TIMER_B
13205 * @arg @ref LL_HRTIM_TIMER_C
13206 * @arg @ref LL_HRTIM_TIMER_D
13207 * @arg @ref LL_HRTIM_TIMER_E
13208 * @arg @ref LL_HRTIM_TIMER_F
13209 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13210 */
LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13211 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13212 {
13213 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13214 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13215 REG_OFFSET_TAB_TIMER[iTimer]));
13216
13217 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
13218 }
13219
13220 /**
13221 * @brief Enable the compare 3 DMA request for a given timer.
13222 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
13223 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
13224 * @param HRTIMx High Resolution Timer instance
13225 * @param Timer This parameter can be one of the following values:
13226 * @arg @ref LL_HRTIM_TIMER_MASTER
13227 * @arg @ref LL_HRTIM_TIMER_A
13228 * @arg @ref LL_HRTIM_TIMER_B
13229 * @arg @ref LL_HRTIM_TIMER_C
13230 * @arg @ref LL_HRTIM_TIMER_D
13231 * @arg @ref LL_HRTIM_TIMER_E
13232 * @arg @ref LL_HRTIM_TIMER_F
13233 * @retval None
13234 */
LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13235 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13236 {
13237 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13238 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13239 REG_OFFSET_TAB_TIMER[iTimer]));
13240 SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
13241 }
13242
13243 /**
13244 * @brief Disable the compare 3 DMA request for a given timer.
13245 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
13246 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
13247 * @param HRTIMx High Resolution Timer instance
13248 * @param Timer This parameter can be one of the following values:
13249 * @arg @ref LL_HRTIM_TIMER_MASTER
13250 * @arg @ref LL_HRTIM_TIMER_A
13251 * @arg @ref LL_HRTIM_TIMER_B
13252 * @arg @ref LL_HRTIM_TIMER_C
13253 * @arg @ref LL_HRTIM_TIMER_D
13254 * @arg @ref LL_HRTIM_TIMER_E
13255 * @arg @ref LL_HRTIM_TIMER_F
13256 * @retval None
13257 */
LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13258 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13259 {
13260 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13261 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13262 REG_OFFSET_TAB_TIMER[iTimer]));
13263 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
13264 }
13265
13266 /**
13267 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
13268 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
13269 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
13270 * @param HRTIMx High Resolution Timer instance
13271 * @param Timer This parameter can be one of the following values:
13272 * @arg @ref LL_HRTIM_TIMER_MASTER
13273 * @arg @ref LL_HRTIM_TIMER_A
13274 * @arg @ref LL_HRTIM_TIMER_B
13275 * @arg @ref LL_HRTIM_TIMER_C
13276 * @arg @ref LL_HRTIM_TIMER_D
13277 * @arg @ref LL_HRTIM_TIMER_E
13278 * @arg @ref LL_HRTIM_TIMER_F
13279 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13280 */
LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13281 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13282 {
13283 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13284 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13285 REG_OFFSET_TAB_TIMER[iTimer]));
13286
13287 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
13288 }
13289
13290 /**
13291 * @brief Enable the compare 4 DMA request for a given timer.
13292 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
13293 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
13294 * @param HRTIMx High Resolution Timer instance
13295 * @param Timer This parameter can be one of the following values:
13296 * @arg @ref LL_HRTIM_TIMER_MASTER
13297 * @arg @ref LL_HRTIM_TIMER_A
13298 * @arg @ref LL_HRTIM_TIMER_B
13299 * @arg @ref LL_HRTIM_TIMER_C
13300 * @arg @ref LL_HRTIM_TIMER_D
13301 * @arg @ref LL_HRTIM_TIMER_E
13302 * @arg @ref LL_HRTIM_TIMER_F
13303 * @retval None
13304 */
LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13305 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13306 {
13307 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13308 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13309 REG_OFFSET_TAB_TIMER[iTimer]));
13310 SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
13311 }
13312
13313 /**
13314 * @brief Disable the compare 4 DMA request for a given timer.
13315 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
13316 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
13317 * @param HRTIMx High Resolution Timer instance
13318 * @param Timer This parameter can be one of the following values:
13319 * @arg @ref LL_HRTIM_TIMER_MASTER
13320 * @arg @ref LL_HRTIM_TIMER_A
13321 * @arg @ref LL_HRTIM_TIMER_B
13322 * @arg @ref LL_HRTIM_TIMER_C
13323 * @arg @ref LL_HRTIM_TIMER_D
13324 * @arg @ref LL_HRTIM_TIMER_E
13325 * @arg @ref LL_HRTIM_TIMER_F
13326 * @retval None
13327 */
LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13328 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13329 {
13330 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13331 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13332 REG_OFFSET_TAB_TIMER[iTimer]));
13333 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
13334 }
13335
13336 /**
13337 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
13338 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
13339 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
13340 * @param HRTIMx High Resolution Timer instance
13341 * @param Timer This parameter can be one of the following values:
13342 * @arg @ref LL_HRTIM_TIMER_MASTER
13343 * @arg @ref LL_HRTIM_TIMER_A
13344 * @arg @ref LL_HRTIM_TIMER_B
13345 * @arg @ref LL_HRTIM_TIMER_C
13346 * @arg @ref LL_HRTIM_TIMER_D
13347 * @arg @ref LL_HRTIM_TIMER_E
13348 * @arg @ref LL_HRTIM_TIMER_F
13349 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13350 */
LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13351 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13352 {
13353 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13354 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13355 REG_OFFSET_TAB_TIMER[iTimer]));
13356
13357 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
13358 }
13359
13360 /**
13361 * @brief Enable the capture 1 DMA request for a given timer.
13362 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
13363 * @param HRTIMx High Resolution Timer instance
13364 * @param Timer This parameter can be one of the following values:
13365 * @arg @ref LL_HRTIM_TIMER_A
13366 * @arg @ref LL_HRTIM_TIMER_B
13367 * @arg @ref LL_HRTIM_TIMER_C
13368 * @arg @ref LL_HRTIM_TIMER_D
13369 * @arg @ref LL_HRTIM_TIMER_E
13370 * @arg @ref LL_HRTIM_TIMER_F
13371 * @retval None
13372 */
LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13373 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13374 {
13375 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13376 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13377 REG_OFFSET_TAB_TIMER[iTimer]));
13378 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
13379 }
13380
13381 /**
13382 * @brief Disable the capture 1 DMA request for a given timer.
13383 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
13384 * @param HRTIMx High Resolution Timer instance
13385 * @param Timer This parameter can be one of the following values:
13386 * @arg @ref LL_HRTIM_TIMER_A
13387 * @arg @ref LL_HRTIM_TIMER_B
13388 * @arg @ref LL_HRTIM_TIMER_C
13389 * @arg @ref LL_HRTIM_TIMER_D
13390 * @arg @ref LL_HRTIM_TIMER_E
13391 * @arg @ref LL_HRTIM_TIMER_F
13392 * @retval None
13393 */
LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13394 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13395 {
13396 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13397 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13398 REG_OFFSET_TAB_TIMER[iTimer]));
13399 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
13400 }
13401
13402 /**
13403 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
13404 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
13405 * @param HRTIMx High Resolution Timer instance
13406 * @param Timer This parameter can be one of the following values:
13407 * @arg @ref LL_HRTIM_TIMER_A
13408 * @arg @ref LL_HRTIM_TIMER_B
13409 * @arg @ref LL_HRTIM_TIMER_C
13410 * @arg @ref LL_HRTIM_TIMER_D
13411 * @arg @ref LL_HRTIM_TIMER_E
13412 * @arg @ref LL_HRTIM_TIMER_F
13413 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
13414 */
LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13415 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13416 {
13417 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13418 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13419 REG_OFFSET_TAB_TIMER[iTimer]));
13420
13421 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
13422 }
13423
13424 /**
13425 * @brief Enable the capture 2 DMA request for a given timer.
13426 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
13427 * @param HRTIMx High Resolution Timer instance
13428 * @param Timer This parameter can be one of the following values:
13429 * @arg @ref LL_HRTIM_TIMER_A
13430 * @arg @ref LL_HRTIM_TIMER_B
13431 * @arg @ref LL_HRTIM_TIMER_C
13432 * @arg @ref LL_HRTIM_TIMER_D
13433 * @arg @ref LL_HRTIM_TIMER_E
13434 * @arg @ref LL_HRTIM_TIMER_F
13435 * @retval None
13436 */
LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13437 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13438 {
13439 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13440 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13441 REG_OFFSET_TAB_TIMER[iTimer]));
13442 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
13443 }
13444
13445 /**
13446 * @brief Disable the capture 2 DMA request for a given timer.
13447 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
13448 * @param HRTIMx High Resolution Timer instance
13449 * @param Timer This parameter can be one of the following values:
13450 * @arg @ref LL_HRTIM_TIMER_A
13451 * @arg @ref LL_HRTIM_TIMER_B
13452 * @arg @ref LL_HRTIM_TIMER_C
13453 * @arg @ref LL_HRTIM_TIMER_D
13454 * @arg @ref LL_HRTIM_TIMER_E
13455 * @arg @ref LL_HRTIM_TIMER_F
13456 * @retval None
13457 */
LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13458 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13459 {
13460 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13461 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13462 REG_OFFSET_TAB_TIMER[iTimer]));
13463 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
13464 }
13465
13466 /**
13467 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
13468 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
13469 * @param HRTIMx High Resolution Timer instance
13470 * @param Timer This parameter can be one of the following values:
13471 * @arg @ref LL_HRTIM_TIMER_A
13472 * @arg @ref LL_HRTIM_TIMER_B
13473 * @arg @ref LL_HRTIM_TIMER_C
13474 * @arg @ref LL_HRTIM_TIMER_D
13475 * @arg @ref LL_HRTIM_TIMER_E
13476 * @arg @ref LL_HRTIM_TIMER_F
13477 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
13478 */
LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13479 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13480 {
13481 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13482 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13483 REG_OFFSET_TAB_TIMER[iTimer]));
13484
13485 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
13486 }
13487
13488 /**
13489 * @brief Enable the output 1 set DMA request for a given timer.
13490 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
13491 * @param HRTIMx High Resolution Timer instance
13492 * @param Timer This parameter can be one of the following values:
13493 * @arg @ref LL_HRTIM_TIMER_A
13494 * @arg @ref LL_HRTIM_TIMER_B
13495 * @arg @ref LL_HRTIM_TIMER_C
13496 * @arg @ref LL_HRTIM_TIMER_D
13497 * @arg @ref LL_HRTIM_TIMER_E
13498 * @arg @ref LL_HRTIM_TIMER_F
13499 * @retval None
13500 */
LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13501 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13502 {
13503 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13504 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13505 REG_OFFSET_TAB_TIMER[iTimer]));
13506 SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
13507 }
13508
13509 /**
13510 * @brief Disable the output 1 set DMA request for a given timer.
13511 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
13512 * @param HRTIMx High Resolution Timer instance
13513 * @param Timer This parameter can be one of the following values:
13514 * @arg @ref LL_HRTIM_TIMER_A
13515 * @arg @ref LL_HRTIM_TIMER_B
13516 * @arg @ref LL_HRTIM_TIMER_C
13517 * @arg @ref LL_HRTIM_TIMER_D
13518 * @arg @ref LL_HRTIM_TIMER_E
13519 * @arg @ref LL_HRTIM_TIMER_F
13520 * @retval None
13521 */
LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13522 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13523 {
13524 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13525 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13526 REG_OFFSET_TAB_TIMER[iTimer]));
13527 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
13528 }
13529
13530 /**
13531 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
13532 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
13533 * @param HRTIMx High Resolution Timer instance
13534 * @param Timer This parameter can be one of the following values:
13535 * @arg @ref LL_HRTIM_TIMER_A
13536 * @arg @ref LL_HRTIM_TIMER_B
13537 * @arg @ref LL_HRTIM_TIMER_C
13538 * @arg @ref LL_HRTIM_TIMER_D
13539 * @arg @ref LL_HRTIM_TIMER_E
13540 * @arg @ref LL_HRTIM_TIMER_F
13541 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13542 */
LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13543 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13544 {
13545 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13546 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13547 REG_OFFSET_TAB_TIMER[iTimer]));
13548
13549 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
13550 }
13551
13552 /**
13553 * @brief Enable the output 1 reset DMA request for a given timer.
13554 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
13555 * @param HRTIMx High Resolution Timer instance
13556 * @param Timer This parameter can be one of the following values:
13557 * @arg @ref LL_HRTIM_TIMER_A
13558 * @arg @ref LL_HRTIM_TIMER_B
13559 * @arg @ref LL_HRTIM_TIMER_C
13560 * @arg @ref LL_HRTIM_TIMER_D
13561 * @arg @ref LL_HRTIM_TIMER_E
13562 * @arg @ref LL_HRTIM_TIMER_F
13563 * @retval None
13564 */
LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13565 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13566 {
13567 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13568 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13569 REG_OFFSET_TAB_TIMER[iTimer]));
13570 SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
13571 }
13572
13573 /**
13574 * @brief Disable the output 1 reset DMA request for a given timer.
13575 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
13576 * @param HRTIMx High Resolution Timer instance
13577 * @param Timer This parameter can be one of the following values:
13578 * @arg @ref LL_HRTIM_TIMER_A
13579 * @arg @ref LL_HRTIM_TIMER_B
13580 * @arg @ref LL_HRTIM_TIMER_C
13581 * @arg @ref LL_HRTIM_TIMER_D
13582 * @arg @ref LL_HRTIM_TIMER_E
13583 * @arg @ref LL_HRTIM_TIMER_F
13584 * @retval None
13585 */
LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13586 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13587 {
13588 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13589 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13590 REG_OFFSET_TAB_TIMER[iTimer]));
13591 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
13592 }
13593
13594 /**
13595 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
13596 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
13597 * @param HRTIMx High Resolution Timer instance
13598 * @param Timer This parameter can be one of the following values:
13599 * @arg @ref LL_HRTIM_TIMER_A
13600 * @arg @ref LL_HRTIM_TIMER_B
13601 * @arg @ref LL_HRTIM_TIMER_C
13602 * @arg @ref LL_HRTIM_TIMER_D
13603 * @arg @ref LL_HRTIM_TIMER_E
13604 * @arg @ref LL_HRTIM_TIMER_F
13605 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13606 */
LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13607 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13608 {
13609 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13610 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13611 REG_OFFSET_TAB_TIMER[iTimer]));
13612
13613 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
13614 }
13615
13616 /**
13617 * @brief Enable the output 2 set DMA request for a given timer.
13618 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
13619 * @param HRTIMx High Resolution Timer instance
13620 * @param Timer This parameter can be one of the following values:
13621 * @arg @ref LL_HRTIM_TIMER_A
13622 * @arg @ref LL_HRTIM_TIMER_B
13623 * @arg @ref LL_HRTIM_TIMER_C
13624 * @arg @ref LL_HRTIM_TIMER_D
13625 * @arg @ref LL_HRTIM_TIMER_E
13626 * @arg @ref LL_HRTIM_TIMER_F
13627 * @retval None
13628 */
LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13629 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13630 {
13631 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13632 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13633 REG_OFFSET_TAB_TIMER[iTimer]));
13634 SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
13635 }
13636
13637 /**
13638 * @brief Disable the output 2 set DMA request for a given timer.
13639 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
13640 * @param HRTIMx High Resolution Timer instance
13641 * @param Timer This parameter can be one of the following values:
13642 * @arg @ref LL_HRTIM_TIMER_A
13643 * @arg @ref LL_HRTIM_TIMER_B
13644 * @arg @ref LL_HRTIM_TIMER_C
13645 * @arg @ref LL_HRTIM_TIMER_D
13646 * @arg @ref LL_HRTIM_TIMER_E
13647 * @arg @ref LL_HRTIM_TIMER_F
13648 * @retval None
13649 */
LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13650 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13651 {
13652 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13653 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13654 REG_OFFSET_TAB_TIMER[iTimer]));
13655 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
13656 }
13657
13658 /**
13659 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
13660 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
13661 * @param HRTIMx High Resolution Timer instance
13662 * @param Timer This parameter can be one of the following values:
13663 * @arg @ref LL_HRTIM_TIMER_A
13664 * @arg @ref LL_HRTIM_TIMER_B
13665 * @arg @ref LL_HRTIM_TIMER_C
13666 * @arg @ref LL_HRTIM_TIMER_D
13667 * @arg @ref LL_HRTIM_TIMER_E
13668 * @arg @ref LL_HRTIM_TIMER_F
13669 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13670 */
LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13671 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13672 {
13673 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13674 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13675 REG_OFFSET_TAB_TIMER[iTimer]));
13676
13677 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
13678 }
13679
13680 /**
13681 * @brief Enable the output 2 reset DMA request for a given timer.
13682 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
13683 * @param HRTIMx High Resolution Timer instance
13684 * @param Timer This parameter can be one of the following values:
13685 * @arg @ref LL_HRTIM_TIMER_A
13686 * @arg @ref LL_HRTIM_TIMER_B
13687 * @arg @ref LL_HRTIM_TIMER_C
13688 * @arg @ref LL_HRTIM_TIMER_D
13689 * @arg @ref LL_HRTIM_TIMER_E
13690 * @arg @ref LL_HRTIM_TIMER_F
13691 * @retval None
13692 */
LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13693 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13694 {
13695 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13696 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13697 REG_OFFSET_TAB_TIMER[iTimer]));
13698 SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
13699 }
13700
13701 /**
13702 * @brief Disable the output 2 reset DMA request for a given timer.
13703 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
13704 * @param HRTIMx High Resolution Timer instance
13705 * @param Timer This parameter can be one of the following values:
13706 * @arg @ref LL_HRTIM_TIMER_A
13707 * @arg @ref LL_HRTIM_TIMER_B
13708 * @arg @ref LL_HRTIM_TIMER_C
13709 * @arg @ref LL_HRTIM_TIMER_D
13710 * @arg @ref LL_HRTIM_TIMER_E
13711 * @arg @ref LL_HRTIM_TIMER_F
13712 * @retval None
13713 */
LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13714 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13715 {
13716 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13717 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13718 REG_OFFSET_TAB_TIMER[iTimer]));
13719 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
13720 }
13721
13722 /**
13723 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
13724 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
13725 * @param HRTIMx High Resolution Timer instance
13726 * @param Timer This parameter can be one of the following values:
13727 * @arg @ref LL_HRTIM_TIMER_A
13728 * @arg @ref LL_HRTIM_TIMER_B
13729 * @arg @ref LL_HRTIM_TIMER_C
13730 * @arg @ref LL_HRTIM_TIMER_D
13731 * @arg @ref LL_HRTIM_TIMER_E
13732 * @arg @ref LL_HRTIM_TIMER_F
13733 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13734 */
LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13735 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13736 {
13737 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13738 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13739 REG_OFFSET_TAB_TIMER[iTimer]));
13740
13741 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
13742 }
13743
13744 /**
13745 * @brief Enable the reset/roll-over DMA request for a given timer.
13746 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
13747 * @param HRTIMx High Resolution Timer instance
13748 * @param Timer This parameter can be one of the following values:
13749 * @arg @ref LL_HRTIM_TIMER_A
13750 * @arg @ref LL_HRTIM_TIMER_B
13751 * @arg @ref LL_HRTIM_TIMER_C
13752 * @arg @ref LL_HRTIM_TIMER_D
13753 * @arg @ref LL_HRTIM_TIMER_E
13754 * @arg @ref LL_HRTIM_TIMER_F
13755 * @retval None
13756 */
LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13757 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13758 {
13759 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13760 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13761 REG_OFFSET_TAB_TIMER[iTimer]));
13762 SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
13763 }
13764
13765 /**
13766 * @brief Disable the reset/roll-over DMA request for a given timer.
13767 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
13768 * @param HRTIMx High Resolution Timer instance
13769 * @param Timer This parameter can be one of the following values:
13770 * @arg @ref LL_HRTIM_TIMER_A
13771 * @arg @ref LL_HRTIM_TIMER_B
13772 * @arg @ref LL_HRTIM_TIMER_C
13773 * @arg @ref LL_HRTIM_TIMER_D
13774 * @arg @ref LL_HRTIM_TIMER_E
13775 * @arg @ref LL_HRTIM_TIMER_F
13776 * @retval None
13777 */
LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13778 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13779 {
13780 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13781 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13782 REG_OFFSET_TAB_TIMER[iTimer]));
13783 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
13784 }
13785
13786 /**
13787 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
13788 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
13789 * @param HRTIMx High Resolution Timer instance
13790 * @param Timer This parameter can be one of the following values:
13791 * @arg @ref LL_HRTIM_TIMER_A
13792 * @arg @ref LL_HRTIM_TIMER_B
13793 * @arg @ref LL_HRTIM_TIMER_C
13794 * @arg @ref LL_HRTIM_TIMER_D
13795 * @arg @ref LL_HRTIM_TIMER_E
13796 * @arg @ref LL_HRTIM_TIMER_F
13797 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
13798 */
LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13799 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13800 {
13801 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13802 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13803 REG_OFFSET_TAB_TIMER[iTimer]));
13804
13805 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
13806 }
13807
13808 /**
13809 * @brief Enable the delayed protection DMA request for a given timer.
13810 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
13811 * @param HRTIMx High Resolution Timer instance
13812 * @param Timer This parameter can be one of the following values:
13813 * @arg @ref LL_HRTIM_TIMER_A
13814 * @arg @ref LL_HRTIM_TIMER_B
13815 * @arg @ref LL_HRTIM_TIMER_C
13816 * @arg @ref LL_HRTIM_TIMER_D
13817 * @arg @ref LL_HRTIM_TIMER_E
13818 * @arg @ref LL_HRTIM_TIMER_F
13819 * @retval None
13820 */
LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13821 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13822 {
13823 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13824 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13825 REG_OFFSET_TAB_TIMER[iTimer]));
13826 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
13827 }
13828
13829 /**
13830 * @brief Disable the delayed protection DMA request for a given timer.
13831 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
13832 * @param HRTIMx High Resolution Timer instance
13833 * @param Timer This parameter can be one of the following values:
13834 * @arg @ref LL_HRTIM_TIMER_A
13835 * @arg @ref LL_HRTIM_TIMER_B
13836 * @arg @ref LL_HRTIM_TIMER_C
13837 * @arg @ref LL_HRTIM_TIMER_D
13838 * @arg @ref LL_HRTIM_TIMER_E
13839 * @arg @ref LL_HRTIM_TIMER_F
13840 * @retval None
13841 */
LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13842 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13843 {
13844 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13845 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13846 REG_OFFSET_TAB_TIMER[iTimer]));
13847 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
13848 }
13849
13850 /**
13851 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
13852 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
13853 * @param HRTIMx High Resolution Timer instance
13854 * @param Timer This parameter can be one of the following values:
13855 * @arg @ref LL_HRTIM_TIMER_A
13856 * @arg @ref LL_HRTIM_TIMER_B
13857 * @arg @ref LL_HRTIM_TIMER_C
13858 * @arg @ref LL_HRTIM_TIMER_D
13859 * @arg @ref LL_HRTIM_TIMER_E
13860 * @arg @ref LL_HRTIM_TIMER_F
13861 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
13862 */
LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)13863 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13864 {
13865 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13866 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13867 REG_OFFSET_TAB_TIMER[iTimer]));
13868
13869 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
13870 }
13871
13872 /**
13873 * @}
13874 */
13875
13876 #if defined(USE_FULL_LL_DRIVER)
13877 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
13878 * @{
13879 */
13880 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx);
13881 /**
13882 * @}
13883 */
13884 #endif /* USE_FULL_LL_DRIVER */
13885
13886 /**
13887 * @}
13888 */
13889
13890 /**
13891 * @}
13892 */
13893
13894 #endif /* HRTIM1 */
13895
13896 /**
13897 * @}
13898 */
13899
13900 #ifdef __cplusplus
13901 }
13902 #endif
13903
13904 #endif /* STM32G4xx_LL_HRTIM_H */
13905
13906
