1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32N6xx_LL_DMA_H
41 #define STM32N6xx_LL_DMA_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif /* __cplusplus */
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32n6xx.h"
49
50 /** @addtogroup STM32N6xx_LL_Driver
51 * @{
52 */
53
54 #if (defined (GPDMA1) || defined (HPDMA1))
55
56 /** @defgroup DMA_LL DMA
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62
63 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
64 * @{
65 */
66 #define DMA_CHANNEL0_OFFSET (0x00000050UL)
67 #define DMA_CHANNEL1_OFFSET (0x000000D0UL)
68 #define DMA_CHANNEL2_OFFSET (0x00000150UL)
69 #define DMA_CHANNEL3_OFFSET (0x000001D0UL)
70 #define DMA_CHANNEL4_OFFSET (0x00000250UL)
71 #define DMA_CHANNEL5_OFFSET (0x000002D0UL)
72 #define DMA_CHANNEL6_OFFSET (0x00000350UL)
73 #define DMA_CHANNEL7_OFFSET (0x000003D0UL)
74 #define DMA_CHANNEL8_OFFSET (0x00000450UL)
75 #define DMA_CHANNEL9_OFFSET (0x000004D0UL)
76 #define DMA_CHANNEL10_OFFSET (0x00000550UL)
77 #define DMA_CHANNEL11_OFFSET (0x000005D0UL)
78 #define DMA_CHANNEL12_OFFSET (0x00000650UL)
79 #define DMA_CHANNEL13_OFFSET (0x000006D0UL)
80 #define DMA_CHANNEL14_OFFSET (0x00000750UL)
81 #define DMA_CHANNEL15_OFFSET (0x000007D0UL)
82
83 /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
84 static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
85 {
86 DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
87 DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
88 DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET,
89 DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET,
90 };
91
92 /**
93 * @}
94 */
95
96 /* Private constants ---------------------------------------------------------*/
97 /* Private macros ------------------------------------------------------------*/
98 /* Exported types ------------------------------------------------------------*/
99
100 #if defined (USE_FULL_LL_DRIVER)
101 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
102 * @{
103 */
104
105 /**
106 * @brief LL DMA init structure definition.
107 */
108 typedef struct
109 {
110 uint32_t SrcAddress; /*!< This field specify the data transfer source address.
111 Programming this field is mandatory for all available DMA channels.
112 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
113 This feature can be modified afterwards using unitary function
114 @ref LL_DMA_SetSrcAddress(). */
115
116 uint32_t DestAddress; /*!< This field specify the data transfer destination address.
117 Programming this field is mandatory for all available DMA channels.
118 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
119 This feature can be modified afterwards using unitary function
120 @ref LL_DMA_SetDestAddress(). */
121
122 uint32_t Direction; /*!< This field specify the data transfer direction.
123 Programming this field is mandatory for all available DMA channels.
124 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
125 This feature can be modified afterwards using unitary function
126 @ref LL_DMA_SetDataTransferDirection(). */
127
128 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
129 Programming this field is mandatory for all available DMA channels.
130 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
131 This feature can be modified afterwards using unitary function
132 @ref LL_DMA_SetBlkHWRequest(). */
133
134 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
135 Programming this field is mandatory for all available DMA channels.
136 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
137 This feature can be modified afterwards using unitary function
138 @ref LL_DMA_SetDataAlignment(). */
139
140 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
141 Programming this field is mandatory for all available DMA channels.
142 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
143 This feature can be modified afterwards using unitary function
144 @ref LL_DMA_SetSrcBurstLength(). */
145
146 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
147 Programming this field is mandatory for all available DMA channels.
148 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
149 This feature can be modified afterwards using unitary function
150 @ref LL_DMA_SetDestBurstLength(). */
151
152 uint32_t SrcDataWidth; /*!< This field specify the source data width.
153 Programming this field is mandatory for all available DMA channels.
154 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
155 This feature can be modified afterwards using unitary function
156 @ref LL_DMA_SetSrcDataWidth(). */
157
158 uint32_t DestDataWidth; /*!< This field specify the destination data width.
159 Programming this field is mandatory for all available DMA channels.
160 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
161 This feature can be modified afterwards using unitary function
162 @ref LL_DMA_SetDestDataWidth(). */
163
164 uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
165 Programming this field is mandatory for all available DMA channels.
166 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
167 This feature can be modified afterwards using unitary function
168 @ref LL_DMA_SetSrcIncMode(). */
169
170 uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
171 Programming this field is mandatory for all available DMA channels.
172 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
173 This feature can be modified afterwards using unitary function
174 @ref LL_DMA_SetDestIncMode(). */
175
176 uint32_t Priority; /*!< This field specify the channel priority level.
177 Programming this field is mandatory for all available DMA channels.
178 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
179 This feature can be modified afterwards using unitary function
180 @ref LL_DMA_SetChannelPriorityLevel(). */
181
182 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
183 Programming this field is mandatory for all available DMA channels.
184 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
185 This feature can be modified afterwards using unitary function
186 @ref LL_DMA_SetBlkDataLength(). */
187
188 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
189 Programming this field is mandatory only for 2D addressing channels.
190 This parameter can be a value between 1 and 2048 Min_Data = 0
191 and Max_Data = 0x000007FF.
192 This feature can be modified afterwards using unitary function
193 @ref LL_DMA_SetBlkRptCount(). */
194
195 uint32_t TriggerMode; /*!< This field specify the trigger mode.
196 Programming this field is mandatory for all available DMA channels.
197 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
198 This feature can be modified afterwards using unitary function
199 @ref LL_DMA_SetTriggerMode(). */
200
201 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
202 Programming this field is mandatory for all available DMA channels.
203 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
204 This feature can be modified afterwards using unitary function
205 @ref LL_DMA_SetTriggerPolarity(). */
206
207 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
208 Programming this field is mandatory for all available DMA channels.
209 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
210 This feature can be modified afterwards using unitary function
211 @ref LL_DMA_SetHWTrigger(). */
212
213 uint32_t Request; /*!< This field specify the peripheral request selection.
214 Programming this field is mandatory for all available DMA channels.
215 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
216 This feature can be modified afterwards using unitary function
217 @ref LL_DMA_SetPeriphRequest(). */
218
219 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
220 Programming this field is mandatory for all available DMA channels.
221 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
222 This feature can be modified afterwards using unitary function
223 @ref LL_DMA_SetTransferEventMode(). */
224
225 uint32_t DestWordExchange; /*!< This field specify the destination word exchange.
226 Programming this field is mandatory for all available HPDMA channels.
227 This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE.
228 This feature can be modified afterwards using unitary function
229 @ref LL_DMA_SetDestWordExchange(). */
230
231 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
232 Programming this field is mandatory for all available DMA channels.
233 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
234 This feature can be modified afterwards using unitary function
235 @ref LL_DMA_SetDestHWordExchange(). */
236
237 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
238 Programming this field is mandatory for all available DMA channels.
239 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
240 This feature can be modified afterwards using unitary function
241 @ref LL_DMA_SetDestByteExchange(). */
242
243 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
244 Programming this field is mandatory for all available DMA channels.
245 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
246 This feature can be modified afterwards using unitary function
247 @ref LL_DMA_SetSrcByteExchange(). */
248
249 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
250 Programming this field is mandatory for all available DMA channels.
251 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
252 This feature can be modified afterwards using unitary function
253 @ref LL_DMA_SetSrcAllocatedPort(). */
254
255 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
256 Programming this field is mandatory for all available DMA channels.
257 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
258 This feature can be modified afterwards using unitary function
259 @ref LL_DMA_SetDestAllocatedPort(). */
260
261 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
262 Programming this field is mandatory for all available DMA channels.
263 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
264 This feature can be modified afterwards using unitary function
265 @ref LL_DMA_SetLinkAllocatedPort(). */
266
267 uint32_t LinkStepMode; /*!< This field specify the link step mode.
268 Programming this field is mandatory for all available DMA channels.
269 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
270 This feature can be modified afterwards using unitary function
271 @ref LL_DMA_SetLinkStepMode(). */
272
273 uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode.
274 Programming this field is mandatory only for 2D addressing channels.
275 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.
276 This feature can be modified afterwards using unitary function
277 @ref LL_DMA_SetSrcAddrUpdate(). */
278
279 uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode.
280 Programming this field is mandatory only for 2D addressing channels.
281 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.
282 This feature can be modified afterwards using unitary function
283 @ref LL_DMA_SetDestAddrUpdate(). */
284
285 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
286 Programming this field is mandatory only for 2D addressing channels.
287 This parameter can be a value Between 0 to 0x00001FFF.
288 This feature can be modified afterwards using unitary function
289 @ref LL_DMA_SetSrcAddrUpdateValue(). */
290
291 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
292 Programming this field is mandatory only for 2D addressing channels.
293 This parameter can be a value Between 0 to 0x00001FFF.
294 This feature can be modified afterwards using unitary function
295 @ref LL_DMA_SetDestAddrUpdateValue(). */
296
297 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
298 Programming this field is mandatory only for 2D addressing channels.
299 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.
300 This feature can be modified afterwards using unitary function
301 @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */
302
303 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
304 Programming this field is mandatory only for 2D addressing channels.
305 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.
306 This feature can be modified afterwards using unitary function
307 @ref LL_DMA_SetBlkRptDestAddrUpdate(). */
308
309 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
310 Programming this field is mandatory only for 2D addressing channels.
311 This parameter can be a value Between 0 to 0x0000FFFF.
312 This feature can be modified afterwards using unitary function
313 @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */
314
315 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
316 Programming this field is mandatory only for 2D addressing channels.
317 This parameter can be a value Between 0 to 0x0000FFFF.
318 This feature can be modified afterwards using unitary function
319 @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */
320
321 uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
322 Programming this field is mandatory for all available DMA channels.
323 This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
324 bytes are always forced to 0).
325 This feature can be modified afterwards using unitary function
326 @ref LL_DMA_SetLinkedListBaseAddr(). */
327
328 uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
329 Programming this field is mandatory for all available DMA channels.
330 This parameter can be a value Between 0 to 0x0000FFFC.
331 This feature can be modified afterwards using unitary function
332 @ref LL_DMA_SetLinkedListAddrOffset(). */
333
334 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel.
335 This parameter can be a value of @ref DMA_LL_TRANSFER_MODE */
336 } LL_DMA_InitTypeDef;
337
338
339 /**
340 * @brief LL DMA init linked list structure definition.
341 */
342 typedef struct
343 {
344 uint32_t Priority; /*!< This field specify the channel priority level.
345 Programming this field is mandatory for all available DMA channels.
346 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
347 This feature can be modified afterwards using unitary function
348 @ref LL_DMA_SetChannelPriorityLevel(). */
349
350 uint32_t LinkStepMode; /*!< This field specify the link step mode.
351 Programming this field is mandatory for all available DMA channels.
352 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
353 This feature can be modified afterwards using unitary function
354 @ref LL_DMA_SetLinkStepMode(). */
355
356 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
357 Programming this field is mandatory for all available DMA channels.
358 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
359 This feature can be modified afterwards using unitary function
360 @ref LL_DMA_SetLinkAllocatedPort(). */
361
362 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
363 Programming this field is mandatory for all available DMA channels.
364 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
365 This feature can be modified afterwards using unitary function
366 @ref LL_DMA_SetTransferEventMode(). */
367 } LL_DMA_InitLinkedListTypeDef;
368
369
370 /**
371 * @brief LL DMA node init structure definition.
372 */
373 typedef struct
374 {
375 /* CTR1 register fields ******************************************************
376 If any CTR1 fields need to be updated comparing to previous node, it is
377 mandatory to update the new value in CTR1 register fields and enable update
378 CTR1 register in UpdateRegisters fields if it is not enabled in the
379 previous node.
380
381 */
382 #if defined (CPU_IN_SECURE_STATE)
383 uint32_t DestSecure; /*!< This field specify the destination secure.
384 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
385 #endif /* CPU_IN_SECURE_STATE */
386
387 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
388 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
389
390 uint32_t DestWordExchange; /*!< This field specify the destination word exchange.
391 This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE. */
392
393 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
394 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
395
396 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
397 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
398
399 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
400 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
401
402 uint32_t DestIncMode; /*!< This field specify the destination increment mode.
403 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
404
405 uint32_t DestDataWidth; /*!< This field specify the destination data width.
406 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
407
408 #if defined (CPU_IN_SECURE_STATE)
409 uint32_t SrcSecure; /*!< This field specify the source secure.
410 This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */
411 #endif /* CPU_IN_SECURE_STATE */
412
413 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
414 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
415
416 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
417 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
418
419 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
420 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
421
422 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
423 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
424
425 uint32_t SrcIncMode; /*!< This field specify the source increment mode.
426 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
427
428 uint32_t SrcDataWidth; /*!< This field specify the source data width.
429 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
430
431
432 /* CTR2 register fields ******************************************************
433 If any CTR2 fields need to be updated comparing to previous node, it is
434 mandatory to update the new value in CTR2 register fields and enable update
435 CTR2 register in UpdateRegisters fields if it is not enabled in the
436 previous node.
437
438 For all node created, filling all fields is mandatory.
439 */
440 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
441 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
442
443 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
444 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
445
446 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
447 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
448
449 uint32_t TriggerMode; /*!< This field specify the trigger mode.
450 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
451
452 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
453 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
454
455 uint32_t Direction; /*!< This field specify the transfer direction.
456 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
457
458 uint32_t Request; /*!< This field specify the peripheral request selection.
459 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
460
461 uint32_t Mode; /*!< This field DMA Transfer Mode.
462 This parameter can be a value of @ref DMA_LL_TRANSFER_MODE. */
463
464 /* CBR1 register fields ******************************************************
465 If any CBR1 fields need to be updated comparing to previous node, it is
466 mandatory to update the new value in CBR1 register fields and enable update
467 CBR1 register in UpdateRegisters fields if it is not enabled in the
468 previous node.
469
470 If the node to be created is not for 2D addressing channels, there is no
471 need to fill the following fields for CBR1 register :
472 - BlkReptDestAddrUpdate.
473 - BlkRptSrcAddrUpdate.
474 - DestAddrUpdate.
475 - SrcAddrUpdate.
476 - BlkRptCount.
477 */
478 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
479 This parameter can be a value of
480 @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */
481
482 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
483 This parameter can be a value of
484 @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */
485
486 uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode.
487 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */
488
489 uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode.
490 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */
491
492 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
493 This parameter can be a value between 1 and 2048 Min_Data = 0
494 and Max_Data = 0x000007FF. */
495
496 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
497 This parameter must be a value between Min_Data = 0
498 and Max_Data = 0x0000FFFF. */
499
500 /* CSAR register fields ******************************************************
501 If any CSAR fields need to be updated comparing to previous node, it is
502 mandatory to update the new value in CSAR register fields and enable update
503 CSAR register in UpdateRegisters fields if it is not enabled in the
504 previous node.
505
506 For all node created, filling all fields is mandatory.
507 */
508 uint32_t SrcAddress; /*!< This field specify the transfer source address.
509 This parameter must be a value between Min_Data = 0
510 and Max_Data = 0xFFFFFFFF. */
511
512
513 /* CDAR register fields ******************************************************
514 If any CDAR fields need to be updated comparing to previous node, it is
515 mandatory to update the new value in CDAR register fields and enable update
516 CDAR register in UpdateRegisters fields if it is not enabled in the
517 previous node.
518
519 For all node created, filling all fields is mandatory.
520 */
521 uint32_t DestAddress; /*!< This field specify the transfer destination address.
522 This parameter must be a value between Min_Data = 0
523 and Max_Data = 0xFFFFFFFF. */
524
525 /* CTR3 register fields ******************************************************
526 If any CTR3 fields need to be updated comparing to previous node, it is
527 mandatory to update the new value in CTR3 register fields and enable update
528 CTR3 register in UpdateRegisters fields if it is not enabled in the
529 previous node.
530
531 This register is used only for 2D addressing channels.
532 If used channel is linear addressing, this register will be overwritten by
533 CLLR register in memory.
534 When this register is enabled on UpdateRegisters and the selected channel
535 is linear addressing, LL APIs will discard this register update in memory.
536 */
537 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
538 This parameter can be a value Between 0 to 0x00001FFF. */
539
540 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
541 This parameter can be a value Between 0 to 0x00001FFF. */
542
543
544 /* CBR2 register fields ******************************************************
545 If any CBR2 fields need to be updated comparing to previous node, it is
546 mandatory to update the new value in CBR2 register fields and enable update
547 CBR2 register in UpdateRegisters fields if it is not enabled in the
548 previous node.
549
550 This register is used only for 2D addressing channels.
551 If used channel is linear addressing, this register will be discarded in
552 memory. When this register is enabled on UpdateRegisters and the selected
553 channel is linear addressing, LL APIs will discard this register update in
554 memory.
555 */
556 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
557 This parameter can be a value Between 0 to 0x0000FFFF. */
558
559 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
560 This parameter can be a value Between 0 to 0x0000FFFF. */
561
562 /* CLLR register fields ******************************************************
563 If any CLLR fields need to be updated comparing to previous node, it is
564 mandatory to update the new value in CLLR register fields and enable update
565 CLLR register in UpdateRegisters fields if it is not enabled in the
566 previous node.
567
568 If used channel is linear addressing, there is no need to enable/disable
569 CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded
570 by LL APIs.
571 */
572 uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
573 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
574
575 /* DMA Node type field *******************************************************
576 This parameter defines node types as node size and node content varies
577 between channels.
578 Thanks to this fields, linked list queue could be created independently
579 from channel selection. So, one queue could be executed by all DMA channels.
580 */
581 uint32_t NodeType; /*!< Specifies the node type to be created.
582 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
583 } LL_DMA_InitNodeTypeDef;
584
585 /**
586 * @brief LL DMA linked list node structure definition.
587 * @note For 2D addressing channels, the maximum node size is :
588 * (4 Bytes * 8 registers = 32 Bytes).
589 * For GPDMA & HPDMA linear addressing channels, the maximum node size is :
590 * (4 Bytes * 6 registers = 24 Bytes).
591 */
592 typedef struct
593 {
594 __IO uint32_t LinkRegisters[8U];
595
596 } LL_DMA_LinkNodeTypeDef;
597 /**
598 * @}
599 */
600
601 #endif /* USE_FULL_LL_DRIVER */
602
603 /* Exported constants --------------------------------------------------------*/
604
605 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
606 * @{
607 */
608
609 /** @defgroup DMA_LL_EC_CHANNEL Channel
610 * @{
611 */
612 #define LL_DMA_CHANNEL_0 (0x00U)
613 #define LL_DMA_CHANNEL_1 (0x01U)
614 #define LL_DMA_CHANNEL_2 (0x02U)
615 #define LL_DMA_CHANNEL_3 (0x03U)
616 #define LL_DMA_CHANNEL_4 (0x04U)
617 #define LL_DMA_CHANNEL_5 (0x05U)
618 #define LL_DMA_CHANNEL_6 (0x06U)
619 #define LL_DMA_CHANNEL_7 (0x07U)
620 #define LL_DMA_CHANNEL_8 (0x08U)
621 #define LL_DMA_CHANNEL_9 (0x09U)
622 #define LL_DMA_CHANNEL_10 (0x0AU)
623 #define LL_DMA_CHANNEL_11 (0x0BU)
624 #define LL_DMA_CHANNEL_12 (0x0CU)
625 #define LL_DMA_CHANNEL_13 (0x0DU)
626 #define LL_DMA_CHANNEL_14 (0x0EU)
627 #define LL_DMA_CHANNEL_15 (0x0FU)
628 #if defined (USE_FULL_LL_DRIVER)
629 #define LL_DMA_CHANNEL_ALL (0x10U)
630 #endif /* USE_FULL_LL_DRIVER */
631 /**
632 * @}
633 */
634
635 #if defined (USE_FULL_LL_DRIVER)
636 /** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
637 * @{
638 */
639 #define LL_DMA_CLLR_OFFSET0 (0x00U)
640 #define LL_DMA_CLLR_OFFSET1 (0x01U)
641 #define LL_DMA_CLLR_OFFSET2 (0x02U)
642 #define LL_DMA_CLLR_OFFSET3 (0x03U)
643 #define LL_DMA_CLLR_OFFSET4 (0x04U)
644 #define LL_DMA_CLLR_OFFSET5 (0x05U)
645 #define LL_DMA_CLLR_OFFSET6 (0x06U)
646 #define LL_DMA_CLLR_OFFSET7 (0x07U)
647 /**
648 * @}
649 */
650 #endif /* USE_FULL_LL_DRIVER */
651
652 /** @defgroup DMA_LL_EC_CID Priority Level
653 * @{
654 */
655 #define LL_DMA_CHANNEL_STATIC_CID_0 (0U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel is assigned to CID0 */
656 #define LL_DMA_CHANNEL_STATIC_CID_1 (1U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel is assigned to CID1 */
657 #define LL_DMA_CHANNEL_STATIC_CID_2 (2U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel is assigned to CID2 */
658 #define LL_DMA_CHANNEL_STATIC_CID_3 (3U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel is assigned to CID3 */
659 #define LL_DMA_CHANNEL_STATIC_CID_4 (4U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel is assigned to CID4 */
660 #define LL_DMA_CHANNEL_STATIC_CID_5 (5U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel is assigned to CID5 */
661 #define LL_DMA_CHANNEL_STATIC_CID_6 (6U<<DMA_CCIDCFGR_SCID_Pos) /*!< Channel is assigned to CID6 */
662 /**
663 * @}
664 */
665
666 /** @defgroup DMA_LL_EC_PRIORITY_LEVEL DMA Priority Level
667 * @{
668 */
669 #define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
670 #define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
671 #define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
672 #define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
673 /**
674 * @}
675 */
676
677 /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
678 * @{
679 */
680 #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
681 #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
682 /**
683 * @}
684 */
685
686 /** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
687 * @{
688 */
689 #define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
690 #define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
691 /**
692 * @}
693 */
694
695 /** @defgroup DMA_LL_EC_DEST_WORD_EXCHANGE Destination Word Exchange
696 * @{
697 */
698 #define LL_DMA_DEST_WORD_PRESERVE 0x00000000U /*!< No destination Word exchange when destination data width
699 is double-word */
700 #define LL_DMA_DEST_WORD_EXCHANGE DMA_CTR1_DWX /*!< Destination Word exchange when destination data width
701 is double-word */
702 /**
703 * @}
704 */
705
706 /** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
707 * @{
708 */
709 #define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width
710 is word */
711 #define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width
712 is word */
713 /**
714 * @}
715 */
716
717 /** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
718 * @{
719 */
720 #define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
721 #define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
722 /**
723 * @}
724 */
725
726 /** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
727 * @{
728 */
729 #define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
730 #define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
731 /**
732 * @}
733 */
734
735 /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
736 * @{
737 */
738 #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
739 #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
740 /**
741 * @}
742 */
743
744 /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
745 * @{
746 */
747 #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
748 #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
749 /**
750 * @}
751 */
752
753 /** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
754 * @{
755 */
756 #define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
757 #define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
758 /**
759 * @}
760 */
761
762 /** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
763 * @{
764 */
765 #define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
766 #define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
767 #define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
768 #define LL_DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination Data Width : DoubleWord */
769 /**
770 * @}
771 */
772
773 /** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
774 * @{
775 */
776 #define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
777 => Right Aligned padded with 0 up to destination
778 data width.
779 If src data width > dest data width :
780 => Right Aligned Left Truncated down to destination
781 data width. */
782 #define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
783 => Right Aligned padded with sign extended up to destination
784 data width.
785 If src data width > dest data width :
786 => Left Aligned Right Truncated down to the destination
787 data width */
788 #define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
789 => Packed at the destination data width
790 If src data width > dest data width :
791 => Unpacked at the destination data width */
792 /**
793 * @}
794 */
795
796 /** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
797 * @{
798 */
799 #define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
800 #define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
801 /**
802 * @}
803 */
804
805 /** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
806 * @{
807 */
808 #define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
809 #define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
810 #define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
811 #define LL_DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source Data Width : DoubleWord */
812 /**
813 * @}
814 */
815
816 /** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
817 * @{
818 */
819 #define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
820 request/acknowledge protocol at a burst level */
821 #define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
822 request/acknowledge protocol at a block level */
823 /**
824 * @}
825 */
826
827 /** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
828 * @{
829 */
830 #define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
831 (respectively half) end of each block */
832 #define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
833 (respectively half) end of the repeated block */
834 #define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
835 (respectively half) end of each linked-list item */
836 #define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
837 (respectively half) end of the last linked-list item */
838 /**
839 * @}
840 */
841
842 /** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
843 * @{
844 */
845 #define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
846 Masked trigger event */
847 #define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
848 edge of the selected trigger event input */
849 #define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
850 edge of the selected trigger event input */
851 /**
852 * @}
853 */
854
855 /** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
856 * @{
857 */
858 #define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
859 one hit trigger */
860 #define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
861 one hit trigger */
862 #define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
863 one hit trigger */
864 #define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
865 one hit trigger */
866 /**
867 * @}
868 */
869
870 /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
871 * @{
872 */
873 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
874 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
875 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
876 /**
877 * @}
878 */
879
880 /** @defgroup DMA_LL_TRANSFER_MODE Transfer Mode
881 * @{
882 */
883 #define LL_DMA_NORMAL 0x00000000U /*!< Normal DMA transfer */
884 #define LL_DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */
885 /**
886 * @}
887 */
888
889 /** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode
890 * @{
891 */
892 #define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block
893 transfer by source update value */
894 #define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block
895 transfer by source update value */
896 /**
897 * @}
898 */
899
900 /** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode
901 * @{
902 */
903 #define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block
904 transfer by destination update value */
905 #define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block
906 transfer by destination update value */
907 /**
908 * @}
909 */
910
911 /** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode
912 * @{
913 */
914 #define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst
915 transfer by source update value */
916 #define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst
917 transfer by source update value */
918 /**
919 * @}
920 */
921
922 /** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode
923 * @{
924 */
925 #define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each
926 burst transfer by destination update value */
927 #define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each
928 burst transfer by destination update value */
929 /**
930 * @}
931 */
932
933 #if defined (CPU_IN_SECURE_STATE)
934 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
935 * @{
936 */
937 #define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
938 #define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */
939 /**
940 * @}
941 */
942
943 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
944 * @{
945 */
946 #define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */
947 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
948 /**
949 * @}
950 */
951
952 /** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
953 * @{
954 */
955 #define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */
956 #define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */
957 /**
958 * @}
959 */
960 #endif /* CPU_IN_SECURE_STATE */
961
962 /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
963 * @{
964 */
965 #define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
966 #define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */
967 #define LL_DMA_HPDMA_LINEAR_NODE 0x04U /*!< HPDMA node : linear addressing node */
968 #define LL_DMA_HPDMA_2D_NODE 0x08U /*!< HPDMA node : 2 dimension addressing node */
969
970 /**
971 * @}
972 */
973
974 /** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
975 * @{
976 */
977 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
978 available for all DMA channels */
979 #define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
980 available for all DMA channels */
981 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
982 available for all DMA channels */
983 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
984 available for all DMA channels */
985 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
986 available for all DMA channels */
987 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
988 available only for 2D addressing DMA channels */
989 #define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory :
990 available only for 2D addressing DMA channels */
991 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
992 available for all DMA channels */
993 /**
994 * @}
995 */
996
997 /** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
998 * @{
999 */
1000 /* HPDMA1 requests */
1001 #define LL_HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_RX */
1002 #define LL_HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_TX */
1003 #define LL_HPDMA1_REQUEST_OCTOSPI1 2U /*!< HPDMA1 HW request is OCTOSPI1 */
1004 #define LL_HPDMA1_REQUEST_OCTOSPI2 3U /*!< HPDMA1 HW request is OCTOSPI2 */
1005 #define LL_HPDMA1_REQUEST_OCTOSPI3 4U /*!< HPDMA1 HW request is OCTOSPI3 */
1006 #define LL_HPDMA1_REQUEST_FMC2_TXRX 5U /*!< HPDMA1 HW request is FMC2_TXRX */
1007 #define LL_HPDMA1_REQUEST_FMC2_BCH 6U /*!< HPDMA1 HW request is FMC2_BCH */
1008 #define LL_HPDMA1_REQUEST_ADC1 7U /*!< HPDMA1 HW request is ADC1 */
1009 #define LL_HPDMA1_REQUEST_ADC2 8U /*!< HPDMA1 HW request is ADC2 */
1010 #define LL_HPDMA1_REQUEST_CRYP_IN 9U /*!< HPDMA1 HW request is CRYP_IN */
1011 #define LL_HPDMA1_REQUEST_CRYP_OUT 10U /*!< HPDMA1 HW request is CRYP_OUT */
1012 #define LL_HPDMA1_REQUEST_SAES_OUT 11U /*!< HPDMA1 HW request is SAES_OUT */
1013 #define LL_HPDMA1_REQUEST_SAES_IN 12U /*!< HPDMA1 HW request is SAES_IN */
1014 #define LL_HPDMA1_REQUEST_HASH_IN 13U /*!< HPDMA1 HW request is HASH_IN */
1015
1016 #define LL_HPDMA1_REQUEST_TIM1_CH1 14U /*!< HPDMA1 HW request is TIM1_CH1 */
1017 #define LL_HPDMA1_REQUEST_TIM1_CH2 15U /*!< HPDMA1 HW request is TIM1_CH2 */
1018 #define LL_HPDMA1_REQUEST_TIM1_CH3 16U /*!< HPDMA1 HW request is TIM1_CH3 */
1019 #define LL_HPDMA1_REQUEST_TIM1_CH4 17U /*!< HPDMA1 HW request is TIM1_CH4 */
1020 #define LL_HPDMA1_REQUEST_TIM1_UP 18U /*!< HPDMA1 HW request is TIM1_UP */
1021 #define LL_HPDMA1_REQUEST_TIM1_TRIG 19U /*!< HPDMA1 HW request is TIM1_TRIG */
1022 #define LL_HPDMA1_REQUEST_TIM1_COM 20U /*!< HPDMA1 HW request is TIM1_COM */
1023
1024 #define LL_HPDMA1_REQUEST_TIM2_CH1 21U /*!< HPDMA1 HW request is TIM2_CH1 */
1025 #define LL_HPDMA1_REQUEST_TIM2_CH2 22U /*!< HPDMA1 HW request is TIM2_CH2 */
1026 #define LL_HPDMA1_REQUEST_TIM2_CH3 23U /*!< HPDMA1 HW request is TIM2_CH3 */
1027 #define LL_HPDMA1_REQUEST_TIM2_CH4 24U /*!< HPDMA1 HW request is TIM2_CH4 */
1028 #define LL_HPDMA1_REQUEST_TIM2_UP 25U /*!< HPDMA1 HW request is TIM2_UP */
1029 #define LL_HPDMA1_REQUEST_TIM2_TRIG 26U /*!< HPDMA1 HW request is TIM2_TRIG */
1030
1031 #define LL_HPDMA1_REQUEST_TIM3_CH1 27U /*!< HPDMA1 HW request is TIM3_CH1 */
1032 #define LL_HPDMA1_REQUEST_TIM3_CH2 28U /*!< HPDMA1 HW request is TIM3_CH2 */
1033 #define LL_HPDMA1_REQUEST_TIM3_CH3 29U /*!< HPDMA1 HW request is TIM3_CH3 */
1034 #define LL_HPDMA1_REQUEST_TIM3_CH4 30U /*!< HPDMA1 HW request is TIM3_CH4 */
1035 #define LL_HPDMA1_REQUEST_TIM3_UP 31U /*!< HPDMA1 HW request is TIM3_UP */
1036 #define LL_HPDMA1_REQUEST_TIM3_TRIG 32U /*!< HPDMA1 HW request is TIM3_TRIG */
1037
1038 #define LL_HPDMA1_REQUEST_TIM4_CH1 33U /*!< HPDMA1 HW request is TIM4_CH1 */
1039 #define LL_HPDMA1_REQUEST_TIM4_CH2 34U /*!< HPDMA1 HW request is TIM4_CH2 */
1040 #define LL_HPDMA1_REQUEST_TIM4_CH3 35U /*!< HPDMA1 HW request is TIM4_CH3 */
1041 #define LL_HPDMA1_REQUEST_TIM4_CH4 36U /*!< HPDMA1 HW request is TIM4_CH4 */
1042 #define LL_HPDMA1_REQUEST_TIM4_UP 37U /*!< HPDMA1 HW request is TIM4_UP */
1043 #define LL_HPDMA1_REQUEST_TIM4_TRIG 38U /*!< HPDMA1 HW request is TIM4_TRIG */
1044
1045 #define LL_HPDMA1_REQUEST_TIM5_CH1 39U /*!< HPDMA1 HW request is TIM5_CH1 */
1046 #define LL_HPDMA1_REQUEST_TIM5_CH2 40U /*!< HPDMA1 HW request is TIM5_CH2 */
1047 #define LL_HPDMA1_REQUEST_TIM5_CH3 41U /*!< HPDMA1 HW request is TIM5_CH3 */
1048 #define LL_HPDMA1_REQUEST_TIM5_CH4 42U /*!< HPDMA1 HW request is TIM5_CH4 */
1049 #define LL_HPDMA1_REQUEST_TIM5_UP 43U /*!< HPDMA1 HW request is TIM5_UP */
1050 #define LL_HPDMA1_REQUEST_TIM5_TRIG 44U /*!< HPDMA1 HW request is TIM5_TRIG */
1051
1052 #define LL_HPDMA1_REQUEST_TIM6_UP 45U /*!< HPDMA1 HW request is TIM6_UP */
1053 #define LL_HPDMA1_REQUEST_TIM7_UP 46U /*!< HPDMA1 HW request is TIM7_UP */
1054
1055 #define LL_HPDMA1_REQUEST_TIM8_CH1 47U /*!< HPDMA1 HW request is TIM8_CH1 */
1056 #define LL_HPDMA1_REQUEST_TIM8_CH2 48U /*!< HPDMA1 HW request is TIM8_CH2 */
1057 #define LL_HPDMA1_REQUEST_TIM8_CH3 49U /*!< HPDMA1 HW request is TIM8_CH3 */
1058 #define LL_HPDMA1_REQUEST_TIM8_CH4 50U /*!< HPDMA1 HW request is TIM8_CH4 */
1059 #define LL_HPDMA1_REQUEST_TIM8_UP 51U /*!< HPDMA1 HW request is TIM8_UP */
1060 #define LL_HPDMA1_REQUEST_TIM8_TRIG 52U /*!< HPDMA1 HW request is TIM8_TRIG */
1061 #define LL_HPDMA1_REQUEST_TIM8_COM 53U /*!< HPDMA1 HW request is TIM8_COM */
1062
1063 /* reserved 54U */
1064 /* reserved 55U */
1065
1066 #define LL_HPDMA1_REQUEST_TIM15_CH1 56U /*!< HPDMA1 HW request is TIM15_CH1 */
1067 #define LL_HPDMA1_REQUEST_TIM15_CH2 57U /*!< HPDMA1 HW request is TIM15_CH2 */
1068 #define LL_HPDMA1_REQUEST_TIM15_UP 58U /*!< HPDMA1 HW request is TIM15_UP */
1069 #define LL_HPDMA1_REQUEST_TIM15_TRIG 59U /*!< HPDMA1 HW request is TIM15_TRIG */
1070 #define LL_HPDMA1_REQUEST_TIM15_COM 60U /*!< HPDMA1 HW request is TIM15_COM */
1071
1072 #define LL_HPDMA1_REQUEST_TIM16_CH1 61U /*!< HPDMA1 HW request is TIM16_CH1 */
1073 #define LL_HPDMA1_REQUEST_TIM16_UP 62U /*!< HPDMA1 HW request is TIM16_UP */
1074 #define LL_HPDMA1_REQUEST_TIM16_COM 63U /*!< HPDMA1 HW request is TIM16_COM */
1075
1076 #define LL_HPDMA1_REQUEST_TIM17_CH1 64U /*!< HPDMA1 HW request is TIM17_CH1 */
1077 #define LL_HPDMA1_REQUEST_TIM17_UP 65U /*!< HPDMA1 HW request is TIM17_UP */
1078 #define LL_HPDMA1_REQUEST_TIM17_COM 66U /*!< HPDMA1 HW request is TIM17_COM */
1079
1080 #define LL_HPDMA1_REQUEST_TIM18_CH1 67U /*!< HPDMA1 HW request is TIM18_CH1 */
1081 #define LL_HPDMA1_REQUEST_TIM18_UP 68U /*!< HPDMA1 HW request is TIM18_UP */
1082 #define LL_HPDMA1_REQUEST_TIM18_COM 69U /*!< HPDMA1 HW request is TIM18_COM */
1083
1084 #define LL_HPDMA1_REQUEST_LPTIM1_IC1 70U /*!< HPDMA1 HW request is LPTIM1_IC1 */
1085 #define LL_HPDMA1_REQUEST_LPTIM1_IC2 71U /*!< HPDMA1 HW request is LPTIM1_IC2 */
1086 #define LL_HPDMA1_REQUEST_LPTIM1_UE 72U /*!< HPDMA1 HW request is LPTIM1_UE */
1087 #define LL_HPDMA1_REQUEST_LPTIM2_IC1 73U /*!< HPDMA1 HW request is LPTIM2_IC1 */
1088 #define LL_HPDMA1_REQUEST_LPTIM2_IC2 74U /*!< HPDMA1 HW request is LPTIM2_IC2 */
1089 #define LL_HPDMA1_REQUEST_LPTIM2_UE 75U /*!< HPDMA1 HW request is LPTIM2_UE */
1090 #define LL_HPDMA1_REQUEST_LPTIM3_IC1 76U /*!< HPDMA1 HW request is LPTIM3_IC1 */
1091 #define LL_HPDMA1_REQUEST_LPTIM3_IC2 77U /*!< HPDMA1 HW request is LPTIM3_IC2 */
1092 #define LL_HPDMA1_REQUEST_LPTIM3_UE 78U /*!< HPDMA1 HW request is LPTIM3_UE */
1093
1094 #define LL_HPDMA1_REQUEST_SPI1_RX 79U /*!< HPDMA1 HW request is SPI1_RX */
1095 #define LL_HPDMA1_REQUEST_SPI1_TX 80U /*!< HPDMA1 HW request is SPI1_TX */
1096 #define LL_HPDMA1_REQUEST_SPI2_RX 81U /*!< HPDMA1 HW request is SPI2_RX */
1097 #define LL_HPDMA1_REQUEST_SPI2_TX 82U /*!< HPDMA1 HW request is SPI2_TX */
1098 #define LL_HPDMA1_REQUEST_SPI3_RX 83U /*!< HPDMA1 HW request is SPI3_RX */
1099 #define LL_HPDMA1_REQUEST_SPI3_TX 84U /*!< HPDMA1 HW request is SPI3_TX */
1100 #define LL_HPDMA1_REQUEST_SPI4_RX 85U /*!< HPDMA1 HW request is SPI4_RX */
1101 #define LL_HPDMA1_REQUEST_SPI4_TX 86U /*!< HPDMA1 HW request is SPI4_TX */
1102 #define LL_HPDMA1_REQUEST_SPI5_RX 87U /*!< HPDMA1 HW request is SPI5_RX */
1103 #define LL_HPDMA1_REQUEST_SPI5_TX 88U /*!< HPDMA1 HW request is SPI5_TX */
1104 #define LL_HPDMA1_REQUEST_SPI6_RX 89U /*!< HPDMA1 HW request is SPI6_RX */
1105 #define LL_HPDMA1_REQUEST_SPI6_TX 90U /*!< HPDMA1 HW request is SPI6_TX */
1106
1107 #define LL_HPDMA1_REQUEST_SAI1_A 91U /*!< HPDMA1 HW request is SAI1_A */
1108 #define LL_HPDMA1_REQUEST_SAI1_B 92U /*!< HPDMA1 HW request is SAI1_B */
1109 #define LL_HPDMA1_REQUEST_SAI2_A 93U /*!< HPDMA1 HW request is SAI2_A */
1110 #define LL_HPDMA1_REQUEST_SAI2_B 94U /*!< HPDMA1 HW request is SAI2_B */
1111
1112 #define LL_HPDMA1_REQUEST_I2C1_RX 95U /*!< HPDMA1 HW request is I2C1_RX */
1113 #define LL_HPDMA1_REQUEST_I2C1_TX 96U /*!< HPDMA1 HW request is I2C1_TX */
1114 #define LL_HPDMA1_REQUEST_I2C2_RX 97U /*!< HPDMA1 HW request is I2C2_RX */
1115 #define LL_HPDMA1_REQUEST_I2C2_TX 98U /*!< HPDMA1 HW request is I2C2_TX */
1116 #define LL_HPDMA1_REQUEST_I2C3_RX 99U /*!< HPDMA1 HW request is I2C3_RX */
1117 #define LL_HPDMA1_REQUEST_I2C3_TX 100U /*!< HPDMA1 HW request is I2C3_TX */
1118
1119 #define LL_HPDMA1_REQUEST_I2C4_RX 101U /*!< HPDMA1 HW request is I2C4_RX */
1120 #define LL_HPDMA1_REQUEST_I2C4_TX 102U /*!< HPDMA1 HW request is I2C4_TX */
1121
1122 #define LL_HPDMA1_REQUEST_I3C1_RX 103U /*!< HPDMA1 HW request is I3C1_RX */
1123 #define LL_HPDMA1_REQUEST_I3C1_TX 104U /*!< HPDMA1 HW request is I3C1_TX */
1124 #define LL_HPDMA1_REQUEST_I3C2_RX 105U /*!< HPDMA1 HW request is I3C2_RX */
1125 #define LL_HPDMA1_REQUEST_I3C2_TX 106U /*!< HPDMA1 HW request is I3C2_TX */
1126
1127 #define LL_HPDMA1_REQUEST_USART1_RX 107U /*!< HPDMA1 HW request is USART1_RX */
1128 #define LL_HPDMA1_REQUEST_USART1_TX 108U /*!< HPDMA1 HW request is USART1_TX */
1129 #define LL_HPDMA1_REQUEST_USART2_RX 109U /*!< HPDMA1 HW request is USART2_RX */
1130 #define LL_HPDMA1_REQUEST_USART2_TX 110U /*!< HPDMA1 HW request is USART2_TX */
1131 #define LL_HPDMA1_REQUEST_USART3_RX 111U /*!< HPDMA1 HW request is USART3_RX */
1132 #define LL_HPDMA1_REQUEST_USART3_TX 112U /*!< HPDMA1 HW request is USART3_TX */
1133 #define LL_HPDMA1_REQUEST_UART4_RX 113U /*!< HPDMA1 HW request is UART4_RX */
1134 #define LL_HPDMA1_REQUEST_UART4_TX 114U /*!< HPDMA1 HW request is UART4_TX */
1135 #define LL_HPDMA1_REQUEST_UART5_RX 115U /*!< HPDMA1 HW request is UART5_RX */
1136 #define LL_HPDMA1_REQUEST_UART5_TX 116U /*!< HPDMA1 HW request is UART5_TX */
1137 #define LL_HPDMA1_REQUEST_USART6_RX 117U /*!< HPDMA1 HW request is USART6_RX */
1138 #define LL_HPDMA1_REQUEST_USART6_TX 118U /*!< HPDMA1 HW request is USART6_TX */
1139 #define LL_HPDMA1_REQUEST_UART7_RX 119U /*!< HPDMA1 HW request is UART7_RX */
1140 #define LL_HPDMA1_REQUEST_UART7_TX 120U /*!< HPDMA1 HW request is UART7_TX */
1141 #define LL_HPDMA1_REQUEST_UART8_RX 121U /*!< HPDMA1 HW request is UART8_RX */
1142 #define LL_HPDMA1_REQUEST_UART8_TX 122U /*!< HPDMA1 HW request is UART8_TX */
1143 #define LL_HPDMA1_REQUEST_UART9_RX 123U /*!< HPDMA1 HW request is UART9_RX */
1144 #define LL_HPDMA1_REQUEST_UART9_TX 124U /*!< HPDMA1 HW request is UART9_TX */
1145 #define LL_HPDMA1_REQUEST_USART10_RX 125U /*!< HPDMA1 HW request is USART10_RX */
1146 #define LL_HPDMA1_REQUEST_USART10_TX 126U /*!< HPDMA1 HW request is USART10_TX */
1147
1148 #define LL_HPDMA1_REQUEST_LPUART1_RX 127U /*!< HPDMA1 HW request is LPUART1_RX */
1149 #define LL_HPDMA1_REQUEST_LPUART1_TX 128U /*!< HPDMA1 HW request is LPUART1_TX */
1150
1151 #define LL_HPDMA1_REQUEST_SPDIFRX_CS 129U /*!< HPDMA1 HW request is SPDIFRX_CS */
1152 #define LL_HPDMA1_REQUEST_SPDIFRX_DT 130U /*!< HPDMA1 HW request is SPDIFRX_DT */
1153
1154 #define LL_HPDMA1_REQUEST_ADF1_FLT0 131U /*!< HPDMA1 HW request is ADF1_FLT0 */
1155
1156 #define LL_HPDMA1_REQUEST_MDF1_FLT0 132U /*!< HPDMA1 HW request is MDF1_FLT0 */
1157 #define LL_HPDMA1_REQUEST_MDF1_FLT1 133U /*!< HPDMA1 HW request is MDF1_FLT1 */
1158 #define LL_HPDMA1_REQUEST_MDF1_FLT2 134U /*!< HPDMA1 HW request is MDF1_FLT2 */
1159 #define LL_HPDMA1_REQUEST_MDF1_FLT3 135U /*!< HPDMA1 HW request is MDF1_FLT3 */
1160 #define LL_HPDMA1_REQUEST_MDF1_FLT4 136U /*!< HPDMA1 HW request is MDF1_FLT4 */
1161 #define LL_HPDMA1_REQUEST_MDF1_FLT5 137U /*!< HPDMA1 HW request is MDF1_FLT5 */
1162
1163 #define LL_HPDMA1_REQUEST_UCPD1_TX 138U /*!< HPDMA1 HW request is UCPD1_TX */
1164 #define LL_HPDMA1_REQUEST_UCPD1_RX 139U /*!< HPDMA1 HW request is UCPD1_RX */
1165
1166 #define LL_HPDMA1_REQUEST_DCMI_PSSI 140U /*!< HPDMA1 HW request is DCMI_PSSI */
1167
1168 #define LL_HPDMA1_REQUEST_I3C1_TC 141U /*!< HPDMA1 HW request is I3C1_TC */
1169 #define LL_HPDMA1_REQUEST_I3C1_RS 142U /*!< HPDMA1 HW request is I3C1_RS */
1170
1171 #define LL_HPDMA1_REQUEST_I3C2_TC 143U /*!< HPDMA1 HW request is I3C2_TC */
1172 #define LL_HPDMA1_REQUEST_I3C2_RS 144U /*!< HPDMA1 HW request is I3C2_RS */
1173
1174
1175 /* GPDMA1 requests */
1176 #define LL_GPDMA1_REQUEST_JPEG_RX 0U /*!< GPDMA1 HW request is JPEG_DMA_RX */
1177 #define LL_GPDMA1_REQUEST_JPEG_TX 1U /*!< GPDMA1 HW request is JPEG_DMA_TX */
1178 #define LL_GPDMA1_REQUEST_OCTOSPI1 2U /*!< GPDMA1 HW request is OCTOSPI1 */
1179 #define LL_GPDMA1_REQUEST_OCTOSPI2 3U /*!< GPDMA1 HW request is OCTOSPI2 */
1180 #define LL_GPDMA1_REQUEST_OCTOSPI3 4U /*!< GPDMA1 HW request is OCTOSPI3 */
1181 #define LL_GPDMA1_REQUEST_FMC2_TXRX 5U /*!< GPDMA1 HW request is FMC2_TXRX */
1182 #define LL_GPDMA1_REQUEST_FMC2_BCH 6U /*!< GPDMA1 HW request is FMC2_BCH */
1183 #define LL_GPDMA1_REQUEST_ADC1 7U /*!< GPDMA1 HW request is ADC1 */
1184 #define LL_GPDMA1_REQUEST_ADC2 8U /*!< GPDMA1 HW request is ADC2 */
1185 #define LL_GPDMA1_REQUEST_CRYP_IN 9U /*!< GPDMA1 HW request is CRYP_IN */
1186 #define LL_GPDMA1_REQUEST_CRYP_OUT 10U /*!< GPDMA1 HW request is CRYP_OUT */
1187 #define LL_GPDMA1_REQUEST_SAES_OUT 11U /*!< GPDMA1 HW request is SAES_OUT */
1188 #define LL_GPDMA1_REQUEST_SAES_IN 12U /*!< GPDMA1 HW request is SAES_IN */
1189 #define LL_GPDMA1_REQUEST_HASH_IN 13U /*!< GPDMA1 HW request is HASH_IN */
1190
1191 #define LL_GPDMA1_REQUEST_TIM1_CH1 14U /*!< GPDMA1 HW request is TIM1_CH1 */
1192 #define LL_GPDMA1_REQUEST_TIM1_CH2 15U /*!< GPDMA1 HW request is TIM1_CH2 */
1193 #define LL_GPDMA1_REQUEST_TIM1_CH3 16U /*!< GPDMA1 HW request is TIM1_CH3 */
1194 #define LL_GPDMA1_REQUEST_TIM1_CH4 17U /*!< GPDMA1 HW request is TIM1_CH4 */
1195 #define LL_GPDMA1_REQUEST_TIM1_UP 18U /*!< GPDMA1 HW request is TIM1_UP */
1196 #define LL_GPDMA1_REQUEST_TIM1_TRIG 19U /*!< GPDMA1 HW request is TIM1_TRIG */
1197 #define LL_GPDMA1_REQUEST_TIM1_COM 20U /*!< GPDMA1 HW request is TIM1_COM */
1198
1199 #define LL_GPDMA1_REQUEST_TIM2_CH1 21U /*!< GPDMA1 HW request is TIM2_CH1 */
1200 #define LL_GPDMA1_REQUEST_TIM2_CH2 22U /*!< GPDMA1 HW request is TIM2_CH2 */
1201 #define LL_GPDMA1_REQUEST_TIM2_CH3 23U /*!< GPDMA1 HW request is TIM2_CH3 */
1202 #define LL_GPDMA1_REQUEST_TIM2_CH4 24U /*!< GPDMA1 HW request is TIM2_CH4 */
1203 #define LL_GPDMA1_REQUEST_TIM2_UP 25U /*!< GPDMA1 HW request is TIM2_UP */
1204 #define LL_GPDMA1_REQUEST_TIM2_TRIG 26U /*!< GPDMA1 HW request is TIM2_TRIG */
1205
1206 #define LL_GPDMA1_REQUEST_TIM3_CH1 27U /*!< GPDMA1 HW request is TIM3_CH1 */
1207 #define LL_GPDMA1_REQUEST_TIM3_CH2 28U /*!< GPDMA1 HW request is TIM3_CH2 */
1208 #define LL_GPDMA1_REQUEST_TIM3_CH3 29U /*!< GPDMA1 HW request is TIM3_CH3 */
1209 #define LL_GPDMA1_REQUEST_TIM3_CH4 30U /*!< GPDMA1 HW request is TIM3_CH4 */
1210 #define LL_GPDMA1_REQUEST_TIM3_UP 31U /*!< GPDMA1 HW request is TIM3_UP */
1211 #define LL_GPDMA1_REQUEST_TIM3_TRIG 32U /*!< GPDMA1 HW request is TIM3_TRIG */
1212
1213 #define LL_GPDMA1_REQUEST_TIM4_CH1 33U /*!< GPDMA1 HW request is TIM4_CH1 */
1214 #define LL_GPDMA1_REQUEST_TIM4_CH2 34U /*!< GPDMA1 HW request is TIM4_CH2 */
1215 #define LL_GPDMA1_REQUEST_TIM4_CH3 35U /*!< GPDMA1 HW request is TIM4_CH3 */
1216 #define LL_GPDMA1_REQUEST_TIM4_CH4 36U /*!< GPDMA1 HW request is TIM4_CH4 */
1217 #define LL_GPDMA1_REQUEST_TIM4_UP 37U /*!< GPDMA1 HW request is TIM4_UP */
1218 #define LL_GPDMA1_REQUEST_TIM4_TRIG 38U /*!< GPDMA1 HW request is TIM4_TRIG */
1219
1220 #define LL_GPDMA1_REQUEST_TIM5_CH1 39U /*!< GPDMA1 HW request is TIM5_CH1 */
1221 #define LL_GPDMA1_REQUEST_TIM5_CH2 40U /*!< GPDMA1 HW request is TIM5_CH2 */
1222 #define LL_GPDMA1_REQUEST_TIM5_CH3 41U /*!< GPDMA1 HW request is TIM5_CH3 */
1223 #define LL_GPDMA1_REQUEST_TIM5_CH4 42U /*!< GPDMA1 HW request is TIM5_CH4 */
1224 #define LL_GPDMA1_REQUEST_TIM5_UP 43U /*!< GPDMA1 HW request is TIM5_UP */
1225 #define LL_GPDMA1_REQUEST_TIM5_TRIG 44U /*!< GPDMA1 HW request is TIM5_TRIG */
1226
1227 #define LL_GPDMA1_REQUEST_TIM6_UP 45U /*!< GPDMA1 HW request is TIM6_UP */
1228 #define LL_GPDMA1_REQUEST_TIM7_UP 46U /*!< GPDMA1 HW request is TIM6_UP */
1229
1230 #define LL_GPDMA1_REQUEST_TIM8_CH1 47U /*!< GPDMA1 HW request is TIM8_CH1 */
1231 #define LL_GPDMA1_REQUEST_TIM8_CH2 48U /*!< GPDMA1 HW request is TIM8_CH2 */
1232 #define LL_GPDMA1_REQUEST_TIM8_CH3 49U /*!< GPDMA1 HW request is TIM8_CH3 */
1233 #define LL_GPDMA1_REQUEST_TIM8_CH4 50U /*!< GPDMA1 HW request is TIM8_CH4 */
1234 #define LL_GPDMA1_REQUEST_TIM8_UP 51U /*!< GPDMA1 HW request is TIM8_UP */
1235 #define LL_GPDMA1_REQUEST_TIM8_TRIG 52U /*!< GPDMA1 HW request is TIM8_TRIG */
1236 #define LL_GPDMA1_REQUEST_TIM8_COM 53U /*!< GPDMA1 HW request is TIM8_COM */
1237
1238 /* reserved 54U */
1239 /* reserved 55U */
1240
1241 #define LL_GPDMA1_REQUEST_TIM15_CH1 56U /*!< GPDMA1 HW request is TIM15_CH1 */
1242 #define LL_GPDMA1_REQUEST_TIM15_CH2 57U /*!< GPDMA1 HW request is TIM15_CH2 */
1243 #define LL_GPDMA1_REQUEST_TIM15_UP 58U /*!< GPDMA1 HW request is TIM15_UP */
1244 #define LL_GPDMA1_REQUEST_TIM15_TRIG 59U /*!< GPDMA1 HW request is TIM15_TRIG */
1245 #define LL_GPDMA1_REQUEST_TIM15_COM 60U /*!< GPDMA1 HW request is TIM15_COM */
1246
1247 #define LL_GPDMA1_REQUEST_TIM16_CH1 61U /*!< GPDMA1 HW request is TIM16_CH1 */
1248 #define LL_GPDMA1_REQUEST_TIM16_UP 62U /*!< GPDMA1 HW request is TIM16_UP */
1249 #define LL_GPDMA1_REQUEST_TIM16_COM 63U /*!< GPDMA1 HW request is TIM16_COM */
1250
1251 #define LL_GPDMA1_REQUEST_TIM17_CH1 64U /*!< GPDMA1 HW request is TIM17_CH1 */
1252 #define LL_GPDMA1_REQUEST_TIM17_UP 65U /*!< GPDMA1 HW request is TIM17_UP */
1253 #define LL_GPDMA1_REQUEST_TIM17_COM 66U /*!< GPDMA1 HW request is TIM17_COM */
1254
1255 #define LL_GPDMA1_REQUEST_TIM18_CH1 67U /*!< GPDMA1 HW request is TIM18_CH1 */
1256 #define LL_GPDMA1_REQUEST_TIM18_UP 68U /*!< GPDMA1 HW request is TIM18_UP */
1257 #define LL_GPDMA1_REQUEST_TIM18_COM 69U /*!< GPDMA1 HW request is TIM18_COM */
1258
1259 #define LL_GPDMA1_REQUEST_LPTIM1_IC1 70U /*!< GPDMA1 HW request is LPTIM1_IC1 */
1260 #define LL_GPDMA1_REQUEST_LPTIM1_IC2 71U /*!< GPDMA1 HW request is LPTIM1_IC2 */
1261 #define LL_GPDMA1_REQUEST_LPTIM1_UE 72U /*!< GPDMA1 HW request is LPTIM1_UE */
1262 #define LL_GPDMA1_REQUEST_LPTIM2_IC1 73U /*!< GPDMA1 HW request is LPTIM2_IC1 */
1263 #define LL_GPDMA1_REQUEST_LPTIM2_IC2 74U /*!< GPDMA1 HW request is LPTIM2_IC2 */
1264 #define LL_GPDMA1_REQUEST_LPTIM2_UE 75U /*!< GPDMA1 HW request is LPTIM2_UE */
1265 #define LL_GPDMA1_REQUEST_LPTIM3_IC1 76U /*!< GPDMA1 HW request is LPTIM3_IC1 */
1266 #define LL_GPDMA1_REQUEST_LPTIM3_IC2 77U /*!< GPDMA1 HW request is LPTIM3_IC2 */
1267 #define LL_GPDMA1_REQUEST_LPTIM3_UE 78U /*!< GPDMA1 HW request is LPTIM3_UE */
1268
1269 #define LL_GPDMA1_REQUEST_SPI1_RX 79U /*!< GPDMA1 HW request is SPI1_RX */
1270 #define LL_GPDMA1_REQUEST_SPI1_TX 80U /*!< GPDMA1 HW request is SPI1_TX */
1271 #define LL_GPDMA1_REQUEST_SPI2_RX 81U /*!< GPDMA1 HW request is SPI2_RX */
1272 #define LL_GPDMA1_REQUEST_SPI2_TX 82U /*!< GPDMA1 HW request is SPI2_TX */
1273 #define LL_GPDMA1_REQUEST_SPI3_RX 83U /*!< GPDMA1 HW request is SPI3_RX */
1274 #define LL_GPDMA1_REQUEST_SPI3_TX 84U /*!< GPDMA1 HW request is SPI3_TX */
1275 #define LL_GPDMA1_REQUEST_SPI4_RX 85U /*!< GPDMA1 HW request is SPI4_RX */
1276 #define LL_GPDMA1_REQUEST_SPI4_TX 86U /*!< GPDMA1 HW request is SPI4_TX */
1277 #define LL_GPDMA1_REQUEST_SPI5_RX 87U /*!< GPDMA1 HW request is SPI5_RX */
1278 #define LL_GPDMA1_REQUEST_SPI5_TX 88U /*!< GPDMA1 HW request is SPI5_TX */
1279 #define LL_GPDMA1_REQUEST_SPI6_RX 89U /*!< GPDMA1 HW request is SPI6_RX */
1280 #define LL_GPDMA1_REQUEST_SPI6_TX 90U /*!< GPDMA1 HW request is SPI6_TX */
1281
1282 #define LL_GPDMA1_REQUEST_SAI1_A 91U /*!< GPDMA1 HW request is SAI1_A */
1283 #define LL_GPDMA1_REQUEST_SAI1_B 92U /*!< GPDMA1 HW request is SAI1_B */
1284 #define LL_GPDMA1_REQUEST_SAI2_A 93U /*!< GPDMA1 HW request is SAI2_A */
1285 #define LL_GPDMA1_REQUEST_SAI2_B 94U /*!< GPDMA1 HW request is SAI2_B */
1286
1287 #define LL_GPDMA1_REQUEST_I2C1_RX 95U /*!< GPDMA1 HW request is I2C1_RX */
1288 #define LL_GPDMA1_REQUEST_I2C1_TX 96U /*!< GPDMA1 HW request is I2C1_TX */
1289 #define LL_GPDMA1_REQUEST_I2C2_RX 97U /*!< GPDMA1 HW request is I2C2_RX */
1290 #define LL_GPDMA1_REQUEST_I2C2_TX 98U /*!< GPDMA1 HW request is I2C2_TX */
1291 #define LL_GPDMA1_REQUEST_I2C3_RX 99U /*!< GPDMA1 HW request is I2C3_RX */
1292 #define LL_GPDMA1_REQUEST_I2C3_TX 100U /*!< GPDMA1 HW request is I2C3_TX */
1293
1294 #define LL_GPDMA1_REQUEST_I2C4_RX 101U /*!< GPDMA1 HW request is I2C4_RX */
1295 #define LL_GPDMA1_REQUEST_I2C4_TX 102U /*!< GPDMA1 HW request is I2C4_TX */
1296
1297 #define LL_GPDMA1_REQUEST_I3C1_RX 103U /*!< GPDMA1 HW request is I3C1_RX */
1298 #define LL_GPDMA1_REQUEST_I3C1_TX 104U /*!< GPDMA1 HW request is I3C1_TX */
1299 #define LL_GPDMA1_REQUEST_I3C2_RX 105U /*!< GPDMA1 HW request is I3C2_RX */
1300 #define LL_GPDMA1_REQUEST_I3C2_TX 106U /*!< GPDMA1 HW request is I3C2_TX */
1301
1302 #define LL_GPDMA1_REQUEST_USART1_RX 107U /*!< GPDMA1 HW request is USART1_RX */
1303 #define LL_GPDMA1_REQUEST_USART1_TX 108U /*!< GPDMA1 HW request is USART1_TX */
1304 #define LL_GPDMA1_REQUEST_USART2_RX 109U /*!< GPDMA1 HW request is USART2_RX */
1305 #define LL_GPDMA1_REQUEST_USART2_TX 110U /*!< GPDMA1 HW request is USART2_TX */
1306 #define LL_GPDMA1_REQUEST_USART3_RX 111U /*!< GPDMA1 HW request is USART3_RX */
1307 #define LL_GPDMA1_REQUEST_USART3_TX 112U /*!< GPDMA1 HW request is USART3_TX */
1308 #define LL_GPDMA1_REQUEST_UART4_RX 113U /*!< GPDMA1 HW request is UART4_RX */
1309 #define LL_GPDMA1_REQUEST_UART4_TX 114U /*!< GPDMA1 HW request is UART4_TX */
1310 #define LL_GPDMA1_REQUEST_UART5_RX 115U /*!< GPDMA1 HW request is UART5_RX */
1311 #define LL_GPDMA1_REQUEST_UART5_TX 116U /*!< GPDMA1 HW request is UART5_TX */
1312 #define LL_GPDMA1_REQUEST_USART6_RX 117U /*!< GPDMA1 HW request is USART6_RX */
1313 #define LL_GPDMA1_REQUEST_USART6_TX 118U /*!< GPDMA1 HW request is USART6_TX */
1314 #define LL_GPDMA1_REQUEST_UART7_RX 119U /*!< GPDMA1 HW request is UART7_RX */
1315 #define LL_GPDMA1_REQUEST_UART7_TX 120U /*!< GPDMA1 HW request is UART7_TX */
1316 #define LL_GPDMA1_REQUEST_UART8_RX 121U /*!< GPDMA1 HW request is UART8_RX */
1317 #define LL_GPDMA1_REQUEST_UART8_TX 122U /*!< GPDMA1 HW request is UART8_TX */
1318 #define LL_GPDMA1_REQUEST_UART9_RX 123U /*!< GPDMA1 HW request is UART9_RX */
1319 #define LL_GPDMA1_REQUEST_UART9_TX 124U /*!< GPDMA1 HW request is UART9_TX */
1320 #define LL_GPDMA1_REQUEST_USART10_RX 125U /*!< GPDMA1 HW request is USART10_RX */
1321 #define LL_GPDMA1_REQUEST_USART10_TX 126U /*!< GPDMA1 HW request is USART10_TX */
1322
1323 #define LL_GPDMA1_REQUEST_LPUART1_RX 127U /*!< GPDMA1 HW request is LPUART1_RX */
1324 #define LL_GPDMA1_REQUEST_LPUART1_TX 128U /*!< GPDMA1 HW request is LPUART1_TX */
1325
1326 #define LL_GPDMA1_REQUEST_SPDIFRX_CS 129U /*!< GPDMA1 HW request is SPDIFRX_CS */
1327 #define LL_GPDMA1_REQUEST_SPDIFRX_DT 130U /*!< GPDMA1 HW request is SPDIFRX_DT */
1328
1329 #define LL_GPDMA1_REQUEST_ADF1_FLT0 131U /*!< GPDMA1 HW request is ADF1_FLT0 */
1330
1331 #define LL_GPDMA1_REQUEST_MDF1_FLT0 132U /*!< GPDMA1 HW request is MDF1_FLT0 */
1332 #define LL_GPDMA1_REQUEST_MDF1_FLT1 133U /*!< GPDMA1 HW request is MDF1_FLT1 */
1333 #define LL_GPDMA1_REQUEST_MDF1_FLT2 134U /*!< GPDMA1 HW request is MDF1_FLT2 */
1334 #define LL_GPDMA1_REQUEST_MDF1_FLT3 135U /*!< GPDMA1 HW request is MDF1_FLT3 */
1335 #define LL_GPDMA1_REQUEST_MDF1_FLT4 136U /*!< GPDMA1 HW request is MDF1_FLT4 */
1336 #define LL_GPDMA1_REQUEST_MDF1_FLT5 137U /*!< GPDMA1 HW request is MDF1_FLT5 */
1337
1338 #define LL_GPDMA1_REQUEST_UCPD1_TX 138U /*!< GPDMA1 HW request is UCPD1_TX */
1339 #define LL_GPDMA1_REQUEST_UCPD1_RX 139U /*!< GPDMA1 HW request is UCPD1_RX */
1340
1341 #define LL_GPDMA1_REQUEST_DCMI_PSSI 140U /*!< GPDMA1 HW request is DCMI_PSSI */
1342
1343 #define LL_GPDMA1_REQUEST_I3C1_TC 141U /*!< GPDMA1 HW request is I3C1_TC */
1344 #define LL_GPDMA1_REQUEST_I3C1_RS 142U /*!< GPDMA1 HW request is I3C1_RS */
1345
1346 #define LL_GPDMA1_REQUEST_I3C2_TC 143U /*!< GPDMA1 HW request is I3C2_TC */
1347 #define LL_GPDMA1_REQUEST_I3C2_RS 144U /*!< GPDMA1 HW request is I3C2_RS */
1348
1349 /**
1350 * @}
1351 */
1352
1353 /** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
1354 * @{
1355 */
1356 /* HPDMA1 triggers */
1357 #define LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_FEND */
1358 #define LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_LEND */
1359 #define LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC */
1360 #define LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC */
1361
1362 #define LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND 4U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_FEND */
1363 #define LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND 5U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_LEND */
1364 #define LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC 6U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC */
1365 #define LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC 7U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC */
1366
1367 #define LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND 8U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_FEND */
1368 #define LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND 9U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_LEND */
1369 #define LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC 10U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC */
1370 #define LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC 11U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC */
1371
1372 #define LL_HPDMA1_TRIGGER_DMA2D_CTC 12U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC */
1373 #define LL_HPDMA1_TRIGGER_DMA2D_TC 13U /*!< HPDMA1 HW Trigger signal is DMA2D_TC */
1374 #define LL_HPDMA1_TRIGGER_DMA2D_TW 14U /*!< HPDMA1 HW Trigger signal is DMA2D_TW */
1375
1376 #define LL_HPDMA1_TRIGGER_JPEG_EOC 15U /*!< HPDMA1 HW Trigger signal is JPEG_EOC */
1377 #define LL_HPDMA1_TRIGGER_JPEG_IFNF 16U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF */
1378 #define LL_HPDMA1_TRIGGER_JPEG_IFT 17U /*!< HPDMA1 HW Trigger signal is JPEG_IFT */
1379 #define LL_HPDMA1_TRIGGER_JPEG_OFNE 18U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE */
1380 #define LL_HPDMA1_TRIGGER_JPEG_OFT 19U /*!< HPDMA1 HW Trigger signal is JPEG_OFT */
1381
1382 #define LL_HPDMA1_TRIGGER_LCD_LI 20U /*!< HPDMA1 HW Trigger signal is LCD_LI */
1383
1384 #define LL_HPDMA1_TRIGGER_GPU2D1_GP_0 21U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_0 */
1385 #define LL_HPDMA1_TRIGGER_GPU2D1_GP_1 22U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_1 */
1386 #define LL_HPDMA1_TRIGGER_GPU2D1_GP_2 23U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_2 */
1387 #define LL_HPDMA1_TRIGGER_GPU2D1_GP_3 24U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_3 */
1388
1389 #define LL_HPDMA1_TRIGGER_GFXTIM_3 25U /*!< HPDMA1 HW Trigger signal is GFXTIM_3 */
1390 #define LL_HPDMA1_TRIGGER_GFXTIM_2 26U /*!< HPDMA1 HW Trigger signal is GFXTIM_2 */
1391 #define LL_HPDMA1_TRIGGER_GFXTIM_1 27U /*!< HPDMA1 HW Trigger signal is GFXTIM_1 */
1392 #define LL_HPDMA1_TRIGGER_GFXTIM_0 28U /*!< HPDMA1 HW Trigger signal is GFXTIM_0 */
1393
1394 /* reserved 29U */
1395
1396 #define LL_HPDMA1_TRIGGER_LPTIM1_CH1 30U /*!< HPDMA1 HW Trigger signal is LPTIM1_CH1 */
1397 #define LL_HPDMA1_TRIGGER_LPTIM1_CH2 31U /*!< HPDMA1 HW Trigger signal is LPTIM1_CH2 */
1398 #define LL_HPDMA1_TRIGGER_LPTIM2_CH1 32U /*!< HPDMA1 HW Trigger signal is LPTIM2_CH1 */
1399 #define LL_HPDMA1_TRIGGER_LPTIM2_CH2 33U /*!< HPDMA1 HW Trigger signal is LPTIM2_CH2 */
1400 #define LL_HPDMA1_TRIGGER_LPTIM3_CH1 34U /*!< HPDMA1 HW Trigger signal is LPTIM3_CH1 */
1401 #define LL_HPDMA1_TRIGGER_LPTIM3_CH2 35U /*!< HPDMA1 HW Trigger signal is LPTIM3_CH2 */
1402 #define LL_HPDMA1_TRIGGER_LPTIM4_OUT 36U /*!< HPDMA1 HW Trigger signal is LPTIM4_OUT */
1403 #define LL_HPDMA1_TRIGGER_LPTIM5_OUT 37U /*!< HPDMA1 HW Trigger signal is LPTIM5_OUT */
1404
1405 /* reserved 38U */
1406
1407 #define LL_HPDMA1_TRIGGER_RTC_WKUP 39U /*!< HPDMA1 HW Trigger signal is RTC_WKUP */
1408
1409 #define LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 40U /*!< HPDMA1 HW Trigger signal is IT_R_WUP_ASYNC */
1410 #define LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 41U /*!< HPDMA1 HW Trigger signal is IT_T_WUP_ASYNC */
1411
1412 #define LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U /*!< HPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */
1413
1414 /* reserved 43U */
1415
1416 #define LL_HPDMA1_TRIGGER_TIM1_TRGO 44U /*!< HPDMA1 HW Trigger signal is TIM1_TRGO */
1417 #define LL_HPDMA1_TRIGGER_TIM1_TRGO2 45U /*!< HPDMA1 HW Trigger signal is TIM1_TRGO2 */
1418 #define LL_HPDMA1_TRIGGER_TIM2_TRGO 46U /*!< HPDMA1 HW Trigger signal is TIM2_TRGO */
1419 #define LL_HPDMA1_TRIGGER_TIM3_TRGO 47U /*!< HPDMA1 HW Trigger signal is TIM3_TRGO */
1420 #define LL_HPDMA1_TRIGGER_TIM4_TRGO 48U /*!< HPDMA1 HW Trigger signal is TIM4_TRGO */
1421 #define LL_HPDMA1_TRIGGER_TIM5_TRGO 49U /*!< HPDMA1 HW Trigger signal is TIM5_TRGO */
1422 #define LL_HPDMA1_TRIGGER_TIM6_TRGO 50U /*!< HPDMA1 HW Trigger signal is TIM6_TRGO */
1423 #define LL_HPDMA1_TRIGGER_TIM7_TRGO 51U /*!< HPDMA1 HW Trigger signal is TIM7_TRGO */
1424 #define LL_HPDMA1_TRIGGER_TIM8_TRGO 52U /*!< HPDMA1 HW Trigger signal is TIM8_TRGO */
1425 #define LL_HPDMA1_TRIGGER_TIM8_TRGO2 53U /*!< HPDMA1 HW Trigger signal is TIM8_TRGO2 */
1426
1427 /* reserved 54U */
1428 /* reserved 55U */
1429 /* reserved 56U */
1430
1431 #define LL_HPDMA1_TRIGGER_TIM12_TRGO 57U /*!< HPDMA1 HW Trigger signal is TIM12_TRGO */
1432 #define LL_HPDMA1_TRIGGER_TIM15_TRGO 58U /*!< HPDMA1 HW Trigger signal is TIM15_TRGO */
1433
1434 /* reserved 59U */
1435
1436 #define LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF 60U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */
1437 #define LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF 61U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */
1438 #define LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF 62U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */
1439 #define LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF 63U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */
1440 #define LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF 64U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */
1441 #define LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF 65U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */
1442 #define LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF 66U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */
1443 #define LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF 67U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */
1444 #define LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF 68U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */
1445 #define LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF 69U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */
1446 #define LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF 70U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */
1447 #define LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF 71U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */
1448 #define LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF 72U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */
1449 #define LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF 73U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */
1450 #define LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF 74U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */
1451 #define LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF 75U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */
1452
1453 #define LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF 76U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
1454 #define LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF 77U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
1455 #define LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF 78U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
1456 #define LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF 79U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
1457 #define LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF 80U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
1458 #define LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF 81U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
1459 #define LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF 82U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
1460 #define LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF 83U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
1461 #define LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF 84U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
1462 #define LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF 85U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
1463 #define LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF 86U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
1464 #define LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF 87U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
1465 #define LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF 88U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
1466 #define LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF 89U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
1467 #define LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF 90U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
1468 #define LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF 91U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
1469
1470 /* reserved 92U */
1471
1472 #define LL_HPDMA1_TRIGGER_EXTIT0_SYNC 93U /*!< HPDMA1 HW Trigger signal is EXTIT0_SYNC */
1473 #define LL_HPDMA1_TRIGGER_EXTIT1_SYNC 94U /*!< HPDMA1 HW Trigger signal is EXTIT1_SYNC */
1474 #define LL_HPDMA1_TRIGGER_EXTIT2_SYNC 95U /*!< HPDMA1 HW Trigger signal is EXTIT2_SYNC */
1475 #define LL_HPDMA1_TRIGGER_EXTIT3_SYNC 96U /*!< HPDMA1 HW Trigger signal is EXTIT3_SYNC */
1476 #define LL_HPDMA1_TRIGGER_EXTIT4_SYNC 97U /*!< HPDMA1 HW Trigger signal is EXTIT4_SYNC */
1477 #define LL_HPDMA1_TRIGGER_EXTIT5_SYNC 98U /*!< HPDMA1 HW Trigger signal is EXTIT5_SYNC */
1478 #define LL_HPDMA1_TRIGGER_EXTIT6_SYNC 99U /*!< HPDMA1 HW Trigger signal is EXTIT6_SYNC */
1479 #define LL_HPDMA1_TRIGGER_EXTIT7_SYNC 100U /*!< HPDMA1 HW Trigger signal is EXTIT7_SYNC */
1480 #define LL_HPDMA1_TRIGGER_EXTIT8_SYNC 101U /*!< HPDMA1 HW Trigger signal is EXTIT8_SYNC */
1481 #define LL_HPDMA1_TRIGGER_EXTIT9_SYNC 102U /*!< HPDMA1 HW Trigger signal is EXTIT9_SYNC */
1482 #define LL_HPDMA1_TRIGGER_EXTIT10_SYNC 103U /*!< HPDMA1 HW Trigger signal is EXTIT10_SYNC */
1483 #define LL_HPDMA1_TRIGGER_EXTIT11_SYNC 104U /*!< HPDMA1 HW Trigger signal is EXTIT11_SYNC */
1484 #define LL_HPDMA1_TRIGGER_EXTIT12_SYNC 105U /*!< HPDMA1 HW Trigger signal is EXTIT12_SYNC */
1485 #define LL_HPDMA1_TRIGGER_EXTIT13_SYNC 106U /*!< HPDMA1 HW Trigger signal is EXTIT13_SYNC */
1486 #define LL_HPDMA1_TRIGGER_EXTIT14_SYNC 107U /*!< HPDMA1 HW Trigger signal is EXTIT14_SYNC */
1487 #define LL_HPDMA1_TRIGGER_EXTIT15_SYNC 108U /*!< HPDMA1 HW Trigger signal is EXTIT15_SYNC */
1488
1489
1490 /* GPDMA1 triggers */
1491 #define LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND 0U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_FEND */
1492 #define LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND 1U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_LEND */
1493 #define LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC 2U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC */
1494 #define LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC 3U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC */
1495
1496 #define LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND 4U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_FEND */
1497 #define LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND 5U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_LEND */
1498 #define LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC 6U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC */
1499 #define LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC 7U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC */
1500
1501 #define LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND 8U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_FEND */
1502 #define LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND 9U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_LEND */
1503 #define LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC 10U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC */
1504 #define LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC 11U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC */
1505
1506 #define LL_GPDMA1_TRIGGER_DMA2D_CTC 12U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */
1507 #define LL_GPDMA1_TRIGGER_DMA2D_TC 13U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */
1508 #define LL_GPDMA1_TRIGGER_DMA2D_TW 14U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */
1509
1510 #define LL_GPDMA1_TRIGGER_JPEG_EOC 15U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */
1511 #define LL_GPDMA1_TRIGGER_JPEG_IFNF 16U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */
1512 #define LL_GPDMA1_TRIGGER_JPEG_IFT 17U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */
1513 #define LL_GPDMA1_TRIGGER_JPEG_OFNE 18U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */
1514 #define LL_GPDMA1_TRIGGER_JPEG_OFT 19U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */
1515
1516 #define LL_GPDMA1_TRIGGER_LCD_LI 20U /*!< GPDMA1 HW Trigger signal is LCD_LI */
1517
1518 #define LL_GPDMA1_TRIGGER_GPU2D1_GP_0 21U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_0 */
1519 #define LL_GPDMA1_TRIGGER_GPU2D1_GP_1 22U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_1 */
1520 #define LL_GPDMA1_TRIGGER_GPU2D1_GP_2 23U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_2 */
1521 #define LL_GPDMA1_TRIGGER_GPU2D1_GP_3 24U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_3 */
1522
1523 #define LL_GPDMA1_TRIGGER_GFXTIM_3 25U /*!< GPDMA1 HW Trigger signal is GFXTIM_3 */
1524 #define LL_GPDMA1_TRIGGER_GFXTIM_2 26U /*!< GPDMA1 HW Trigger signal is GFXTIM_2 */
1525 #define LL_GPDMA1_TRIGGER_GFXTIM_1 27U /*!< GPDMA1 HW Trigger signal is GFXTIM_1 */
1526 #define LL_GPDMA1_TRIGGER_GFXTIM_0 28U /*!< GPDMA1 HW Trigger signal is GFXTIM_0 */
1527
1528 /* reserved 29U */
1529
1530 #define LL_GPDMA1_TRIGGER_LPTIM1_CH1 30U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
1531 #define LL_GPDMA1_TRIGGER_LPTIM1_CH2 31U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
1532 #define LL_GPDMA1_TRIGGER_LPTIM2_CH1 32U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
1533 #define LL_GPDMA1_TRIGGER_LPTIM2_CH2 33U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
1534 #define LL_GPDMA1_TRIGGER_LPTIM3_CH1 34U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */
1535 #define LL_GPDMA1_TRIGGER_LPTIM3_CH2 35U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */
1536 #define LL_GPDMA1_TRIGGER_LPTIM4_OUT 36U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */
1537 #define LL_GPDMA1_TRIGGER_LPTIM5_OUT 37U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */
1538
1539 /* reserved 38U */
1540
1541 #define LL_GPDMA1_TRIGGER_RTC_WKUP 39U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */
1542
1543 #define LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 40U /*!< GPDMA1 HW Trigger signal is IT_R_WUP_ASYNC */
1544 #define LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 41U /*!< GPDMA1 HW Trigger signal is IT_T_WUP_ASYNC */
1545
1546 #define LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U /*!< GPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */
1547
1548 /* reserved 43U */
1549
1550 #define LL_GPDMA1_TRIGGER_TIM1_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */
1551 #define LL_GPDMA1_TRIGGER_TIM1_TRGO2 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */
1552 #define LL_GPDMA1_TRIGGER_TIM2_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
1553 #define LL_GPDMA1_TRIGGER_TIM3_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
1554 #define LL_GPDMA1_TRIGGER_TIM4_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */
1555 #define LL_GPDMA1_TRIGGER_TIM5_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */
1556 #define LL_GPDMA1_TRIGGER_TIM6_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */
1557 #define LL_GPDMA1_TRIGGER_TIM7_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */
1558 #define LL_GPDMA1_TRIGGER_TIM8_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO */
1559 #define LL_GPDMA1_TRIGGER_TIM8_TRGO2 53U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO2 */
1560
1561 /* reserved 54U */
1562 /* reserved 55U */
1563 /* reserved 56U */
1564
1565 #define LL_GPDMA1_TRIGGER_TIM12_TRGO 57U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
1566 #define LL_GPDMA1_TRIGGER_TIM15_TRGO 58U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
1567
1568 /* reserved 59U */
1569
1570 #define LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF 60U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */
1571 #define LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF 61U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */
1572 #define LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF 62U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */
1573 #define LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF 63U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */
1574 #define LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF 64U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */
1575 #define LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF 65U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */
1576 #define LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF 66U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */
1577 #define LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF 67U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */
1578 #define LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF 68U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */
1579 #define LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF 69U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */
1580 #define LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF 70U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */
1581 #define LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF 71U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */
1582 #define LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF 72U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */
1583 #define LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF 73U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */
1584 #define LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF 74U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */
1585 #define LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF 75U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */
1586
1587 #define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 76U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
1588 #define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 77U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
1589 #define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 78U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
1590 #define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 79U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
1591 #define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 80U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
1592 #define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 81U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
1593 #define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 82U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
1594 #define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 83U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
1595 #define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 84U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
1596 #define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 85U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
1597 #define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 86U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
1598 #define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 87U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
1599 #define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 88U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
1600 #define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 89U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
1601 #define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 90U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
1602 #define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 91U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
1603
1604 /* reserved 92U */
1605
1606 #define LL_GPDMA1_TRIGGER_EXTIT0_SYNC 93U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */
1607 #define LL_GPDMA1_TRIGGER_EXTIT1_SYNC 94U /*!< GPDMA1 HW Trigger signal is EXTIT1_SYNC */
1608 #define LL_GPDMA1_TRIGGER_EXTIT2_SYNC 95U /*!< GPDMA1 HW Trigger signal is EXTIT2_SYNC */
1609 #define LL_GPDMA1_TRIGGER_EXTIT3_SYNC 96U /*!< GPDMA1 HW Trigger signal is EXTIT3_SYNC */
1610 #define LL_GPDMA1_TRIGGER_EXTIT4_SYNC 97U /*!< GPDMA1 HW Trigger signal is EXTIT4_SYNC */
1611 #define LL_GPDMA1_TRIGGER_EXTIT5_SYNC 98U /*!< GPDMA1 HW Trigger signal is EXTIT5_SYNC */
1612 #define LL_GPDMA1_TRIGGER_EXTIT6_SYNC 99U /*!< GPDMA1 HW Trigger signal is EXTIT6_SYNC */
1613 #define LL_GPDMA1_TRIGGER_EXTIT7_SYNC 100U /*!< GPDMA1 HW Trigger signal is EXTIT7_SYNC */
1614 #define LL_GPDMA1_TRIGGER_EXTIT8_SYNC 101U /*!< GPDMA1 HW Trigger signal is EXTIT8_SYNC */
1615 #define LL_GPDMA1_TRIGGER_EXTIT9_SYNC 102U /*!< GPDMA1 HW Trigger signal is EXTIT9_SYNC */
1616 #define LL_GPDMA1_TRIGGER_EXTIT10_SYNC 103U /*!< GPDMA1 HW Trigger signal is EXTIT10_SYNC */
1617 #define LL_GPDMA1_TRIGGER_EXTIT11_SYNC 104U /*!< GPDMA1 HW Trigger signal is EXTIT11_SYNC */
1618 #define LL_GPDMA1_TRIGGER_EXTIT12_SYNC 105U /*!< GPDMA1 HW Trigger signal is EXTIT12_SYNC */
1619 #define LL_GPDMA1_TRIGGER_EXTIT13_SYNC 106U /*!< GPDMA1 HW Trigger signal is EXTIT13_SYNC */
1620 #define LL_GPDMA1_TRIGGER_EXTIT14_SYNC 107U /*!< GPDMA1 HW Trigger signal is EXTIT14_SYNC */
1621 #define LL_GPDMA1_TRIGGER_EXTIT15_SYNC 108U /*!< GPDMA1 HW Trigger signal is EXTIT15_SYNC */
1622 /**
1623 * @}
1624 */
1625
1626 /**
1627 * @}
1628 */
1629
1630 /* Exported macro ------------------------------------------------------------*/
1631
1632 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
1633 * @{
1634 */
1635
1636 /** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
1637 * @{
1638 */
1639 /**
1640 * @brief Write a value in DMA register.
1641 * @param __INSTANCE__ DMA Instance.
1642 * @param __REG__ Register to be written.
1643 * @param __VALUE__ Value to be written in the register.
1644 * @retval None.
1645 */
1646 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1647
1648 /**
1649 * @brief Read a value in DMA register.
1650 * @param __INSTANCE__ DMA Instance.
1651 * @param __REG__ Register to be read.
1652 * @retval Register value.
1653 */
1654 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1655 /**
1656 * @}
1657 */
1658
1659 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
1660 * @{
1661 */
1662 /**
1663 * @brief Convert DMAx_Channely into DMAx.
1664 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1665 * @retval DMAx.
1666 */
1667 #define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
1668 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? HPDMA1 : GPDMA1)
1669
1670 /**
1671 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
1672 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1673 * @retval LL_DMA_CHANNEL_y.
1674 */
1675 #define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
1676 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
1677 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
1678 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
1679 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
1680 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
1681 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
1682 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
1683 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
1684 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
1685 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
1686 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
1687 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
1688 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
1689 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
1690 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
1691 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
1692 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \
1693 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \
1694 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \
1695 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \
1696 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
1697 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
1698 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
1699 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
1700 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
1701 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
1702 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
1703 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
1704 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
1705 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
1706 LL_DMA_CHANNEL_15)
1707
1708 /**
1709 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
1710 * @param __DMA_INSTANCE__ DMAx.
1711 * @param __CHANNEL__ LL_DMA_CHANNEL_y.
1712 * @retval DMAx_Channely.
1713 */
1714 #define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
1715 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1716 ? HPDMA1_Channel0 : \
1717 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1718 ? GPDMA1_Channel0 : \
1719 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1720 ? HPDMA1_Channel1 : \
1721 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1722 ? GPDMA1_Channel1 : \
1723 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
1724 ? HPDMA1_Channel2 : \
1725 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
1726 ? GPDMA1_Channel2 : \
1727 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
1728 ? HPDMA1_Channel3 : \
1729 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
1730 ? GPDMA1_Channel3 : \
1731 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
1732 ? HPDMA1_Channel4 : \
1733 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
1734 ? GPDMA1_Channel4 : \
1735 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
1736 ? HPDMA1_Channel5 : \
1737 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
1738 ? GPDMA1_Channel5 : \
1739 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
1740 ? HPDMA1_Channel6 : \
1741 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
1742 ? GPDMA1_Channel6 : \
1743 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
1744 ? HPDMA1_Channel7 : \
1745 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
1746 ? GPDMA1_Channel7 : \
1747 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
1748 ? HPDMA1_Channel8 : \
1749 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
1750 ? GPDMA1_Channel8 : \
1751 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
1752 ? HPDMA1_Channel9 : \
1753 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
1754 ? GPDMA1_Channel9 : \
1755 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
1756 ? HPDMA1_Channel10 : \
1757 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
1758 ? GPDMA1_Channel10 : \
1759 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
1760 ? HPDMA1_Channel11 : \
1761 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
1762 ? GPDMA1_Channel11 : \
1763 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
1764 ? HPDMA1_Channel12 : \
1765 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
1766 ? GPDMA1_Channel12 : \
1767 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
1768 ? HPDMA1_Channel13 : \
1769 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
1770 ? GPDMA1_Channel13 : \
1771 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
1772 ? HPDMA1_Channel14 : \
1773 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
1774 ? GPDMA1_Channel14 : \
1775 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_15)))\
1776 ? HPDMA1_Channel15 : GPDMA1_Channel15)
1777
1778 /**
1779 * @}
1780 */
1781
1782 /**
1783 * @}
1784 */
1785
1786 /* Exported functions --------------------------------------------------------*/
1787
1788 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
1789 * @{
1790 */
1791
1792 /** @defgroup DMA_LL_EF_Configuration Configuration
1793 * @{
1794 */
1795 /**
1796 * @brief Enable channel.
1797 * @note This API is used for all available DMA channels.
1798 * @rmtoll CCR EN LL_DMA_EnableChannel
1799 * @param DMAx DMAx Instance.
1800 * @param Channel This parameter can be one of the following values:
1801 * @arg @ref LL_DMA_CHANNEL_0
1802 * @arg @ref LL_DMA_CHANNEL_1
1803 * @arg @ref LL_DMA_CHANNEL_2
1804 * @arg @ref LL_DMA_CHANNEL_3
1805 * @arg @ref LL_DMA_CHANNEL_4
1806 * @arg @ref LL_DMA_CHANNEL_5
1807 * @arg @ref LL_DMA_CHANNEL_6
1808 * @arg @ref LL_DMA_CHANNEL_7
1809 * @arg @ref LL_DMA_CHANNEL_8
1810 * @arg @ref LL_DMA_CHANNEL_9
1811 * @arg @ref LL_DMA_CHANNEL_10
1812 * @arg @ref LL_DMA_CHANNEL_11
1813 * @arg @ref LL_DMA_CHANNEL_12
1814 * @arg @ref LL_DMA_CHANNEL_13
1815 * @arg @ref LL_DMA_CHANNEL_14
1816 * @arg @ref LL_DMA_CHANNEL_15
1817 * @retval None.
1818 */
LL_DMA_EnableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1819 __STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1820 {
1821 uint32_t dma_base_addr = (uint32_t)DMAx;
1822 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
1823 }
1824
1825 /**
1826 * @brief Disable channel.
1827 * @note This API is used for all available DMA channels.
1828 * @rmtoll CCR EN LL_DMA_DisableChannel
1829 * @param DMAx DMAx Instance.
1830 * @param Channel This parameter can be one of the following values:
1831 * @arg @ref LL_DMA_CHANNEL_0
1832 * @arg @ref LL_DMA_CHANNEL_1
1833 * @arg @ref LL_DMA_CHANNEL_2
1834 * @arg @ref LL_DMA_CHANNEL_3
1835 * @arg @ref LL_DMA_CHANNEL_4
1836 * @arg @ref LL_DMA_CHANNEL_5
1837 * @arg @ref LL_DMA_CHANNEL_6
1838 * @arg @ref LL_DMA_CHANNEL_7
1839 * @arg @ref LL_DMA_CHANNEL_8
1840 * @arg @ref LL_DMA_CHANNEL_9
1841 * @arg @ref LL_DMA_CHANNEL_10
1842 * @arg @ref LL_DMA_CHANNEL_11
1843 * @arg @ref LL_DMA_CHANNEL_12
1844 * @arg @ref LL_DMA_CHANNEL_13
1845 * @arg @ref LL_DMA_CHANNEL_14
1846 * @arg @ref LL_DMA_CHANNEL_15
1847 * @retval None.
1848 */
LL_DMA_DisableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1849 __STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1850 {
1851 uint32_t dma_base_addr = (uint32_t)DMAx;
1852 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1853 (DMA_CCR_SUSP | DMA_CCR_RESET));
1854 }
1855
1856 /**
1857 * @brief Check if channel is enabled or disabled.
1858 * @note This API is used for all available DMA channels.
1859 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
1860 * @param DMAx DMAx Instance
1861 * @param Channel This parameter can be one of the following values:
1862 * @arg @ref LL_DMA_CHANNEL_0
1863 * @arg @ref LL_DMA_CHANNEL_1
1864 * @arg @ref LL_DMA_CHANNEL_2
1865 * @arg @ref LL_DMA_CHANNEL_3
1866 * @arg @ref LL_DMA_CHANNEL_4
1867 * @arg @ref LL_DMA_CHANNEL_5
1868 * @arg @ref LL_DMA_CHANNEL_6
1869 * @arg @ref LL_DMA_CHANNEL_7
1870 * @arg @ref LL_DMA_CHANNEL_8
1871 * @arg @ref LL_DMA_CHANNEL_9
1872 * @arg @ref LL_DMA_CHANNEL_10
1873 * @arg @ref LL_DMA_CHANNEL_11
1874 * @arg @ref LL_DMA_CHANNEL_12
1875 * @arg @ref LL_DMA_CHANNEL_13
1876 * @arg @ref LL_DMA_CHANNEL_14
1877 * @arg @ref LL_DMA_CHANNEL_15
1878 * @retval State of bit (1 or 0).
1879 */
LL_DMA_IsEnabledChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1880 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1881 {
1882 uint32_t dma_base_addr = (uint32_t)DMAx;
1883 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
1884 == (DMA_CCR_EN)) ? 1UL : 0UL);
1885 }
1886
1887 /**
1888 * @brief Reset channel.
1889 * @note This API is used for all available DMA channels.
1890 * @rmtoll CCR RESET LL_DMA_ResetChannel
1891 * @param DMAx DMAx Instance
1892 * @param Channel This parameter can be one of the following values:
1893 * @arg @ref LL_DMA_CHANNEL_0
1894 * @arg @ref LL_DMA_CHANNEL_1
1895 * @arg @ref LL_DMA_CHANNEL_2
1896 * @arg @ref LL_DMA_CHANNEL_3
1897 * @arg @ref LL_DMA_CHANNEL_4
1898 * @arg @ref LL_DMA_CHANNEL_5
1899 * @arg @ref LL_DMA_CHANNEL_6
1900 * @arg @ref LL_DMA_CHANNEL_7
1901 * @arg @ref LL_DMA_CHANNEL_8
1902 * @arg @ref LL_DMA_CHANNEL_9
1903 * @arg @ref LL_DMA_CHANNEL_10
1904 * @arg @ref LL_DMA_CHANNEL_11
1905 * @arg @ref LL_DMA_CHANNEL_12
1906 * @arg @ref LL_DMA_CHANNEL_13
1907 * @arg @ref LL_DMA_CHANNEL_14
1908 * @arg @ref LL_DMA_CHANNEL_15
1909 * @retval None.
1910 */
LL_DMA_ResetChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1911 __STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1912 {
1913 uint32_t dma_base_addr = (uint32_t)DMAx;
1914 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
1915 }
1916
1917 /**
1918 * @brief Suspend channel.
1919 * @note This API is used for all available DMA channels.
1920 * @rmtoll CCR SUSP LL_DMA_SuspendChannel
1921 * @param DMAx DMAx Instance
1922 * @param Channel This parameter can be one of the following values:
1923 * @arg @ref LL_DMA_CHANNEL_0
1924 * @arg @ref LL_DMA_CHANNEL_1
1925 * @arg @ref LL_DMA_CHANNEL_2
1926 * @arg @ref LL_DMA_CHANNEL_3
1927 * @arg @ref LL_DMA_CHANNEL_4
1928 * @arg @ref LL_DMA_CHANNEL_5
1929 * @arg @ref LL_DMA_CHANNEL_6
1930 * @arg @ref LL_DMA_CHANNEL_7
1931 * @arg @ref LL_DMA_CHANNEL_8
1932 * @arg @ref LL_DMA_CHANNEL_9
1933 * @arg @ref LL_DMA_CHANNEL_10
1934 * @arg @ref LL_DMA_CHANNEL_11
1935 * @arg @ref LL_DMA_CHANNEL_12
1936 * @arg @ref LL_DMA_CHANNEL_13
1937 * @arg @ref LL_DMA_CHANNEL_14
1938 * @arg @ref LL_DMA_CHANNEL_15
1939 * @retval None.
1940 */
LL_DMA_SuspendChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1941 __STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1942 {
1943 uint32_t dma_base_addr = (uint32_t)DMAx;
1944 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1945 }
1946
1947 /**
1948 * @brief Resume channel.
1949 * @note This API is used for all available DMA channels.
1950 * @rmtoll CCR SUSP LL_DMA_ResumeChannel
1951 * @param DMAx DMAx Instance
1952 * @param Channel This parameter can be one of the following values:
1953 * @arg @ref LL_DMA_CHANNEL_0
1954 * @arg @ref LL_DMA_CHANNEL_1
1955 * @arg @ref LL_DMA_CHANNEL_2
1956 * @arg @ref LL_DMA_CHANNEL_3
1957 * @arg @ref LL_DMA_CHANNEL_4
1958 * @arg @ref LL_DMA_CHANNEL_5
1959 * @arg @ref LL_DMA_CHANNEL_6
1960 * @arg @ref LL_DMA_CHANNEL_7
1961 * @arg @ref LL_DMA_CHANNEL_8
1962 * @arg @ref LL_DMA_CHANNEL_9
1963 * @arg @ref LL_DMA_CHANNEL_10
1964 * @arg @ref LL_DMA_CHANNEL_11
1965 * @arg @ref LL_DMA_CHANNEL_12
1966 * @arg @ref LL_DMA_CHANNEL_13
1967 * @arg @ref LL_DMA_CHANNEL_14
1968 * @arg @ref LL_DMA_CHANNEL_15
1969 * @retval None.
1970 */
LL_DMA_ResumeChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1971 __STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1972 {
1973 uint32_t dma_base_addr = (uint32_t)DMAx;
1974 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1975 }
1976
1977 /**
1978 * @brief Check if channel is suspended.
1979 * @note This API is used for all available DMA channels.
1980 * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
1981 * @param DMAx DMAx Instance
1982 * @param Channel This parameter can be one of the following values:
1983 * @arg @ref LL_DMA_CHANNEL_0
1984 * @arg @ref LL_DMA_CHANNEL_1
1985 * @arg @ref LL_DMA_CHANNEL_2
1986 * @arg @ref LL_DMA_CHANNEL_3
1987 * @arg @ref LL_DMA_CHANNEL_4
1988 * @arg @ref LL_DMA_CHANNEL_5
1989 * @arg @ref LL_DMA_CHANNEL_6
1990 * @arg @ref LL_DMA_CHANNEL_7
1991 * @arg @ref LL_DMA_CHANNEL_8
1992 * @arg @ref LL_DMA_CHANNEL_9
1993 * @arg @ref LL_DMA_CHANNEL_10
1994 * @arg @ref LL_DMA_CHANNEL_11
1995 * @arg @ref LL_DMA_CHANNEL_12
1996 * @arg @ref LL_DMA_CHANNEL_13
1997 * @arg @ref LL_DMA_CHANNEL_14
1998 * @arg @ref LL_DMA_CHANNEL_15
1999 * @retval State of bit (1 or 0).
2000 */
LL_DMA_IsSuspendedChannel(const DMA_TypeDef * DMAx,uint32_t Channel)2001 __STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
2002 {
2003 uint32_t dma_base_addr = (uint32_t)DMAx;
2004 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
2005 == (DMA_CCR_SUSP)) ? 1UL : 0UL);
2006 }
2007
2008 /**
2009 * @brief Set linked-list base address.
2010 * @note This API is used for all available DMA channels.
2011 * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
2012 * @param DMAx DMAx Instance
2013 * @param Channel This parameter can be one of the following values:
2014 * @arg @ref LL_DMA_CHANNEL_0
2015 * @arg @ref LL_DMA_CHANNEL_1
2016 * @arg @ref LL_DMA_CHANNEL_2
2017 * @arg @ref LL_DMA_CHANNEL_3
2018 * @arg @ref LL_DMA_CHANNEL_4
2019 * @arg @ref LL_DMA_CHANNEL_5
2020 * @arg @ref LL_DMA_CHANNEL_6
2021 * @arg @ref LL_DMA_CHANNEL_7
2022 * @arg @ref LL_DMA_CHANNEL_8
2023 * @arg @ref LL_DMA_CHANNEL_9
2024 * @arg @ref LL_DMA_CHANNEL_10
2025 * @arg @ref LL_DMA_CHANNEL_11
2026 * @arg @ref LL_DMA_CHANNEL_12
2027 * @arg @ref LL_DMA_CHANNEL_13
2028 * @arg @ref LL_DMA_CHANNEL_14
2029 * @arg @ref LL_DMA_CHANNEL_15
2030 * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
2031 * are always 0)
2032 * @retval None.
2033 */
LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListBaseAddr)2034 __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel,
2035 uint32_t LinkedListBaseAddr)
2036 {
2037 uint32_t dma_base_addr = (uint32_t)DMAx;
2038 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
2039 (LinkedListBaseAddr & DMA_CLBAR_LBA));
2040 }
2041
2042 /**
2043 * @brief Get linked-list base address.
2044 * @note This API is used for all available DMA channels.
2045 * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
2046 * @param DMAx DMAx Instance
2047 * @param Channel This parameter can be one of the following values:
2048 * @arg @ref LL_DMA_CHANNEL_0
2049 * @arg @ref LL_DMA_CHANNEL_1
2050 * @arg @ref LL_DMA_CHANNEL_2
2051 * @arg @ref LL_DMA_CHANNEL_3
2052 * @arg @ref LL_DMA_CHANNEL_4
2053 * @arg @ref LL_DMA_CHANNEL_5
2054 * @arg @ref LL_DMA_CHANNEL_6
2055 * @arg @ref LL_DMA_CHANNEL_7
2056 * @arg @ref LL_DMA_CHANNEL_8
2057 * @arg @ref LL_DMA_CHANNEL_9
2058 * @arg @ref LL_DMA_CHANNEL_10
2059 * @arg @ref LL_DMA_CHANNEL_11
2060 * @arg @ref LL_DMA_CHANNEL_12
2061 * @arg @ref LL_DMA_CHANNEL_13
2062 * @arg @ref LL_DMA_CHANNEL_14
2063 * @arg @ref LL_DMA_CHANNEL_15
2064 * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
2065 */
LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel)2066 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel)
2067 {
2068 uint32_t dma_base_addr = (uint32_t)DMAx;
2069 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
2070 }
2071
2072 /**
2073 * @brief Configure all parameters linked to channel control.
2074 * @note This API is used for all available DMA channels.
2075 * @rmtoll CCR PRIO LL_DMA_ConfigControl\n
2076 * CCR LAP LL_DMA_ConfigControl\n
2077 * CCR LSM LL_DMA_ConfigControl
2078 * @param DMAx DMAx Instance
2079 * @param Channel This parameter can be one of the following values:
2080 * @arg @ref LL_DMA_CHANNEL_0
2081 * @arg @ref LL_DMA_CHANNEL_1
2082 * @arg @ref LL_DMA_CHANNEL_2
2083 * @arg @ref LL_DMA_CHANNEL_3
2084 * @arg @ref LL_DMA_CHANNEL_4
2085 * @arg @ref LL_DMA_CHANNEL_5
2086 * @arg @ref LL_DMA_CHANNEL_6
2087 * @arg @ref LL_DMA_CHANNEL_7
2088 * @arg @ref LL_DMA_CHANNEL_8
2089 * @arg @ref LL_DMA_CHANNEL_9
2090 * @arg @ref LL_DMA_CHANNEL_10
2091 * @arg @ref LL_DMA_CHANNEL_11
2092 * @arg @ref LL_DMA_CHANNEL_12
2093 * @arg @ref LL_DMA_CHANNEL_13
2094 * @arg @ref LL_DMA_CHANNEL_14
2095 * @arg @ref LL_DMA_CHANNEL_15
2096 * @param Configuration This parameter must be a combination of all the following values:
2097 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
2098 * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
2099 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
2100 * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
2101 *@retval None.
2102 */
LL_DMA_ConfigControl(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2103 __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2104 {
2105 uint32_t dma_base_addr = (uint32_t)DMAx;
2106 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
2107 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
2108 }
2109
2110 /**
2111 * @brief Set priority level.
2112 * @note This API is used for all available DMA channels.
2113 * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
2114 * @param DMAx DMAx Instance
2115 * @param Channel This parameter can be one of the following values:
2116 * @arg @ref LL_DMA_CHANNEL_0
2117 * @arg @ref LL_DMA_CHANNEL_1
2118 * @arg @ref LL_DMA_CHANNEL_2
2119 * @arg @ref LL_DMA_CHANNEL_3
2120 * @arg @ref LL_DMA_CHANNEL_4
2121 * @arg @ref LL_DMA_CHANNEL_5
2122 * @arg @ref LL_DMA_CHANNEL_6
2123 * @arg @ref LL_DMA_CHANNEL_7
2124 * @arg @ref LL_DMA_CHANNEL_8
2125 * @arg @ref LL_DMA_CHANNEL_9
2126 * @arg @ref LL_DMA_CHANNEL_10
2127 * @arg @ref LL_DMA_CHANNEL_11
2128 * @arg @ref LL_DMA_CHANNEL_12
2129 * @arg @ref LL_DMA_CHANNEL_13
2130 * @arg @ref LL_DMA_CHANNEL_14
2131 * @arg @ref LL_DMA_CHANNEL_15
2132 * @param Priority This parameter can be one of the following values:
2133 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
2134 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
2135 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
2136 * @arg @ref LL_DMA_HIGH_PRIORITY
2137 * @retval None.
2138 */
LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)2139 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
2140 {
2141 uint32_t dma_base_addr = (uint32_t)DMAx;
2142 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
2143 }
2144
2145 /**
2146 * @brief Get Channel priority level.
2147 * @note This API is used for all available DMA channels.
2148 * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
2149 * @param DMAx DMAx Instance
2150 * @param Channel This parameter can be one of the following values:
2151 * @arg @ref LL_DMA_CHANNEL_0
2152 * @arg @ref LL_DMA_CHANNEL_1
2153 * @arg @ref LL_DMA_CHANNEL_2
2154 * @arg @ref LL_DMA_CHANNEL_3
2155 * @arg @ref LL_DMA_CHANNEL_4
2156 * @arg @ref LL_DMA_CHANNEL_5
2157 * @arg @ref LL_DMA_CHANNEL_6
2158 * @arg @ref LL_DMA_CHANNEL_7
2159 * @arg @ref LL_DMA_CHANNEL_8
2160 * @arg @ref LL_DMA_CHANNEL_9
2161 * @arg @ref LL_DMA_CHANNEL_10
2162 * @arg @ref LL_DMA_CHANNEL_11
2163 * @arg @ref LL_DMA_CHANNEL_12
2164 * @arg @ref LL_DMA_CHANNEL_13
2165 * @arg @ref LL_DMA_CHANNEL_14
2166 * @arg @ref LL_DMA_CHANNEL_15
2167 * @retval Returned value can be one of the following values:
2168 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
2169 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
2170 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
2171 * @arg @ref LL_DMA_HIGH_PRIORITY
2172 */
LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel)2173 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
2174 {
2175 uint32_t dma_base_addr = (uint32_t)DMAx;
2176 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
2177 }
2178
2179 /**
2180 * @brief Set linked-list allocated port.
2181 * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
2182 * @param DMAx DMAx Instance
2183 * @param Channel This parameter can be one of the following values:
2184 * @arg @ref LL_DMA_CHANNEL_0
2185 * @arg @ref LL_DMA_CHANNEL_1
2186 * @arg @ref LL_DMA_CHANNEL_2
2187 * @arg @ref LL_DMA_CHANNEL_3
2188 * @arg @ref LL_DMA_CHANNEL_4
2189 * @arg @ref LL_DMA_CHANNEL_5
2190 * @arg @ref LL_DMA_CHANNEL_6
2191 * @arg @ref LL_DMA_CHANNEL_7
2192 * @arg @ref LL_DMA_CHANNEL_8
2193 * @arg @ref LL_DMA_CHANNEL_9
2194 * @arg @ref LL_DMA_CHANNEL_10
2195 * @arg @ref LL_DMA_CHANNEL_11
2196 * @arg @ref LL_DMA_CHANNEL_12
2197 * @arg @ref LL_DMA_CHANNEL_13
2198 * @arg @ref LL_DMA_CHANNEL_14
2199 * @arg @ref LL_DMA_CHANNEL_15
2200 * @param LinkAllocatedPort This parameter can be one of the following values:
2201 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
2202 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
2203 * @retval None.
2204 */
LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkAllocatedPort)2205 __STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
2206 {
2207 uint32_t dma_base_addr = (uint32_t)DMAx;
2208 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
2209 DMA_CCR_LAP, LinkAllocatedPort);
2210 }
2211
2212 /**
2213 * @brief Get linked-list allocated port.
2214 * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
2215 * @param DMAx DMAx Instance
2216 * @param Channel This parameter can be one of the following values:
2217 * @arg @ref LL_DMA_CHANNEL_0
2218 * @arg @ref LL_DMA_CHANNEL_1
2219 * @arg @ref LL_DMA_CHANNEL_2
2220 * @arg @ref LL_DMA_CHANNEL_3
2221 * @arg @ref LL_DMA_CHANNEL_4
2222 * @arg @ref LL_DMA_CHANNEL_5
2223 * @arg @ref LL_DMA_CHANNEL_6
2224 * @arg @ref LL_DMA_CHANNEL_7
2225 * @arg @ref LL_DMA_CHANNEL_8
2226 * @arg @ref LL_DMA_CHANNEL_9
2227 * @arg @ref LL_DMA_CHANNEL_10
2228 * @arg @ref LL_DMA_CHANNEL_11
2229 * @arg @ref LL_DMA_CHANNEL_12
2230 * @arg @ref LL_DMA_CHANNEL_13
2231 * @arg @ref LL_DMA_CHANNEL_14
2232 * @arg @ref LL_DMA_CHANNEL_15
2233 * @retval Returned value can be one of the following values:
2234 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
2235 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
2236 */
LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)2237 __STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
2238 {
2239 uint32_t dma_base_addr = (uint32_t)DMAx;
2240 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
2241 }
2242
2243 /**
2244 * @brief Set link step mode.
2245 * @note This API is used for all available DMA channels.
2246 * @rmtoll CCR LSM LL_DMA_SetLinkStepMode
2247 * @param DMAx DMAx Instance
2248 * @param Channel This parameter can be one of the following values:
2249 * @arg @ref LL_DMA_CHANNEL_0
2250 * @arg @ref LL_DMA_CHANNEL_1
2251 * @arg @ref LL_DMA_CHANNEL_2
2252 * @arg @ref LL_DMA_CHANNEL_3
2253 * @arg @ref LL_DMA_CHANNEL_4
2254 * @arg @ref LL_DMA_CHANNEL_5
2255 * @arg @ref LL_DMA_CHANNEL_6
2256 * @arg @ref LL_DMA_CHANNEL_7
2257 * @arg @ref LL_DMA_CHANNEL_8
2258 * @arg @ref LL_DMA_CHANNEL_9
2259 * @arg @ref LL_DMA_CHANNEL_10
2260 * @arg @ref LL_DMA_CHANNEL_11
2261 * @arg @ref LL_DMA_CHANNEL_12
2262 * @arg @ref LL_DMA_CHANNEL_13
2263 * @arg @ref LL_DMA_CHANNEL_14
2264 * @arg @ref LL_DMA_CHANNEL_15
2265 * @param LinkStepMode This parameter can be one of the following values:
2266 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
2267 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
2268 * @retval None.
2269 */
LL_DMA_SetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkStepMode)2270 __STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
2271 {
2272 uint32_t dma_base_addr = (uint32_t)DMAx;
2273 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
2274 }
2275
2276 /**
2277 * @brief Get Link step mode.
2278 * @note This API is used for all available DMA channels.
2279 * @rmtoll CCR LSM LL_DMA_GetLinkStepMode
2280 * @param DMAx DMAx Instance
2281 * @param Channel This parameter can be one of the following values:
2282 * @arg @ref LL_DMA_CHANNEL_0
2283 * @arg @ref LL_DMA_CHANNEL_1
2284 * @arg @ref LL_DMA_CHANNEL_2
2285 * @arg @ref LL_DMA_CHANNEL_3
2286 * @arg @ref LL_DMA_CHANNEL_4
2287 * @arg @ref LL_DMA_CHANNEL_5
2288 * @arg @ref LL_DMA_CHANNEL_6
2289 * @arg @ref LL_DMA_CHANNEL_7
2290 * @arg @ref LL_DMA_CHANNEL_8
2291 * @arg @ref LL_DMA_CHANNEL_9
2292 * @arg @ref LL_DMA_CHANNEL_10
2293 * @arg @ref LL_DMA_CHANNEL_11
2294 * @arg @ref LL_DMA_CHANNEL_12
2295 * @arg @ref LL_DMA_CHANNEL_13
2296 * @arg @ref LL_DMA_CHANNEL_14
2297 * @arg @ref LL_DMA_CHANNEL_15
2298 * @retval Returned value can be one of the following values:
2299 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
2300 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
2301 */
LL_DMA_GetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel)2302 __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2303 {
2304 uint32_t dma_base_addr = (uint32_t)DMAx;
2305 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
2306 }
2307
2308 /**
2309 * @brief Configure data transfer.
2310 * @note This API is used for all available DMA channels.
2311 * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
2312 * CTR1 DWX LL_DMA_ConfigTransfer\n
2313 * CTR1 DHX LL_DMA_ConfigTransfer\n
2314 * CTR1 DBX LL_DMA_ConfigTransfer\n
2315 * CTR1 DINC LL_DMA_ConfigTransfer\n
2316 * CTR1 SAP LL_DMA_ConfigTransfer\n
2317 * CTR1 SBX LL_DMA_ConfigTransfer\n
2318 * CTR1 PAM LL_DMA_ConfigTransfer\n
2319 * CTR1 SINC LL_DMA_ConfigTransfer
2320 * @param DMAx DMAx Instance
2321 * @param Channel This parameter can be one of the following values:
2322 * @arg @ref LL_DMA_CHANNEL_0
2323 * @arg @ref LL_DMA_CHANNEL_1
2324 * @arg @ref LL_DMA_CHANNEL_2
2325 * @arg @ref LL_DMA_CHANNEL_3
2326 * @arg @ref LL_DMA_CHANNEL_4
2327 * @arg @ref LL_DMA_CHANNEL_5
2328 * @arg @ref LL_DMA_CHANNEL_6
2329 * @arg @ref LL_DMA_CHANNEL_7
2330 * @arg @ref LL_DMA_CHANNEL_8
2331 * @arg @ref LL_DMA_CHANNEL_9
2332 * @arg @ref LL_DMA_CHANNEL_10
2333 * @arg @ref LL_DMA_CHANNEL_11
2334 * @arg @ref LL_DMA_CHANNEL_12
2335 * @arg @ref LL_DMA_CHANNEL_13
2336 * @arg @ref LL_DMA_CHANNEL_14
2337 * @arg @ref LL_DMA_CHANNEL_15
2338 * @param Configuration This parameter must be a combination of all the following values:
2339 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
2340 * @arg @ref LL_DMA_DEST_WORD_PRESERVE or @ref LL_DMA_DEST_WORD_EXCHANGE
2341 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2342 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
2343 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
2344 * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
2345 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
2346 * @ref LL_DMA_DEST_DATAWIDTH_WORD or @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
2347 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
2348 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
2349 * @ref LL_DMA_DATA_PACK_UNPACK
2350 * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
2351 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
2352 * @ref LL_DMA_SRC_DATAWIDTH_WORD or @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
2353 *@retval None.
2354 */
LL_DMA_ConfigTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2355 __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2356 {
2357 uint32_t dma_base_addr = (uint32_t)DMAx;
2358 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2359 DMA_CTR1_DAP | DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | \
2360 DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
2361 }
2362
2363 /**
2364 * @brief Configure source and destination burst length.
2365 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
2366 * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
2367 * @param DMAx DMAx Instance
2368 * @param Channel This parameter can be one of the following values:
2369 * @arg @ref LL_DMA_CHANNEL_0
2370 * @arg @ref LL_DMA_CHANNEL_1
2371 * @arg @ref LL_DMA_CHANNEL_2
2372 * @arg @ref LL_DMA_CHANNEL_3
2373 * @arg @ref LL_DMA_CHANNEL_4
2374 * @arg @ref LL_DMA_CHANNEL_5
2375 * @arg @ref LL_DMA_CHANNEL_6
2376 * @arg @ref LL_DMA_CHANNEL_7
2377 * @arg @ref LL_DMA_CHANNEL_8
2378 * @arg @ref LL_DMA_CHANNEL_9
2379 * @arg @ref LL_DMA_CHANNEL_10
2380 * @arg @ref LL_DMA_CHANNEL_11
2381 * @arg @ref LL_DMA_CHANNEL_12
2382 * @arg @ref LL_DMA_CHANNEL_13
2383 * @arg @ref LL_DMA_CHANNEL_14
2384 * @arg @ref LL_DMA_CHANNEL_15
2385 * @param SrcBurstLength Between 1 to 64
2386 * @param DestBurstLength Between 1 to 64
2387 * @retval None.
2388 */
LL_DMA_ConfigBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength,uint32_t DestBurstLength)2389 __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
2390 uint32_t DestBurstLength)
2391 {
2392 uint32_t dma_base_addr = (uint32_t)DMAx;
2393 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2394 (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
2395 (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
2396 }
2397
2398 #if defined(CPU_IN_SECURE_STATE)
2399 /**
2400 * @brief Set the static isolation attribute (CID) of the DMA channel.
2401 * @note This API is used for HPDMA channels.
2402 * @rmtoll CCIDCFGR SCID LL_DMA_SetStaticIsolation\n
2403 * @param DMAx DMAx Instance
2404 * @param Channel This parameter can be one of the following values:
2405 * @arg @ref LL_DMA_CHANNEL_0
2406 * @arg @ref LL_DMA_CHANNEL_1
2407 * @arg @ref LL_DMA_CHANNEL_2
2408 * @arg @ref LL_DMA_CHANNEL_3
2409 * @arg @ref LL_DMA_CHANNEL_4
2410 * @arg @ref LL_DMA_CHANNEL_5
2411 * @arg @ref LL_DMA_CHANNEL_6
2412 * @arg @ref LL_DMA_CHANNEL_7
2413 * @arg @ref LL_DMA_CHANNEL_8
2414 * @arg @ref LL_DMA_CHANNEL_9
2415 * @arg @ref LL_DMA_CHANNEL_10
2416 * @arg @ref LL_DMA_CHANNEL_11
2417 * @arg @ref LL_DMA_CHANNEL_12
2418 * @arg @ref LL_DMA_CHANNEL_13
2419 * @arg @ref LL_DMA_CHANNEL_14
2420 * @arg @ref LL_DMA_CHANNEL_15
2421 * @param Cid This parameter must be a combination of all the following values:
2422 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_0
2423 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_1
2424 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_2
2425 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_3
2426 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_4
2427 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_5
2428 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_6
2429 * @retval None.
2430 */
LL_DMA_SetStaticIsolation(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Cid)2431 __STATIC_INLINE void LL_DMA_SetStaticIsolation(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Cid)
2432 {
2433 uint32_t dma_base_addr = (uint32_t)DMAx;
2434 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR,
2435 DMA_CCIDCFGR_SCID, Cid);
2436 }
2437 #endif /* CPU_IN_SECURE_STATE */
2438
2439 /**
2440 * @brief Get the static isolation attribute (CID) of the DMA channel.
2441 * @note This API is used for HPDMA channels.
2442 * @rmtoll CCIDCFGR SCID LL_DMA_GetStaticIsolation\n
2443 * @param DMAx DMAx Instance
2444 * @param Channel This parameter can be one of the following values:
2445 * @arg @ref LL_DMA_CHANNEL_0
2446 * @arg @ref LL_DMA_CHANNEL_1
2447 * @arg @ref LL_DMA_CHANNEL_2
2448 * @arg @ref LL_DMA_CHANNEL_3
2449 * @arg @ref LL_DMA_CHANNEL_4
2450 * @arg @ref LL_DMA_CHANNEL_5
2451 * @arg @ref LL_DMA_CHANNEL_6
2452 * @arg @ref LL_DMA_CHANNEL_7
2453 * @arg @ref LL_DMA_CHANNEL_8
2454 * @arg @ref LL_DMA_CHANNEL_9
2455 * @arg @ref LL_DMA_CHANNEL_10
2456 * @arg @ref LL_DMA_CHANNEL_11
2457 * @arg @ref LL_DMA_CHANNEL_12
2458 * @arg @ref LL_DMA_CHANNEL_13
2459 * @arg @ref LL_DMA_CHANNEL_14
2460 * @arg @ref LL_DMA_CHANNEL_15
2461 * @retval Returned value can be one of the following values:
2462 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_0
2463 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_1
2464 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_2
2465 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_3
2466 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_4
2467 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_5
2468 * @arg @ref LL_DMA_CHANNEL_STATIC_CID_6
2469 */
LL_DMA_GetStaticIsolation(DMA_TypeDef * DMAx,uint32_t Channel)2470 __STATIC_INLINE uint32_t LL_DMA_GetStaticIsolation(DMA_TypeDef *DMAx, uint32_t Channel)
2471 {
2472 uint32_t dma_base_addr = (uint32_t)DMAx;
2473 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR,
2474 DMA_CCIDCFGR_SCID));
2475 }
2476
2477 /**
2478 * @brief Enable the isolation (CID filtering) of the DMA channel.
2479 * @note This API is used for HPDMA channels.
2480 * @rmtoll CCIDCFGR CFEN LL_DMA_EnableIsolation
2481 * @param DMAx DMAx Instance
2482 * @param Channel This parameter can be one of the following values:
2483 * @arg @ref LL_DMA_CHANNEL_0
2484 * @arg @ref LL_DMA_CHANNEL_1
2485 * @arg @ref LL_DMA_CHANNEL_2
2486 * @arg @ref LL_DMA_CHANNEL_3
2487 * @arg @ref LL_DMA_CHANNEL_4
2488 * @arg @ref LL_DMA_CHANNEL_5
2489 * @arg @ref LL_DMA_CHANNEL_6
2490 * @arg @ref LL_DMA_CHANNEL_7
2491 * @arg @ref LL_DMA_CHANNEL_8
2492 * @arg @ref LL_DMA_CHANNEL_9
2493 * @arg @ref LL_DMA_CHANNEL_10
2494 * @arg @ref LL_DMA_CHANNEL_11
2495 * @arg @ref LL_DMA_CHANNEL_12
2496 * @arg @ref LL_DMA_CHANNEL_13
2497 * @arg @ref LL_DMA_CHANNEL_14
2498 * @arg @ref LL_DMA_CHANNEL_15
2499 * @retval None.
2500 */
LL_DMA_EnableIsolation(const DMA_TypeDef * DMAx,uint32_t Channel)2501 __STATIC_INLINE void LL_DMA_EnableIsolation(const DMA_TypeDef *DMAx, uint32_t Channel)
2502 {
2503 uint32_t dma_base_addr = (uint32_t)DMAx;
2504 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, DMA_CCIDCFGR_CFEN);
2505 }
2506
2507 /**
2508 * @brief Disable the isolation (CID filtering) of the DMA channel.
2509 * @note This API is used for HPDMA channels.
2510 * @rmtoll CCIDCFGR CFEN LL_DMA_DisableIsolation
2511 * @param DMAx DMAx Instance
2512 * @param Channel This parameter can be one of the following values:
2513 * @arg @ref LL_DMA_CHANNEL_0
2514 * @arg @ref LL_DMA_CHANNEL_1
2515 * @arg @ref LL_DMA_CHANNEL_2
2516 * @arg @ref LL_DMA_CHANNEL_3
2517 * @arg @ref LL_DMA_CHANNEL_4
2518 * @arg @ref LL_DMA_CHANNEL_5
2519 * @arg @ref LL_DMA_CHANNEL_6
2520 * @arg @ref LL_DMA_CHANNEL_7
2521 * @arg @ref LL_DMA_CHANNEL_8
2522 * @arg @ref LL_DMA_CHANNEL_9
2523 * @arg @ref LL_DMA_CHANNEL_10
2524 * @arg @ref LL_DMA_CHANNEL_11
2525 * @arg @ref LL_DMA_CHANNEL_12
2526 * @arg @ref LL_DMA_CHANNEL_13
2527 * @arg @ref LL_DMA_CHANNEL_14
2528 * @arg @ref LL_DMA_CHANNEL_15
2529 * @retval None.
2530 */
LL_DMA_DisableIsolation(const DMA_TypeDef * DMAx,uint32_t Channel)2531 __STATIC_INLINE void LL_DMA_DisableIsolation(const DMA_TypeDef *DMAx, uint32_t Channel)
2532 {
2533 uint32_t dma_base_addr = (uint32_t)DMAx;
2534 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, DMA_CCIDCFGR_CFEN);
2535 }
2536
2537 /**
2538 * @brief Check isolation (CID filtering) of the DMA channel.
2539 * @note This API is used for HPDMA channels.
2540 * @rmtoll CCIDCFGR CFEN LL_DMA_IsEnabledIsolation
2541 * @param DMAx DMAx Instance
2542 * @param Channel This parameter can be one of the following values:
2543 * @arg @ref LL_DMA_CHANNEL_0
2544 * @arg @ref LL_DMA_CHANNEL_1
2545 * @arg @ref LL_DMA_CHANNEL_2
2546 * @arg @ref LL_DMA_CHANNEL_3
2547 * @arg @ref LL_DMA_CHANNEL_4
2548 * @arg @ref LL_DMA_CHANNEL_5
2549 * @arg @ref LL_DMA_CHANNEL_6
2550 * @arg @ref LL_DMA_CHANNEL_7
2551 * @arg @ref LL_DMA_CHANNEL_8
2552 * @arg @ref LL_DMA_CHANNEL_9
2553 * @arg @ref LL_DMA_CHANNEL_10
2554 * @arg @ref LL_DMA_CHANNEL_11
2555 * @arg @ref LL_DMA_CHANNEL_12
2556 * @arg @ref LL_DMA_CHANNEL_13
2557 * @arg @ref LL_DMA_CHANNEL_14
2558 * @arg @ref LL_DMA_CHANNEL_15
2559 * @retval State of bit (1 or 0).
2560 */
LL_DMA_IsEnabledIsolation(const DMA_TypeDef * DMAx,uint32_t Channel)2561 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIsolation(const DMA_TypeDef *DMAx, uint32_t Channel)
2562 {
2563 uint32_t dma_base_addr = (uint32_t)DMAx;
2564 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR,
2565 DMA_CCIDCFGR_CFEN) == (DMA_CCIDCFGR_CFEN)) ? 1UL : 0UL);
2566 }
2567
2568 #if defined (CPU_IN_SECURE_STATE)
2569 /**
2570 * @brief Configure all secure parameters linked to DMA channel.
2571 * @note This API is used for all available DMA channels.
2572 * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n
2573 * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n
2574 * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure
2575 * @param DMAx DMAx Instance
2576 * @param Channel This parameter can be one of the following values:
2577 * @arg @ref LL_DMA_CHANNEL_0
2578 * @arg @ref LL_DMA_CHANNEL_1
2579 * @arg @ref LL_DMA_CHANNEL_2
2580 * @arg @ref LL_DMA_CHANNEL_3
2581 * @arg @ref LL_DMA_CHANNEL_4
2582 * @arg @ref LL_DMA_CHANNEL_5
2583 * @arg @ref LL_DMA_CHANNEL_6
2584 * @arg @ref LL_DMA_CHANNEL_7
2585 * @arg @ref LL_DMA_CHANNEL_8
2586 * @arg @ref LL_DMA_CHANNEL_9
2587 * @arg @ref LL_DMA_CHANNEL_10
2588 * @arg @ref LL_DMA_CHANNEL_11
2589 * @arg @ref LL_DMA_CHANNEL_12
2590 * @arg @ref LL_DMA_CHANNEL_13
2591 * @arg @ref LL_DMA_CHANNEL_14
2592 * @arg @ref LL_DMA_CHANNEL_15
2593 * @param Configuration This parameter must be a combination of all the following values:
2594 * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC
2595 * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC
2596 * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
2597 * @retval None.
2598 */
LL_DMA_ConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2599 __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2600 {
2601 uint32_t dma_base_addr = (uint32_t)DMAx;
2602 MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
2603 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2604 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
2605 }
2606
2607 /**
2608 * @brief Enable security attribute of the DMA transfer to the destination.
2609 * @note This API is used for all available DMA channels.
2610 * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure
2611 * @param DMAx DMAx Instance
2612 * @param Channel This parameter can be one of the following values:
2613 * @arg @ref LL_DMA_CHANNEL_0
2614 * @arg @ref LL_DMA_CHANNEL_1
2615 * @arg @ref LL_DMA_CHANNEL_2
2616 * @arg @ref LL_DMA_CHANNEL_3
2617 * @arg @ref LL_DMA_CHANNEL_4
2618 * @arg @ref LL_DMA_CHANNEL_5
2619 * @arg @ref LL_DMA_CHANNEL_6
2620 * @arg @ref LL_DMA_CHANNEL_7
2621 * @arg @ref LL_DMA_CHANNEL_8
2622 * @arg @ref LL_DMA_CHANNEL_9
2623 * @arg @ref LL_DMA_CHANNEL_10
2624 * @arg @ref LL_DMA_CHANNEL_11
2625 * @arg @ref LL_DMA_CHANNEL_12
2626 * @arg @ref LL_DMA_CHANNEL_13
2627 * @arg @ref LL_DMA_CHANNEL_14
2628 * @arg @ref LL_DMA_CHANNEL_15
2629 * @retval None.
2630 */
LL_DMA_EnableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2631 __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2632 {
2633 uint32_t dma_base_addr = (uint32_t)DMAx;
2634 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
2635 }
2636
2637 /**
2638 * @brief Disable security attribute of the DMA transfer to the destination.
2639 * @note This API is used for all available DMA channels.
2640 * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure
2641 * @param DMAx DMAx Instance
2642 * @param Channel This parameter can be one of the following values:
2643 * @arg @ref LL_DMA_CHANNEL_0
2644 * @arg @ref LL_DMA_CHANNEL_1
2645 * @arg @ref LL_DMA_CHANNEL_2
2646 * @arg @ref LL_DMA_CHANNEL_3
2647 * @arg @ref LL_DMA_CHANNEL_4
2648 * @arg @ref LL_DMA_CHANNEL_5
2649 * @arg @ref LL_DMA_CHANNEL_6
2650 * @arg @ref LL_DMA_CHANNEL_7
2651 * @arg @ref LL_DMA_CHANNEL_8
2652 * @arg @ref LL_DMA_CHANNEL_9
2653 * @arg @ref LL_DMA_CHANNEL_10
2654 * @arg @ref LL_DMA_CHANNEL_11
2655 * @arg @ref LL_DMA_CHANNEL_12
2656 * @arg @ref LL_DMA_CHANNEL_13
2657 * @arg @ref LL_DMA_CHANNEL_14
2658 * @arg @ref LL_DMA_CHANNEL_15
2659 * @retval None.
2660 */
LL_DMA_DisableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2661 __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2662 {
2663 uint32_t dma_base_addr = (uint32_t)DMAx;
2664 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
2665 }
2666 #endif /* CPU_IN_SECURE_STATE */
2667
2668 /**
2669 * @brief Check security attribute of the DMA transfer to the destination.
2670 * @note This API is used for all available DMA channels.
2671 * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure
2672 * @param DMAx DMAx Instance
2673 * @param Channel This parameter can be one of the following values:
2674 * @arg @ref LL_DMA_CHANNEL_0
2675 * @arg @ref LL_DMA_CHANNEL_1
2676 * @arg @ref LL_DMA_CHANNEL_2
2677 * @arg @ref LL_DMA_CHANNEL_3
2678 * @arg @ref LL_DMA_CHANNEL_4
2679 * @arg @ref LL_DMA_CHANNEL_5
2680 * @arg @ref LL_DMA_CHANNEL_6
2681 * @arg @ref LL_DMA_CHANNEL_7
2682 * @arg @ref LL_DMA_CHANNEL_8
2683 * @arg @ref LL_DMA_CHANNEL_9
2684 * @arg @ref LL_DMA_CHANNEL_10
2685 * @arg @ref LL_DMA_CHANNEL_11
2686 * @arg @ref LL_DMA_CHANNEL_12
2687 * @arg @ref LL_DMA_CHANNEL_13
2688 * @arg @ref LL_DMA_CHANNEL_14
2689 * @arg @ref LL_DMA_CHANNEL_15
2690 * @retval State of bit (1 or 0).
2691 */
LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2692 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2693 {
2694 uint32_t dma_base_addr = (uint32_t)DMAx;
2695 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
2696 == (DMA_CTR1_DSEC)) ? 1UL : 0UL);
2697 }
2698
2699 #if defined (CPU_IN_SECURE_STATE)
2700 /**
2701 * @brief Enable security attribute of the DMA transfer from the source.
2702 * @note This API is used for all available DMA channels.
2703 * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure
2704 * @param DMAx DMAx Instance
2705 * @param Channel This parameter can be one of the following values:
2706 * @arg @ref LL_DMA_CHANNEL_0
2707 * @arg @ref LL_DMA_CHANNEL_1
2708 * @arg @ref LL_DMA_CHANNEL_2
2709 * @arg @ref LL_DMA_CHANNEL_3
2710 * @arg @ref LL_DMA_CHANNEL_4
2711 * @arg @ref LL_DMA_CHANNEL_5
2712 * @arg @ref LL_DMA_CHANNEL_6
2713 * @arg @ref LL_DMA_CHANNEL_7
2714 * @arg @ref LL_DMA_CHANNEL_8
2715 * @arg @ref LL_DMA_CHANNEL_9
2716 * @arg @ref LL_DMA_CHANNEL_10
2717 * @arg @ref LL_DMA_CHANNEL_11
2718 * @arg @ref LL_DMA_CHANNEL_12
2719 * @arg @ref LL_DMA_CHANNEL_13
2720 * @arg @ref LL_DMA_CHANNEL_14
2721 * @arg @ref LL_DMA_CHANNEL_15
2722 * @retval None.
2723 */
LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2724 __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2725 {
2726 uint32_t dma_base_addr = (uint32_t)DMAx;
2727 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
2728 }
2729
2730 /**
2731 * @brief Disable security attribute of the DMA transfer from the source.
2732 * @note This API is used for all available DMA channels.
2733 * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure
2734 * @param DMAx DMAx Instance
2735 * @param Channel This parameter can be one of the following values:
2736 * @arg @ref LL_DMA_CHANNEL_0
2737 * @arg @ref LL_DMA_CHANNEL_1
2738 * @arg @ref LL_DMA_CHANNEL_2
2739 * @arg @ref LL_DMA_CHANNEL_3
2740 * @arg @ref LL_DMA_CHANNEL_4
2741 * @arg @ref LL_DMA_CHANNEL_5
2742 * @arg @ref LL_DMA_CHANNEL_6
2743 * @arg @ref LL_DMA_CHANNEL_7
2744 * @arg @ref LL_DMA_CHANNEL_8
2745 * @arg @ref LL_DMA_CHANNEL_9
2746 * @arg @ref LL_DMA_CHANNEL_10
2747 * @arg @ref LL_DMA_CHANNEL_11
2748 * @arg @ref LL_DMA_CHANNEL_12
2749 * @arg @ref LL_DMA_CHANNEL_13
2750 * @arg @ref LL_DMA_CHANNEL_14
2751 * @arg @ref LL_DMA_CHANNEL_15
2752 * @retval None.
2753 */
LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2754 __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2755 {
2756 uint32_t dma_base_addr = (uint32_t)DMAx;
2757 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
2758 }
2759 #endif /* CPU_IN_SECURE_STATE */
2760
2761 /**
2762 * @brief Check security attribute of the DMA transfer from the source.
2763 * @note This API is used for all available DMA channels.
2764 * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure
2765 * @param DMAx DMAx Instance
2766 * @param Channel This parameter can be one of the following values:
2767 * @arg @ref LL_DMA_CHANNEL_0
2768 * @arg @ref LL_DMA_CHANNEL_1
2769 * @arg @ref LL_DMA_CHANNEL_2
2770 * @arg @ref LL_DMA_CHANNEL_3
2771 * @arg @ref LL_DMA_CHANNEL_4
2772 * @arg @ref LL_DMA_CHANNEL_5
2773 * @arg @ref LL_DMA_CHANNEL_6
2774 * @arg @ref LL_DMA_CHANNEL_7
2775 * @arg @ref LL_DMA_CHANNEL_8
2776 * @arg @ref LL_DMA_CHANNEL_9
2777 * @arg @ref LL_DMA_CHANNEL_10
2778 * @arg @ref LL_DMA_CHANNEL_11
2779 * @arg @ref LL_DMA_CHANNEL_12
2780 * @arg @ref LL_DMA_CHANNEL_13
2781 * @arg @ref LL_DMA_CHANNEL_14
2782 * @arg @ref LL_DMA_CHANNEL_15
2783 * @retval State of bit (1 or 0).
2784 */
LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2785 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2786 {
2787 uint32_t dma_base_addr = (uint32_t)DMAx;
2788 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
2789 == (DMA_CTR1_SSEC)) ? 1UL : 0UL);
2790 }
2791
2792 /**
2793 * @brief Set destination allocated port.
2794 * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
2795 * @param DMAx DMAx Instance
2796 * @param Channel This parameter can be one of the following values:
2797 * @arg @ref LL_DMA_CHANNEL_0
2798 * @arg @ref LL_DMA_CHANNEL_1
2799 * @arg @ref LL_DMA_CHANNEL_2
2800 * @arg @ref LL_DMA_CHANNEL_3
2801 * @arg @ref LL_DMA_CHANNEL_4
2802 * @arg @ref LL_DMA_CHANNEL_5
2803 * @arg @ref LL_DMA_CHANNEL_6
2804 * @arg @ref LL_DMA_CHANNEL_7
2805 * @arg @ref LL_DMA_CHANNEL_8
2806 * @arg @ref LL_DMA_CHANNEL_9
2807 * @arg @ref LL_DMA_CHANNEL_10
2808 * @arg @ref LL_DMA_CHANNEL_11
2809 * @arg @ref LL_DMA_CHANNEL_12
2810 * @arg @ref LL_DMA_CHANNEL_13
2811 * @arg @ref LL_DMA_CHANNEL_14
2812 * @arg @ref LL_DMA_CHANNEL_15
2813 * @param DestAllocatedPort This parameter can be one of the following values:
2814 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2815 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2816 * @retval None.
2817 */
LL_DMA_SetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAllocatedPort)2818 __STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
2819 {
2820 uint32_t dma_base_addr = (uint32_t)DMAx;
2821 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
2822 DestAllocatedPort);
2823 }
2824
2825 /**
2826 * @brief Get destination allocated port.
2827 * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
2828 * @param DMAx DMAx Instance
2829 * @param Channel This parameter can be one of the following values:
2830 * @arg @ref LL_DMA_CHANNEL_0
2831 * @arg @ref LL_DMA_CHANNEL_1
2832 * @arg @ref LL_DMA_CHANNEL_2
2833 * @arg @ref LL_DMA_CHANNEL_3
2834 * @arg @ref LL_DMA_CHANNEL_4
2835 * @arg @ref LL_DMA_CHANNEL_5
2836 * @arg @ref LL_DMA_CHANNEL_6
2837 * @arg @ref LL_DMA_CHANNEL_7
2838 * @arg @ref LL_DMA_CHANNEL_8
2839 * @arg @ref LL_DMA_CHANNEL_9
2840 * @arg @ref LL_DMA_CHANNEL_10
2841 * @arg @ref LL_DMA_CHANNEL_11
2842 * @arg @ref LL_DMA_CHANNEL_12
2843 * @arg @ref LL_DMA_CHANNEL_13
2844 * @arg @ref LL_DMA_CHANNEL_14
2845 * @arg @ref LL_DMA_CHANNEL_15
2846 * @retval Returned value can be one of the following values:
2847 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2848 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2849 */
LL_DMA_GetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)2850 __STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
2851 {
2852 uint32_t dma_base_addr = (uint32_t)DMAx;
2853 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
2854 }
2855
2856 /**
2857 * @brief Set destination word exchange.
2858 * @rmtoll CTR1 DWX LL_DMA_SetDestWordExchange
2859 * @param DMAx DMAx Instance
2860 * @param Channel This parameter can be one of the following values:
2861 * @arg @ref LL_DMA_CHANNEL_0
2862 * @arg @ref LL_DMA_CHANNEL_1
2863 * @arg @ref LL_DMA_CHANNEL_2
2864 * @arg @ref LL_DMA_CHANNEL_3
2865 * @arg @ref LL_DMA_CHANNEL_4
2866 * @arg @ref LL_DMA_CHANNEL_5
2867 * @arg @ref LL_DMA_CHANNEL_6
2868 * @arg @ref LL_DMA_CHANNEL_7
2869 * @arg @ref LL_DMA_CHANNEL_8
2870 * @arg @ref LL_DMA_CHANNEL_9
2871 * @arg @ref LL_DMA_CHANNEL_10
2872 * @arg @ref LL_DMA_CHANNEL_11
2873 * @arg @ref LL_DMA_CHANNEL_12
2874 * @arg @ref LL_DMA_CHANNEL_13
2875 * @arg @ref LL_DMA_CHANNEL_14
2876 * @arg @ref LL_DMA_CHANNEL_15
2877 * @param DestWordExchange This parameter can be one of the following values:
2878 * @arg @ref LL_DMA_DEST_WORD_PRESERVE
2879 * @arg @ref LL_DMA_DEST_WORD_EXCHANGE
2880 * @retval None.
2881 */
LL_DMA_SetDestWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestWordExchange)2882 __STATIC_INLINE void LL_DMA_SetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestWordExchange)
2883 {
2884 uint32_t dma_base_addr = (uint32_t)DMAx;
2885 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX,
2886 DestWordExchange);
2887 }
2888
2889 /**
2890 * @brief Get destination word exchange.
2891 * @rmtoll CTR1 DWX LL_DMA_GetDestWordExchange
2892 * @param DMAx DMAx Instance
2893 * @param Channel This parameter can be one of the following values:
2894 * @arg @ref LL_DMA_CHANNEL_0
2895 * @arg @ref LL_DMA_CHANNEL_1
2896 * @arg @ref LL_DMA_CHANNEL_2
2897 * @arg @ref LL_DMA_CHANNEL_3
2898 * @arg @ref LL_DMA_CHANNEL_4
2899 * @arg @ref LL_DMA_CHANNEL_5
2900 * @arg @ref LL_DMA_CHANNEL_6
2901 * @arg @ref LL_DMA_CHANNEL_7
2902 * @arg @ref LL_DMA_CHANNEL_8
2903 * @arg @ref LL_DMA_CHANNEL_9
2904 * @arg @ref LL_DMA_CHANNEL_10
2905 * @arg @ref LL_DMA_CHANNEL_11
2906 * @arg @ref LL_DMA_CHANNEL_12
2907 * @arg @ref LL_DMA_CHANNEL_13
2908 * @arg @ref LL_DMA_CHANNEL_14
2909 * @arg @ref LL_DMA_CHANNEL_15
2910 * @retval Returned value can be one of the following values:
2911 * @arg @ref LL_DMA_DEST_WORD_PRESERVE
2912 * @arg @ref LL_DMA_DEST_WORD_EXCHANGE
2913 */
LL_DMA_GetDestWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2914 __STATIC_INLINE uint32_t LL_DMA_GetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2915 {
2916 uint32_t dma_base_addr = (uint32_t)DMAx;
2917 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX));
2918 }
2919
2920 /**
2921 * @brief Set destination half-word exchange.
2922 * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
2923 * @param DMAx DMAx Instance
2924 * @param Channel This parameter can be one of the following values:
2925 * @arg @ref LL_DMA_CHANNEL_0
2926 * @arg @ref LL_DMA_CHANNEL_1
2927 * @arg @ref LL_DMA_CHANNEL_2
2928 * @arg @ref LL_DMA_CHANNEL_3
2929 * @arg @ref LL_DMA_CHANNEL_4
2930 * @arg @ref LL_DMA_CHANNEL_5
2931 * @arg @ref LL_DMA_CHANNEL_6
2932 * @arg @ref LL_DMA_CHANNEL_7
2933 * @arg @ref LL_DMA_CHANNEL_8
2934 * @arg @ref LL_DMA_CHANNEL_9
2935 * @arg @ref LL_DMA_CHANNEL_10
2936 * @arg @ref LL_DMA_CHANNEL_11
2937 * @arg @ref LL_DMA_CHANNEL_12
2938 * @arg @ref LL_DMA_CHANNEL_13
2939 * @arg @ref LL_DMA_CHANNEL_14
2940 * @arg @ref LL_DMA_CHANNEL_15
2941 * @param DestHWordExchange This parameter can be one of the following values:
2942 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2943 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2944 * @retval None.
2945 */
LL_DMA_SetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestHWordExchange)2946 __STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
2947 {
2948 uint32_t dma_base_addr = (uint32_t)DMAx;
2949 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
2950 DestHWordExchange);
2951 }
2952
2953 /**
2954 * @brief Get destination half-word exchange.
2955 * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
2956 * @param DMAx DMAx Instance
2957 * @param Channel This parameter can be one of the following values:
2958 * @arg @ref LL_DMA_CHANNEL_0
2959 * @arg @ref LL_DMA_CHANNEL_1
2960 * @arg @ref LL_DMA_CHANNEL_2
2961 * @arg @ref LL_DMA_CHANNEL_3
2962 * @arg @ref LL_DMA_CHANNEL_4
2963 * @arg @ref LL_DMA_CHANNEL_5
2964 * @arg @ref LL_DMA_CHANNEL_6
2965 * @arg @ref LL_DMA_CHANNEL_7
2966 * @arg @ref LL_DMA_CHANNEL_8
2967 * @arg @ref LL_DMA_CHANNEL_9
2968 * @arg @ref LL_DMA_CHANNEL_10
2969 * @arg @ref LL_DMA_CHANNEL_11
2970 * @arg @ref LL_DMA_CHANNEL_12
2971 * @arg @ref LL_DMA_CHANNEL_13
2972 * @arg @ref LL_DMA_CHANNEL_14
2973 * @arg @ref LL_DMA_CHANNEL_15
2974 * @retval Returned value can be one of the following values:
2975 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2976 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2977 */
LL_DMA_GetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2978 __STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2979 {
2980 uint32_t dma_base_addr = (uint32_t)DMAx;
2981 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
2982 }
2983
2984 /**
2985 * @brief Set destination byte exchange.
2986 * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
2987 * @param DMAx DMAx Instance
2988 * @param Channel This parameter can be one of the following values:
2989 * @arg @ref LL_DMA_CHANNEL_0
2990 * @arg @ref LL_DMA_CHANNEL_1
2991 * @arg @ref LL_DMA_CHANNEL_2
2992 * @arg @ref LL_DMA_CHANNEL_3
2993 * @arg @ref LL_DMA_CHANNEL_4
2994 * @arg @ref LL_DMA_CHANNEL_5
2995 * @arg @ref LL_DMA_CHANNEL_6
2996 * @arg @ref LL_DMA_CHANNEL_7
2997 * @arg @ref LL_DMA_CHANNEL_8
2998 * @arg @ref LL_DMA_CHANNEL_9
2999 * @arg @ref LL_DMA_CHANNEL_10
3000 * @arg @ref LL_DMA_CHANNEL_11
3001 * @arg @ref LL_DMA_CHANNEL_12
3002 * @arg @ref LL_DMA_CHANNEL_13
3003 * @arg @ref LL_DMA_CHANNEL_14
3004 * @arg @ref LL_DMA_CHANNEL_15
3005 * @param DestByteExchange This parameter can be one of the following values:
3006 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
3007 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
3008 * @retval None.
3009 */
LL_DMA_SetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestByteExchange)3010 __STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
3011 {
3012 uint32_t dma_base_addr = (uint32_t)DMAx;
3013 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
3014 DestByteExchange);
3015 }
3016
3017 /**
3018 * @brief Get destination byte exchange.
3019 * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
3020 * @param DMAx DMAx Instance
3021 * @param Channel This parameter can be one of the following values:
3022 * @arg @ref LL_DMA_CHANNEL_0
3023 * @arg @ref LL_DMA_CHANNEL_1
3024 * @arg @ref LL_DMA_CHANNEL_2
3025 * @arg @ref LL_DMA_CHANNEL_3
3026 * @arg @ref LL_DMA_CHANNEL_4
3027 * @arg @ref LL_DMA_CHANNEL_5
3028 * @arg @ref LL_DMA_CHANNEL_6
3029 * @arg @ref LL_DMA_CHANNEL_7
3030 * @arg @ref LL_DMA_CHANNEL_8
3031 * @arg @ref LL_DMA_CHANNEL_9
3032 * @arg @ref LL_DMA_CHANNEL_10
3033 * @arg @ref LL_DMA_CHANNEL_11
3034 * @arg @ref LL_DMA_CHANNEL_12
3035 * @arg @ref LL_DMA_CHANNEL_13
3036 * @arg @ref LL_DMA_CHANNEL_14
3037 * @arg @ref LL_DMA_CHANNEL_15
3038 * @retval Returned value can be one of the following values:
3039 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
3040 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
3041 */
LL_DMA_GetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)3042 __STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
3043 {
3044 uint32_t dma_base_addr = (uint32_t)DMAx;
3045 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
3046 }
3047
3048 /**
3049 * @brief Set source byte exchange.
3050 * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
3051 * @param DMAx DMAx Instance
3052 * @param Channel This parameter can be one of the following values:
3053 * @arg @ref LL_DMA_CHANNEL_0
3054 * @arg @ref LL_DMA_CHANNEL_1
3055 * @arg @ref LL_DMA_CHANNEL_2
3056 * @arg @ref LL_DMA_CHANNEL_3
3057 * @arg @ref LL_DMA_CHANNEL_4
3058 * @arg @ref LL_DMA_CHANNEL_5
3059 * @arg @ref LL_DMA_CHANNEL_6
3060 * @arg @ref LL_DMA_CHANNEL_7
3061 * @arg @ref LL_DMA_CHANNEL_8
3062 * @arg @ref LL_DMA_CHANNEL_9
3063 * @arg @ref LL_DMA_CHANNEL_10
3064 * @arg @ref LL_DMA_CHANNEL_11
3065 * @arg @ref LL_DMA_CHANNEL_12
3066 * @arg @ref LL_DMA_CHANNEL_13
3067 * @arg @ref LL_DMA_CHANNEL_14
3068 * @arg @ref LL_DMA_CHANNEL_15
3069 * @param SrcByteExchange This parameter can be one of the following values:
3070 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
3071 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
3072 * @retval None.
3073 */
LL_DMA_SetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcByteExchange)3074 __STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
3075 {
3076 uint32_t dma_base_addr = (uint32_t)DMAx;
3077 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
3078 SrcByteExchange);
3079 }
3080
3081 /**
3082 * @brief Get source byte exchange.
3083 * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
3084 * @param DMAx DMAx Instance
3085 * @param Channel This parameter can be one of the following values:
3086 * @arg @ref LL_DMA_CHANNEL_0
3087 * @arg @ref LL_DMA_CHANNEL_1
3088 * @arg @ref LL_DMA_CHANNEL_2
3089 * @arg @ref LL_DMA_CHANNEL_3
3090 * @arg @ref LL_DMA_CHANNEL_4
3091 * @arg @ref LL_DMA_CHANNEL_5
3092 * @arg @ref LL_DMA_CHANNEL_6
3093 * @arg @ref LL_DMA_CHANNEL_7
3094 * @arg @ref LL_DMA_CHANNEL_8
3095 * @arg @ref LL_DMA_CHANNEL_9
3096 * @arg @ref LL_DMA_CHANNEL_10
3097 * @arg @ref LL_DMA_CHANNEL_11
3098 * @arg @ref LL_DMA_CHANNEL_12
3099 * @arg @ref LL_DMA_CHANNEL_13
3100 * @arg @ref LL_DMA_CHANNEL_14
3101 * @arg @ref LL_DMA_CHANNEL_15
3102 * @retval Returned value can be one of the following values:
3103 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
3104 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
3105 */
LL_DMA_GetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)3106 __STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
3107 {
3108 uint32_t dma_base_addr = (uint32_t)DMAx;
3109 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
3110 }
3111
3112 /**
3113 * @brief Set destination burst length.
3114 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
3115 * @param DMAx DMAx Instance
3116 * @param Channel This parameter can be one of the following values:
3117 * @arg @ref LL_DMA_CHANNEL_0
3118 * @arg @ref LL_DMA_CHANNEL_1
3119 * @arg @ref LL_DMA_CHANNEL_2
3120 * @arg @ref LL_DMA_CHANNEL_3
3121 * @arg @ref LL_DMA_CHANNEL_4
3122 * @arg @ref LL_DMA_CHANNEL_5
3123 * @arg @ref LL_DMA_CHANNEL_6
3124 * @arg @ref LL_DMA_CHANNEL_7
3125 * @arg @ref LL_DMA_CHANNEL_8
3126 * @arg @ref LL_DMA_CHANNEL_9
3127 * @arg @ref LL_DMA_CHANNEL_10
3128 * @arg @ref LL_DMA_CHANNEL_11
3129 * @arg @ref LL_DMA_CHANNEL_12
3130 * @arg @ref LL_DMA_CHANNEL_13
3131 * @arg @ref LL_DMA_CHANNEL_14
3132 * @arg @ref LL_DMA_CHANNEL_15
3133 * @param DestBurstLength Between 1 to 64
3134 * @retval None.
3135 */
LL_DMA_SetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestBurstLength)3136 __STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
3137 {
3138 uint32_t dma_base_addr = (uint32_t)DMAx;
3139 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
3140 ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
3141 }
3142
3143 /**
3144 * @brief Get destination burst length.
3145 * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
3146 * @param DMAx DMAx Instance
3147 * @param Channel This parameter can be one of the following values:
3148 * @arg @ref LL_DMA_CHANNEL_0
3149 * @arg @ref LL_DMA_CHANNEL_1
3150 * @arg @ref LL_DMA_CHANNEL_2
3151 * @arg @ref LL_DMA_CHANNEL_3
3152 * @arg @ref LL_DMA_CHANNEL_4
3153 * @arg @ref LL_DMA_CHANNEL_5
3154 * @arg @ref LL_DMA_CHANNEL_6
3155 * @arg @ref LL_DMA_CHANNEL_7
3156 * @arg @ref LL_DMA_CHANNEL_8
3157 * @arg @ref LL_DMA_CHANNEL_9
3158 * @arg @ref LL_DMA_CHANNEL_10
3159 * @arg @ref LL_DMA_CHANNEL_11
3160 * @arg @ref LL_DMA_CHANNEL_12
3161 * @arg @ref LL_DMA_CHANNEL_13
3162 * @arg @ref LL_DMA_CHANNEL_14
3163 * @arg @ref LL_DMA_CHANNEL_15
3164 * @retval Between 1 to 64.
3165 */
LL_DMA_GetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)3166 __STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
3167 {
3168 uint32_t dma_base_addr = (uint32_t)DMAx;
3169 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
3170 DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
3171 }
3172
3173 /**
3174 * @brief Set destination increment mode.
3175 * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
3176 * @param DMAx DMAx Instance
3177 * @param Channel This parameter can be one of the following values:
3178 * @arg @ref LL_DMA_CHANNEL_0
3179 * @arg @ref LL_DMA_CHANNEL_1
3180 * @arg @ref LL_DMA_CHANNEL_2
3181 * @arg @ref LL_DMA_CHANNEL_3
3182 * @arg @ref LL_DMA_CHANNEL_4
3183 * @arg @ref LL_DMA_CHANNEL_5
3184 * @arg @ref LL_DMA_CHANNEL_6
3185 * @arg @ref LL_DMA_CHANNEL_7
3186 * @arg @ref LL_DMA_CHANNEL_8
3187 * @arg @ref LL_DMA_CHANNEL_9
3188 * @arg @ref LL_DMA_CHANNEL_10
3189 * @arg @ref LL_DMA_CHANNEL_11
3190 * @arg @ref LL_DMA_CHANNEL_12
3191 * @arg @ref LL_DMA_CHANNEL_13
3192 * @arg @ref LL_DMA_CHANNEL_14
3193 * @arg @ref LL_DMA_CHANNEL_15
3194 * @param DestInc This parameter can be one of the following values:
3195 * @arg @ref LL_DMA_DEST_FIXED
3196 * @arg @ref LL_DMA_DEST_INCREMENT
3197 * @retval None.
3198 */
LL_DMA_SetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestInc)3199 __STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
3200 {
3201 uint32_t dma_base_addr = (uint32_t)DMAx;
3202 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
3203 }
3204
3205 /**
3206 * @brief Get destination increment mode.
3207 * @note This API is used for all available DMA channels.
3208 * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode
3209 * @param DMAx DMAx Instance
3210 * @param Channel This parameter can be one of the following values:
3211 * @arg @ref LL_DMA_CHANNEL_0
3212 * @arg @ref LL_DMA_CHANNEL_1
3213 * @arg @ref LL_DMA_CHANNEL_2
3214 * @arg @ref LL_DMA_CHANNEL_3
3215 * @arg @ref LL_DMA_CHANNEL_4
3216 * @arg @ref LL_DMA_CHANNEL_5
3217 * @arg @ref LL_DMA_CHANNEL_6
3218 * @arg @ref LL_DMA_CHANNEL_7
3219 * @arg @ref LL_DMA_CHANNEL_8
3220 * @arg @ref LL_DMA_CHANNEL_9
3221 * @arg @ref LL_DMA_CHANNEL_10
3222 * @arg @ref LL_DMA_CHANNEL_11
3223 * @arg @ref LL_DMA_CHANNEL_12
3224 * @arg @ref LL_DMA_CHANNEL_13
3225 * @arg @ref LL_DMA_CHANNEL_14
3226 * @arg @ref LL_DMA_CHANNEL_15
3227 * @retval Returned value can be one of the following values:
3228 * @arg @ref LL_DMA_DEST_FIXED
3229 * @arg @ref LL_DMA_DEST_INCREMENT
3230 */
LL_DMA_GetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)3231 __STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3232 {
3233 uint32_t dma_base_addr = (uint32_t)DMAx;
3234 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
3235 }
3236
3237 /**
3238 * @brief Set destination data width.
3239 * @note This API is used for all available DMA channels.
3240 * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
3241 * @param DMAx DMAx Instance
3242 * @param Channel This parameter can be one of the following values:
3243 * @arg @ref LL_DMA_CHANNEL_0
3244 * @arg @ref LL_DMA_CHANNEL_1
3245 * @arg @ref LL_DMA_CHANNEL_2
3246 * @arg @ref LL_DMA_CHANNEL_3
3247 * @arg @ref LL_DMA_CHANNEL_4
3248 * @arg @ref LL_DMA_CHANNEL_5
3249 * @arg @ref LL_DMA_CHANNEL_6
3250 * @arg @ref LL_DMA_CHANNEL_7
3251 * @arg @ref LL_DMA_CHANNEL_8
3252 * @arg @ref LL_DMA_CHANNEL_9
3253 * @arg @ref LL_DMA_CHANNEL_10
3254 * @arg @ref LL_DMA_CHANNEL_11
3255 * @arg @ref LL_DMA_CHANNEL_12
3256 * @arg @ref LL_DMA_CHANNEL_13
3257 * @arg @ref LL_DMA_CHANNEL_14
3258 * @arg @ref LL_DMA_CHANNEL_15
3259 * @param DestDataWidth This parameter can be one of the following values:
3260 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
3261 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
3262 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
3263 * @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
3264 * @retval None.
3265 */
LL_DMA_SetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestDataWidth)3266 __STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
3267 {
3268 uint32_t dma_base_addr = (uint32_t)DMAx;
3269 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
3270 DestDataWidth);
3271 }
3272
3273 /**
3274 * @brief Get destination data width.
3275 * @note This API is used for all available DMA channels.
3276 * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
3277 * @param DMAx DMAx Instance
3278 * @param Channel This parameter can be one of the following values:
3279 * @arg @ref LL_DMA_CHANNEL_0
3280 * @arg @ref LL_DMA_CHANNEL_1
3281 * @arg @ref LL_DMA_CHANNEL_2
3282 * @arg @ref LL_DMA_CHANNEL_3
3283 * @arg @ref LL_DMA_CHANNEL_4
3284 * @arg @ref LL_DMA_CHANNEL_5
3285 * @arg @ref LL_DMA_CHANNEL_6
3286 * @arg @ref LL_DMA_CHANNEL_7
3287 * @arg @ref LL_DMA_CHANNEL_8
3288 * @arg @ref LL_DMA_CHANNEL_9
3289 * @arg @ref LL_DMA_CHANNEL_10
3290 * @arg @ref LL_DMA_CHANNEL_11
3291 * @arg @ref LL_DMA_CHANNEL_12
3292 * @arg @ref LL_DMA_CHANNEL_13
3293 * @arg @ref LL_DMA_CHANNEL_14
3294 * @arg @ref LL_DMA_CHANNEL_15
3295 * @retval Returned value can be one of the following values:
3296 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
3297 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
3298 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
3299 * @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
3300 */
LL_DMA_GetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)3301 __STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
3302 {
3303 uint32_t dma_base_addr = (uint32_t)DMAx;
3304 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
3305 }
3306
3307 /**
3308 * @brief Set source allocated port.
3309 * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
3310 * @param DMAx DMAx Instance
3311 * @param Channel This parameter can be one of the following values:
3312 * @arg @ref LL_DMA_CHANNEL_0
3313 * @arg @ref LL_DMA_CHANNEL_1
3314 * @arg @ref LL_DMA_CHANNEL_2
3315 * @arg @ref LL_DMA_CHANNEL_3
3316 * @arg @ref LL_DMA_CHANNEL_4
3317 * @arg @ref LL_DMA_CHANNEL_5
3318 * @arg @ref LL_DMA_CHANNEL_6
3319 * @arg @ref LL_DMA_CHANNEL_7
3320 * @arg @ref LL_DMA_CHANNEL_8
3321 * @arg @ref LL_DMA_CHANNEL_9
3322 * @arg @ref LL_DMA_CHANNEL_10
3323 * @arg @ref LL_DMA_CHANNEL_11
3324 * @arg @ref LL_DMA_CHANNEL_12
3325 * @arg @ref LL_DMA_CHANNEL_13
3326 * @arg @ref LL_DMA_CHANNEL_14
3327 * @arg @ref LL_DMA_CHANNEL_15
3328 * @param SrcAllocatedPort This parameter can be one of the following values:
3329 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
3330 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
3331 * @retval None.
3332 */
LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAllocatedPort)3333 __STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
3334 {
3335 uint32_t dma_base_addr = (uint32_t)DMAx;
3336 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
3337 SrcAllocatedPort);
3338 }
3339
3340 /**
3341 * @brief Get source allocated port.
3342 * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
3343 * @param DMAx DMAx Instance
3344 * @param Channel This parameter can be one of the following values:
3345 * @arg @ref LL_DMA_CHANNEL_0
3346 * @arg @ref LL_DMA_CHANNEL_1
3347 * @arg @ref LL_DMA_CHANNEL_2
3348 * @arg @ref LL_DMA_CHANNEL_3
3349 * @arg @ref LL_DMA_CHANNEL_4
3350 * @arg @ref LL_DMA_CHANNEL_5
3351 * @arg @ref LL_DMA_CHANNEL_6
3352 * @arg @ref LL_DMA_CHANNEL_7
3353 * @arg @ref LL_DMA_CHANNEL_8
3354 * @arg @ref LL_DMA_CHANNEL_9
3355 * @arg @ref LL_DMA_CHANNEL_10
3356 * @arg @ref LL_DMA_CHANNEL_11
3357 * @arg @ref LL_DMA_CHANNEL_12
3358 * @arg @ref LL_DMA_CHANNEL_13
3359 * @arg @ref LL_DMA_CHANNEL_14
3360 * @arg @ref LL_DMA_CHANNEL_15
3361 * @retval Returned value can be one of the following values:
3362 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
3363 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
3364 */
LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)3365 __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
3366 {
3367 uint32_t dma_base_addr = (uint32_t)DMAx;
3368 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
3369 }
3370
3371 /**
3372 * @brief Set data alignment mode.
3373 * @note This API is used for all available DMA channels.
3374 * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
3375 * @param DMAx DMAx Instance
3376 * @param Channel This parameter can be one of the following values:
3377 * @arg @ref LL_DMA_CHANNEL_0
3378 * @arg @ref LL_DMA_CHANNEL_1
3379 * @arg @ref LL_DMA_CHANNEL_2
3380 * @arg @ref LL_DMA_CHANNEL_3
3381 * @arg @ref LL_DMA_CHANNEL_4
3382 * @arg @ref LL_DMA_CHANNEL_5
3383 * @arg @ref LL_DMA_CHANNEL_6
3384 * @arg @ref LL_DMA_CHANNEL_7
3385 * @arg @ref LL_DMA_CHANNEL_8
3386 * @arg @ref LL_DMA_CHANNEL_9
3387 * @arg @ref LL_DMA_CHANNEL_10
3388 * @arg @ref LL_DMA_CHANNEL_11
3389 * @arg @ref LL_DMA_CHANNEL_12
3390 * @arg @ref LL_DMA_CHANNEL_13
3391 * @arg @ref LL_DMA_CHANNEL_14
3392 * @arg @ref LL_DMA_CHANNEL_15
3393 * @param DataAlignment This parameter can be one of the following values:
3394 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
3395 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
3396 * @arg @ref LL_DMA_DATA_PACK_UNPACK
3397 * @retval None.
3398 */
LL_DMA_SetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DataAlignment)3399 __STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
3400 {
3401 uint32_t dma_base_addr = (uint32_t)DMAx;
3402 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
3403 DataAlignment);
3404 }
3405
3406 /**
3407 * @brief Get data alignment mode.
3408 * @note This API is used for all available DMA channels.
3409 * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
3410 * @param DMAx DMAx Instance
3411 * @param Channel This parameter can be one of the following values:
3412 * @arg @ref LL_DMA_CHANNEL_0
3413 * @arg @ref LL_DMA_CHANNEL_1
3414 * @arg @ref LL_DMA_CHANNEL_2
3415 * @arg @ref LL_DMA_CHANNEL_3
3416 * @arg @ref LL_DMA_CHANNEL_4
3417 * @arg @ref LL_DMA_CHANNEL_5
3418 * @arg @ref LL_DMA_CHANNEL_6
3419 * @arg @ref LL_DMA_CHANNEL_7
3420 * @arg @ref LL_DMA_CHANNEL_8
3421 * @arg @ref LL_DMA_CHANNEL_9
3422 * @arg @ref LL_DMA_CHANNEL_10
3423 * @arg @ref LL_DMA_CHANNEL_11
3424 * @arg @ref LL_DMA_CHANNEL_12
3425 * @arg @ref LL_DMA_CHANNEL_13
3426 * @arg @ref LL_DMA_CHANNEL_14
3427 * @arg @ref LL_DMA_CHANNEL_15
3428 * @retval Returned value can be one of the following values:
3429 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
3430 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
3431 * @arg @ref LL_DMA_DATA_PACK_UNPACK
3432 */
LL_DMA_GetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel)3433 __STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel)
3434 {
3435 uint32_t dma_base_addr = (uint32_t)DMAx;
3436 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
3437 }
3438
3439 /**
3440 * @brief Set source burst length.
3441 * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
3442 * @param DMAx DMAx Instance
3443 * @param Channel This parameter can be one of the following values:
3444 * @arg @ref LL_DMA_CHANNEL_0
3445 * @arg @ref LL_DMA_CHANNEL_1
3446 * @arg @ref LL_DMA_CHANNEL_2
3447 * @arg @ref LL_DMA_CHANNEL_3
3448 * @arg @ref LL_DMA_CHANNEL_4
3449 * @arg @ref LL_DMA_CHANNEL_5
3450 * @arg @ref LL_DMA_CHANNEL_6
3451 * @arg @ref LL_DMA_CHANNEL_7
3452 * @arg @ref LL_DMA_CHANNEL_8
3453 * @arg @ref LL_DMA_CHANNEL_9
3454 * @arg @ref LL_DMA_CHANNEL_10
3455 * @arg @ref LL_DMA_CHANNEL_11
3456 * @arg @ref LL_DMA_CHANNEL_12
3457 * @arg @ref LL_DMA_CHANNEL_13
3458 * @arg @ref LL_DMA_CHANNEL_14
3459 * @arg @ref LL_DMA_CHANNEL_15
3460 * @param SrcBurstLength Between 1 to 64
3461 * @retval None.
3462 */
LL_DMA_SetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength)3463 __STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
3464 {
3465 uint32_t dma_base_addr = (uint32_t)DMAx;
3466 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
3467 ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
3468 }
3469
3470 /**
3471 * @brief Get source burst length.
3472 * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
3473 * @param DMAx DMAx Instance
3474 * @param Channel This parameter can be one of the following values:
3475 * @arg @ref LL_DMA_CHANNEL_0
3476 * @arg @ref LL_DMA_CHANNEL_1
3477 * @arg @ref LL_DMA_CHANNEL_2
3478 * @arg @ref LL_DMA_CHANNEL_3
3479 * @arg @ref LL_DMA_CHANNEL_4
3480 * @arg @ref LL_DMA_CHANNEL_5
3481 * @arg @ref LL_DMA_CHANNEL_6
3482 * @arg @ref LL_DMA_CHANNEL_7
3483 * @arg @ref LL_DMA_CHANNEL_8
3484 * @arg @ref LL_DMA_CHANNEL_9
3485 * @arg @ref LL_DMA_CHANNEL_10
3486 * @arg @ref LL_DMA_CHANNEL_11
3487 * @arg @ref LL_DMA_CHANNEL_12
3488 * @arg @ref LL_DMA_CHANNEL_13
3489 * @arg @ref LL_DMA_CHANNEL_14
3490 * @arg @ref LL_DMA_CHANNEL_15
3491 * @retval Between 1 to 64
3492 * @retval None.
3493 */
LL_DMA_GetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)3494 __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
3495 {
3496 uint32_t dma_base_addr = (uint32_t)DMAx;
3497 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
3498 DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
3499 }
3500
3501 /**
3502 * @brief Set source increment mode.
3503 * @note This API is used for all available DMA channels.
3504 * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
3505 * @param DMAx DMAx Instance
3506 * @param Channel This parameter can be one of the following values:
3507 * @arg @ref LL_DMA_CHANNEL_0
3508 * @arg @ref LL_DMA_CHANNEL_1
3509 * @arg @ref LL_DMA_CHANNEL_2
3510 * @arg @ref LL_DMA_CHANNEL_3
3511 * @arg @ref LL_DMA_CHANNEL_4
3512 * @arg @ref LL_DMA_CHANNEL_5
3513 * @arg @ref LL_DMA_CHANNEL_6
3514 * @arg @ref LL_DMA_CHANNEL_7
3515 * @arg @ref LL_DMA_CHANNEL_8
3516 * @arg @ref LL_DMA_CHANNEL_9
3517 * @arg @ref LL_DMA_CHANNEL_10
3518 * @arg @ref LL_DMA_CHANNEL_11
3519 * @arg @ref LL_DMA_CHANNEL_12
3520 * @arg @ref LL_DMA_CHANNEL_13
3521 * @arg @ref LL_DMA_CHANNEL_14
3522 * @arg @ref LL_DMA_CHANNEL_15
3523 * @param SrcInc This parameter can be one of the following values:
3524 * @arg @ref LL_DMA_SRC_FIXED
3525 * @arg @ref LL_DMA_SRC_INCREMENT
3526 * @retval None.
3527 */
LL_DMA_SetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcInc)3528 __STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
3529 {
3530 uint32_t dma_base_addr = (uint32_t)DMAx;
3531 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
3532 }
3533
3534 /**
3535 * @brief Get source increment mode.
3536 * @note This API is used for all available DMA channels.
3537 * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
3538 * @param DMAx DMAx Instance
3539 * @param Channel This parameter can be one of the following values:
3540 * @arg @ref LL_DMA_CHANNEL_0
3541 * @arg @ref LL_DMA_CHANNEL_1
3542 * @arg @ref LL_DMA_CHANNEL_2
3543 * @arg @ref LL_DMA_CHANNEL_3
3544 * @arg @ref LL_DMA_CHANNEL_4
3545 * @arg @ref LL_DMA_CHANNEL_5
3546 * @arg @ref LL_DMA_CHANNEL_6
3547 * @arg @ref LL_DMA_CHANNEL_7
3548 * @arg @ref LL_DMA_CHANNEL_8
3549 * @arg @ref LL_DMA_CHANNEL_9
3550 * @arg @ref LL_DMA_CHANNEL_10
3551 * @arg @ref LL_DMA_CHANNEL_11
3552 * @arg @ref LL_DMA_CHANNEL_12
3553 * @arg @ref LL_DMA_CHANNEL_13
3554 * @arg @ref LL_DMA_CHANNEL_14
3555 * @arg @ref LL_DMA_CHANNEL_15
3556 * @retval Returned value can be one of the following values:
3557 * @arg @ref LL_DMA_SRC_FIXED
3558 * @arg @ref LL_DMA_SRC_INCREMENT
3559 */
LL_DMA_GetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)3560 __STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3561 {
3562 uint32_t dma_base_addr = (uint32_t)DMAx;
3563 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
3564 }
3565
3566 /**
3567 * @brief Set source data width.
3568 * @note This API is used for all available DMA channels.
3569 * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
3570 * @param DMAx DMAx Instance
3571 * @param Channel This parameter can be one of the following values:
3572 * @arg @ref LL_DMA_CHANNEL_0
3573 * @arg @ref LL_DMA_CHANNEL_1
3574 * @arg @ref LL_DMA_CHANNEL_2
3575 * @arg @ref LL_DMA_CHANNEL_3
3576 * @arg @ref LL_DMA_CHANNEL_4
3577 * @arg @ref LL_DMA_CHANNEL_5
3578 * @arg @ref LL_DMA_CHANNEL_6
3579 * @arg @ref LL_DMA_CHANNEL_7
3580 * @arg @ref LL_DMA_CHANNEL_8
3581 * @arg @ref LL_DMA_CHANNEL_9
3582 * @arg @ref LL_DMA_CHANNEL_10
3583 * @arg @ref LL_DMA_CHANNEL_11
3584 * @arg @ref LL_DMA_CHANNEL_12
3585 * @arg @ref LL_DMA_CHANNEL_13
3586 * @arg @ref LL_DMA_CHANNEL_14
3587 * @arg @ref LL_DMA_CHANNEL_15
3588 * @param SrcDataWidth This parameter can be one of the following values:
3589 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
3590 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
3591 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
3592 * @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
3593 * @retval None.
3594 */
LL_DMA_SetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcDataWidth)3595 __STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
3596 {
3597 uint32_t dma_base_addr = (uint32_t)DMAx;
3598 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
3599 SrcDataWidth);
3600 }
3601
3602 /**
3603 * @brief Get Source Data width.
3604 * @note This API is used for all available DMA channels.
3605 * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
3606 * @param DMAx DMAx Instance
3607 * @param Channel This parameter can be one of the following values:
3608 * @arg @ref LL_DMA_CHANNEL_0
3609 * @arg @ref LL_DMA_CHANNEL_1
3610 * @arg @ref LL_DMA_CHANNEL_2
3611 * @arg @ref LL_DMA_CHANNEL_3
3612 * @arg @ref LL_DMA_CHANNEL_4
3613 * @arg @ref LL_DMA_CHANNEL_5
3614 * @arg @ref LL_DMA_CHANNEL_6
3615 * @arg @ref LL_DMA_CHANNEL_7
3616 * @arg @ref LL_DMA_CHANNEL_8
3617 * @arg @ref LL_DMA_CHANNEL_9
3618 * @arg @ref LL_DMA_CHANNEL_10
3619 * @arg @ref LL_DMA_CHANNEL_11
3620 * @arg @ref LL_DMA_CHANNEL_12
3621 * @arg @ref LL_DMA_CHANNEL_13
3622 * @arg @ref LL_DMA_CHANNEL_14
3623 * @arg @ref LL_DMA_CHANNEL_15
3624 * @retval Returned value can be one of the following values:
3625 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
3626 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
3627 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
3628 * @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
3629 */
LL_DMA_GetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)3630 __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
3631 {
3632 uint32_t dma_base_addr = (uint32_t)DMAx;
3633 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
3634 }
3635
3636 /**
3637 * @brief Configure channel transfer.
3638 * @note This API is used for all available DMA channels.
3639 * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
3640 * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
3641 * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
3642 * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
3643 * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
3644 * CTR2 SWREQ LL_DMA_ConfigChannelTransfer\n
3645 * CTR2 PFREQ LL_DMA_ConfigChannelTransfer
3646 * @param DMAx DMAx Instance
3647 * @param Channel This parameter can be one of the following values:
3648 * @arg @ref LL_DMA_CHANNEL_0
3649 * @arg @ref LL_DMA_CHANNEL_1
3650 * @arg @ref LL_DMA_CHANNEL_2
3651 * @arg @ref LL_DMA_CHANNEL_3
3652 * @arg @ref LL_DMA_CHANNEL_4
3653 * @arg @ref LL_DMA_CHANNEL_5
3654 * @arg @ref LL_DMA_CHANNEL_6
3655 * @arg @ref LL_DMA_CHANNEL_7
3656 * @arg @ref LL_DMA_CHANNEL_8
3657 * @arg @ref LL_DMA_CHANNEL_9
3658 * @arg @ref LL_DMA_CHANNEL_10
3659 * @arg @ref LL_DMA_CHANNEL_11
3660 * @arg @ref LL_DMA_CHANNEL_12
3661 * @arg @ref LL_DMA_CHANNEL_13
3662 * @arg @ref LL_DMA_CHANNEL_14
3663 * @arg @ref LL_DMA_CHANNEL_15
3664 * @param Configuration This parameter must be a combination of all the following values:
3665 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
3666 * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3667 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK
3668 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or
3669 * @ref LL_DMA_TRIG_POLARITY_FALLING
3670 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
3671 * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3672 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
3673 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3674 * @arg @ref LL_DMA_NORMAL or @ref LL_DMA_PFCTRL
3675 *@retval None.
3676 */
LL_DMA_ConfigChannelTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)3677 __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
3678 {
3679 uint32_t dma_base_addr = (uint32_t)DMAx;
3680 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3681 (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ |
3682 DMA_CTR2_PFREQ), Configuration);
3683 }
3684
3685 /**
3686 * @brief Set transfer event mode.
3687 * @note This API is used for all available DMA channels.
3688 * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
3689 * @param DMAx DMAx Instance
3690 * @param Channel This parameter can be one of the following values:
3691 * @arg @ref LL_DMA_CHANNEL_0
3692 * @arg @ref LL_DMA_CHANNEL_1
3693 * @arg @ref LL_DMA_CHANNEL_2
3694 * @arg @ref LL_DMA_CHANNEL_3
3695 * @arg @ref LL_DMA_CHANNEL_4
3696 * @arg @ref LL_DMA_CHANNEL_5
3697 * @arg @ref LL_DMA_CHANNEL_6
3698 * @arg @ref LL_DMA_CHANNEL_7
3699 * @arg @ref LL_DMA_CHANNEL_8
3700 * @arg @ref LL_DMA_CHANNEL_9
3701 * @arg @ref LL_DMA_CHANNEL_10
3702 * @arg @ref LL_DMA_CHANNEL_11
3703 * @arg @ref LL_DMA_CHANNEL_12
3704 * @arg @ref LL_DMA_CHANNEL_13
3705 * @arg @ref LL_DMA_CHANNEL_14
3706 * @arg @ref LL_DMA_CHANNEL_15
3707 * @param TransferEventMode This parameter can be one of the following values:
3708 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
3709 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
3710 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
3711 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3712 * @retval None.
3713 */
LL_DMA_SetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TransferEventMode)3714 __STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
3715 {
3716 uint32_t dma_base_addr = (uint32_t)DMAx;
3717 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
3718 TransferEventMode);
3719 }
3720
3721 /**
3722 * @brief Get transfer event mode.
3723 * @note This API is used for all available DMA channels.
3724 * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
3725 * @param DMAx DMAx Instance
3726 * @param Channel This parameter can be one of the following values:
3727 * @arg @ref LL_DMA_CHANNEL_0
3728 * @arg @ref LL_DMA_CHANNEL_1
3729 * @arg @ref LL_DMA_CHANNEL_2
3730 * @arg @ref LL_DMA_CHANNEL_3
3731 * @arg @ref LL_DMA_CHANNEL_4
3732 * @arg @ref LL_DMA_CHANNEL_5
3733 * @arg @ref LL_DMA_CHANNEL_6
3734 * @arg @ref LL_DMA_CHANNEL_7
3735 * @arg @ref LL_DMA_CHANNEL_8
3736 * @arg @ref LL_DMA_CHANNEL_9
3737 * @arg @ref LL_DMA_CHANNEL_10
3738 * @arg @ref LL_DMA_CHANNEL_11
3739 * @arg @ref LL_DMA_CHANNEL_12
3740 * @arg @ref LL_DMA_CHANNEL_13
3741 * @arg @ref LL_DMA_CHANNEL_14
3742 * @arg @ref LL_DMA_CHANNEL_15
3743 * @retval Returned value can be one of the following values:
3744 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
3745 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
3746 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
3747 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3748 */
LL_DMA_GetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel)3749 __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3750 {
3751 uint32_t dma_base_addr = (uint32_t)DMAx;
3752 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
3753 }
3754
3755 /**
3756 * @brief Set trigger polarity.
3757 * @note This API is used for all available DMA channels.
3758 * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
3759 * @param DMAx DMAx Instance
3760 * @param Channel This parameter can be one of the following values:
3761 * @arg @ref LL_DMA_CHANNEL_0
3762 * @arg @ref LL_DMA_CHANNEL_1
3763 * @arg @ref LL_DMA_CHANNEL_2
3764 * @arg @ref LL_DMA_CHANNEL_3
3765 * @arg @ref LL_DMA_CHANNEL_4
3766 * @arg @ref LL_DMA_CHANNEL_5
3767 * @arg @ref LL_DMA_CHANNEL_6
3768 * @arg @ref LL_DMA_CHANNEL_7
3769 * @arg @ref LL_DMA_CHANNEL_8
3770 * @arg @ref LL_DMA_CHANNEL_9
3771 * @arg @ref LL_DMA_CHANNEL_10
3772 * @arg @ref LL_DMA_CHANNEL_11
3773 * @arg @ref LL_DMA_CHANNEL_12
3774 * @arg @ref LL_DMA_CHANNEL_13
3775 * @arg @ref LL_DMA_CHANNEL_14
3776 * @arg @ref LL_DMA_CHANNEL_15
3777 * @param TriggerPolarity This parameter can be one of the following values:
3778 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
3779 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
3780 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
3781 * @retval None.
3782 */
LL_DMA_SetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerPolarity)3783 __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
3784 {
3785 uint32_t dma_base_addr = (uint32_t)DMAx;
3786 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
3787 TriggerPolarity);
3788 }
3789
3790 /**
3791 * @brief Get trigger polarity.
3792 * @note This API is used for all available DMA channels.
3793 * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
3794 * @param DMAx DMAx Instance
3795 * @param Channel This parameter can be one of the following values:
3796 * @arg @ref LL_DMA_CHANNEL_0
3797 * @arg @ref LL_DMA_CHANNEL_1
3798 * @arg @ref LL_DMA_CHANNEL_2
3799 * @arg @ref LL_DMA_CHANNEL_3
3800 * @arg @ref LL_DMA_CHANNEL_4
3801 * @arg @ref LL_DMA_CHANNEL_5
3802 * @arg @ref LL_DMA_CHANNEL_6
3803 * @arg @ref LL_DMA_CHANNEL_7
3804 * @arg @ref LL_DMA_CHANNEL_8
3805 * @arg @ref LL_DMA_CHANNEL_9
3806 * @arg @ref LL_DMA_CHANNEL_10
3807 * @arg @ref LL_DMA_CHANNEL_11
3808 * @arg @ref LL_DMA_CHANNEL_12
3809 * @arg @ref LL_DMA_CHANNEL_13
3810 * @arg @ref LL_DMA_CHANNEL_14
3811 * @arg @ref LL_DMA_CHANNEL_15
3812 * @retval Returned value can be one of the following values:
3813 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
3814 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
3815 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
3816 */
LL_DMA_GetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel)3817 __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel)
3818 {
3819 uint32_t dma_base_addr = (uint32_t)DMAx;
3820 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
3821 }
3822
3823 /**
3824 * @brief Set trigger Mode.
3825 * @note This API is used for all available DMA channels.
3826 * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
3827 * @param DMAx DMAx Instance
3828 * @param Channel This parameter can be one of the following values:
3829 * @arg @ref LL_DMA_CHANNEL_0
3830 * @arg @ref LL_DMA_CHANNEL_1
3831 * @arg @ref LL_DMA_CHANNEL_2
3832 * @arg @ref LL_DMA_CHANNEL_3
3833 * @arg @ref LL_DMA_CHANNEL_4
3834 * @arg @ref LL_DMA_CHANNEL_5
3835 * @arg @ref LL_DMA_CHANNEL_6
3836 * @arg @ref LL_DMA_CHANNEL_7
3837 * @arg @ref LL_DMA_CHANNEL_8
3838 * @arg @ref LL_DMA_CHANNEL_9
3839 * @arg @ref LL_DMA_CHANNEL_10
3840 * @arg @ref LL_DMA_CHANNEL_11
3841 * @arg @ref LL_DMA_CHANNEL_12
3842 * @arg @ref LL_DMA_CHANNEL_13
3843 * @arg @ref LL_DMA_CHANNEL_14
3844 * @arg @ref LL_DMA_CHANNEL_15
3845 * @param TriggerMode This parameter can be one of the following values:
3846 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3847 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3848 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3849 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3850 * @retval None.
3851 */
LL_DMA_SetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerMode)3852 __STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
3853 {
3854 uint32_t dma_base_addr = (uint32_t)DMAx;
3855 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
3856 TriggerMode);
3857 }
3858
3859 /**
3860 * @brief Get trigger Mode.
3861 * @note This API is used for all available DMA channels.
3862 * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
3863 * @param DMAx DMAx Instance
3864 * @param Channel This parameter can be one of the following values:
3865 * @arg @ref LL_DMA_CHANNEL_0
3866 * @arg @ref LL_DMA_CHANNEL_1
3867 * @arg @ref LL_DMA_CHANNEL_2
3868 * @arg @ref LL_DMA_CHANNEL_3
3869 * @arg @ref LL_DMA_CHANNEL_4
3870 * @arg @ref LL_DMA_CHANNEL_5
3871 * @arg @ref LL_DMA_CHANNEL_6
3872 * @arg @ref LL_DMA_CHANNEL_7
3873 * @arg @ref LL_DMA_CHANNEL_8
3874 * @arg @ref LL_DMA_CHANNEL_9
3875 * @arg @ref LL_DMA_CHANNEL_10
3876 * @arg @ref LL_DMA_CHANNEL_11
3877 * @arg @ref LL_DMA_CHANNEL_12
3878 * @arg @ref LL_DMA_CHANNEL_13
3879 * @arg @ref LL_DMA_CHANNEL_14
3880 * @arg @ref LL_DMA_CHANNEL_15
3881 * @retval Returned value can be one of the following values:
3882 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3883 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3884 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3885 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3886 */
LL_DMA_GetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel)3887 __STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3888 {
3889 uint32_t dma_base_addr = (uint32_t)DMAx;
3890 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
3891 }
3892
3893 /**
3894 * @brief Set destination hardware and software transfer request.
3895 * @note This API is used for all available DMA channels.
3896 * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
3897 * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
3898 * @param DMAx DMAx Instance
3899 * @param Channel This parameter can be one of the following values:
3900 * @arg @ref LL_DMA_CHANNEL_0
3901 * @arg @ref LL_DMA_CHANNEL_1
3902 * @arg @ref LL_DMA_CHANNEL_2
3903 * @arg @ref LL_DMA_CHANNEL_3
3904 * @arg @ref LL_DMA_CHANNEL_4
3905 * @arg @ref LL_DMA_CHANNEL_5
3906 * @arg @ref LL_DMA_CHANNEL_6
3907 * @arg @ref LL_DMA_CHANNEL_7
3908 * @arg @ref LL_DMA_CHANNEL_8
3909 * @arg @ref LL_DMA_CHANNEL_9
3910 * @arg @ref LL_DMA_CHANNEL_10
3911 * @arg @ref LL_DMA_CHANNEL_11
3912 * @arg @ref LL_DMA_CHANNEL_12
3913 * @arg @ref LL_DMA_CHANNEL_13
3914 * @arg @ref LL_DMA_CHANNEL_14
3915 * @arg @ref LL_DMA_CHANNEL_15
3916 * @param Direction This parameter can be one of the following values:
3917 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3918 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
3919 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3920 * @retval None.
3921 */
LL_DMA_SetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)3922 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
3923 {
3924 uint32_t dma_base_addr = (uint32_t)DMAx;
3925 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3926 DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
3927 }
3928
3929 /**
3930 * @brief Get destination hardware and software transfer request.
3931 * @note This API is used for all available DMA channels.
3932 * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
3933 * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
3934 * @param DMAx DMAx Instance
3935 * @param Channel This parameter can be one of the following values:
3936 * @arg @ref LL_DMA_CHANNEL_0
3937 * @arg @ref LL_DMA_CHANNEL_1
3938 * @arg @ref LL_DMA_CHANNEL_2
3939 * @arg @ref LL_DMA_CHANNEL_3
3940 * @arg @ref LL_DMA_CHANNEL_4
3941 * @arg @ref LL_DMA_CHANNEL_5
3942 * @arg @ref LL_DMA_CHANNEL_6
3943 * @arg @ref LL_DMA_CHANNEL_7
3944 * @arg @ref LL_DMA_CHANNEL_8
3945 * @arg @ref LL_DMA_CHANNEL_9
3946 * @arg @ref LL_DMA_CHANNEL_10
3947 * @arg @ref LL_DMA_CHANNEL_11
3948 * @arg @ref LL_DMA_CHANNEL_12
3949 * @arg @ref LL_DMA_CHANNEL_13
3950 * @arg @ref LL_DMA_CHANNEL_14
3951 * @arg @ref LL_DMA_CHANNEL_15
3952 * @retval Returned value can be one of the following values:
3953 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3954 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
3955 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3956 */
LL_DMA_GetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel)3957 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
3958 {
3959 uint32_t dma_base_addr = (uint32_t)DMAx;
3960 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3961 DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
3962 }
3963
3964 /**
3965 * @brief Set block hardware request.
3966 * @note This API is used for all available DMA channels.
3967 * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
3968 * @param DMAx DMAx Instance
3969 * @param Channel This parameter can be one of the following values:
3970 * @arg @ref LL_DMA_CHANNEL_0
3971 * @arg @ref LL_DMA_CHANNEL_1
3972 * @arg @ref LL_DMA_CHANNEL_2
3973 * @arg @ref LL_DMA_CHANNEL_3
3974 * @arg @ref LL_DMA_CHANNEL_4
3975 * @arg @ref LL_DMA_CHANNEL_5
3976 * @arg @ref LL_DMA_CHANNEL_6
3977 * @arg @ref LL_DMA_CHANNEL_7
3978 * @arg @ref LL_DMA_CHANNEL_8
3979 * @arg @ref LL_DMA_CHANNEL_9
3980 * @arg @ref LL_DMA_CHANNEL_10
3981 * @arg @ref LL_DMA_CHANNEL_11
3982 * @arg @ref LL_DMA_CHANNEL_12
3983 * @arg @ref LL_DMA_CHANNEL_13
3984 * @arg @ref LL_DMA_CHANNEL_14
3985 * @arg @ref LL_DMA_CHANNEL_15
3986 * @param BlkHWRequest This parameter can be one of the following values:
3987 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3988 * @arg @ref LL_DMA_HWREQUEST_BLK
3989 * @retval None.
3990 */
LL_DMA_SetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkHWRequest)3991 __STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
3992 {
3993 uint32_t dma_base_addr = (uint32_t)DMAx;
3994 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
3995 BlkHWRequest);
3996 }
3997
3998 /**
3999 * @brief Get block hardware request.
4000 * @note This API is used for all available DMA channels.
4001 * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
4002 * @param DMAx DMAx Instance
4003 * @param Channel This parameter can be one of the following values:
4004 * @arg @ref LL_DMA_CHANNEL_0
4005 * @arg @ref LL_DMA_CHANNEL_1
4006 * @arg @ref LL_DMA_CHANNEL_2
4007 * @arg @ref LL_DMA_CHANNEL_3
4008 * @arg @ref LL_DMA_CHANNEL_4
4009 * @arg @ref LL_DMA_CHANNEL_5
4010 * @arg @ref LL_DMA_CHANNEL_6
4011 * @arg @ref LL_DMA_CHANNEL_7
4012 * @arg @ref LL_DMA_CHANNEL_8
4013 * @arg @ref LL_DMA_CHANNEL_9
4014 * @arg @ref LL_DMA_CHANNEL_10
4015 * @arg @ref LL_DMA_CHANNEL_11
4016 * @arg @ref LL_DMA_CHANNEL_12
4017 * @arg @ref LL_DMA_CHANNEL_13
4018 * @arg @ref LL_DMA_CHANNEL_14
4019 * @arg @ref LL_DMA_CHANNEL_15
4020 * @retval Returned value can be one of the following values:
4021 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
4022 * @arg @ref LL_DMA_HWREQUEST_BLK
4023 */
LL_DMA_GetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel)4024 __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
4025 {
4026 uint32_t dma_base_addr = (uint32_t)DMAx;
4027 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
4028 }
4029
4030 /**
4031 * @brief Set hardware request.
4032 * @note This API is used for all available DMA channels.
4033 * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
4034 * @param DMAx DMAx Instance
4035 * @param Channel This parameter can be one of the following values:
4036 * @arg @ref LL_DMA_CHANNEL_0
4037 * @arg @ref LL_DMA_CHANNEL_1
4038 * @arg @ref LL_DMA_CHANNEL_2
4039 * @arg @ref LL_DMA_CHANNEL_3
4040 * @arg @ref LL_DMA_CHANNEL_4
4041 * @arg @ref LL_DMA_CHANNEL_5
4042 * @arg @ref LL_DMA_CHANNEL_6
4043 * @arg @ref LL_DMA_CHANNEL_7
4044 * @arg @ref LL_DMA_CHANNEL_8
4045 * @arg @ref LL_DMA_CHANNEL_9
4046 * @arg @ref LL_DMA_CHANNEL_10
4047 * @arg @ref LL_DMA_CHANNEL_11
4048 * @arg @ref LL_DMA_CHANNEL_12
4049 * @arg @ref LL_DMA_CHANNEL_13
4050 * @arg @ref LL_DMA_CHANNEL_14
4051 * @arg @ref LL_DMA_CHANNEL_15
4052 * @param Request This parameter can be one of the following values:
4053 * @arg @ref LL_HPDMA1_REQUEST_JPEG_RX
4054 * @arg @ref LL_HPDMA1_REQUEST_JPEG_TX
4055 * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI1
4056 * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI2
4057 * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI3
4058 * @arg @ref LL_HPDMA1_REQUEST_FMC2_TXRX
4059 * @arg @ref LL_HPDMA1_REQUEST_FMC2_BCH
4060 * @arg @ref LL_HPDMA1_REQUEST_ADC1
4061 * @arg @ref LL_HPDMA1_REQUEST_ADC2
4062 * @arg @ref LL_HPDMA1_REQUEST_CRYP_IN
4063 * @arg @ref LL_HPDMA1_REQUEST_CRYP_OUT
4064 * @arg @ref LL_HPDMA1_REQUEST_SAES_OUT
4065 * @arg @ref LL_HPDMA1_REQUEST_SAES_IN
4066 * @arg @ref LL_HPDMA1_REQUEST_HASH_IN
4067 * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH1
4068 * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH2
4069 * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH3
4070 * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH4
4071 * @arg @ref LL_HPDMA1_REQUEST_TIM1_UP
4072 * @arg @ref LL_HPDMA1_REQUEST_TIM1_TRIG
4073 * @arg @ref LL_HPDMA1_REQUEST_TIM1_COM
4074 * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH1
4075 * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH2
4076 * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH3
4077 * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH4
4078 * @arg @ref LL_HPDMA1_REQUEST_TIM2_UP
4079 * @arg @ref LL_HPDMA1_REQUEST_TIM2_TRIG
4080 * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH1
4081 * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH2
4082 * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH3
4083 * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH4
4084 * @arg @ref LL_HPDMA1_REQUEST_TIM3_UP
4085 * @arg @ref LL_HPDMA1_REQUEST_TIM3_TRIG
4086 * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH1
4087 * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH2
4088 * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH3
4089 * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH4
4090 * @arg @ref LL_HPDMA1_REQUEST_TIM4_UP
4091 * @arg @ref LL_HPDMA1_REQUEST_TIM4_TRIG
4092 * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH1
4093 * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH2
4094 * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH3
4095 * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH4
4096 * @arg @ref LL_HPDMA1_REQUEST_TIM5_UP
4097 * @arg @ref LL_HPDMA1_REQUEST_TIM5_TRIG
4098 * @arg @ref LL_HPDMA1_REQUEST_TIM6_UP
4099 * @arg @ref LL_HPDMA1_REQUEST_TIM7_UP
4100 * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH1
4101 * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH2
4102 * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH3
4103 * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH4
4104 * @arg @ref LL_HPDMA1_REQUEST_TIM8_UP
4105 * @arg @ref LL_HPDMA1_REQUEST_TIM8_TRIG
4106 * @arg @ref LL_HPDMA1_REQUEST_TIM8_COM
4107 * @arg @ref LL_HPDMA1_REQUEST_TIM15_CH1
4108 * @arg @ref LL_HPDMA1_REQUEST_TIM15_CH2
4109 * @arg @ref LL_HPDMA1_REQUEST_TIM15_UP
4110 * @arg @ref LL_HPDMA1_REQUEST_TIM15_TRIG
4111 * @arg @ref LL_HPDMA1_REQUEST_TIM15_COM
4112 * @arg @ref LL_HPDMA1_REQUEST_TIM16_CH1
4113 * @arg @ref LL_HPDMA1_REQUEST_TIM16_UP
4114 * @arg @ref LL_HPDMA1_REQUEST_TIM16_COM
4115 * @arg @ref LL_HPDMA1_REQUEST_TIM17_CH1
4116 * @arg @ref LL_HPDMA1_REQUEST_TIM17_UP
4117 * @arg @ref LL_HPDMA1_REQUEST_TIM17_COM
4118 * @arg @ref LL_HPDMA1_REQUEST_TIM18_CH1
4119 * @arg @ref LL_HPDMA1_REQUEST_TIM18_UP
4120 * @arg @ref LL_HPDMA1_REQUEST_TIM18_COM
4121 * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC1
4122 * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC2
4123 * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_UE
4124 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1
4125 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2
4126 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE
4127 * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC1
4128 * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC2
4129 * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_UE
4130 * @arg @ref LL_HPDMA1_REQUEST_SPI1_RX
4131 * @arg @ref LL_HPDMA1_REQUEST_SPI1_TX
4132 * @arg @ref LL_HPDMA1_REQUEST_SPI2_RX
4133 * @arg @ref LL_HPDMA1_REQUEST_SPI2_TX
4134 * @arg @ref LL_HPDMA1_REQUEST_SPI3_RX
4135 * @arg @ref LL_HPDMA1_REQUEST_SPI3_TX
4136 * @arg @ref LL_HPDMA1_REQUEST_SPI4_RX
4137 * @arg @ref LL_HPDMA1_REQUEST_SPI4_TX
4138 * @arg @ref LL_HPDMA1_REQUEST_SPI5_RX
4139 * @arg @ref LL_HPDMA1_REQUEST_SPI5_TX
4140 * @arg @ref LL_HPDMA1_REQUEST_SPI6_RX
4141 * @arg @ref LL_HPDMA1_REQUEST_SPI6_TX
4142 * @arg @ref LL_HPDMA1_REQUEST_SAI1_A
4143 * @arg @ref LL_HPDMA1_REQUEST_SAI1_B
4144 * @arg @ref LL_HPDMA1_REQUEST_SAI1_A
4145 * @arg @ref LL_HPDMA1_REQUEST_SAI1_B
4146 * @arg @ref LL_HPDMA1_REQUEST_I2C1_RX
4147 * @arg @ref LL_HPDMA1_REQUEST_I2C1_TX
4148 * @arg @ref LL_HPDMA1_REQUEST_I2C2_RX
4149 * @arg @ref LL_HPDMA1_REQUEST_I2C2_TX
4150 * @arg @ref LL_HPDMA1_REQUEST_I2C3_RX
4151 * @arg @ref LL_HPDMA1_REQUEST_I2C3_TX
4152 * @arg @ref LL_HPDMA1_REQUEST_I2C4_RX
4153 * @arg @ref LL_HPDMA1_REQUEST_I2C4_TX
4154 * @arg @ref LL_HPDMA1_REQUEST_I3C1_RX
4155 * @arg @ref LL_HPDMA1_REQUEST_I3C1_TX
4156 * @arg @ref LL_HPDMA1_REQUEST_I3C2_RX
4157 * @arg @ref LL_HPDMA1_REQUEST_I3C2_TX
4158 * @arg @ref LL_HPDMA1_REQUEST_USART1_RX
4159 * @arg @ref LL_HPDMA1_REQUEST_USART1_TX
4160 * @arg @ref LL_HPDMA1_REQUEST_USART2_RX
4161 * @arg @ref LL_HPDMA1_REQUEST_USART2_TX
4162 * @arg @ref LL_HPDMA1_REQUEST_USART3_RX
4163 * @arg @ref LL_HPDMA1_REQUEST_USART3_TX
4164 * @arg @ref LL_HPDMA1_REQUEST_UART4_RX
4165 * @arg @ref LL_HPDMA1_REQUEST_UART4_TX
4166 * @arg @ref LL_HPDMA1_REQUEST_UART5_RX
4167 * @arg @ref LL_HPDMA1_REQUEST_UART5_TX
4168 * @arg @ref LL_HPDMA1_REQUEST_USART6_RX
4169 * @arg @ref LL_HPDMA1_REQUEST_USART6_TX
4170 * @arg @ref LL_HPDMA1_REQUEST_UART7_RX
4171 * @arg @ref LL_HPDMA1_REQUEST_UART7_TX
4172 * @arg @ref LL_HPDMA1_REQUEST_UART8_RX
4173 * @arg @ref LL_HPDMA1_REQUEST_UART8_TX
4174 * @arg @ref LL_HPDMA1_REQUEST_UART9_RX
4175 * @arg @ref LL_HPDMA1_REQUEST_UART9_TX
4176 * @arg @ref LL_HPDMA1_REQUEST_USART10_RX
4177 * @arg @ref LL_HPDMA1_REQUEST_USART10_TX
4178 * @arg @ref LL_HPDMA1_REQUEST_LPUART1_RX
4179 * @arg @ref LL_HPDMA1_REQUEST_LPUART1_TX
4180 * @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_CS
4181 * @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_DT
4182 * @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0
4183 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT0
4184 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT1
4185 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT2
4186 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT3
4187 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT4
4188 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT5
4189 * @arg @ref LL_HPDMA1_REQUEST_UCPD1_TX
4190 * @arg @ref LL_HPDMA1_REQUEST_UCPD1_RX
4191 * @arg @ref LL_HPDMA1_REQUEST_DCMI_PSSI
4192 * @arg @ref LL_HPDMA1_REQUEST_I3C1_TC
4193 * @arg @ref LL_HPDMA1_REQUEST_I3C1_RS
4194 * @arg @ref LL_HPDMA1_REQUEST_I3C2_TC
4195 * @arg @ref LL_HPDMA1_REQUEST_I3C2_RS
4196 * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX
4197 * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX
4198 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
4199 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2
4200 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI3
4201 * @arg @ref LL_GPDMA1_REQUEST_FMC2_TXRX
4202 * @arg @ref LL_GPDMA1_REQUEST_FMC2_BCH
4203 * @arg @ref LL_GPDMA1_REQUEST_ADC1
4204 * @arg @ref LL_GPDMA1_REQUEST_ADC2
4205 * @arg @ref LL_GPDMA1_REQUEST_CRYP_IN
4206 * @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT
4207 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
4208 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN
4209 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
4210 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
4211 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
4212 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
4213 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
4214 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
4215 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
4216 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
4217 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
4218 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
4219 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
4220 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
4221 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
4222 * @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG
4223 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
4224 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
4225 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
4226 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
4227 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
4228 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
4229 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
4230 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
4231 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
4232 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
4233 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
4234 * @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG
4235 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
4236 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
4237 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
4238 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
4239 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
4240 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
4241 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
4242 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
4243 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
4244 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
4245 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
4246 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
4247 * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
4248 * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
4249 * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
4250 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
4251 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2
4252 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
4253 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
4254 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
4255 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
4256 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
4257 * @arg @ref LL_GPDMA1_REQUEST_TIM16_COM
4258 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
4259 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
4260 * @arg @ref LL_GPDMA1_REQUEST_TIM17_COM
4261 * @arg @ref LL_GPDMA1_REQUEST_TIM18_CH1
4262 * @arg @ref LL_GPDMA1_REQUEST_TIM18_UP
4263 * @arg @ref LL_GPDMA1_REQUEST_TIM18_COM
4264 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
4265 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
4266 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
4267 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
4268 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
4269 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
4270 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
4271 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
4272 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
4273 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
4274 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
4275 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
4276 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
4277 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
4278 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
4279 * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX
4280 * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX
4281 * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX
4282 * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX
4283 * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX
4284 * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX
4285 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
4286 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
4287 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
4288 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
4289 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
4290 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
4291 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
4292 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
4293 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
4294 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
4295 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
4296 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
4297 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
4298 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
4299 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX
4300 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX
4301 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
4302 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
4303 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
4304 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
4305 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
4306 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
4307 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX
4308 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX
4309 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX
4310 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX
4311 * @arg @ref LL_GPDMA1_REQUEST_USART6_RX
4312 * @arg @ref LL_GPDMA1_REQUEST_USART6_TX
4313 * @arg @ref LL_GPDMA1_REQUEST_UART7_RX
4314 * @arg @ref LL_GPDMA1_REQUEST_UART7_TX
4315 * @arg @ref LL_GPDMA1_REQUEST_UART8_RX
4316 * @arg @ref LL_GPDMA1_REQUEST_UART8_TX
4317 * @arg @ref LL_GPDMA1_REQUEST_UART9_RX
4318 * @arg @ref LL_GPDMA1_REQUEST_UART9_TX
4319 * @arg @ref LL_GPDMA1_REQUEST_USART10_RX
4320 * @arg @ref LL_GPDMA1_REQUEST_USART10_TX
4321 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
4322 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
4323 * @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_DT
4324 * @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_CS
4325 * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
4326 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
4327 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
4328 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
4329 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
4330 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
4331 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
4332 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
4333 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
4334 * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI
4335 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
4336 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
4337 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC
4338 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS
4339 * @retval None.
4340 */
LL_DMA_SetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)4341 __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
4342 {
4343 uint32_t dma_base_addr = (uint32_t)DMAx;
4344 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
4345 }
4346
4347 /**
4348 * @brief Get hardware request.
4349 * @note This API is used for all available DMA channels.
4350 * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
4351 * @param DMAx DMAx Instance
4352 * @param Channel This parameter can be one of the following values:
4353 * @arg @ref LL_DMA_CHANNEL_0
4354 * @arg @ref LL_DMA_CHANNEL_1
4355 * @arg @ref LL_DMA_CHANNEL_2
4356 * @arg @ref LL_DMA_CHANNEL_3
4357 * @arg @ref LL_DMA_CHANNEL_4
4358 * @arg @ref LL_DMA_CHANNEL_5
4359 * @arg @ref LL_DMA_CHANNEL_6
4360 * @arg @ref LL_DMA_CHANNEL_7
4361 * @arg @ref LL_DMA_CHANNEL_8
4362 * @arg @ref LL_DMA_CHANNEL_9
4363 * @arg @ref LL_DMA_CHANNEL_10
4364 * @arg @ref LL_DMA_CHANNEL_11
4365 * @arg @ref LL_DMA_CHANNEL_12
4366 * @arg @ref LL_DMA_CHANNEL_13
4367 * @arg @ref LL_DMA_CHANNEL_14
4368 * @arg @ref LL_DMA_CHANNEL_15
4369 * @retval Returned value can be one of the following values:
4370 * @arg @ref LL_HPDMA1_REQUEST_JPEG_RX
4371 * @arg @ref LL_HPDMA1_REQUEST_JPEG_TX
4372 * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI1
4373 * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI2
4374 * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI3
4375 * @arg @ref LL_HPDMA1_REQUEST_FMC2_TXRX
4376 * @arg @ref LL_HPDMA1_REQUEST_FMC2_BCH
4377 * @arg @ref LL_HPDMA1_REQUEST_ADC1
4378 * @arg @ref LL_HPDMA1_REQUEST_ADC2
4379 * @arg @ref LL_HPDMA1_REQUEST_CRYP_IN
4380 * @arg @ref LL_HPDMA1_REQUEST_CRYP_OUT
4381 * @arg @ref LL_HPDMA1_REQUEST_SAES_OUT
4382 * @arg @ref LL_HPDMA1_REQUEST_SAES_IN
4383 * @arg @ref LL_HPDMA1_REQUEST_HASH_IN
4384 * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH1
4385 * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH2
4386 * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH3
4387 * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH4
4388 * @arg @ref LL_HPDMA1_REQUEST_TIM1_UP
4389 * @arg @ref LL_HPDMA1_REQUEST_TIM1_TRIG
4390 * @arg @ref LL_HPDMA1_REQUEST_TIM1_COM
4391 * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH1
4392 * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH2
4393 * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH3
4394 * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH4
4395 * @arg @ref LL_HPDMA1_REQUEST_TIM2_UP
4396 * @arg @ref LL_HPDMA1_REQUEST_TIM2_TRIG
4397 * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH1
4398 * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH2
4399 * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH3
4400 * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH4
4401 * @arg @ref LL_HPDMA1_REQUEST_TIM3_UP
4402 * @arg @ref LL_HPDMA1_REQUEST_TIM3_TRIG
4403 * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH1
4404 * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH2
4405 * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH3
4406 * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH4
4407 * @arg @ref LL_HPDMA1_REQUEST_TIM4_UP
4408 * @arg @ref LL_HPDMA1_REQUEST_TIM4_TRIG
4409 * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH1
4410 * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH2
4411 * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH3
4412 * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH4
4413 * @arg @ref LL_HPDMA1_REQUEST_TIM5_UP
4414 * @arg @ref LL_HPDMA1_REQUEST_TIM5_TRIG
4415 * @arg @ref LL_HPDMA1_REQUEST_TIM6_UP
4416 * @arg @ref LL_HPDMA1_REQUEST_TIM7_UP
4417 * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH1
4418 * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH2
4419 * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH3
4420 * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH4
4421 * @arg @ref LL_HPDMA1_REQUEST_TIM8_UP
4422 * @arg @ref LL_HPDMA1_REQUEST_TIM8_TRIG
4423 * @arg @ref LL_HPDMA1_REQUEST_TIM8_COM
4424 * @arg @ref LL_HPDMA1_REQUEST_TIM15_CH1
4425 * @arg @ref LL_HPDMA1_REQUEST_TIM15_CH2
4426 * @arg @ref LL_HPDMA1_REQUEST_TIM15_UP
4427 * @arg @ref LL_HPDMA1_REQUEST_TIM15_TRIG
4428 * @arg @ref LL_HPDMA1_REQUEST_TIM15_COM
4429 * @arg @ref LL_HPDMA1_REQUEST_TIM16_CH1
4430 * @arg @ref LL_HPDMA1_REQUEST_TIM16_UP
4431 * @arg @ref LL_HPDMA1_REQUEST_TIM16_COM
4432 * @arg @ref LL_HPDMA1_REQUEST_TIM17_CH1
4433 * @arg @ref LL_HPDMA1_REQUEST_TIM17_UP
4434 * @arg @ref LL_HPDMA1_REQUEST_TIM17_COM
4435 * @arg @ref LL_HPDMA1_REQUEST_TIM18_CH1
4436 * @arg @ref LL_HPDMA1_REQUEST_TIM18_UP
4437 * @arg @ref LL_HPDMA1_REQUEST_TIM18_COM
4438 * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC1
4439 * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC2
4440 * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_UE
4441 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1
4442 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2
4443 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE
4444 * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC1
4445 * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC2
4446 * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_UE
4447 * @arg @ref LL_HPDMA1_REQUEST_SPI1_RX
4448 * @arg @ref LL_HPDMA1_REQUEST_SPI1_TX
4449 * @arg @ref LL_HPDMA1_REQUEST_SPI2_RX
4450 * @arg @ref LL_HPDMA1_REQUEST_SPI2_TX
4451 * @arg @ref LL_HPDMA1_REQUEST_SPI3_RX
4452 * @arg @ref LL_HPDMA1_REQUEST_SPI3_TX
4453 * @arg @ref LL_HPDMA1_REQUEST_SPI4_RX
4454 * @arg @ref LL_HPDMA1_REQUEST_SPI4_TX
4455 * @arg @ref LL_HPDMA1_REQUEST_SPI5_RX
4456 * @arg @ref LL_HPDMA1_REQUEST_SPI5_TX
4457 * @arg @ref LL_HPDMA1_REQUEST_SPI6_RX
4458 * @arg @ref LL_HPDMA1_REQUEST_SPI6_TX
4459 * @arg @ref LL_HPDMA1_REQUEST_SAI1_A
4460 * @arg @ref LL_HPDMA1_REQUEST_SAI1_B
4461 * @arg @ref LL_HPDMA1_REQUEST_SAI1_A
4462 * @arg @ref LL_HPDMA1_REQUEST_SAI1_B
4463 * @arg @ref LL_HPDMA1_REQUEST_I2C1_RX
4464 * @arg @ref LL_HPDMA1_REQUEST_I2C1_TX
4465 * @arg @ref LL_HPDMA1_REQUEST_I2C2_RX
4466 * @arg @ref LL_HPDMA1_REQUEST_I2C2_TX
4467 * @arg @ref LL_HPDMA1_REQUEST_I2C3_RX
4468 * @arg @ref LL_HPDMA1_REQUEST_I2C3_TX
4469 * @arg @ref LL_HPDMA1_REQUEST_I2C4_RX
4470 * @arg @ref LL_HPDMA1_REQUEST_I2C4_TX
4471 * @arg @ref LL_HPDMA1_REQUEST_I3C1_RX
4472 * @arg @ref LL_HPDMA1_REQUEST_I3C1_TX
4473 * @arg @ref LL_HPDMA1_REQUEST_I3C2_RX
4474 * @arg @ref LL_HPDMA1_REQUEST_I3C2_TX
4475 * @arg @ref LL_HPDMA1_REQUEST_USART1_RX
4476 * @arg @ref LL_HPDMA1_REQUEST_USART1_TX
4477 * @arg @ref LL_HPDMA1_REQUEST_USART2_RX
4478 * @arg @ref LL_HPDMA1_REQUEST_USART2_TX
4479 * @arg @ref LL_HPDMA1_REQUEST_USART3_RX
4480 * @arg @ref LL_HPDMA1_REQUEST_USART3_TX
4481 * @arg @ref LL_HPDMA1_REQUEST_UART4_RX
4482 * @arg @ref LL_HPDMA1_REQUEST_UART4_TX
4483 * @arg @ref LL_HPDMA1_REQUEST_UART5_RX
4484 * @arg @ref LL_HPDMA1_REQUEST_UART5_TX
4485 * @arg @ref LL_HPDMA1_REQUEST_USART6_RX
4486 * @arg @ref LL_HPDMA1_REQUEST_USART6_TX
4487 * @arg @ref LL_HPDMA1_REQUEST_UART7_RX
4488 * @arg @ref LL_HPDMA1_REQUEST_UART7_TX
4489 * @arg @ref LL_HPDMA1_REQUEST_UART8_RX
4490 * @arg @ref LL_HPDMA1_REQUEST_UART8_TX
4491 * @arg @ref LL_HPDMA1_REQUEST_UART9_RX
4492 * @arg @ref LL_HPDMA1_REQUEST_UART9_TX
4493 * @arg @ref LL_HPDMA1_REQUEST_USART10_RX
4494 * @arg @ref LL_HPDMA1_REQUEST_USART10_TX
4495 * @arg @ref LL_HPDMA1_REQUEST_LPUART1_RX
4496 * @arg @ref LL_HPDMA1_REQUEST_LPUART1_TX
4497 * @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_CS
4498 * @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_DT
4499 * @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0
4500 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT0
4501 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT1
4502 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT2
4503 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT3
4504 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT4
4505 * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT5
4506 * @arg @ref LL_HPDMA1_REQUEST_UCPD1_TX
4507 * @arg @ref LL_HPDMA1_REQUEST_UCPD1_RX
4508 * @arg @ref LL_HPDMA1_REQUEST_DCMI_PSSI
4509 * @arg @ref LL_HPDMA1_REQUEST_I3C1_TC
4510 * @arg @ref LL_HPDMA1_REQUEST_I3C1_RS
4511 * @arg @ref LL_HPDMA1_REQUEST_I3C2_TC
4512 * @arg @ref LL_HPDMA1_REQUEST_I3C2_RS
4513 * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX
4514 * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX
4515 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
4516 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2
4517 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI3
4518 * @arg @ref LL_GPDMA1_REQUEST_FMC2_TXRX
4519 * @arg @ref LL_GPDMA1_REQUEST_FMC2_BCH
4520 * @arg @ref LL_GPDMA1_REQUEST_ADC1
4521 * @arg @ref LL_GPDMA1_REQUEST_ADC2
4522 * @arg @ref LL_GPDMA1_REQUEST_CRYP_IN
4523 * @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT
4524 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
4525 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN
4526 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
4527 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
4528 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
4529 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
4530 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
4531 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
4532 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
4533 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
4534 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
4535 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
4536 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
4537 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
4538 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
4539 * @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG
4540 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
4541 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
4542 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
4543 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
4544 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
4545 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
4546 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
4547 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
4548 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
4549 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
4550 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
4551 * @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG
4552 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
4553 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
4554 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
4555 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
4556 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
4557 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
4558 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
4559 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
4560 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
4561 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
4562 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
4563 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
4564 * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
4565 * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
4566 * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
4567 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
4568 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2
4569 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
4570 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
4571 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
4572 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
4573 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
4574 * @arg @ref LL_GPDMA1_REQUEST_TIM16_COM
4575 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
4576 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
4577 * @arg @ref LL_GPDMA1_REQUEST_TIM17_COM
4578 * @arg @ref LL_GPDMA1_REQUEST_TIM18_CH1
4579 * @arg @ref LL_GPDMA1_REQUEST_TIM18_UP
4580 * @arg @ref LL_GPDMA1_REQUEST_TIM18_COM
4581 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
4582 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
4583 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
4584 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
4585 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
4586 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
4587 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
4588 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
4589 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
4590 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
4591 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
4592 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
4593 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
4594 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
4595 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
4596 * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX
4597 * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX
4598 * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX
4599 * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX
4600 * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX
4601 * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX
4602 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
4603 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
4604 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
4605 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
4606 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
4607 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
4608 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
4609 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
4610 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
4611 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
4612 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
4613 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
4614 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
4615 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
4616 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX
4617 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX
4618 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
4619 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
4620 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
4621 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
4622 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
4623 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
4624 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX
4625 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX
4626 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX
4627 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX
4628 * @arg @ref LL_GPDMA1_REQUEST_USART6_RX
4629 * @arg @ref LL_GPDMA1_REQUEST_USART6_TX
4630 * @arg @ref LL_GPDMA1_REQUEST_UART7_RX
4631 * @arg @ref LL_GPDMA1_REQUEST_UART7_TX
4632 * @arg @ref LL_GPDMA1_REQUEST_UART8_RX
4633 * @arg @ref LL_GPDMA1_REQUEST_UART8_TX
4634 * @arg @ref LL_GPDMA1_REQUEST_UART9_RX
4635 * @arg @ref LL_GPDMA1_REQUEST_UART9_TX
4636 * @arg @ref LL_GPDMA1_REQUEST_USART10_RX
4637 * @arg @ref LL_GPDMA1_REQUEST_USART10_TX
4638 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
4639 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
4640 * @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_DT
4641 * @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_CS
4642 * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
4643 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
4644 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
4645 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
4646 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
4647 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
4648 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
4649 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
4650 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
4651 * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI
4652 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
4653 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
4654 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC
4655 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS
4656 */
LL_DMA_GetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel)4657 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
4658 {
4659 uint32_t dma_base_addr = (uint32_t)DMAx;
4660 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
4661 }
4662
4663 /**
4664 * @brief Set hardware trigger.
4665 * @note This API is used for all available DMA channels.
4666 * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
4667 * @param DMAx DMAx Instance
4668 * @param Channel This parameter can be one of the following values:
4669 * @arg @ref LL_DMA_CHANNEL_0
4670 * @arg @ref LL_DMA_CHANNEL_1
4671 * @arg @ref LL_DMA_CHANNEL_2
4672 * @arg @ref LL_DMA_CHANNEL_3
4673 * @arg @ref LL_DMA_CHANNEL_4
4674 * @arg @ref LL_DMA_CHANNEL_5
4675 * @arg @ref LL_DMA_CHANNEL_6
4676 * @arg @ref LL_DMA_CHANNEL_7
4677 * @arg @ref LL_DMA_CHANNEL_8
4678 * @arg @ref LL_DMA_CHANNEL_9
4679 * @arg @ref LL_DMA_CHANNEL_10
4680 * @arg @ref LL_DMA_CHANNEL_11
4681 * @arg @ref LL_DMA_CHANNEL_12
4682 * @arg @ref LL_DMA_CHANNEL_13
4683 * @arg @ref LL_DMA_CHANNEL_14
4684 * @arg @ref LL_DMA_CHANNEL_15
4685 * @param Trigger This parameter can be one of the following values:
4686 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND
4687 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND
4688 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC
4689 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC
4690 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND
4691 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND
4692 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC
4693 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC
4694 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND
4695 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND
4696 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC
4697 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC
4698 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC
4699 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC
4700 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW
4701 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC
4702 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF
4703 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT
4704 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE
4705 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT
4706 * @arg @ref LL_HPDMA1_TRIGGER_LCD_LI
4707 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_0
4708 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_1
4709 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_2
4710 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_3
4711 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_3
4712 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_2
4713 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_1
4714 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0
4715 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH1
4716 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH2
4717 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH1
4718 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH2
4719 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH1
4720 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH2
4721 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM4_OUT
4722 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM5_OUT
4723 * @arg @ref LL_HPDMA1_TRIGGER_RTC_WKUP
4724 * @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
4725 * @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
4726 * @arg @ref LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
4727 * @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO
4728 * @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO2
4729 * @arg @ref LL_HPDMA1_TRIGGER_TIM2_TRGO
4730 * @arg @ref LL_HPDMA1_TRIGGER_TIM3_TRGO
4731 * @arg @ref LL_HPDMA1_TRIGGER_TIM4_TRGO
4732 * @arg @ref LL_HPDMA1_TRIGGER_TIM5_TRGO
4733 * @arg @ref LL_HPDMA1_TRIGGER_TIM6_TRGO
4734 * @arg @ref LL_HPDMA1_TRIGGER_TIM7_TRGO
4735 * @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO
4736 * @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO2
4737 * @arg @ref LL_HPDMA1_TRIGGER_TIM12_TRGO
4738 * @arg @ref LL_HPDMA1_TRIGGER_TIM15_TRGO
4739 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF
4740 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF
4741 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF
4742 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF
4743 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF
4744 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF
4745 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF
4746 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF
4747 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF
4748 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF
4749 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF
4750 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF
4751 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF
4752 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF
4753 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF
4754 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF
4755 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF
4756 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF
4757 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF
4758 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF
4759 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF
4760 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF
4761 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF
4762 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF
4763 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF
4764 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF
4765 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF
4766 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF
4767 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF
4768 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF
4769 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF
4770 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF
4771 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT0_SYNC
4772 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT1_SYNC
4773 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT2_SYNC
4774 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT3_SYNC
4775 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT4_SYNC
4776 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT5_SYNC
4777 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT6_SYNC
4778 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT7_SYNC
4779 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT8_SYNC
4780 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT9_SYNC
4781 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT10_SYNC
4782 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT11_SYNC
4783 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT12_SYNC
4784 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT13_SYNC
4785 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT14_SYNC
4786 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT15_SYNC
4787 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND
4788 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND
4789 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC
4790 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC
4791 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND
4792 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND
4793 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC
4794 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC
4795 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND
4796 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND
4797 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC
4798 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC
4799 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC
4800 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC
4801 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW
4802 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC
4803 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF
4804 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT
4805 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE
4806 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT
4807 * @arg @ref LL_GPDMA1_TRIGGER_LCD_LI
4808 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_0
4809 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_1
4810 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_2
4811 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_3
4812 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_3
4813 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_2
4814 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_1
4815 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_0
4816 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
4817 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
4818 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
4819 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
4820 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
4821 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
4822 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
4823 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT
4824 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP
4825 * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
4826 * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
4827 * @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
4828 * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO
4829 * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2
4830 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
4831 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO
4832 * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO
4833 * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO
4834 * @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO
4835 * @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO
4836 * @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO
4837 * @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO2
4838 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
4839 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
4840 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF
4841 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF
4842 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF
4843 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF
4844 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF
4845 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF
4846 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF
4847 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF
4848 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF
4849 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF
4850 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF
4851 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF
4852 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF
4853 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF
4854 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF
4855 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF
4856 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
4857 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
4858 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
4859 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
4860 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
4861 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
4862 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
4863 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
4864 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
4865 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
4866 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
4867 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
4868 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
4869 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
4870 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
4871 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
4872 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC
4873 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT1_SYNC
4874 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT2_SYNC
4875 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT3_SYNC
4876 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT4_SYNC
4877 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT5_SYNC
4878 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT6_SYNC
4879 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT7_SYNC
4880 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT8_SYNC
4881 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT9_SYNC
4882 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT10_SYNC
4883 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT11_SYNC
4884 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT12_SYNC
4885 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT13_SYNC
4886 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT14_SYNC
4887 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT15_SYNC
4888 * @retval None.
4889 */
LL_DMA_SetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Trigger)4890 __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
4891 {
4892 uint32_t dma_base_addr = (uint32_t)DMAx;
4893 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
4894 (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
4895 }
4896
4897 /**
4898 * @brief Get hardware triggers.
4899 * @note This API is used for all available DMA channels.
4900 * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
4901 * @param DMAx DMAx Instance
4902 * @param Channel This parameter can be one of the following values:
4903 * @arg @ref LL_DMA_CHANNEL_0
4904 * @arg @ref LL_DMA_CHANNEL_1
4905 * @arg @ref LL_DMA_CHANNEL_2
4906 * @arg @ref LL_DMA_CHANNEL_3
4907 * @arg @ref LL_DMA_CHANNEL_4
4908 * @arg @ref LL_DMA_CHANNEL_5
4909 * @arg @ref LL_DMA_CHANNEL_6
4910 * @arg @ref LL_DMA_CHANNEL_7
4911 * @arg @ref LL_DMA_CHANNEL_8
4912 * @arg @ref LL_DMA_CHANNEL_9
4913 * @arg @ref LL_DMA_CHANNEL_10
4914 * @arg @ref LL_DMA_CHANNEL_11
4915 * @arg @ref LL_DMA_CHANNEL_12
4916 * @arg @ref LL_DMA_CHANNEL_13
4917 * @arg @ref LL_DMA_CHANNEL_14
4918 * @arg @ref LL_DMA_CHANNEL_15
4919 * @retval Returned value can be one of the following values:
4920 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND
4921 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND
4922 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC
4923 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC
4924 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND
4925 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND
4926 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC
4927 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC
4928 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND
4929 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND
4930 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC
4931 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC
4932 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC
4933 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC
4934 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW
4935 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC
4936 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF
4937 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT
4938 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE
4939 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT
4940 * @arg @ref LL_HPDMA1_TRIGGER_LCD_LI
4941 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_0
4942 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_1
4943 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_2
4944 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_3
4945 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_3
4946 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_2
4947 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_1
4948 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0
4949 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH1
4950 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH2
4951 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH1
4952 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH2
4953 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH1
4954 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH2
4955 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM4_OUT
4956 * @arg @ref LL_HPDMA1_TRIGGER_LPTIM5_OUT
4957 * @arg @ref LL_HPDMA1_TRIGGER_RTC_WKUP
4958 * @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
4959 * @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
4960 * @arg @ref LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
4961 * @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO
4962 * @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO2
4963 * @arg @ref LL_HPDMA1_TRIGGER_TIM2_TRGO
4964 * @arg @ref LL_HPDMA1_TRIGGER_TIM3_TRGO
4965 * @arg @ref LL_HPDMA1_TRIGGER_TIM4_TRGO
4966 * @arg @ref LL_HPDMA1_TRIGGER_TIM5_TRGO
4967 * @arg @ref LL_HPDMA1_TRIGGER_TIM6_TRGO
4968 * @arg @ref LL_HPDMA1_TRIGGER_TIM7_TRGO
4969 * @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO
4970 * @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO2
4971 * @arg @ref LL_HPDMA1_TRIGGER_TIM12_TRGO
4972 * @arg @ref LL_HPDMA1_TRIGGER_TIM15_TRGO
4973 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF
4974 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF
4975 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF
4976 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF
4977 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF
4978 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF
4979 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF
4980 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF
4981 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF
4982 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF
4983 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF
4984 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF
4985 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF
4986 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF
4987 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF
4988 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF
4989 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF
4990 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF
4991 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF
4992 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF
4993 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF
4994 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF
4995 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF
4996 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF
4997 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF
4998 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF
4999 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF
5000 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF
5001 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF
5002 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF
5003 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF
5004 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF
5005 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT0_SYNC
5006 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT1_SYNC
5007 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT2_SYNC
5008 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT3_SYNC
5009 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT4_SYNC
5010 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT5_SYNC
5011 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT6_SYNC
5012 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT7_SYNC
5013 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT8_SYNC
5014 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT9_SYNC
5015 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT10_SYNC
5016 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT11_SYNC
5017 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT12_SYNC
5018 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT13_SYNC
5019 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT14_SYNC
5020 * @arg @ref LL_HPDMA1_TRIGGER_EXTIT15_SYNC
5021 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND
5022 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND
5023 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC
5024 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC
5025 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND
5026 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND
5027 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC
5028 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC
5029 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND
5030 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND
5031 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC
5032 * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC
5033 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC
5034 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC
5035 * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW
5036 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC
5037 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF
5038 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT
5039 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE
5040 * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT
5041 * @arg @ref LL_GPDMA1_TRIGGER_LCD_LI
5042 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_0
5043 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_1
5044 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_2
5045 * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_3
5046 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_3
5047 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_2
5048 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_1
5049 * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_0
5050 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
5051 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
5052 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
5053 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
5054 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
5055 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
5056 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
5057 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT
5058 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP
5059 * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
5060 * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
5061 * @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
5062 * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO
5063 * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2
5064 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
5065 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO
5066 * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO
5067 * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO
5068 * @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO
5069 * @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO
5070 * @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO
5071 * @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO2
5072 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
5073 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
5074 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF
5075 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF
5076 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF
5077 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF
5078 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF
5079 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF
5080 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF
5081 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF
5082 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF
5083 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF
5084 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF
5085 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF
5086 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF
5087 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF
5088 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF
5089 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF
5090 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
5091 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
5092 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
5093 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
5094 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
5095 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
5096 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
5097 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
5098 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
5099 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
5100 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
5101 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
5102 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
5103 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
5104 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
5105 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
5106 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC
5107 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT1_SYNC
5108 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT2_SYNC
5109 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT3_SYNC
5110 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT4_SYNC
5111 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT5_SYNC
5112 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT6_SYNC
5113 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT7_SYNC
5114 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT8_SYNC
5115 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT9_SYNC
5116 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT10_SYNC
5117 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT11_SYNC
5118 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT12_SYNC
5119 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT13_SYNC
5120 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT14_SYNC
5121 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT15_SYNC
5122 */
LL_DMA_GetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel)5123 __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel)
5124 {
5125 uint32_t dma_base_addr = (uint32_t)DMAx;
5126 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
5127 DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
5128 }
5129
5130 /**
5131 * @brief Set DMA transfer mode.
5132 * @note This API is used for all available DMA channels.
5133 * @rmtoll CTR2 PFREQ LL_DMA_SetTransferMode
5134 * @param DMAx DMAx Instance
5135 * @param Channel This parameter can be one of the following values:
5136 * @arg @ref LL_DMA_CHANNEL_0
5137 * @arg @ref LL_DMA_CHANNEL_1
5138 * @arg @ref LL_DMA_CHANNEL_15
5139 * @param Mode This parameter can be one of the following values:
5140 * @arg @ref LL_DMA_NORMAL
5141 * @arg @ref LL_DMA_PFCTRL
5142 * @retval None.
5143 */
LL_DMA_SetTransferMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)5144 __STATIC_INLINE void LL_DMA_SetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
5145 {
5146 uint32_t dma_base_addr = (uint32_t)DMAx;
5147 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_PFREQ,
5148 Mode & DMA_CTR2_PFREQ);
5149 }
5150
5151 /**
5152 * @brief Get DMA transfer mode.
5153 * @note This API is used for all available DMA channels.
5154 * @rmtoll CTR2 TRIGSEL LL_DMA_GetTransferMode
5155 * @param DMAx DMAx Instance
5156 * @param Channel This parameter can be one of the following values:
5157 * @arg @ref LL_DMA_CHANNEL_0
5158 * @arg @ref LL_DMA_CHANNEL_1
5159 * @arg @ref LL_DMA_CHANNEL_15
5160 * @retval Returned value can be one of the following values:
5161 * @arg @ref LL_DMA_NORMAL
5162 * @arg @ref LL_DMA_PFCTRL
5163 */
LL_DMA_GetTransferMode(const DMA_TypeDef * DMAx,uint32_t Channel)5164 __STATIC_INLINE uint32_t LL_DMA_GetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel)
5165 {
5166 uint32_t dma_base_addr = (uint32_t)DMAx;
5167 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
5168 DMA_CTR2_PFREQ));
5169 }
5170
5171 /**
5172 * @brief Configure addresses update.
5173 * @note This API is used only for 2D addressing channels.
5174 * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n
5175 * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n
5176 * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n
5177 * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate
5178 * @param DMAx DMAx Instance
5179 * @param Channel This parameter can be one of the following values:
5180 * @arg @ref LL_DMA_CHANNEL_12
5181 * @arg @ref LL_DMA_CHANNEL_13
5182 * @arg @ref LL_DMA_CHANNEL_14
5183 * @arg @ref LL_DMA_CHANNEL_15
5184 * @param Configuration This parameter must be a combination of all the following values:
5185 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
5186 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
5187 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
5188 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
5189 *@retval None.
5190 */
LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)5191 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
5192 {
5193 uint32_t dma_base_addr = (uint32_t)DMAx;
5194 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
5195 DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration);
5196 }
5197
5198 /**
5199 * @brief Configure DMA Block number of data and repeat Count.
5200 * @note This API is used only for 2D addressing channels.
5201 * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n
5202 * CBR1 BRC LL_DMA_ConfigBlkCounters
5203 * @param DMAx DMAx Instance
5204 * @param Channel This parameter can be one of the following values:
5205 * @arg @ref LL_DMA_CHANNEL_12
5206 * @arg @ref LL_DMA_CHANNEL_13
5207 * @arg @ref LL_DMA_CHANNEL_14
5208 * @arg @ref LL_DMA_CHANNEL_15
5209 * @param BlkDataLength Block transfer length
5210 Value between 0 to 0x0000FFFF
5211 * @param BlkRptCount Block repeat counter
5212 * Value between 0 to 0x000007FF
5213 *@retval None.
5214 */
LL_DMA_ConfigBlkCounters(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength,uint32_t BlkRptCount)5215 __STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength,
5216 uint32_t BlkRptCount)
5217 {
5218 uint32_t dma_base_addr = (uint32_t)DMAx;
5219 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
5220 (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos)));
5221 }
5222
5223 /**
5224 * @brief Set block repeat destination address update.
5225 * @note This API is used only for 2D addressing channels.
5226 * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate
5227 * @param DMAx DMAx Instance
5228 * @param Channel This parameter can be one of the following values:
5229 * @arg @ref LL_DMA_CHANNEL_12
5230 * @arg @ref LL_DMA_CHANNEL_13
5231 * @arg @ref LL_DMA_CHANNEL_14
5232 * @arg @ref LL_DMA_CHANNEL_15
5233 * @param BlkRptDestAddrUpdate This parameter can be one of the following values:
5234 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
5235 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
5236 * @retval None.
5237 */
LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrUpdate)5238 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
5239 uint32_t BlkRptDestAddrUpdate)
5240 {
5241 uint32_t dma_base_addr = (uint32_t)DMAx;
5242 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC,
5243 BlkRptDestAddrUpdate);
5244 }
5245
5246 /**
5247 * @brief Get block repeat destination address update.
5248 * @note This API is used only for 2D addressing channels.
5249 * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate
5250 * @param DMAx DMAx Instance
5251 * @param Channel This parameter can be one of the following values:
5252 * @arg @ref LL_DMA_CHANNEL_12
5253 * @arg @ref LL_DMA_CHANNEL_13
5254 * @arg @ref LL_DMA_CHANNEL_14
5255 * @arg @ref LL_DMA_CHANNEL_15
5256 * @retval Returned value can be one of the following values:
5257 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
5258 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
5259 */
LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5260 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5261 {
5262 uint32_t dma_base_addr = (uint32_t)DMAx;
5263 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC));
5264 }
5265
5266 /**
5267 * @brief Set block repeat source address update.
5268 * @note This API is used only for 2D addressing channels.
5269 * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate
5270 * @param DMAx DMAx Instance
5271 * @param Channel This parameter can be one of the following values:
5272 * @arg @ref LL_DMA_CHANNEL_12
5273 * @arg @ref LL_DMA_CHANNEL_13
5274 * @arg @ref LL_DMA_CHANNEL_14
5275 * @arg @ref LL_DMA_CHANNEL_15
5276 * @param BlkRptSrcAddrUpdate This parameter can be one of the following values:
5277 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
5278 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
5279 * @retval None.
5280 */
LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrUpdate)5281 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
5282 uint32_t BlkRptSrcAddrUpdate)
5283 {
5284 uint32_t dma_base_addr = (uint32_t)DMAx;
5285 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC,
5286 BlkRptSrcAddrUpdate);
5287 }
5288
5289 /**
5290 * @brief Get block repeat source address update.
5291 * @note This API is used only for 2D addressing channels.
5292 * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate
5293 * @param DMAx DMAx Instance
5294 * @param Channel This parameter can be one of the following values:
5295 * @arg @ref LL_DMA_CHANNEL_12
5296 * @arg @ref LL_DMA_CHANNEL_13
5297 * @arg @ref LL_DMA_CHANNEL_14
5298 * @arg @ref LL_DMA_CHANNEL_15
5299 * @retval Returned value can be one of the following values:
5300 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
5301 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
5302 */
LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5303 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5304 {
5305 uint32_t dma_base_addr = (uint32_t)DMAx;
5306 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC));
5307 }
5308
5309 /**
5310 * @brief Set destination address update.
5311 * @note This API is used only for 2D addressing channels.
5312 * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate
5313 * @param DMAx DMAx Instance
5314 * @param Channel This parameter can be one of the following values:
5315 * @arg @ref LL_DMA_CHANNEL_12
5316 * @arg @ref LL_DMA_CHANNEL_13
5317 * @arg @ref LL_DMA_CHANNEL_14
5318 * @arg @ref LL_DMA_CHANNEL_15
5319 * @param DestAddrUpdate This parameter can be one of the following values:
5320 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
5321 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
5322 * @retval None.
5323 */
LL_DMA_SetDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrUpdate)5324 __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate)
5325 {
5326 uint32_t dma_base_addr = (uint32_t)DMAx;
5327 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC,
5328 DestAddrUpdate);
5329 }
5330
5331 /**
5332 * @brief Get destination address update.
5333 * @note This API is used only for 2D addressing channels.
5334 * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate
5335 * @param DMAx DMAx Instance
5336 * @param Channel This parameter can be one of the following values:
5337 * @arg @ref LL_DMA_CHANNEL_12
5338 * @arg @ref LL_DMA_CHANNEL_13
5339 * @arg @ref LL_DMA_CHANNEL_14
5340 * @arg @ref LL_DMA_CHANNEL_15
5341 * @retval Returned value can be one of the following values:
5342 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
5343 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
5344 */
LL_DMA_GetDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5345 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5346 {
5347 uint32_t dma_base_addr = (uint32_t)DMAx;
5348 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC));
5349 }
5350
5351 /**
5352 * @brief Set source address update.
5353 * @note This API is used only for 2D addressing channels.
5354 * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate
5355 * @param DMAx DMAx Instance
5356 * @param Channel This parameter can be one of the following values:
5357 * @arg @ref LL_DMA_CHANNEL_12
5358 * @arg @ref LL_DMA_CHANNEL_13
5359 * @arg @ref LL_DMA_CHANNEL_14
5360 * @arg @ref LL_DMA_CHANNEL_15
5361 * @param SrcAddrUpdate This parameter can be one of the following values:
5362 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
5363 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
5364 * @retval None.
5365 */
LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrUpdate)5366 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate)
5367 {
5368 uint32_t dma_base_addr = (uint32_t)DMAx;
5369 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC,
5370 SrcAddrUpdate);
5371 }
5372
5373 /**
5374 * @brief Get source address update.
5375 * @note This API is used only for 2D addressing channels.
5376 * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate
5377 * @param DMAx DMAx Instance
5378 * @param Channel This parameter can be one of the following values:
5379 * @arg @ref LL_DMA_CHANNEL_12
5380 * @arg @ref LL_DMA_CHANNEL_13
5381 * @arg @ref LL_DMA_CHANNEL_14
5382 * @arg @ref LL_DMA_CHANNEL_15
5383 * @retval Returned value can be one of the following values:
5384 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
5385 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
5386 */
LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5387 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5388 {
5389 uint32_t dma_base_addr = (uint32_t)DMAx;
5390 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC));
5391 }
5392
5393 /**
5394 * @brief Set block repeat count.
5395 * @note This API is used only for 2D addressing channels.
5396 * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount
5397 * @param DMAx DMAx Instance
5398 * @param Channel This parameter can be one of the following values:
5399 * @arg @ref LL_DMA_CHANNEL_12
5400 * @arg @ref LL_DMA_CHANNEL_13
5401 * @arg @ref LL_DMA_CHANNEL_14
5402 * @arg @ref LL_DMA_CHANNEL_15
5403 * @param BlkRptCount Block repeat counter
5404 * Value between 0 to 0x000007FF
5405 * @retval None.
5406 */
LL_DMA_SetBlkRptCount(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptCount)5407 __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount)
5408 {
5409 uint32_t dma_base_addr = (uint32_t)DMAx;
5410 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC,
5411 (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
5412 }
5413
5414 /**
5415 * @brief Get block repeat count.
5416 * @note This API is used only for 2D addressing channels.
5417 * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount
5418 * @param DMAx DMAx Instance
5419 * @param Channel This parameter can be one of the following values:
5420 * @arg @ref LL_DMA_CHANNEL_12
5421 * @arg @ref LL_DMA_CHANNEL_13
5422 * @arg @ref LL_DMA_CHANNEL_14
5423 * @arg @ref LL_DMA_CHANNEL_15
5424 * @retval Between 0 to 0x000007FF
5425 */
LL_DMA_GetBlkRptCount(const DMA_TypeDef * DMAx,uint32_t Channel)5426 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel)
5427 {
5428 uint32_t dma_base_addr = (uint32_t)DMAx;
5429 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
5430 DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos);
5431 }
5432
5433 /**
5434 * @brief Set block data length in bytes to transfer.
5435 * @note This API is used for all available DMA channels.
5436 * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
5437 * @param DMAx DMAx Instance
5438 * @param Channel This parameter can be one of the following values:
5439 * @arg @ref LL_DMA_CHANNEL_0
5440 * @arg @ref LL_DMA_CHANNEL_1
5441 * @arg @ref LL_DMA_CHANNEL_2
5442 * @arg @ref LL_DMA_CHANNEL_3
5443 * @arg @ref LL_DMA_CHANNEL_4
5444 * @arg @ref LL_DMA_CHANNEL_5
5445 * @arg @ref LL_DMA_CHANNEL_6
5446 * @arg @ref LL_DMA_CHANNEL_7
5447 * @arg @ref LL_DMA_CHANNEL_8
5448 * @arg @ref LL_DMA_CHANNEL_9
5449 * @arg @ref LL_DMA_CHANNEL_10
5450 * @arg @ref LL_DMA_CHANNEL_11
5451 * @arg @ref LL_DMA_CHANNEL_12
5452 * @arg @ref LL_DMA_CHANNEL_13
5453 * @arg @ref LL_DMA_CHANNEL_14
5454 * @arg @ref LL_DMA_CHANNEL_15
5455 * @param BlkDataLength Between 0 to 0x0000FFFF
5456 * @retval None.
5457 */
LL_DMA_SetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength)5458 __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
5459 {
5460 uint32_t dma_base_addr = (uint32_t)DMAx;
5461 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
5462 BlkDataLength);
5463 }
5464
5465 /**
5466 * @brief Get block data length in bytes to transfer.
5467 * @note This API is used for all available DMA channels.
5468 * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
5469 * @param DMAx DMAx Instance
5470 * @param Channel This parameter can be one of the following values:
5471 * @arg @ref LL_DMA_CHANNEL_0
5472 * @arg @ref LL_DMA_CHANNEL_1
5473 * @arg @ref LL_DMA_CHANNEL_2
5474 * @arg @ref LL_DMA_CHANNEL_3
5475 * @arg @ref LL_DMA_CHANNEL_4
5476 * @arg @ref LL_DMA_CHANNEL_5
5477 * @arg @ref LL_DMA_CHANNEL_6
5478 * @arg @ref LL_DMA_CHANNEL_7
5479 * @arg @ref LL_DMA_CHANNEL_8
5480 * @arg @ref LL_DMA_CHANNEL_9
5481 * @arg @ref LL_DMA_CHANNEL_10
5482 * @arg @ref LL_DMA_CHANNEL_11
5483 * @arg @ref LL_DMA_CHANNEL_12
5484 * @arg @ref LL_DMA_CHANNEL_13
5485 * @arg @ref LL_DMA_CHANNEL_14
5486 * @arg @ref LL_DMA_CHANNEL_15
5487 * @retval Between 0 to 0x0000FFFF
5488 */
LL_DMA_GetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel)5489 __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
5490 {
5491 uint32_t dma_base_addr = (uint32_t)DMAx;
5492 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
5493 }
5494
5495 /**
5496 * @brief Configure the source and destination addresses.
5497 * @note This API is used for all available DMA channels.
5498 * @note This API must not be called when the DMA Channel is enabled.
5499 * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
5500 * CDAR DA LL_DMA_ConfigAddresses
5501 * @param DMAx DMAx Instance
5502 * @param Channel This parameter can be one of the following values:
5503 * @arg @ref LL_DMA_CHANNEL_0
5504 * @arg @ref LL_DMA_CHANNEL_1
5505 * @arg @ref LL_DMA_CHANNEL_2
5506 * @arg @ref LL_DMA_CHANNEL_3
5507 * @arg @ref LL_DMA_CHANNEL_4
5508 * @arg @ref LL_DMA_CHANNEL_5
5509 * @arg @ref LL_DMA_CHANNEL_6
5510 * @arg @ref LL_DMA_CHANNEL_7
5511 * @arg @ref LL_DMA_CHANNEL_8
5512 * @arg @ref LL_DMA_CHANNEL_9
5513 * @arg @ref LL_DMA_CHANNEL_10
5514 * @arg @ref LL_DMA_CHANNEL_11
5515 * @arg @ref LL_DMA_CHANNEL_12
5516 * @arg @ref LL_DMA_CHANNEL_13
5517 * @arg @ref LL_DMA_CHANNEL_14
5518 * @arg @ref LL_DMA_CHANNEL_15
5519 * @param SrcAddress Between 0 to 0xFFFFFFFF
5520 * @param DestAddress Between 0 to 0xFFFFFFFF
5521 * @retval None.
5522 */
LL_DMA_ConfigAddresses(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DestAddress)5523 __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
5524 DestAddress)
5525 {
5526 uint32_t dma_base_addr = (uint32_t)DMAx;
5527 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
5528 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
5529 }
5530
5531 /**
5532 * @brief Set source address.
5533 * @note This API is used for all available DMA channels.
5534 * @rmtoll CSAR SA LL_DMA_SetSrcAddress
5535 * @param DMAx DMAx Instance
5536 * @param Channel This parameter can be one of the following values:
5537 * @arg @ref LL_DMA_CHANNEL_0
5538 * @arg @ref LL_DMA_CHANNEL_1
5539 * @arg @ref LL_DMA_CHANNEL_2
5540 * @arg @ref LL_DMA_CHANNEL_3
5541 * @arg @ref LL_DMA_CHANNEL_4
5542 * @arg @ref LL_DMA_CHANNEL_5
5543 * @arg @ref LL_DMA_CHANNEL_6
5544 * @arg @ref LL_DMA_CHANNEL_7
5545 * @arg @ref LL_DMA_CHANNEL_8
5546 * @arg @ref LL_DMA_CHANNEL_9
5547 * @arg @ref LL_DMA_CHANNEL_10
5548 * @arg @ref LL_DMA_CHANNEL_11
5549 * @arg @ref LL_DMA_CHANNEL_12
5550 * @arg @ref LL_DMA_CHANNEL_13
5551 * @arg @ref LL_DMA_CHANNEL_14
5552 * @arg @ref LL_DMA_CHANNEL_15
5553 * @param SrcAddress Between 0 to 0xFFFFFFFF
5554 * @retval None.
5555 */
LL_DMA_SetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress)5556 __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
5557 {
5558 uint32_t dma_base_addr = (uint32_t)DMAx;
5559 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
5560 }
5561
5562 /**
5563 * @brief Get source address.
5564 * @note This API is used for all available DMA channels.
5565 * @rmtoll CSAR SA LL_DMA_GetSrcAddress
5566 * @param DMAx DMAx Instance
5567 * @param Channel This parameter can be one of the following values:
5568 * @arg @ref LL_DMA_CHANNEL_0
5569 * @arg @ref LL_DMA_CHANNEL_1
5570 * @arg @ref LL_DMA_CHANNEL_2
5571 * @arg @ref LL_DMA_CHANNEL_3
5572 * @arg @ref LL_DMA_CHANNEL_4
5573 * @arg @ref LL_DMA_CHANNEL_5
5574 * @arg @ref LL_DMA_CHANNEL_6
5575 * @arg @ref LL_DMA_CHANNEL_7
5576 * @arg @ref LL_DMA_CHANNEL_8
5577 * @arg @ref LL_DMA_CHANNEL_9
5578 * @arg @ref LL_DMA_CHANNEL_10
5579 * @arg @ref LL_DMA_CHANNEL_11
5580 * @arg @ref LL_DMA_CHANNEL_12
5581 * @arg @ref LL_DMA_CHANNEL_13
5582 * @arg @ref LL_DMA_CHANNEL_14
5583 * @arg @ref LL_DMA_CHANNEL_15
5584 * @retval Between 0 to 0xFFFFFFFF
5585 */
LL_DMA_GetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel)5586 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
5587 {
5588 uint32_t dma_base_addr = (uint32_t)DMAx;
5589 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
5590 }
5591
5592 /**
5593 * @brief Set destination address.
5594 * @note This API is used for all available DMA channels.
5595 * @rmtoll CDAR DA LL_DMA_SetDestAddress
5596 * @param DMAx DMAx Instance
5597 * @param Channel This parameter can be one of the following values:
5598 * @arg @ref LL_DMA_CHANNEL_0
5599 * @arg @ref LL_DMA_CHANNEL_1
5600 * @arg @ref LL_DMA_CHANNEL_2
5601 * @arg @ref LL_DMA_CHANNEL_3
5602 * @arg @ref LL_DMA_CHANNEL_4
5603 * @arg @ref LL_DMA_CHANNEL_5
5604 * @arg @ref LL_DMA_CHANNEL_6
5605 * @arg @ref LL_DMA_CHANNEL_7
5606 * @arg @ref LL_DMA_CHANNEL_8
5607 * @arg @ref LL_DMA_CHANNEL_9
5608 * @arg @ref LL_DMA_CHANNEL_10
5609 * @arg @ref LL_DMA_CHANNEL_11
5610 * @arg @ref LL_DMA_CHANNEL_12
5611 * @arg @ref LL_DMA_CHANNEL_13
5612 * @arg @ref LL_DMA_CHANNEL_14
5613 * @arg @ref LL_DMA_CHANNEL_15
5614 * @param DestAddress Between 0 to 0xFFFFFFFF
5615 * @retval None.
5616 */
LL_DMA_SetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddress)5617 __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
5618 {
5619 uint32_t dma_base_addr = (uint32_t)DMAx;
5620 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
5621 }
5622
5623 /**
5624 * @brief Get destination address.
5625 * @note This API is used for all available DMA channels.
5626 * @rmtoll CDAR DA LL_DMA_GetDestAddress
5627 * @param DMAx DMAx Instance
5628 * @param Channel This parameter can be one of the following values:
5629 * @arg @ref LL_DMA_CHANNEL_0
5630 * @arg @ref LL_DMA_CHANNEL_1
5631 * @arg @ref LL_DMA_CHANNEL_2
5632 * @arg @ref LL_DMA_CHANNEL_3
5633 * @arg @ref LL_DMA_CHANNEL_4
5634 * @arg @ref LL_DMA_CHANNEL_5
5635 * @arg @ref LL_DMA_CHANNEL_6
5636 * @arg @ref LL_DMA_CHANNEL_7
5637 * @arg @ref LL_DMA_CHANNEL_8
5638 * @arg @ref LL_DMA_CHANNEL_9
5639 * @arg @ref LL_DMA_CHANNEL_10
5640 * @arg @ref LL_DMA_CHANNEL_11
5641 * @arg @ref LL_DMA_CHANNEL_12
5642 * @arg @ref LL_DMA_CHANNEL_13
5643 * @arg @ref LL_DMA_CHANNEL_14
5644 * @arg @ref LL_DMA_CHANNEL_15
5645 * @retval Between 0 to 0xFFFFFFFF
5646 */
LL_DMA_GetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel)5647 __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
5648 {
5649 uint32_t dma_base_addr = (uint32_t)DMAx;
5650 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
5651 }
5652
5653 /**
5654 * @brief Configure source and destination addresses offset.
5655 * @note This API is used only for 2D addressing channels.
5656 * @note This API must not be called when the DMA Channel is enabled.
5657 * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n
5658 * CTR3 SAO LL_DMA_ConfigAddrUpdateValue
5659 * @param DMAx DMAx Instance
5660 * @param Channel This parameter can be one of the following values:
5661 * @arg @ref LL_DMA_CHANNEL_12
5662 * @arg @ref LL_DMA_CHANNEL_13
5663 * @arg @ref LL_DMA_CHANNEL_14
5664 * @arg @ref LL_DMA_CHANNEL_15
5665 * @param DestAddrOffset Between 0 to 0x00001FFF
5666 * @param SrcAddrOffset Between 0 to 0x00001FFF
5667 * @retval None.
5668 */
LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset,uint32_t DestAddrOffset)5669 __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset,
5670 uint32_t DestAddrOffset)
5671 {
5672 uint32_t dma_base_addr = (uint32_t)DMAx;
5673 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
5674 (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
5675 }
5676
5677 /**
5678 * @brief Set destination address offset.
5679 * @note This API is used only for 2D addressing channels.
5680 * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue
5681 * @param DMAx DMAx Instance
5682 * @param Channel This parameter can be one of the following values:
5683 * @arg @ref LL_DMA_CHANNEL_12
5684 * @arg @ref LL_DMA_CHANNEL_13
5685 * @arg @ref LL_DMA_CHANNEL_14
5686 * @arg @ref LL_DMA_CHANNEL_15
5687 * @param DestAddrOffset Between 0 to 0x00001FFF
5688 * @retval None.
5689 */
LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrOffset)5690 __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset)
5691 {
5692 uint32_t dma_base_addr = (uint32_t)DMAx;
5693 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO,
5694 ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
5695 }
5696
5697 /**
5698 * @brief Get destination address offset.
5699 * @note This API is used only for 2D addressing channels.
5700 * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue
5701 * @param DMAx DMAx Instance
5702 * @param Channel This parameter can be one of the following values:
5703 * @arg @ref LL_DMA_CHANNEL_12
5704 * @arg @ref LL_DMA_CHANNEL_13
5705 * @arg @ref LL_DMA_CHANNEL_14
5706 * @arg @ref LL_DMA_CHANNEL_15
5707 * @retval Between 0 to 0x00001FFF
5708 */
LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)5709 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
5710 {
5711 uint32_t dma_base_addr = (uint32_t)DMAx;
5712 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
5713 DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
5714 }
5715
5716 /**
5717 * @brief Set source address offset.
5718 * @note This API is used only for 2D addressing channels.
5719 * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue
5720 * @param DMAx DMAx Instance
5721 * @param Channel This parameter can be one of the following values:
5722 * @arg @ref LL_DMA_CHANNEL_12
5723 * @arg @ref LL_DMA_CHANNEL_13
5724 * @arg @ref LL_DMA_CHANNEL_14
5725 * @arg @ref LL_DMA_CHANNEL_15
5726 * @param SrcAddrOffset Between 0 to 0x00001FFF
5727 * @retval None.
5728 */
LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset)5729 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset)
5730 {
5731 uint32_t dma_base_addr = (uint32_t)DMAx;
5732 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO,
5733 SrcAddrOffset & DMA_CTR3_SAO);
5734 }
5735
5736 /**
5737 * @brief Get source address offset.
5738 * @note This API is used only for 2D addressing channels.
5739 * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue
5740 * @param DMAx DMAx Instance
5741 * @param Channel This parameter can be one of the following values:
5742 * @arg @ref LL_DMA_CHANNEL_12
5743 * @arg @ref LL_DMA_CHANNEL_13
5744 * @arg @ref LL_DMA_CHANNEL_14
5745 * @arg @ref LL_DMA_CHANNEL_15
5746 * @retval Between 0 to 0x00001FFF
5747 */
LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)5748 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
5749 {
5750 uint32_t dma_base_addr = (uint32_t)DMAx;
5751 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO));
5752 }
5753
5754 /**
5755 * @brief Configure the block repeated source and destination addresses offset.
5756 * @note This API is used only for 2D addressing channels.
5757 * @note This API must not be called when the DMA Channel is enabled.
5758 * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n
5759 * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue
5760 * @param DMAx DMAx Instance
5761 * @param Channel This parameter can be one of the following values:
5762 * @arg @ref LL_DMA_CHANNEL_12
5763 * @arg @ref LL_DMA_CHANNEL_13
5764 * @arg @ref LL_DMA_CHANNEL_14
5765 * @arg @ref LL_DMA_CHANNEL_15
5766 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
5767 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
5768 * @retval None.
5769 */
LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset,uint32_t BlkRptDestAddrOffset)5770 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
5771 uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset)
5772 {
5773 uint32_t dma_base_addr = (uint32_t)DMAx;
5774 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
5775 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO));
5776 }
5777
5778 /**
5779 * @brief Set block repeated destination address offset.
5780 * @note This API is used only for 2D addressing channels.
5781 * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue
5782 * @param DMAx DMAx Instance
5783 * @param Channel This parameter can be one of the following values:
5784 * @arg @ref LL_DMA_CHANNEL_12
5785 * @arg @ref LL_DMA_CHANNEL_13
5786 * @arg @ref LL_DMA_CHANNEL_14
5787 * @arg @ref LL_DMA_CHANNEL_15
5788 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
5789 * @retval None.
5790 */
LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrOffset)5791 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
5792 uint32_t BlkRptDestAddrOffset)
5793 {
5794 uint32_t dma_base_addr = (uint32_t)DMAx;
5795 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO,
5796 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO));
5797 }
5798
5799 /**
5800 * @brief Get block repeated destination address offset.
5801 * @note This API is used only for 2D addressing channels.
5802 * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue
5803 * @param DMAx DMAx Instance
5804 * @param Channel This parameter can be one of the following values:
5805 * @arg @ref LL_DMA_CHANNEL_12
5806 * @arg @ref LL_DMA_CHANNEL_13
5807 * @arg @ref LL_DMA_CHANNEL_14
5808 * @arg @ref LL_DMA_CHANNEL_15
5809 * @retval Between 0 to 0x0000FFFF.
5810 */
LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)5811 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
5812 {
5813 uint32_t dma_base_addr = (uint32_t)DMAx;
5814 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
5815 DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
5816 }
5817
5818 /**
5819 * @brief Set block repeated source address offset.
5820 * @note This API is used only for 2D addressing channels.
5821 * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue
5822 * @param DMAx DMAx Instance
5823 * @param Channel This parameter can be one of the following values:
5824 * @arg @ref LL_DMA_CHANNEL_12
5825 * @arg @ref LL_DMA_CHANNEL_13
5826 * @arg @ref LL_DMA_CHANNEL_14
5827 * @arg @ref LL_DMA_CHANNEL_15
5828 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
5829 * @retval None.
5830 */
LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset)5831 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
5832 uint32_t BlkRptSrcAddrOffset)
5833 {
5834 uint32_t dma_base_addr = (uint32_t)DMAx;
5835 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO,
5836 BlkRptSrcAddrOffset);
5837 }
5838
5839 /**
5840 * @brief Get block repeated source address offset.
5841 * @note This API is used only for 2D addressing channels.
5842 * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue
5843 * @param DMAx DMAx Instance
5844 * @param Channel This parameter can be one of the following values:
5845 * @arg @ref LL_DMA_CHANNEL_12
5846 * @arg @ref LL_DMA_CHANNEL_13
5847 * @arg @ref LL_DMA_CHANNEL_14
5848 * @arg @ref LL_DMA_CHANNEL_15
5849 * @retval Between 0 to 0x0000FFFF
5850 */
LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)5851 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
5852 {
5853 uint32_t dma_base_addr = (uint32_t)DMAx;
5854 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO));
5855 }
5856
5857 /**
5858 * @brief Configure registers update and node address offset during the link transfer.
5859 * @note This API is used for all available DMA channels.
5860 * For linear addressing channels, UT3 and UB2 fields are discarded.
5861 * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n
5862 * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n
5863 * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n
5864 * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n
5865 * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n
5866 * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n
5867 * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n
5868 * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate
5869 * @param DMAx DMAx Instance
5870 * @param Channel This parameter can be one of the following values:
5871 * @arg @ref LL_DMA_CHANNEL_0
5872 * @arg @ref LL_DMA_CHANNEL_1
5873 * @arg @ref LL_DMA_CHANNEL_2
5874 * @arg @ref LL_DMA_CHANNEL_3
5875 * @arg @ref LL_DMA_CHANNEL_4
5876 * @arg @ref LL_DMA_CHANNEL_5
5877 * @arg @ref LL_DMA_CHANNEL_6
5878 * @arg @ref LL_DMA_CHANNEL_7
5879 * @arg @ref LL_DMA_CHANNEL_8
5880 * @arg @ref LL_DMA_CHANNEL_9
5881 * @arg @ref LL_DMA_CHANNEL_10
5882 * @arg @ref LL_DMA_CHANNEL_11
5883 * @arg @ref LL_DMA_CHANNEL_12
5884 * @arg @ref LL_DMA_CHANNEL_13
5885 * @arg @ref LL_DMA_CHANNEL_14
5886 * @arg @ref LL_DMA_CHANNEL_15
5887 * @param RegistersUpdate This parameter must be a combination of all the following values:
5888 * @arg @ref LL_DMA_UPDATE_CTR1
5889 * @arg @ref LL_DMA_UPDATE_CTR2
5890 * @arg @ref LL_DMA_UPDATE_CBR1
5891 * @arg @ref LL_DMA_UPDATE_CSAR
5892 * @arg @ref LL_DMA_UPDATE_CDAR
5893 * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels)
5894 * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels)
5895 * @arg @ref LL_DMA_UPDATE_CLLR
5896 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
5897 * @retval None.
5898 */
LL_DMA_ConfigLinkUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t RegistersUpdate,uint32_t LinkedListAddrOffset)5899 __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
5900 uint32_t LinkedListAddrOffset)
5901 {
5902 uint32_t dma_base_addr = (uint32_t)DMAx;
5903 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
5904 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \
5905 DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
5906 }
5907
5908 /**
5909 * @brief Enable CTR1 update during the link transfer.
5910 * @note This API is used for all available DMA channels.
5911 * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
5912 * @param DMAx DMAx Instance
5913 * @param Channel This parameter can be one of the following values:
5914 * @arg @ref LL_DMA_CHANNEL_0
5915 * @arg @ref LL_DMA_CHANNEL_1
5916 * @arg @ref LL_DMA_CHANNEL_2
5917 * @arg @ref LL_DMA_CHANNEL_3
5918 * @arg @ref LL_DMA_CHANNEL_4
5919 * @arg @ref LL_DMA_CHANNEL_5
5920 * @arg @ref LL_DMA_CHANNEL_6
5921 * @arg @ref LL_DMA_CHANNEL_7
5922 * @arg @ref LL_DMA_CHANNEL_8
5923 * @arg @ref LL_DMA_CHANNEL_9
5924 * @arg @ref LL_DMA_CHANNEL_10
5925 * @arg @ref LL_DMA_CHANNEL_11
5926 * @arg @ref LL_DMA_CHANNEL_12
5927 * @arg @ref LL_DMA_CHANNEL_13
5928 * @arg @ref LL_DMA_CHANNEL_14
5929 * @arg @ref LL_DMA_CHANNEL_15
5930 * @retval None.
5931 */
LL_DMA_EnableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)5932 __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5933 {
5934 uint32_t dma_base_addr = (uint32_t)DMAx;
5935 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
5936 }
5937
5938 /**
5939 * @brief Disable CTR1 update during the link transfer.
5940 * @note This API is used for all available DMA channels.
5941 * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
5942 * @param DMAx DMAx Instance
5943 * @param Channel This parameter can be one of the following values:
5944 * @arg @ref LL_DMA_CHANNEL_0
5945 * @arg @ref LL_DMA_CHANNEL_1
5946 * @arg @ref LL_DMA_CHANNEL_2
5947 * @arg @ref LL_DMA_CHANNEL_3
5948 * @arg @ref LL_DMA_CHANNEL_4
5949 * @arg @ref LL_DMA_CHANNEL_5
5950 * @arg @ref LL_DMA_CHANNEL_6
5951 * @arg @ref LL_DMA_CHANNEL_7
5952 * @arg @ref LL_DMA_CHANNEL_8
5953 * @arg @ref LL_DMA_CHANNEL_9
5954 * @arg @ref LL_DMA_CHANNEL_10
5955 * @arg @ref LL_DMA_CHANNEL_11
5956 * @arg @ref LL_DMA_CHANNEL_12
5957 * @arg @ref LL_DMA_CHANNEL_13
5958 * @arg @ref LL_DMA_CHANNEL_14
5959 * @arg @ref LL_DMA_CHANNEL_15
5960 * @retval None.
5961 */
LL_DMA_DisableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)5962 __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5963 {
5964 uint32_t dma_base_addr = (uint32_t)DMAx;
5965 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
5966 }
5967
5968 /**
5969 * @brief Check if CTR1 update during the link transfer is enabled.
5970 * @note This API is used for all available DMA channels.
5971 * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
5972 * @param DMAx DMAx Instance
5973 * @param Channel This parameter can be one of the following values:
5974 * @arg @ref LL_DMA_CHANNEL_0
5975 * @arg @ref LL_DMA_CHANNEL_1
5976 * @arg @ref LL_DMA_CHANNEL_2
5977 * @arg @ref LL_DMA_CHANNEL_3
5978 * @arg @ref LL_DMA_CHANNEL_4
5979 * @arg @ref LL_DMA_CHANNEL_5
5980 * @arg @ref LL_DMA_CHANNEL_6
5981 * @arg @ref LL_DMA_CHANNEL_7
5982 * @arg @ref LL_DMA_CHANNEL_8
5983 * @arg @ref LL_DMA_CHANNEL_9
5984 * @arg @ref LL_DMA_CHANNEL_10
5985 * @arg @ref LL_DMA_CHANNEL_11
5986 * @arg @ref LL_DMA_CHANNEL_12
5987 * @arg @ref LL_DMA_CHANNEL_13
5988 * @arg @ref LL_DMA_CHANNEL_14
5989 * @arg @ref LL_DMA_CHANNEL_15
5990 * @retval State of bit (1 or 0).
5991 */
LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)5992 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5993 {
5994 uint32_t dma_base_addr = (uint32_t)DMAx;
5995 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
5996 == (DMA_CLLR_UT1)) ? 1UL : 0UL);
5997 }
5998
5999 /**
6000 * @brief Enable CTR2 update during the link transfer.
6001 * @note This API is used for all available DMA channels.
6002 * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
6003 * @param DMAx DMAx Instance
6004 * @param Channel This parameter can be one of the following values:
6005 * @arg @ref LL_DMA_CHANNEL_0
6006 * @arg @ref LL_DMA_CHANNEL_1
6007 * @arg @ref LL_DMA_CHANNEL_2
6008 * @arg @ref LL_DMA_CHANNEL_3
6009 * @arg @ref LL_DMA_CHANNEL_4
6010 * @arg @ref LL_DMA_CHANNEL_5
6011 * @arg @ref LL_DMA_CHANNEL_6
6012 * @arg @ref LL_DMA_CHANNEL_7
6013 * @arg @ref LL_DMA_CHANNEL_8
6014 * @arg @ref LL_DMA_CHANNEL_9
6015 * @arg @ref LL_DMA_CHANNEL_10
6016 * @arg @ref LL_DMA_CHANNEL_11
6017 * @arg @ref LL_DMA_CHANNEL_12
6018 * @arg @ref LL_DMA_CHANNEL_13
6019 * @arg @ref LL_DMA_CHANNEL_14
6020 * @arg @ref LL_DMA_CHANNEL_15
6021 * @retval None.
6022 */
LL_DMA_EnableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)6023 __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6024 {
6025 uint32_t dma_base_addr = (uint32_t)DMAx;
6026 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
6027 }
6028
6029 /**
6030 * @brief Disable CTR2 update during the link transfer.
6031 * @note This API is used for all available DMA channels.
6032 * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
6033 * @param DMAx DMAx Instance
6034 * @param Channel This parameter can be one of the following values:
6035 * @arg @ref LL_DMA_CHANNEL_0
6036 * @arg @ref LL_DMA_CHANNEL_1
6037 * @arg @ref LL_DMA_CHANNEL_2
6038 * @arg @ref LL_DMA_CHANNEL_3
6039 * @arg @ref LL_DMA_CHANNEL_4
6040 * @arg @ref LL_DMA_CHANNEL_5
6041 * @arg @ref LL_DMA_CHANNEL_6
6042 * @arg @ref LL_DMA_CHANNEL_7
6043 * @arg @ref LL_DMA_CHANNEL_8
6044 * @arg @ref LL_DMA_CHANNEL_9
6045 * @arg @ref LL_DMA_CHANNEL_10
6046 * @arg @ref LL_DMA_CHANNEL_11
6047 * @arg @ref LL_DMA_CHANNEL_12
6048 * @arg @ref LL_DMA_CHANNEL_13
6049 * @arg @ref LL_DMA_CHANNEL_14
6050 * @arg @ref LL_DMA_CHANNEL_15
6051 * @retval None.
6052 */
LL_DMA_DisableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)6053 __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6054 {
6055 uint32_t dma_base_addr = (uint32_t)DMAx;
6056 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
6057 }
6058
6059 /**
6060 * @brief Check if CTR2 update during the link transfer is enabled.
6061 * @note This API is used for all available DMA channels.
6062 * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
6063 * @param DMAx DMAx Instance
6064 * @param Channel This parameter can be one of the following values:
6065 * @arg @ref LL_DMA_CHANNEL_0
6066 * @arg @ref LL_DMA_CHANNEL_1
6067 * @arg @ref LL_DMA_CHANNEL_2
6068 * @arg @ref LL_DMA_CHANNEL_3
6069 * @arg @ref LL_DMA_CHANNEL_4
6070 * @arg @ref LL_DMA_CHANNEL_5
6071 * @arg @ref LL_DMA_CHANNEL_6
6072 * @arg @ref LL_DMA_CHANNEL_7
6073 * @arg @ref LL_DMA_CHANNEL_8
6074 * @arg @ref LL_DMA_CHANNEL_9
6075 * @arg @ref LL_DMA_CHANNEL_10
6076 * @arg @ref LL_DMA_CHANNEL_11
6077 * @arg @ref LL_DMA_CHANNEL_12
6078 * @arg @ref LL_DMA_CHANNEL_13
6079 * @arg @ref LL_DMA_CHANNEL_14
6080 * @arg @ref LL_DMA_CHANNEL_15
6081 * @retval State of bit (1 or 0).
6082 */
LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)6083 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6084 {
6085 uint32_t dma_base_addr = (uint32_t)DMAx;
6086 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
6087 == (DMA_CLLR_UT2)) ? 1UL : 0UL);
6088 }
6089
6090 /**
6091 * @brief Enable CBR1 update during the link transfer.
6092 * @note This API is used for all available DMA channels.
6093 * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
6094 * @param DMAx DMAx Instance
6095 * @param Channel This parameter can be one of the following values:
6096 * @arg @ref LL_DMA_CHANNEL_0
6097 * @arg @ref LL_DMA_CHANNEL_1
6098 * @arg @ref LL_DMA_CHANNEL_2
6099 * @arg @ref LL_DMA_CHANNEL_3
6100 * @arg @ref LL_DMA_CHANNEL_4
6101 * @arg @ref LL_DMA_CHANNEL_5
6102 * @arg @ref LL_DMA_CHANNEL_6
6103 * @arg @ref LL_DMA_CHANNEL_7
6104 * @arg @ref LL_DMA_CHANNEL_8
6105 * @arg @ref LL_DMA_CHANNEL_9
6106 * @arg @ref LL_DMA_CHANNEL_10
6107 * @arg @ref LL_DMA_CHANNEL_11
6108 * @arg @ref LL_DMA_CHANNEL_12
6109 * @arg @ref LL_DMA_CHANNEL_13
6110 * @arg @ref LL_DMA_CHANNEL_14
6111 * @arg @ref LL_DMA_CHANNEL_15
6112 * @retval None.
6113 */
LL_DMA_EnableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)6114 __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6115 {
6116 uint32_t dma_base_addr = (uint32_t)DMAx;
6117 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
6118 }
6119
6120 /**
6121 * @brief Disable CBR1 update during the link transfer.
6122 * @note This API is used for all available DMA channels.
6123 * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
6124 * @param DMAx DMAx Instance
6125 * @param Channel This parameter can be one of the following values:
6126 * @arg @ref LL_DMA_CHANNEL_0
6127 * @arg @ref LL_DMA_CHANNEL_1
6128 * @arg @ref LL_DMA_CHANNEL_2
6129 * @arg @ref LL_DMA_CHANNEL_3
6130 * @arg @ref LL_DMA_CHANNEL_4
6131 * @arg @ref LL_DMA_CHANNEL_5
6132 * @arg @ref LL_DMA_CHANNEL_6
6133 * @arg @ref LL_DMA_CHANNEL_7
6134 * @arg @ref LL_DMA_CHANNEL_8
6135 * @arg @ref LL_DMA_CHANNEL_9
6136 * @arg @ref LL_DMA_CHANNEL_10
6137 * @arg @ref LL_DMA_CHANNEL_11
6138 * @arg @ref LL_DMA_CHANNEL_12
6139 * @arg @ref LL_DMA_CHANNEL_13
6140 * @arg @ref LL_DMA_CHANNEL_14
6141 * @arg @ref LL_DMA_CHANNEL_15
6142 * @retval None.
6143 */
LL_DMA_DisableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)6144 __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6145 {
6146 uint32_t dma_base_addr = (uint32_t)DMAx;
6147 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
6148 }
6149
6150 /**
6151 * @brief Check if CBR1 update during the link transfer is enabled.
6152 * @note This API is used for all available DMA channels.
6153 * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
6154 * @param DMAx DMAx Instance
6155 * @param Channel This parameter can be one of the following values:
6156 * @arg @ref LL_DMA_CHANNEL_0
6157 * @arg @ref LL_DMA_CHANNEL_1
6158 * @arg @ref LL_DMA_CHANNEL_2
6159 * @arg @ref LL_DMA_CHANNEL_3
6160 * @arg @ref LL_DMA_CHANNEL_4
6161 * @arg @ref LL_DMA_CHANNEL_5
6162 * @arg @ref LL_DMA_CHANNEL_6
6163 * @arg @ref LL_DMA_CHANNEL_7
6164 * @arg @ref LL_DMA_CHANNEL_8
6165 * @arg @ref LL_DMA_CHANNEL_9
6166 * @arg @ref LL_DMA_CHANNEL_10
6167 * @arg @ref LL_DMA_CHANNEL_11
6168 * @arg @ref LL_DMA_CHANNEL_12
6169 * @arg @ref LL_DMA_CHANNEL_13
6170 * @arg @ref LL_DMA_CHANNEL_14
6171 * @arg @ref LL_DMA_CHANNEL_15
6172 * @retval State of bit (1 or 0).
6173 */
LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)6174 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6175 {
6176 uint32_t dma_base_addr = (uint32_t)DMAx;
6177 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
6178 == (DMA_CLLR_UB1)) ? 1UL : 0UL);
6179 }
6180
6181 /**
6182 * @brief Enable CSAR update during the link transfer.
6183 * @note This API is used for all available DMA channels.
6184 * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
6185 * @param DMAx DMAx Instance
6186 * @param Channel This parameter can be one of the following values:
6187 * @arg @ref LL_DMA_CHANNEL_0
6188 * @arg @ref LL_DMA_CHANNEL_1
6189 * @arg @ref LL_DMA_CHANNEL_2
6190 * @arg @ref LL_DMA_CHANNEL_3
6191 * @arg @ref LL_DMA_CHANNEL_4
6192 * @arg @ref LL_DMA_CHANNEL_5
6193 * @arg @ref LL_DMA_CHANNEL_6
6194 * @arg @ref LL_DMA_CHANNEL_7
6195 * @arg @ref LL_DMA_CHANNEL_8
6196 * @arg @ref LL_DMA_CHANNEL_9
6197 * @arg @ref LL_DMA_CHANNEL_10
6198 * @arg @ref LL_DMA_CHANNEL_11
6199 * @arg @ref LL_DMA_CHANNEL_12
6200 * @arg @ref LL_DMA_CHANNEL_13
6201 * @arg @ref LL_DMA_CHANNEL_14
6202 * @arg @ref LL_DMA_CHANNEL_15
6203 * @retval None.
6204 */
LL_DMA_EnableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6205 __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6206 {
6207 uint32_t dma_base_addr = (uint32_t)DMAx;
6208 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
6209 }
6210
6211 /**
6212 * @brief Disable CSAR update during the link transfer.
6213 * @note This API is used for all available DMA channels.
6214 * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
6215 * @param DMAx DMAx Instance
6216 * @param Channel This parameter can be one of the following values:
6217 * @arg @ref LL_DMA_CHANNEL_0
6218 * @arg @ref LL_DMA_CHANNEL_1
6219 * @arg @ref LL_DMA_CHANNEL_2
6220 * @arg @ref LL_DMA_CHANNEL_3
6221 * @arg @ref LL_DMA_CHANNEL_4
6222 * @arg @ref LL_DMA_CHANNEL_5
6223 * @arg @ref LL_DMA_CHANNEL_6
6224 * @arg @ref LL_DMA_CHANNEL_7
6225 * @arg @ref LL_DMA_CHANNEL_8
6226 * @arg @ref LL_DMA_CHANNEL_9
6227 * @arg @ref LL_DMA_CHANNEL_10
6228 * @arg @ref LL_DMA_CHANNEL_11
6229 * @arg @ref LL_DMA_CHANNEL_12
6230 * @arg @ref LL_DMA_CHANNEL_13
6231 * @arg @ref LL_DMA_CHANNEL_14
6232 * @arg @ref LL_DMA_CHANNEL_15
6233 * @retval None.
6234 */
LL_DMA_DisableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6235 __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6236 {
6237 uint32_t dma_base_addr = (uint32_t)DMAx;
6238 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
6239 }
6240
6241 /**
6242 * @brief Check if CSAR update during the link transfer is enabled.
6243 * @note This API is used for all available DMA channels.
6244 * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
6245 * @param DMAx DMAx Instance
6246 * @param Channel This parameter can be one of the following values:
6247 * @arg @ref LL_DMA_CHANNEL_0
6248 * @arg @ref LL_DMA_CHANNEL_1
6249 * @arg @ref LL_DMA_CHANNEL_2
6250 * @arg @ref LL_DMA_CHANNEL_3
6251 * @arg @ref LL_DMA_CHANNEL_4
6252 * @arg @ref LL_DMA_CHANNEL_5
6253 * @arg @ref LL_DMA_CHANNEL_6
6254 * @arg @ref LL_DMA_CHANNEL_7
6255 * @arg @ref LL_DMA_CHANNEL_8
6256 * @arg @ref LL_DMA_CHANNEL_9
6257 * @arg @ref LL_DMA_CHANNEL_10
6258 * @arg @ref LL_DMA_CHANNEL_11
6259 * @arg @ref LL_DMA_CHANNEL_12
6260 * @arg @ref LL_DMA_CHANNEL_13
6261 * @arg @ref LL_DMA_CHANNEL_14
6262 * @arg @ref LL_DMA_CHANNEL_15
6263 * @retval State of bit (1 or 0).
6264 */
LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6265 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6266 {
6267 uint32_t dma_base_addr = (uint32_t)DMAx;
6268 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
6269 == (DMA_CLLR_USA)) ? 1UL : 0UL);
6270 }
6271
6272 /**
6273 * @brief Enable CDAR update during the link transfer.
6274 * @note This API is used for all available DMA channels.
6275 * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
6276 * @param DMAx DMAx Instance
6277 * @param Channel This parameter can be one of the following values:
6278 * @arg @ref LL_DMA_CHANNEL_0
6279 * @arg @ref LL_DMA_CHANNEL_1
6280 * @arg @ref LL_DMA_CHANNEL_2
6281 * @arg @ref LL_DMA_CHANNEL_3
6282 * @arg @ref LL_DMA_CHANNEL_4
6283 * @arg @ref LL_DMA_CHANNEL_5
6284 * @arg @ref LL_DMA_CHANNEL_6
6285 * @arg @ref LL_DMA_CHANNEL_7
6286 * @arg @ref LL_DMA_CHANNEL_8
6287 * @arg @ref LL_DMA_CHANNEL_9
6288 * @arg @ref LL_DMA_CHANNEL_10
6289 * @arg @ref LL_DMA_CHANNEL_11
6290 * @arg @ref LL_DMA_CHANNEL_12
6291 * @arg @ref LL_DMA_CHANNEL_13
6292 * @arg @ref LL_DMA_CHANNEL_14
6293 * @arg @ref LL_DMA_CHANNEL_15
6294 * @retval None.
6295 */
LL_DMA_EnableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6296 __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6297 {
6298 uint32_t dma_base_addr = (uint32_t)DMAx;
6299 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
6300 }
6301
6302 /**
6303 * @brief Disable CDAR update during the link transfer.
6304 * @note This API is used for all available DMA channels.
6305 * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
6306 * @param DMAx DMAx Instance
6307 * @param Channel This parameter can be one of the following values:
6308 * @arg @ref LL_DMA_CHANNEL_0
6309 * @arg @ref LL_DMA_CHANNEL_1
6310 * @arg @ref LL_DMA_CHANNEL_2
6311 * @arg @ref LL_DMA_CHANNEL_3
6312 * @arg @ref LL_DMA_CHANNEL_4
6313 * @arg @ref LL_DMA_CHANNEL_5
6314 * @arg @ref LL_DMA_CHANNEL_6
6315 * @arg @ref LL_DMA_CHANNEL_7
6316 * @arg @ref LL_DMA_CHANNEL_8
6317 * @arg @ref LL_DMA_CHANNEL_9
6318 * @arg @ref LL_DMA_CHANNEL_10
6319 * @arg @ref LL_DMA_CHANNEL_11
6320 * @arg @ref LL_DMA_CHANNEL_12
6321 * @arg @ref LL_DMA_CHANNEL_13
6322 * @arg @ref LL_DMA_CHANNEL_14
6323 * @arg @ref LL_DMA_CHANNEL_15
6324 * @retval None.
6325 */
LL_DMA_DisableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6326 __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6327 {
6328 uint32_t dma_base_addr = (uint32_t)DMAx;
6329 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
6330 }
6331
6332 /**
6333 * @brief Check if CDAR update during the link transfer is enabled.
6334 * @note This API is used for all available DMA channels.
6335 * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
6336 * @param DMAx DMAx Instance
6337 * @param Channel This parameter can be one of the following values:
6338 * @arg @ref LL_DMA_CHANNEL_0
6339 * @arg @ref LL_DMA_CHANNEL_1
6340 * @arg @ref LL_DMA_CHANNEL_2
6341 * @arg @ref LL_DMA_CHANNEL_3
6342 * @arg @ref LL_DMA_CHANNEL_4
6343 * @arg @ref LL_DMA_CHANNEL_5
6344 * @arg @ref LL_DMA_CHANNEL_6
6345 * @arg @ref LL_DMA_CHANNEL_7
6346 * @arg @ref LL_DMA_CHANNEL_8
6347 * @arg @ref LL_DMA_CHANNEL_9
6348 * @arg @ref LL_DMA_CHANNEL_10
6349 * @arg @ref LL_DMA_CHANNEL_11
6350 * @arg @ref LL_DMA_CHANNEL_12
6351 * @arg @ref LL_DMA_CHANNEL_13
6352 * @arg @ref LL_DMA_CHANNEL_14
6353 * @arg @ref LL_DMA_CHANNEL_15
6354 * @retval State of bit (1 or 0).
6355 */
LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6356 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6357 {
6358 uint32_t dma_base_addr = (uint32_t)DMAx;
6359 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
6360 == (DMA_CLLR_UDA)) ? 1UL : 0UL);
6361 }
6362
6363 /**
6364 * @brief Enable CTR3 update during the link transfer.
6365 * @note This API is used only for 2D addressing channels.
6366 * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update
6367 * @param DMAx DMAx Instance
6368 * @param Channel This parameter can be one of the following values:
6369 * @arg @ref LL_DMA_CHANNEL_12
6370 * @arg @ref LL_DMA_CHANNEL_13
6371 * @arg @ref LL_DMA_CHANNEL_14
6372 * @arg @ref LL_DMA_CHANNEL_15
6373 * @retval None.
6374 */
LL_DMA_EnableCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)6375 __STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6376 {
6377 uint32_t dma_base_addr = (uint32_t)DMAx;
6378 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
6379 }
6380
6381 /**
6382 * @brief Disable CTR3 update during the link transfer.
6383 * @note This API is used only for 2D addressing channels.
6384 * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update
6385 * @param DMAx DMAx Instance
6386 * @param Channel This parameter can be one of the following values:
6387 * @arg @ref LL_DMA_CHANNEL_12
6388 * @arg @ref LL_DMA_CHANNEL_13
6389 * @arg @ref LL_DMA_CHANNEL_14
6390 * @arg @ref LL_DMA_CHANNEL_15
6391 * @retval None.
6392 */
LL_DMA_DisableCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)6393 __STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6394 {
6395 uint32_t dma_base_addr = (uint32_t)DMAx;
6396 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
6397 }
6398
6399 /**
6400 * @brief Check if CTR3 update during the link transfer is enabled.
6401 * @note This API is used only for 2D addressing channels.
6402 * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update
6403 * @param DMAx DMAx Instance
6404 * @param Channel This parameter can be one of the following values:
6405 * @arg @ref LL_DMA_CHANNEL_12
6406 * @arg @ref LL_DMA_CHANNEL_13
6407 * @arg @ref LL_DMA_CHANNEL_14
6408 * @arg @ref LL_DMA_CHANNEL_15
6409 * @retval State of bit (1 or 0).
6410 */
LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)6411 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6412 {
6413 uint32_t dma_base_addr = (uint32_t)DMAx;
6414 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3)
6415 == (DMA_CLLR_UT3)) ? 1UL : 0UL);
6416 }
6417
6418 /**
6419 * @brief Enable CBR2 update during the link transfer.
6420 * @note This API is used only for 2D addressing channels.
6421 * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update
6422 * @param DMAx DMAx Instance
6423 * @param Channel This parameter can be one of the following values:
6424 * @arg @ref LL_DMA_CHANNEL_12
6425 * @arg @ref LL_DMA_CHANNEL_13
6426 * @arg @ref LL_DMA_CHANNEL_14
6427 * @arg @ref LL_DMA_CHANNEL_15
6428 * @retval None.
6429 */
LL_DMA_EnableCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)6430 __STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6431 {
6432 uint32_t dma_base_addr = (uint32_t)DMAx;
6433 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
6434 }
6435
6436 /**
6437 * @brief Disable CBR2 update during the link transfer.
6438 * @note This API is used only for 2D addressing channels.
6439 * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update
6440 * @param DMAx DMAx Instance
6441 * @param Channel This parameter can be one of the following values:
6442 * @arg @ref LL_DMA_CHANNEL_12
6443 * @arg @ref LL_DMA_CHANNEL_13
6444 * @arg @ref LL_DMA_CHANNEL_14
6445 * @arg @ref LL_DMA_CHANNEL_15
6446 * @retval None.
6447 */
LL_DMA_DisableCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)6448 __STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6449 {
6450 uint32_t dma_base_addr = (uint32_t)DMAx;
6451 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
6452 }
6453
6454 /**
6455 * @brief Check if CBR2 update during the link transfer is enabled.
6456 * @note This API is used only for 2D addressing channels.
6457 * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update
6458 * @param DMAx DMAx Instance
6459 * @param Channel This parameter can be one of the following values:
6460 * @arg @ref LL_DMA_CHANNEL_12
6461 * @arg @ref LL_DMA_CHANNEL_13
6462 * @arg @ref LL_DMA_CHANNEL_14
6463 * @arg @ref LL_DMA_CHANNEL_15
6464 * @retval State of bit (1 or 0).
6465 */
LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)6466 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
6467 {
6468 uint32_t dma_base_addr = (uint32_t)DMAx;
6469 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2)
6470 == (DMA_CLLR_UB2)) ? 1UL : 0UL);
6471 }
6472
6473 /**
6474 * @brief Enable CLLR update during the link transfer.
6475 * @note This API is used for all available DMA channels.
6476 * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
6477 * @param DMAx DMAx Instance
6478 * @param Channel This parameter can be one of the following values:
6479 * @arg @ref LL_DMA_CHANNEL_0
6480 * @arg @ref LL_DMA_CHANNEL_1
6481 * @arg @ref LL_DMA_CHANNEL_2
6482 * @arg @ref LL_DMA_CHANNEL_3
6483 * @arg @ref LL_DMA_CHANNEL_4
6484 * @arg @ref LL_DMA_CHANNEL_5
6485 * @arg @ref LL_DMA_CHANNEL_6
6486 * @arg @ref LL_DMA_CHANNEL_7
6487 * @arg @ref LL_DMA_CHANNEL_8
6488 * @arg @ref LL_DMA_CHANNEL_9
6489 * @arg @ref LL_DMA_CHANNEL_10
6490 * @arg @ref LL_DMA_CHANNEL_11
6491 * @arg @ref LL_DMA_CHANNEL_12
6492 * @arg @ref LL_DMA_CHANNEL_13
6493 * @arg @ref LL_DMA_CHANNEL_14
6494 * @arg @ref LL_DMA_CHANNEL_15
6495 * @retval None.
6496 */
LL_DMA_EnableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6497 __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6498 {
6499 uint32_t dma_base_addr = (uint32_t)DMAx;
6500 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
6501 }
6502
6503 /**
6504 * @brief Disable CLLR update during the link transfer.
6505 * @note This API is used for all available DMA channels.
6506 * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
6507 * @param DMAx DMAx Instance
6508 * @param Channel This parameter can be one of the following values:
6509 * @arg @ref LL_DMA_CHANNEL_0
6510 * @arg @ref LL_DMA_CHANNEL_1
6511 * @arg @ref LL_DMA_CHANNEL_2
6512 * @arg @ref LL_DMA_CHANNEL_3
6513 * @arg @ref LL_DMA_CHANNEL_4
6514 * @arg @ref LL_DMA_CHANNEL_5
6515 * @arg @ref LL_DMA_CHANNEL_6
6516 * @arg @ref LL_DMA_CHANNEL_7
6517 * @arg @ref LL_DMA_CHANNEL_8
6518 * @arg @ref LL_DMA_CHANNEL_9
6519 * @arg @ref LL_DMA_CHANNEL_10
6520 * @arg @ref LL_DMA_CHANNEL_11
6521 * @arg @ref LL_DMA_CHANNEL_12
6522 * @arg @ref LL_DMA_CHANNEL_13
6523 * @arg @ref LL_DMA_CHANNEL_14
6524 * @arg @ref LL_DMA_CHANNEL_15
6525 * @retval None.
6526 */
LL_DMA_DisableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6527 __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6528 {
6529 uint32_t dma_base_addr = (uint32_t)DMAx;
6530 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
6531 }
6532
6533 /**
6534 * @brief Check if CLLR update during the link transfer is enabled.
6535 * @note This API is used for all available DMA channels.
6536 * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
6537 * @param DMAx DMAx Instance
6538 * @param Channel This parameter can be one of the following values:
6539 * @arg @ref LL_DMA_CHANNEL_0
6540 * @arg @ref LL_DMA_CHANNEL_1
6541 * @arg @ref LL_DMA_CHANNEL_2
6542 * @arg @ref LL_DMA_CHANNEL_3
6543 * @arg @ref LL_DMA_CHANNEL_4
6544 * @arg @ref LL_DMA_CHANNEL_5
6545 * @arg @ref LL_DMA_CHANNEL_6
6546 * @arg @ref LL_DMA_CHANNEL_7
6547 * @arg @ref LL_DMA_CHANNEL_8
6548 * @arg @ref LL_DMA_CHANNEL_9
6549 * @arg @ref LL_DMA_CHANNEL_10
6550 * @arg @ref LL_DMA_CHANNEL_11
6551 * @arg @ref LL_DMA_CHANNEL_12
6552 * @arg @ref LL_DMA_CHANNEL_13
6553 * @arg @ref LL_DMA_CHANNEL_14
6554 * @arg @ref LL_DMA_CHANNEL_15
6555 * @retval State of bit (1 or 0).
6556 */
LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)6557 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
6558 {
6559 uint32_t dma_base_addr = (uint32_t)DMAx;
6560 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
6561 == (DMA_CLLR_ULL)) ? 1UL : 0UL);
6562 }
6563
6564 /**
6565 * @brief Set linked list address offset.
6566 * @note This API is used for all available DMA channels.
6567 * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
6568 * @param DMAx DMAx Instance
6569 * @param Channel This parameter can be one of the following values:
6570 * @arg @ref LL_DMA_CHANNEL_0
6571 * @arg @ref LL_DMA_CHANNEL_1
6572 * @arg @ref LL_DMA_CHANNEL_2
6573 * @arg @ref LL_DMA_CHANNEL_3
6574 * @arg @ref LL_DMA_CHANNEL_4
6575 * @arg @ref LL_DMA_CHANNEL_5
6576 * @arg @ref LL_DMA_CHANNEL_6
6577 * @arg @ref LL_DMA_CHANNEL_7
6578 * @arg @ref LL_DMA_CHANNEL_8
6579 * @arg @ref LL_DMA_CHANNEL_9
6580 * @arg @ref LL_DMA_CHANNEL_10
6581 * @arg @ref LL_DMA_CHANNEL_11
6582 * @arg @ref LL_DMA_CHANNEL_12
6583 * @arg @ref LL_DMA_CHANNEL_13
6584 * @arg @ref LL_DMA_CHANNEL_14
6585 * @arg @ref LL_DMA_CHANNEL_15
6586 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
6587 * @retval None.
6588 */
LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListAddrOffset)6589 __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel,
6590 uint32_t LinkedListAddrOffset)
6591 {
6592 uint32_t dma_base_addr = (uint32_t)DMAx;
6593 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
6594 (LinkedListAddrOffset & DMA_CLLR_LA));
6595 }
6596
6597 /**
6598 * @brief Get linked list address offset.
6599 * @note This API is used for all available DMA channels.
6600 * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
6601 * @param DMAx DMAx Instance
6602 * @param Channel This parameter can be one of the following values:
6603 * @arg @ref LL_DMA_CHANNEL_0
6604 * @arg @ref LL_DMA_CHANNEL_1
6605 * @arg @ref LL_DMA_CHANNEL_2
6606 * @arg @ref LL_DMA_CHANNEL_3
6607 * @arg @ref LL_DMA_CHANNEL_4
6608 * @arg @ref LL_DMA_CHANNEL_5
6609 * @arg @ref LL_DMA_CHANNEL_6
6610 * @arg @ref LL_DMA_CHANNEL_7
6611 * @arg @ref LL_DMA_CHANNEL_8
6612 * @arg @ref LL_DMA_CHANNEL_9
6613 * @arg @ref LL_DMA_CHANNEL_10
6614 * @arg @ref LL_DMA_CHANNEL_11
6615 * @arg @ref LL_DMA_CHANNEL_12
6616 * @arg @ref LL_DMA_CHANNEL_13
6617 * @arg @ref LL_DMA_CHANNEL_14
6618 * @arg @ref LL_DMA_CHANNEL_15
6619 * @retval Between 0 to 0x0000FFFC.
6620 */
LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel)6621 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel)
6622 {
6623 uint32_t dma_base_addr = (uint32_t)DMAx;
6624 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
6625 DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
6626 }
6627
6628 /**
6629 * @brief Get FIFO level.
6630 * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
6631 * @param DMAx DMAx Instance
6632 * @param Channel This parameter can be one of the following values:
6633 * @arg @ref LL_DMA_CHANNEL_0
6634 * @arg @ref LL_DMA_CHANNEL_1
6635 * @arg @ref LL_DMA_CHANNEL_2
6636 * @arg @ref LL_DMA_CHANNEL_3
6637 * @arg @ref LL_DMA_CHANNEL_4
6638 * @arg @ref LL_DMA_CHANNEL_5
6639 * @arg @ref LL_DMA_CHANNEL_6
6640 * @arg @ref LL_DMA_CHANNEL_7
6641 * @arg @ref LL_DMA_CHANNEL_8
6642 * @arg @ref LL_DMA_CHANNEL_9
6643 * @arg @ref LL_DMA_CHANNEL_10
6644 * @arg @ref LL_DMA_CHANNEL_11
6645 * @arg @ref LL_DMA_CHANNEL_12
6646 * @arg @ref LL_DMA_CHANNEL_13
6647 * @arg @ref LL_DMA_CHANNEL_14
6648 * @arg @ref LL_DMA_CHANNEL_15
6649 * @retval Between 0 to 0x000000FF.
6650 */
LL_DMA_GetFIFOLevel(const DMA_TypeDef * DMAx,uint32_t Channel)6651 __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
6652 {
6653 uint32_t dma_base_addr = (uint32_t)DMAx;
6654 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
6655 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
6656 }
6657
6658 #if defined (CPU_IN_SECURE_STATE)
6659 /**
6660 * @brief Enable the DMA channel secure attribute.
6661 * @note This API is used for all available DMA channels.
6662 * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure
6663 * @param DMAx DMAx Instance
6664 * @param Channel This parameter can be one of the following values:
6665 * @arg @ref LL_DMA_CHANNEL_0
6666 * @arg @ref LL_DMA_CHANNEL_1
6667 * @arg @ref LL_DMA_CHANNEL_2
6668 * @arg @ref LL_DMA_CHANNEL_3
6669 * @arg @ref LL_DMA_CHANNEL_4
6670 * @arg @ref LL_DMA_CHANNEL_5
6671 * @arg @ref LL_DMA_CHANNEL_6
6672 * @arg @ref LL_DMA_CHANNEL_7
6673 * @arg @ref LL_DMA_CHANNEL_8
6674 * @arg @ref LL_DMA_CHANNEL_9
6675 * @arg @ref LL_DMA_CHANNEL_10
6676 * @arg @ref LL_DMA_CHANNEL_11
6677 * @arg @ref LL_DMA_CHANNEL_12
6678 * @arg @ref LL_DMA_CHANNEL_13
6679 * @arg @ref LL_DMA_CHANNEL_14
6680 * @arg @ref LL_DMA_CHANNEL_15
6681 * @retval None.
6682 */
LL_DMA_EnableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)6683 __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
6684 {
6685 SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
6686 }
6687
6688 /**
6689 * @brief Disable the DMA channel secure attribute.
6690 * @note This API is used for all available DMA channels.
6691 * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure
6692 * @param DMAx DMAx Instance
6693 * @param Channel This parameter can be one of the following values:
6694 * @arg @ref LL_DMA_CHANNEL_0
6695 * @arg @ref LL_DMA_CHANNEL_1
6696 * @arg @ref LL_DMA_CHANNEL_2
6697 * @arg @ref LL_DMA_CHANNEL_3
6698 * @arg @ref LL_DMA_CHANNEL_4
6699 * @arg @ref LL_DMA_CHANNEL_5
6700 * @arg @ref LL_DMA_CHANNEL_6
6701 * @arg @ref LL_DMA_CHANNEL_7
6702 * @arg @ref LL_DMA_CHANNEL_8
6703 * @arg @ref LL_DMA_CHANNEL_9
6704 * @arg @ref LL_DMA_CHANNEL_10
6705 * @arg @ref LL_DMA_CHANNEL_11
6706 * @arg @ref LL_DMA_CHANNEL_12
6707 * @arg @ref LL_DMA_CHANNEL_13
6708 * @arg @ref LL_DMA_CHANNEL_14
6709 * @arg @ref LL_DMA_CHANNEL_15
6710 * @retval None.
6711 */
LL_DMA_DisableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)6712 __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
6713 {
6714 CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
6715 }
6716 #endif /* CPU_IN_SECURE_STATE */
6717
6718 /**
6719 * @brief Check if DMA channel secure is enabled.
6720 * @note This API is used for all available DMA channels.
6721 * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure
6722 * @param DMAx DMAx Instance
6723 * @param Channel This parameter can be one of the following values:
6724 * @arg @ref LL_DMA_CHANNEL_0
6725 * @arg @ref LL_DMA_CHANNEL_1
6726 * @arg @ref LL_DMA_CHANNEL_2
6727 * @arg @ref LL_DMA_CHANNEL_3
6728 * @arg @ref LL_DMA_CHANNEL_4
6729 * @arg @ref LL_DMA_CHANNEL_5
6730 * @arg @ref LL_DMA_CHANNEL_6
6731 * @arg @ref LL_DMA_CHANNEL_7
6732 * @arg @ref LL_DMA_CHANNEL_8
6733 * @arg @ref LL_DMA_CHANNEL_9
6734 * @arg @ref LL_DMA_CHANNEL_10
6735 * @arg @ref LL_DMA_CHANNEL_11
6736 * @arg @ref LL_DMA_CHANNEL_12
6737 * @arg @ref LL_DMA_CHANNEL_13
6738 * @arg @ref LL_DMA_CHANNEL_14
6739 * @arg @ref LL_DMA_CHANNEL_15
6740 * @retval State of bit (1 or 0).
6741 */
LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef * DMAx,uint32_t Channel)6742 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
6743 {
6744 return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
6745 == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
6746 }
6747
6748 /**
6749 * @brief Enable the DMA channel privilege attribute.
6750 * @note This API is used for all available DMA channels.
6751 * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
6752 * @param DMAx DMAx Instance
6753 * @param Channel This parameter can be one of the following values:
6754 * @arg @ref LL_DMA_CHANNEL_0
6755 * @arg @ref LL_DMA_CHANNEL_1
6756 * @arg @ref LL_DMA_CHANNEL_2
6757 * @arg @ref LL_DMA_CHANNEL_3
6758 * @arg @ref LL_DMA_CHANNEL_4
6759 * @arg @ref LL_DMA_CHANNEL_5
6760 * @arg @ref LL_DMA_CHANNEL_6
6761 * @arg @ref LL_DMA_CHANNEL_7
6762 * @arg @ref LL_DMA_CHANNEL_8
6763 * @arg @ref LL_DMA_CHANNEL_9
6764 * @arg @ref LL_DMA_CHANNEL_10
6765 * @arg @ref LL_DMA_CHANNEL_11
6766 * @arg @ref LL_DMA_CHANNEL_12
6767 * @arg @ref LL_DMA_CHANNEL_13
6768 * @arg @ref LL_DMA_CHANNEL_14
6769 * @arg @ref LL_DMA_CHANNEL_15
6770 * @retval None.
6771 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)6772 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
6773 {
6774 SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
6775 }
6776
6777 /**
6778 * @brief Disable the DMA channel privilege attribute.
6779 * @note This API is used for all available DMA channels.
6780 * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
6781 * @param DMAx DMAx Instance
6782 * @param Channel This parameter can be one of the following values:
6783 * @arg @ref LL_DMA_CHANNEL_0
6784 * @arg @ref LL_DMA_CHANNEL_1
6785 * @arg @ref LL_DMA_CHANNEL_2
6786 * @arg @ref LL_DMA_CHANNEL_3
6787 * @arg @ref LL_DMA_CHANNEL_4
6788 * @arg @ref LL_DMA_CHANNEL_5
6789 * @arg @ref LL_DMA_CHANNEL_6
6790 * @arg @ref LL_DMA_CHANNEL_7
6791 * @arg @ref LL_DMA_CHANNEL_8
6792 * @arg @ref LL_DMA_CHANNEL_9
6793 * @arg @ref LL_DMA_CHANNEL_10
6794 * @arg @ref LL_DMA_CHANNEL_11
6795 * @arg @ref LL_DMA_CHANNEL_12
6796 * @arg @ref LL_DMA_CHANNEL_13
6797 * @arg @ref LL_DMA_CHANNEL_14
6798 * @arg @ref LL_DMA_CHANNEL_15
6799 * @retval None.
6800 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)6801 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
6802 {
6803 CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
6804 }
6805
6806 /**
6807 * @brief Check if DMA Channel privilege is enabled.
6808 * @note This API is used for all available DMA channels.
6809 * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege
6810 * @param DMAx DMAx Instance
6811 * @param Channel This parameter can be one of the following values:
6812 * @arg @ref LL_DMA_CHANNEL_0
6813 * @arg @ref LL_DMA_CHANNEL_1
6814 * @arg @ref LL_DMA_CHANNEL_2
6815 * @arg @ref LL_DMA_CHANNEL_3
6816 * @arg @ref LL_DMA_CHANNEL_4
6817 * @arg @ref LL_DMA_CHANNEL_5
6818 * @arg @ref LL_DMA_CHANNEL_6
6819 * @arg @ref LL_DMA_CHANNEL_7
6820 * @arg @ref LL_DMA_CHANNEL_8
6821 * @arg @ref LL_DMA_CHANNEL_9
6822 * @arg @ref LL_DMA_CHANNEL_10
6823 * @arg @ref LL_DMA_CHANNEL_11
6824 * @arg @ref LL_DMA_CHANNEL_12
6825 * @arg @ref LL_DMA_CHANNEL_13
6826 * @arg @ref LL_DMA_CHANNEL_14
6827 * @arg @ref LL_DMA_CHANNEL_15
6828 * @retval State of bit (1 or 0).
6829 */
LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef * DMAx,uint32_t Channel)6830 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel)
6831 {
6832 return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
6833 == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
6834 }
6835
6836 #if defined (CPU_IN_SECURE_STATE)
6837 /**
6838 * @brief Enable the DMA channel lock attributes.
6839 * @note This API is used for all available DMA channels.
6840 * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
6841 * @param DMAx DMAx Instance
6842 * @param Channel This parameter can be one of the following values:
6843 * @arg @ref LL_DMA_CHANNEL_0
6844 * @arg @ref LL_DMA_CHANNEL_1
6845 * @arg @ref LL_DMA_CHANNEL_2
6846 * @arg @ref LL_DMA_CHANNEL_3
6847 * @arg @ref LL_DMA_CHANNEL_4
6848 * @arg @ref LL_DMA_CHANNEL_5
6849 * @arg @ref LL_DMA_CHANNEL_6
6850 * @arg @ref LL_DMA_CHANNEL_7
6851 * @arg @ref LL_DMA_CHANNEL_8
6852 * @arg @ref LL_DMA_CHANNEL_9
6853 * @arg @ref LL_DMA_CHANNEL_10
6854 * @arg @ref LL_DMA_CHANNEL_11
6855 * @arg @ref LL_DMA_CHANNEL_12
6856 * @arg @ref LL_DMA_CHANNEL_13
6857 * @arg @ref LL_DMA_CHANNEL_14
6858 * @arg @ref LL_DMA_CHANNEL_15
6859 * @retval None.
6860 */
LL_DMA_EnableChannelLockAttribute(DMA_TypeDef * DMAx,uint32_t Channel)6861 __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
6862 {
6863 SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
6864 }
6865 #endif /* CPU_IN_SECURE_STATE */
6866
6867 /**
6868 * @brief Check if DMA channel attributes are locked.
6869 * @note This API is used for all available DMA channels.
6870 * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
6871 * @param DMAx DMAx Instance
6872 * @param Channel This parameter can be one of the following values:
6873 * @arg @ref LL_DMA_CHANNEL_0
6874 * @arg @ref LL_DMA_CHANNEL_1
6875 * @arg @ref LL_DMA_CHANNEL_2
6876 * @arg @ref LL_DMA_CHANNEL_3
6877 * @arg @ref LL_DMA_CHANNEL_4
6878 * @arg @ref LL_DMA_CHANNEL_5
6879 * @arg @ref LL_DMA_CHANNEL_6
6880 * @arg @ref LL_DMA_CHANNEL_7
6881 * @arg @ref LL_DMA_CHANNEL_8
6882 * @arg @ref LL_DMA_CHANNEL_9
6883 * @arg @ref LL_DMA_CHANNEL_10
6884 * @arg @ref LL_DMA_CHANNEL_11
6885 * @arg @ref LL_DMA_CHANNEL_12
6886 * @arg @ref LL_DMA_CHANNEL_13
6887 * @arg @ref LL_DMA_CHANNEL_14
6888 * @arg @ref LL_DMA_CHANNEL_15
6889 * @retval State of bit (1 or 0).
6890 */
LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef * DMAx,uint32_t Channel)6891 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel)
6892 {
6893 return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
6894 == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
6895 }
6896
6897 /**
6898 * @}
6899 */
6900
6901 /** @defgroup DMA_LL_EF_FLAG_Management Flag Management
6902 * @{
6903 */
6904
6905 /**
6906 * @brief Clear trigger overrun flag.
6907 * @note This API is used for all available DMA channels.
6908 * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
6909 * @param DMAx DMAx Instance
6910 * @param Channel This parameter can be one of the following values:
6911 * @arg @ref LL_DMA_CHANNEL_0
6912 * @arg @ref LL_DMA_CHANNEL_1
6913 * @arg @ref LL_DMA_CHANNEL_2
6914 * @arg @ref LL_DMA_CHANNEL_3
6915 * @arg @ref LL_DMA_CHANNEL_4
6916 * @arg @ref LL_DMA_CHANNEL_5
6917 * @arg @ref LL_DMA_CHANNEL_6
6918 * @arg @ref LL_DMA_CHANNEL_7
6919 * @arg @ref LL_DMA_CHANNEL_8
6920 * @arg @ref LL_DMA_CHANNEL_9
6921 * @arg @ref LL_DMA_CHANNEL_10
6922 * @arg @ref LL_DMA_CHANNEL_11
6923 * @arg @ref LL_DMA_CHANNEL_12
6924 * @arg @ref LL_DMA_CHANNEL_13
6925 * @arg @ref LL_DMA_CHANNEL_14
6926 * @arg @ref LL_DMA_CHANNEL_15
6927 * @retval None.
6928 */
LL_DMA_ClearFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6929 __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6930 {
6931 uint32_t dma_base_addr = (uint32_t)DMAx;
6932 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
6933 }
6934
6935 /**
6936 * @brief Clear suspension flag.
6937 * @note This API is used for all available DMA channels.
6938 * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
6939 * @param DMAx DMAx Instance
6940 * @param Channel This parameter can be one of the following values:
6941 * @arg @ref LL_DMA_CHANNEL_0
6942 * @arg @ref LL_DMA_CHANNEL_1
6943 * @arg @ref LL_DMA_CHANNEL_2
6944 * @arg @ref LL_DMA_CHANNEL_3
6945 * @arg @ref LL_DMA_CHANNEL_4
6946 * @arg @ref LL_DMA_CHANNEL_5
6947 * @arg @ref LL_DMA_CHANNEL_6
6948 * @arg @ref LL_DMA_CHANNEL_7
6949 * @arg @ref LL_DMA_CHANNEL_8
6950 * @arg @ref LL_DMA_CHANNEL_9
6951 * @arg @ref LL_DMA_CHANNEL_10
6952 * @arg @ref LL_DMA_CHANNEL_11
6953 * @arg @ref LL_DMA_CHANNEL_12
6954 * @arg @ref LL_DMA_CHANNEL_13
6955 * @arg @ref LL_DMA_CHANNEL_14
6956 * @arg @ref LL_DMA_CHANNEL_15
6957 * @retval None.
6958 */
LL_DMA_ClearFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6959 __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6960 {
6961 uint32_t dma_base_addr = (uint32_t)DMAx;
6962 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
6963 }
6964
6965 /**
6966 * @brief Clear user setting error flag.
6967 * @note This API is used for all available DMA channels.
6968 * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
6969 * @param DMAx DMAx Instance
6970 * @param Channel This parameter can be one of the following values:
6971 * @arg @ref LL_DMA_CHANNEL_0
6972 * @arg @ref LL_DMA_CHANNEL_1
6973 * @arg @ref LL_DMA_CHANNEL_2
6974 * @arg @ref LL_DMA_CHANNEL_3
6975 * @arg @ref LL_DMA_CHANNEL_4
6976 * @arg @ref LL_DMA_CHANNEL_5
6977 * @arg @ref LL_DMA_CHANNEL_6
6978 * @arg @ref LL_DMA_CHANNEL_7
6979 * @arg @ref LL_DMA_CHANNEL_8
6980 * @arg @ref LL_DMA_CHANNEL_9
6981 * @arg @ref LL_DMA_CHANNEL_10
6982 * @arg @ref LL_DMA_CHANNEL_11
6983 * @arg @ref LL_DMA_CHANNEL_12
6984 * @arg @ref LL_DMA_CHANNEL_13
6985 * @arg @ref LL_DMA_CHANNEL_14
6986 * @arg @ref LL_DMA_CHANNEL_15
6987 * @retval None.
6988 */
LL_DMA_ClearFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6989 __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6990 {
6991 uint32_t dma_base_addr = (uint32_t)DMAx;
6992 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
6993 }
6994
6995 /**
6996 * @brief Clear link transfer error flag.
6997 * @note This API is used for all available DMA channels.
6998 * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
6999 * @param DMAx DMAx Instance
7000 * @param Channel This parameter can be one of the following values:
7001 * @arg @ref LL_DMA_CHANNEL_0
7002 * @arg @ref LL_DMA_CHANNEL_1
7003 * @arg @ref LL_DMA_CHANNEL_2
7004 * @arg @ref LL_DMA_CHANNEL_3
7005 * @arg @ref LL_DMA_CHANNEL_4
7006 * @arg @ref LL_DMA_CHANNEL_5
7007 * @arg @ref LL_DMA_CHANNEL_6
7008 * @arg @ref LL_DMA_CHANNEL_7
7009 * @arg @ref LL_DMA_CHANNEL_8
7010 * @arg @ref LL_DMA_CHANNEL_9
7011 * @arg @ref LL_DMA_CHANNEL_10
7012 * @arg @ref LL_DMA_CHANNEL_11
7013 * @arg @ref LL_DMA_CHANNEL_12
7014 * @arg @ref LL_DMA_CHANNEL_13
7015 * @arg @ref LL_DMA_CHANNEL_14
7016 * @arg @ref LL_DMA_CHANNEL_15
7017 * @retval None.
7018 */
LL_DMA_ClearFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)7019 __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
7020 {
7021 uint32_t dma_base_addr = (uint32_t)DMAx;
7022 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
7023 }
7024
7025 /**
7026 * @brief Clear data transfer error flag.
7027 * @note This API is used for all available DMA channels.
7028 * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
7029 * @param DMAx DMAx Instance
7030 * @param Channel This parameter can be one of the following values:
7031 * @arg @ref LL_DMA_CHANNEL_0
7032 * @arg @ref LL_DMA_CHANNEL_1
7033 * @arg @ref LL_DMA_CHANNEL_2
7034 * @arg @ref LL_DMA_CHANNEL_3
7035 * @arg @ref LL_DMA_CHANNEL_4
7036 * @arg @ref LL_DMA_CHANNEL_5
7037 * @arg @ref LL_DMA_CHANNEL_6
7038 * @arg @ref LL_DMA_CHANNEL_7
7039 * @arg @ref LL_DMA_CHANNEL_8
7040 * @arg @ref LL_DMA_CHANNEL_9
7041 * @arg @ref LL_DMA_CHANNEL_10
7042 * @arg @ref LL_DMA_CHANNEL_11
7043 * @arg @ref LL_DMA_CHANNEL_12
7044 * @arg @ref LL_DMA_CHANNEL_13
7045 * @arg @ref LL_DMA_CHANNEL_14
7046 * @arg @ref LL_DMA_CHANNEL_15
7047 * @retval None.
7048 */
LL_DMA_ClearFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)7049 __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
7050 {
7051 uint32_t dma_base_addr = (uint32_t)DMAx;
7052 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
7053 }
7054
7055 /**
7056 * @brief Clear half transfer flag.
7057 * @note This API is used for all available DMA channels.
7058 * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
7059 * @param DMAx DMAx Instance
7060 * @param Channel This parameter can be one of the following values:
7061 * @arg @ref LL_DMA_CHANNEL_0
7062 * @arg @ref LL_DMA_CHANNEL_1
7063 * @arg @ref LL_DMA_CHANNEL_2
7064 * @arg @ref LL_DMA_CHANNEL_3
7065 * @arg @ref LL_DMA_CHANNEL_4
7066 * @arg @ref LL_DMA_CHANNEL_5
7067 * @arg @ref LL_DMA_CHANNEL_6
7068 * @arg @ref LL_DMA_CHANNEL_7
7069 * @arg @ref LL_DMA_CHANNEL_8
7070 * @arg @ref LL_DMA_CHANNEL_9
7071 * @arg @ref LL_DMA_CHANNEL_10
7072 * @arg @ref LL_DMA_CHANNEL_11
7073 * @arg @ref LL_DMA_CHANNEL_12
7074 * @arg @ref LL_DMA_CHANNEL_13
7075 * @arg @ref LL_DMA_CHANNEL_14
7076 * @arg @ref LL_DMA_CHANNEL_15
7077 * @retval None.
7078 */
LL_DMA_ClearFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)7079 __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
7080 {
7081 uint32_t dma_base_addr = (uint32_t)DMAx;
7082 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
7083 }
7084
7085 /**
7086 * @brief Clear transfer complete flag.
7087 * @note This API is used for all available DMA channels.
7088 * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
7089 * @param DMAx DMAx Instance
7090 * @param Channel This parameter can be one of the following values:
7091 * @arg @ref LL_DMA_CHANNEL_0
7092 * @arg @ref LL_DMA_CHANNEL_1
7093 * @arg @ref LL_DMA_CHANNEL_2
7094 * @arg @ref LL_DMA_CHANNEL_3
7095 * @arg @ref LL_DMA_CHANNEL_4
7096 * @arg @ref LL_DMA_CHANNEL_5
7097 * @arg @ref LL_DMA_CHANNEL_6
7098 * @arg @ref LL_DMA_CHANNEL_7
7099 * @arg @ref LL_DMA_CHANNEL_8
7100 * @arg @ref LL_DMA_CHANNEL_9
7101 * @arg @ref LL_DMA_CHANNEL_10
7102 * @arg @ref LL_DMA_CHANNEL_11
7103 * @arg @ref LL_DMA_CHANNEL_12
7104 * @arg @ref LL_DMA_CHANNEL_13
7105 * @arg @ref LL_DMA_CHANNEL_14
7106 * @arg @ref LL_DMA_CHANNEL_15
7107 * @retval None.
7108 */
LL_DMA_ClearFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)7109 __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
7110 {
7111 uint32_t dma_base_addr = (uint32_t)DMAx;
7112 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
7113 }
7114
7115 /**
7116 * @brief Get trigger overrun flag.
7117 * @note This API is used for all available DMA channels.
7118 * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
7119 * @param DMAx DMAx Instance
7120 * @param Channel This parameter can be one of the following values:
7121 * @arg @ref LL_DMA_CHANNEL_0
7122 * @arg @ref LL_DMA_CHANNEL_1
7123 * @arg @ref LL_DMA_CHANNEL_2
7124 * @arg @ref LL_DMA_CHANNEL_3
7125 * @arg @ref LL_DMA_CHANNEL_4
7126 * @arg @ref LL_DMA_CHANNEL_5
7127 * @arg @ref LL_DMA_CHANNEL_6
7128 * @arg @ref LL_DMA_CHANNEL_7
7129 * @arg @ref LL_DMA_CHANNEL_8
7130 * @arg @ref LL_DMA_CHANNEL_9
7131 * @arg @ref LL_DMA_CHANNEL_10
7132 * @arg @ref LL_DMA_CHANNEL_11
7133 * @arg @ref LL_DMA_CHANNEL_12
7134 * @arg @ref LL_DMA_CHANNEL_13
7135 * @arg @ref LL_DMA_CHANNEL_14
7136 * @arg @ref LL_DMA_CHANNEL_15
7137 * @retval State of bit (1 or 0).
7138 */
LL_DMA_IsActiveFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)7139 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
7140 {
7141 uint32_t dma_base_addr = (uint32_t)DMAx;
7142 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
7143 == (DMA_CSR_TOF)) ? 1UL : 0UL);
7144 }
7145
7146 /**
7147 * @brief Get suspension flag.
7148 * @note This API is used for all available DMA channels.
7149 * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
7150 * @param DMAx DMAx Instance
7151 * @param Channel This parameter can be one of the following values:
7152 * @arg @ref LL_DMA_CHANNEL_0
7153 * @arg @ref LL_DMA_CHANNEL_1
7154 * @arg @ref LL_DMA_CHANNEL_2
7155 * @arg @ref LL_DMA_CHANNEL_3
7156 * @arg @ref LL_DMA_CHANNEL_4
7157 * @arg @ref LL_DMA_CHANNEL_5
7158 * @arg @ref LL_DMA_CHANNEL_6
7159 * @arg @ref LL_DMA_CHANNEL_7
7160 * @arg @ref LL_DMA_CHANNEL_8
7161 * @arg @ref LL_DMA_CHANNEL_9
7162 * @arg @ref LL_DMA_CHANNEL_10
7163 * @arg @ref LL_DMA_CHANNEL_11
7164 * @arg @ref LL_DMA_CHANNEL_12
7165 * @arg @ref LL_DMA_CHANNEL_13
7166 * @arg @ref LL_DMA_CHANNEL_14
7167 * @arg @ref LL_DMA_CHANNEL_15
7168 * @retval State of bit (1 or 0).
7169 */
LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)7170 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
7171 {
7172 uint32_t dma_base_addr = (uint32_t)DMAx;
7173 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
7174 == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
7175 }
7176
7177 /**
7178 * @brief Get user setting error flag.
7179 * @note This API is used for all available DMA channels.
7180 * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
7181 * @param DMAx DMAx Instance
7182 * @param Channel This parameter can be one of the following values:
7183 * @arg @ref LL_DMA_CHANNEL_0
7184 * @arg @ref LL_DMA_CHANNEL_1
7185 * @arg @ref LL_DMA_CHANNEL_2
7186 * @arg @ref LL_DMA_CHANNEL_3
7187 * @arg @ref LL_DMA_CHANNEL_4
7188 * @arg @ref LL_DMA_CHANNEL_5
7189 * @arg @ref LL_DMA_CHANNEL_6
7190 * @arg @ref LL_DMA_CHANNEL_7
7191 * @arg @ref LL_DMA_CHANNEL_8
7192 * @arg @ref LL_DMA_CHANNEL_9
7193 * @arg @ref LL_DMA_CHANNEL_10
7194 * @arg @ref LL_DMA_CHANNEL_11
7195 * @arg @ref LL_DMA_CHANNEL_12
7196 * @arg @ref LL_DMA_CHANNEL_13
7197 * @arg @ref LL_DMA_CHANNEL_14
7198 * @arg @ref LL_DMA_CHANNEL_15
7199 * @retval State of bit (1 or 0).
7200 */
LL_DMA_IsActiveFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)7201 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
7202 {
7203 uint32_t dma_base_addr = (uint32_t)DMAx;
7204 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
7205 == (DMA_CSR_USEF)) ? 1UL : 0UL);
7206 }
7207
7208 /**
7209 * @brief Get user setting error flag.
7210 * @note This API is used for all available DMA channels.
7211 * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
7212 * @param DMAx DMAx Instance
7213 * @param Channel This parameter can be one of the following values:
7214 * @arg @ref LL_DMA_CHANNEL_0
7215 * @arg @ref LL_DMA_CHANNEL_1
7216 * @arg @ref LL_DMA_CHANNEL_2
7217 * @arg @ref LL_DMA_CHANNEL_3
7218 * @arg @ref LL_DMA_CHANNEL_4
7219 * @arg @ref LL_DMA_CHANNEL_5
7220 * @arg @ref LL_DMA_CHANNEL_6
7221 * @arg @ref LL_DMA_CHANNEL_7
7222 * @arg @ref LL_DMA_CHANNEL_8
7223 * @arg @ref LL_DMA_CHANNEL_9
7224 * @arg @ref LL_DMA_CHANNEL_10
7225 * @arg @ref LL_DMA_CHANNEL_11
7226 * @arg @ref LL_DMA_CHANNEL_12
7227 * @arg @ref LL_DMA_CHANNEL_13
7228 * @arg @ref LL_DMA_CHANNEL_14
7229 * @arg @ref LL_DMA_CHANNEL_15
7230 * @retval State of bit (1 or 0).
7231 */
LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)7232 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
7233 {
7234 uint32_t dma_base_addr = (uint32_t)DMAx;
7235 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
7236 == (DMA_CSR_ULEF)) ? 1UL : 0UL);
7237 }
7238
7239 /**
7240 * @brief Get data transfer error flag.
7241 * @note This API is used for all available DMA channels.
7242 * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
7243 * @param DMAx DMAx Instance
7244 * @param Channel This parameter can be one of the following values:
7245 * @arg @ref LL_DMA_CHANNEL_0
7246 * @arg @ref LL_DMA_CHANNEL_1
7247 * @arg @ref LL_DMA_CHANNEL_2
7248 * @arg @ref LL_DMA_CHANNEL_3
7249 * @arg @ref LL_DMA_CHANNEL_4
7250 * @arg @ref LL_DMA_CHANNEL_5
7251 * @arg @ref LL_DMA_CHANNEL_6
7252 * @arg @ref LL_DMA_CHANNEL_7
7253 * @arg @ref LL_DMA_CHANNEL_8
7254 * @arg @ref LL_DMA_CHANNEL_9
7255 * @arg @ref LL_DMA_CHANNEL_10
7256 * @arg @ref LL_DMA_CHANNEL_11
7257 * @arg @ref LL_DMA_CHANNEL_12
7258 * @arg @ref LL_DMA_CHANNEL_13
7259 * @arg @ref LL_DMA_CHANNEL_14
7260 * @arg @ref LL_DMA_CHANNEL_15
7261 * @retval State of bit (1 or 0).
7262 */
LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)7263 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
7264 {
7265 uint32_t dma_base_addr = (uint32_t)DMAx;
7266 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
7267 == (DMA_CSR_DTEF)) ? 1UL : 0UL);
7268 }
7269
7270 /**
7271 * @brief Get half transfer flag.
7272 * @note This API is used for all available DMA channels.
7273 * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
7274 * @param DMAx DMAx Instance
7275 * @param Channel This parameter can be one of the following values:
7276 * @arg @ref LL_DMA_CHANNEL_0
7277 * @arg @ref LL_DMA_CHANNEL_1
7278 * @arg @ref LL_DMA_CHANNEL_2
7279 * @arg @ref LL_DMA_CHANNEL_3
7280 * @arg @ref LL_DMA_CHANNEL_4
7281 * @arg @ref LL_DMA_CHANNEL_5
7282 * @arg @ref LL_DMA_CHANNEL_6
7283 * @arg @ref LL_DMA_CHANNEL_7
7284 * @arg @ref LL_DMA_CHANNEL_8
7285 * @arg @ref LL_DMA_CHANNEL_9
7286 * @arg @ref LL_DMA_CHANNEL_10
7287 * @arg @ref LL_DMA_CHANNEL_11
7288 * @arg @ref LL_DMA_CHANNEL_12
7289 * @arg @ref LL_DMA_CHANNEL_13
7290 * @arg @ref LL_DMA_CHANNEL_14
7291 * @arg @ref LL_DMA_CHANNEL_15
7292 * @retval State of bit (1 or 0).
7293 */
LL_DMA_IsActiveFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)7294 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
7295 {
7296 uint32_t dma_base_addr = (uint32_t)DMAx;
7297 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
7298 == (DMA_CSR_HTF)) ? 1UL : 0UL);
7299 }
7300
7301 /**
7302 * @brief Get transfer complete flag.
7303 * @note This API is used for all available DMA channels.
7304 * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
7305 * @param DMAx DMAx Instance
7306 * @param Channel This parameter can be one of the following values:
7307 * @arg @ref LL_DMA_CHANNEL_0
7308 * @arg @ref LL_DMA_CHANNEL_1
7309 * @arg @ref LL_DMA_CHANNEL_2
7310 * @arg @ref LL_DMA_CHANNEL_3
7311 * @arg @ref LL_DMA_CHANNEL_4
7312 * @arg @ref LL_DMA_CHANNEL_5
7313 * @arg @ref LL_DMA_CHANNEL_6
7314 * @arg @ref LL_DMA_CHANNEL_7
7315 * @arg @ref LL_DMA_CHANNEL_8
7316 * @arg @ref LL_DMA_CHANNEL_9
7317 * @arg @ref LL_DMA_CHANNEL_10
7318 * @arg @ref LL_DMA_CHANNEL_11
7319 * @arg @ref LL_DMA_CHANNEL_12
7320 * @arg @ref LL_DMA_CHANNEL_13
7321 * @arg @ref LL_DMA_CHANNEL_14
7322 * @arg @ref LL_DMA_CHANNEL_15
7323 * @retval State of bit (1 or 0).
7324 */
LL_DMA_IsActiveFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)7325 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
7326 {
7327 uint32_t dma_base_addr = (uint32_t)DMAx;
7328 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
7329 == (DMA_CSR_TCF)) ? 1UL : 0UL);
7330 }
7331
7332 /**
7333 * @brief Get idle flag.
7334 * @note This API is used for all available DMA channels.
7335 * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
7336 * @param DMAx DMAx Instance
7337 * @param Channel This parameter can be one of the following values:
7338 * @arg @ref LL_DMA_CHANNEL_0
7339 * @arg @ref LL_DMA_CHANNEL_1
7340 * @arg @ref LL_DMA_CHANNEL_2
7341 * @arg @ref LL_DMA_CHANNEL_3
7342 * @arg @ref LL_DMA_CHANNEL_4
7343 * @arg @ref LL_DMA_CHANNEL_5
7344 * @arg @ref LL_DMA_CHANNEL_6
7345 * @arg @ref LL_DMA_CHANNEL_7
7346 * @arg @ref LL_DMA_CHANNEL_8
7347 * @arg @ref LL_DMA_CHANNEL_9
7348 * @arg @ref LL_DMA_CHANNEL_10
7349 * @arg @ref LL_DMA_CHANNEL_11
7350 * @arg @ref LL_DMA_CHANNEL_12
7351 * @arg @ref LL_DMA_CHANNEL_13
7352 * @arg @ref LL_DMA_CHANNEL_14
7353 * @arg @ref LL_DMA_CHANNEL_15
7354 * @retval State of bit (1 or 0).
7355 */
LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef * DMAx,uint32_t Channel)7356 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel)
7357 {
7358 uint32_t dma_base_addr = (uint32_t)DMAx;
7359 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
7360 == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
7361 }
7362
7363 /**
7364 * @brief Check if nsecure masked interrupt is active.
7365 * @note This API is used for all available DMA channels.
7366 * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS
7367 * @param DMAx DMAx Instance
7368 * @param Channel This parameter can be one of the following values:
7369 * @arg @ref LL_DMA_CHANNEL_0
7370 * @arg @ref LL_DMA_CHANNEL_1
7371 * @arg @ref LL_DMA_CHANNEL_2
7372 * @arg @ref LL_DMA_CHANNEL_3
7373 * @arg @ref LL_DMA_CHANNEL_4
7374 * @arg @ref LL_DMA_CHANNEL_5
7375 * @arg @ref LL_DMA_CHANNEL_6
7376 * @arg @ref LL_DMA_CHANNEL_7
7377 * @arg @ref LL_DMA_CHANNEL_8
7378 * @arg @ref LL_DMA_CHANNEL_9
7379 * @arg @ref LL_DMA_CHANNEL_10
7380 * @arg @ref LL_DMA_CHANNEL_11
7381 * @arg @ref LL_DMA_CHANNEL_12
7382 * @arg @ref LL_DMA_CHANNEL_13
7383 * @arg @ref LL_DMA_CHANNEL_14
7384 * @arg @ref LL_DMA_CHANNEL_15
7385 * @retval State of bit (1 or 0).
7386 */
LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef * DMAx,uint32_t Channel)7387 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel)
7388 {
7389 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
7390 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
7391 }
7392
7393 #if defined (CPU_IN_SECURE_STATE)
7394 /**
7395 * @brief Check if secure masked interrupt is active.
7396 * @note This API is used for all available DMA channels.
7397 * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS
7398 * @param DMAx DMAx Instance
7399 * @param Channel This parameter can be one of the following values:
7400 * @arg @ref LL_DMA_CHANNEL_0
7401 * @arg @ref LL_DMA_CHANNEL_1
7402 * @arg @ref LL_DMA_CHANNEL_2
7403 * @arg @ref LL_DMA_CHANNEL_3
7404 * @arg @ref LL_DMA_CHANNEL_4
7405 * @arg @ref LL_DMA_CHANNEL_5
7406 * @arg @ref LL_DMA_CHANNEL_6
7407 * @arg @ref LL_DMA_CHANNEL_7
7408 * @arg @ref LL_DMA_CHANNEL_8
7409 * @arg @ref LL_DMA_CHANNEL_9
7410 * @arg @ref LL_DMA_CHANNEL_10
7411 * @arg @ref LL_DMA_CHANNEL_11
7412 * @arg @ref LL_DMA_CHANNEL_12
7413 * @arg @ref LL_DMA_CHANNEL_13
7414 * @arg @ref LL_DMA_CHANNEL_14
7415 * @arg @ref LL_DMA_CHANNEL_15
7416 * @retval State of bit (1 or 0).
7417 */
LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef * DMAx,uint32_t Channel)7418 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel)
7419 {
7420 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
7421 == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
7422 }
7423 #endif /* CPU_IN_SECURE_STATE */
7424 /**
7425 * @}
7426 */
7427
7428 /** @defgroup DMA_LL_EF_IT_Management Interrupt Management
7429 * @{
7430 */
7431
7432 /**
7433 * @brief Enable trigger overrun interrupt.
7434 * @note This API is used for all available DMA channels.
7435 * @rmtoll CCR TOIE LL_DMA_EnableIT_TO
7436 * @param DMAx DMAx Instance
7437 * @param Channel This parameter can be one of the following values:
7438 * @arg @ref LL_DMA_CHANNEL_0
7439 * @arg @ref LL_DMA_CHANNEL_1
7440 * @arg @ref LL_DMA_CHANNEL_2
7441 * @arg @ref LL_DMA_CHANNEL_3
7442 * @arg @ref LL_DMA_CHANNEL_4
7443 * @arg @ref LL_DMA_CHANNEL_5
7444 * @arg @ref LL_DMA_CHANNEL_6
7445 * @arg @ref LL_DMA_CHANNEL_7
7446 * @arg @ref LL_DMA_CHANNEL_8
7447 * @arg @ref LL_DMA_CHANNEL_9
7448 * @arg @ref LL_DMA_CHANNEL_10
7449 * @arg @ref LL_DMA_CHANNEL_11
7450 * @arg @ref LL_DMA_CHANNEL_12
7451 * @arg @ref LL_DMA_CHANNEL_13
7452 * @arg @ref LL_DMA_CHANNEL_14
7453 * @arg @ref LL_DMA_CHANNEL_15
7454 * @retval None.
7455 */
LL_DMA_EnableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)7456 __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
7457 {
7458 uint32_t dma_base_addr = (uint32_t)DMAx;
7459 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
7460 }
7461
7462 /**
7463 * @brief Enable suspension interrupt.
7464 * @note This API is used for all available DMA channels.
7465 * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
7466 * @param DMAx DMAx Instance
7467 * @param Channel This parameter can be one of the following values:
7468 * @arg @ref LL_DMA_CHANNEL_0
7469 * @arg @ref LL_DMA_CHANNEL_1
7470 * @arg @ref LL_DMA_CHANNEL_2
7471 * @arg @ref LL_DMA_CHANNEL_3
7472 * @arg @ref LL_DMA_CHANNEL_4
7473 * @arg @ref LL_DMA_CHANNEL_5
7474 * @arg @ref LL_DMA_CHANNEL_6
7475 * @arg @ref LL_DMA_CHANNEL_7
7476 * @arg @ref LL_DMA_CHANNEL_8
7477 * @arg @ref LL_DMA_CHANNEL_9
7478 * @arg @ref LL_DMA_CHANNEL_10
7479 * @arg @ref LL_DMA_CHANNEL_11
7480 * @arg @ref LL_DMA_CHANNEL_12
7481 * @arg @ref LL_DMA_CHANNEL_13
7482 * @arg @ref LL_DMA_CHANNEL_14
7483 * @arg @ref LL_DMA_CHANNEL_15
7484 * @retval None.
7485 */
LL_DMA_EnableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)7486 __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
7487 {
7488 uint32_t dma_base_addr = (uint32_t)DMAx;
7489 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
7490 }
7491
7492 /**
7493 * @brief Enable user setting error interrupt.
7494 * @note This API is used for all available DMA channels.
7495 * @rmtoll CCR USEIE LL_DMA_EnableIT_USE
7496 * @param DMAx DMAx Instance
7497 * @param Channel This parameter can be one of the following values:
7498 * @arg @ref LL_DMA_CHANNEL_0
7499 * @arg @ref LL_DMA_CHANNEL_1
7500 * @arg @ref LL_DMA_CHANNEL_2
7501 * @arg @ref LL_DMA_CHANNEL_3
7502 * @arg @ref LL_DMA_CHANNEL_4
7503 * @arg @ref LL_DMA_CHANNEL_5
7504 * @arg @ref LL_DMA_CHANNEL_6
7505 * @arg @ref LL_DMA_CHANNEL_7
7506 * @arg @ref LL_DMA_CHANNEL_8
7507 * @arg @ref LL_DMA_CHANNEL_9
7508 * @arg @ref LL_DMA_CHANNEL_10
7509 * @arg @ref LL_DMA_CHANNEL_11
7510 * @arg @ref LL_DMA_CHANNEL_12
7511 * @arg @ref LL_DMA_CHANNEL_13
7512 * @arg @ref LL_DMA_CHANNEL_14
7513 * @arg @ref LL_DMA_CHANNEL_15
7514 * @retval None.
7515 */
LL_DMA_EnableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)7516 __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
7517 {
7518 uint32_t dma_base_addr = (uint32_t)DMAx;
7519 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
7520 }
7521
7522 /**
7523 * @brief Enable update link transfer error interrupt.
7524 * @note This API is used for all available DMA channels.
7525 * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
7526 * @param DMAx DMAx Instance
7527 * @param Channel This parameter can be one of the following values:
7528 * @arg @ref LL_DMA_CHANNEL_0
7529 * @arg @ref LL_DMA_CHANNEL_1
7530 * @arg @ref LL_DMA_CHANNEL_2
7531 * @arg @ref LL_DMA_CHANNEL_3
7532 * @arg @ref LL_DMA_CHANNEL_4
7533 * @arg @ref LL_DMA_CHANNEL_5
7534 * @arg @ref LL_DMA_CHANNEL_6
7535 * @arg @ref LL_DMA_CHANNEL_7
7536 * @arg @ref LL_DMA_CHANNEL_8
7537 * @arg @ref LL_DMA_CHANNEL_9
7538 * @arg @ref LL_DMA_CHANNEL_10
7539 * @arg @ref LL_DMA_CHANNEL_11
7540 * @arg @ref LL_DMA_CHANNEL_12
7541 * @arg @ref LL_DMA_CHANNEL_13
7542 * @arg @ref LL_DMA_CHANNEL_14
7543 * @arg @ref LL_DMA_CHANNEL_15
7544 * @retval None.
7545 */
LL_DMA_EnableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)7546 __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
7547 {
7548 uint32_t dma_base_addr = (uint32_t)DMAx;
7549 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
7550 }
7551
7552 /**
7553 * @brief Enable data transfer error interrupt.
7554 * @note This API is used for all available DMA channels.
7555 * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
7556 * @param DMAx DMAx Instance
7557 * @param Channel This parameter can be one of the following values:
7558 * @arg @ref LL_DMA_CHANNEL_0
7559 * @arg @ref LL_DMA_CHANNEL_1
7560 * @arg @ref LL_DMA_CHANNEL_2
7561 * @arg @ref LL_DMA_CHANNEL_3
7562 * @arg @ref LL_DMA_CHANNEL_4
7563 * @arg @ref LL_DMA_CHANNEL_5
7564 * @arg @ref LL_DMA_CHANNEL_6
7565 * @arg @ref LL_DMA_CHANNEL_7
7566 * @arg @ref LL_DMA_CHANNEL_8
7567 * @arg @ref LL_DMA_CHANNEL_9
7568 * @arg @ref LL_DMA_CHANNEL_10
7569 * @arg @ref LL_DMA_CHANNEL_11
7570 * @arg @ref LL_DMA_CHANNEL_12
7571 * @arg @ref LL_DMA_CHANNEL_13
7572 * @arg @ref LL_DMA_CHANNEL_14
7573 * @arg @ref LL_DMA_CHANNEL_15
7574 * @retval None.
7575 */
LL_DMA_EnableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)7576 __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
7577 {
7578 uint32_t dma_base_addr = (uint32_t)DMAx;
7579 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
7580 }
7581
7582 /**
7583 * @brief Enable half transfer complete interrupt.
7584 * @note This API is used for all available DMA channels.
7585 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
7586 * @param DMAx DMAx Instance
7587 * @param Channel This parameter can be one of the following values:
7588 * @arg @ref LL_DMA_CHANNEL_0
7589 * @arg @ref LL_DMA_CHANNEL_1
7590 * @arg @ref LL_DMA_CHANNEL_2
7591 * @arg @ref LL_DMA_CHANNEL_3
7592 * @arg @ref LL_DMA_CHANNEL_4
7593 * @arg @ref LL_DMA_CHANNEL_5
7594 * @arg @ref LL_DMA_CHANNEL_6
7595 * @arg @ref LL_DMA_CHANNEL_7
7596 * @arg @ref LL_DMA_CHANNEL_8
7597 * @arg @ref LL_DMA_CHANNEL_9
7598 * @arg @ref LL_DMA_CHANNEL_10
7599 * @arg @ref LL_DMA_CHANNEL_11
7600 * @arg @ref LL_DMA_CHANNEL_12
7601 * @arg @ref LL_DMA_CHANNEL_13
7602 * @arg @ref LL_DMA_CHANNEL_14
7603 * @arg @ref LL_DMA_CHANNEL_15
7604 * @retval None.
7605 */
LL_DMA_EnableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)7606 __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
7607 {
7608 uint32_t dma_base_addr = (uint32_t)DMAx;
7609 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
7610 }
7611
7612 /**
7613 * @brief Enable transfer complete interrupt.
7614 * @note This API is used for all available DMA channels.
7615 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
7616 * @param DMAx DMAx Instance
7617 * @param Channel This parameter can be one of the following values:
7618 * @arg @ref LL_DMA_CHANNEL_0
7619 * @arg @ref LL_DMA_CHANNEL_1
7620 * @arg @ref LL_DMA_CHANNEL_2
7621 * @arg @ref LL_DMA_CHANNEL_3
7622 * @arg @ref LL_DMA_CHANNEL_4
7623 * @arg @ref LL_DMA_CHANNEL_5
7624 * @arg @ref LL_DMA_CHANNEL_6
7625 * @arg @ref LL_DMA_CHANNEL_7
7626 * @arg @ref LL_DMA_CHANNEL_8
7627 * @arg @ref LL_DMA_CHANNEL_9
7628 * @arg @ref LL_DMA_CHANNEL_10
7629 * @arg @ref LL_DMA_CHANNEL_11
7630 * @arg @ref LL_DMA_CHANNEL_12
7631 * @arg @ref LL_DMA_CHANNEL_13
7632 * @arg @ref LL_DMA_CHANNEL_14
7633 * @arg @ref LL_DMA_CHANNEL_15
7634 * @retval None.
7635 */
LL_DMA_EnableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)7636 __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
7637 {
7638 uint32_t dma_base_addr = (uint32_t)DMAx;
7639 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
7640 }
7641
7642 /**
7643 * @brief Disable trigger overrun interrupt.
7644 * @note This API is used for all available DMA channels.
7645 * @rmtoll CCR TOIE LL_DMA_DisableIT_TO
7646 * @param DMAx DMAx Instance
7647 * @param Channel This parameter can be one of the following values:
7648 * @arg @ref LL_DMA_CHANNEL_0
7649 * @arg @ref LL_DMA_CHANNEL_1
7650 * @arg @ref LL_DMA_CHANNEL_2
7651 * @arg @ref LL_DMA_CHANNEL_3
7652 * @arg @ref LL_DMA_CHANNEL_4
7653 * @arg @ref LL_DMA_CHANNEL_5
7654 * @arg @ref LL_DMA_CHANNEL_6
7655 * @arg @ref LL_DMA_CHANNEL_7
7656 * @arg @ref LL_DMA_CHANNEL_8
7657 * @arg @ref LL_DMA_CHANNEL_9
7658 * @arg @ref LL_DMA_CHANNEL_10
7659 * @arg @ref LL_DMA_CHANNEL_11
7660 * @arg @ref LL_DMA_CHANNEL_12
7661 * @arg @ref LL_DMA_CHANNEL_13
7662 * @arg @ref LL_DMA_CHANNEL_14
7663 * @arg @ref LL_DMA_CHANNEL_15
7664 * @retval None.
7665 */
LL_DMA_DisableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)7666 __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
7667 {
7668 uint32_t dma_base_addr = (uint32_t)DMAx;
7669 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
7670 }
7671
7672 /**
7673 * @brief Disable suspension interrupt.
7674 * @note This API is used for all available DMA channels.
7675 * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
7676 * @param DMAx DMAx Instance
7677 * @param Channel This parameter can be one of the following values:
7678 * @arg @ref LL_DMA_CHANNEL_0
7679 * @arg @ref LL_DMA_CHANNEL_1
7680 * @arg @ref LL_DMA_CHANNEL_2
7681 * @arg @ref LL_DMA_CHANNEL_3
7682 * @arg @ref LL_DMA_CHANNEL_4
7683 * @arg @ref LL_DMA_CHANNEL_5
7684 * @arg @ref LL_DMA_CHANNEL_6
7685 * @arg @ref LL_DMA_CHANNEL_7
7686 * @arg @ref LL_DMA_CHANNEL_8
7687 * @arg @ref LL_DMA_CHANNEL_9
7688 * @arg @ref LL_DMA_CHANNEL_10
7689 * @arg @ref LL_DMA_CHANNEL_11
7690 * @arg @ref LL_DMA_CHANNEL_12
7691 * @arg @ref LL_DMA_CHANNEL_13
7692 * @arg @ref LL_DMA_CHANNEL_14
7693 * @arg @ref LL_DMA_CHANNEL_15
7694 * @retval None.
7695 */
LL_DMA_DisableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)7696 __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
7697 {
7698 uint32_t dma_base_addr = (uint32_t)DMAx;
7699 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
7700 }
7701
7702 /**
7703 * @brief Disable user setting error interrupt.
7704 * @note This API is used for all available DMA channels.
7705 * @rmtoll CCR USEIE LL_DMA_DisableIT_USE
7706 * @param DMAx DMAx Instance
7707 * @param Channel This parameter can be one of the following values:
7708 * @arg @ref LL_DMA_CHANNEL_0
7709 * @arg @ref LL_DMA_CHANNEL_1
7710 * @arg @ref LL_DMA_CHANNEL_2
7711 * @arg @ref LL_DMA_CHANNEL_3
7712 * @arg @ref LL_DMA_CHANNEL_4
7713 * @arg @ref LL_DMA_CHANNEL_5
7714 * @arg @ref LL_DMA_CHANNEL_6
7715 * @arg @ref LL_DMA_CHANNEL_7
7716 * @arg @ref LL_DMA_CHANNEL_8
7717 * @arg @ref LL_DMA_CHANNEL_9
7718 * @arg @ref LL_DMA_CHANNEL_10
7719 * @arg @ref LL_DMA_CHANNEL_11
7720 * @arg @ref LL_DMA_CHANNEL_12
7721 * @arg @ref LL_DMA_CHANNEL_13
7722 * @arg @ref LL_DMA_CHANNEL_14
7723 * @arg @ref LL_DMA_CHANNEL_15
7724 * @retval None.
7725 */
LL_DMA_DisableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)7726 __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
7727 {
7728 uint32_t dma_base_addr = (uint32_t)DMAx;
7729 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
7730 }
7731
7732 /**
7733 * @brief Disable update link transfer error interrupt.
7734 * @note This API is used for all available DMA channels.
7735 * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
7736 * @param DMAx DMAx Instance
7737 * @param Channel This parameter can be one of the following values:
7738 * @arg @ref LL_DMA_CHANNEL_0
7739 * @arg @ref LL_DMA_CHANNEL_1
7740 * @arg @ref LL_DMA_CHANNEL_2
7741 * @arg @ref LL_DMA_CHANNEL_3
7742 * @arg @ref LL_DMA_CHANNEL_4
7743 * @arg @ref LL_DMA_CHANNEL_5
7744 * @arg @ref LL_DMA_CHANNEL_6
7745 * @arg @ref LL_DMA_CHANNEL_7
7746 * @arg @ref LL_DMA_CHANNEL_8
7747 * @arg @ref LL_DMA_CHANNEL_9
7748 * @arg @ref LL_DMA_CHANNEL_10
7749 * @arg @ref LL_DMA_CHANNEL_11
7750 * @arg @ref LL_DMA_CHANNEL_12
7751 * @arg @ref LL_DMA_CHANNEL_13
7752 * @arg @ref LL_DMA_CHANNEL_14
7753 * @arg @ref LL_DMA_CHANNEL_15
7754 * @retval None.
7755 */
LL_DMA_DisableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)7756 __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
7757 {
7758 uint32_t dma_base_addr = (uint32_t)DMAx;
7759 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
7760 }
7761
7762 /**
7763 * @brief Disable data transfer error interrupt.
7764 * @note This API is used for all available DMA channels.
7765 * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
7766 * @param DMAx DMAx Instance
7767 * @param Channel This parameter can be one of the following values:
7768 * @arg @ref LL_DMA_CHANNEL_0
7769 * @arg @ref LL_DMA_CHANNEL_1
7770 * @arg @ref LL_DMA_CHANNEL_2
7771 * @arg @ref LL_DMA_CHANNEL_3
7772 * @arg @ref LL_DMA_CHANNEL_4
7773 * @arg @ref LL_DMA_CHANNEL_5
7774 * @arg @ref LL_DMA_CHANNEL_6
7775 * @arg @ref LL_DMA_CHANNEL_7
7776 * @arg @ref LL_DMA_CHANNEL_8
7777 * @arg @ref LL_DMA_CHANNEL_9
7778 * @arg @ref LL_DMA_CHANNEL_10
7779 * @arg @ref LL_DMA_CHANNEL_11
7780 * @arg @ref LL_DMA_CHANNEL_12
7781 * @arg @ref LL_DMA_CHANNEL_13
7782 * @arg @ref LL_DMA_CHANNEL_14
7783 * @arg @ref LL_DMA_CHANNEL_15
7784 * @retval None.
7785 */
LL_DMA_DisableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)7786 __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
7787 {
7788 uint32_t dma_base_addr = (uint32_t)DMAx;
7789 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
7790 }
7791
7792 /**
7793 * @brief Disable half transfer complete interrupt.
7794 * @note This API is used for all available DMA channels.
7795 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
7796 * @param DMAx DMAx Instance
7797 * @param Channel This parameter can be one of the following values:
7798 * @arg @ref LL_DMA_CHANNEL_0
7799 * @arg @ref LL_DMA_CHANNEL_1
7800 * @arg @ref LL_DMA_CHANNEL_2
7801 * @arg @ref LL_DMA_CHANNEL_3
7802 * @arg @ref LL_DMA_CHANNEL_4
7803 * @arg @ref LL_DMA_CHANNEL_5
7804 * @arg @ref LL_DMA_CHANNEL_6
7805 * @arg @ref LL_DMA_CHANNEL_7
7806 * @arg @ref LL_DMA_CHANNEL_8
7807 * @arg @ref LL_DMA_CHANNEL_9
7808 * @arg @ref LL_DMA_CHANNEL_10
7809 * @arg @ref LL_DMA_CHANNEL_11
7810 * @arg @ref LL_DMA_CHANNEL_12
7811 * @arg @ref LL_DMA_CHANNEL_13
7812 * @arg @ref LL_DMA_CHANNEL_14
7813 * @arg @ref LL_DMA_CHANNEL_15
7814 * @retval None.
7815 */
LL_DMA_DisableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)7816 __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
7817 {
7818 uint32_t dma_base_addr = (uint32_t)DMAx;
7819 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
7820 }
7821
7822 /**
7823 * @brief Disable transfer complete interrupt.
7824 * @note This API is used for all available DMA channels.
7825 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
7826 * @param DMAx DMAx Instance
7827 * @param Channel This parameter can be one of the following values:
7828 * @arg @ref LL_DMA_CHANNEL_0
7829 * @arg @ref LL_DMA_CHANNEL_1
7830 * @arg @ref LL_DMA_CHANNEL_2
7831 * @arg @ref LL_DMA_CHANNEL_3
7832 * @arg @ref LL_DMA_CHANNEL_4
7833 * @arg @ref LL_DMA_CHANNEL_5
7834 * @arg @ref LL_DMA_CHANNEL_6
7835 * @arg @ref LL_DMA_CHANNEL_7
7836 * @arg @ref LL_DMA_CHANNEL_8
7837 * @arg @ref LL_DMA_CHANNEL_9
7838 * @arg @ref LL_DMA_CHANNEL_10
7839 * @arg @ref LL_DMA_CHANNEL_11
7840 * @arg @ref LL_DMA_CHANNEL_12
7841 * @arg @ref LL_DMA_CHANNEL_13
7842 * @arg @ref LL_DMA_CHANNEL_14
7843 * @arg @ref LL_DMA_CHANNEL_15
7844 * @retval None.
7845 */
LL_DMA_DisableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)7846 __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
7847 {
7848 uint32_t dma_base_addr = (uint32_t)DMAx;
7849 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
7850 }
7851
7852 /**
7853 * @brief Check if trigger overrun interrupt is enabled.
7854 * @note This API is used for all available DMA channels.
7855 * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
7856 * @param DMAx DMAx Instance
7857 * @param Channel This parameter can be one of the following values:
7858 * @arg @ref LL_DMA_CHANNEL_0
7859 * @arg @ref LL_DMA_CHANNEL_1
7860 * @arg @ref LL_DMA_CHANNEL_2
7861 * @arg @ref LL_DMA_CHANNEL_3
7862 * @arg @ref LL_DMA_CHANNEL_4
7863 * @arg @ref LL_DMA_CHANNEL_5
7864 * @arg @ref LL_DMA_CHANNEL_6
7865 * @arg @ref LL_DMA_CHANNEL_7
7866 * @arg @ref LL_DMA_CHANNEL_8
7867 * @arg @ref LL_DMA_CHANNEL_9
7868 * @arg @ref LL_DMA_CHANNEL_10
7869 * @arg @ref LL_DMA_CHANNEL_11
7870 * @arg @ref LL_DMA_CHANNEL_12
7871 * @arg @ref LL_DMA_CHANNEL_13
7872 * @arg @ref LL_DMA_CHANNEL_14
7873 * @arg @ref LL_DMA_CHANNEL_15
7874 * @retval State of bit (1 or 0).
7875 */
LL_DMA_IsEnabledIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)7876 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
7877 {
7878 uint32_t dma_base_addr = (uint32_t)DMAx;
7879 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
7880 == DMA_CCR_TOIE) ? 1UL : 0UL);
7881 }
7882
7883 /**
7884 * @brief Check if suspension interrupt is enabled.
7885 * @note This API is used for all available DMA channels.
7886 * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
7887 * @param DMAx DMAx Instance
7888 * @param Channel This parameter can be one of the following values:
7889 * @arg @ref LL_DMA_CHANNEL_0
7890 * @arg @ref LL_DMA_CHANNEL_1
7891 * @arg @ref LL_DMA_CHANNEL_2
7892 * @arg @ref LL_DMA_CHANNEL_3
7893 * @arg @ref LL_DMA_CHANNEL_4
7894 * @arg @ref LL_DMA_CHANNEL_5
7895 * @arg @ref LL_DMA_CHANNEL_6
7896 * @arg @ref LL_DMA_CHANNEL_7
7897 * @arg @ref LL_DMA_CHANNEL_8
7898 * @arg @ref LL_DMA_CHANNEL_9
7899 * @arg @ref LL_DMA_CHANNEL_10
7900 * @arg @ref LL_DMA_CHANNEL_11
7901 * @arg @ref LL_DMA_CHANNEL_12
7902 * @arg @ref LL_DMA_CHANNEL_13
7903 * @arg @ref LL_DMA_CHANNEL_14
7904 * @arg @ref LL_DMA_CHANNEL_15
7905 * @retval State of bit (1 or 0).
7906 */
LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)7907 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
7908 {
7909 uint32_t dma_base_addr = (uint32_t)DMAx;
7910 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
7911 == DMA_CCR_SUSPIE) ? 1UL : 0UL);
7912 }
7913
7914 /**
7915 * @brief Check if user setting error interrupt is enabled.
7916 * @note This API is used for all available DMA channels.
7917 * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
7918 * @param DMAx DMAx Instance
7919 * @param Channel This parameter can be one of the following values:
7920 * @arg @ref LL_DMA_CHANNEL_0
7921 * @arg @ref LL_DMA_CHANNEL_1
7922 * @arg @ref LL_DMA_CHANNEL_2
7923 * @arg @ref LL_DMA_CHANNEL_3
7924 * @arg @ref LL_DMA_CHANNEL_4
7925 * @arg @ref LL_DMA_CHANNEL_5
7926 * @arg @ref LL_DMA_CHANNEL_6
7927 * @arg @ref LL_DMA_CHANNEL_7
7928 * @arg @ref LL_DMA_CHANNEL_8
7929 * @arg @ref LL_DMA_CHANNEL_9
7930 * @arg @ref LL_DMA_CHANNEL_10
7931 * @arg @ref LL_DMA_CHANNEL_11
7932 * @arg @ref LL_DMA_CHANNEL_12
7933 * @arg @ref LL_DMA_CHANNEL_13
7934 * @arg @ref LL_DMA_CHANNEL_14
7935 * @arg @ref LL_DMA_CHANNEL_15
7936 * @retval State of bit (1 or 0).
7937 */
LL_DMA_IsEnabledIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)7938 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
7939 {
7940 uint32_t dma_base_addr = (uint32_t)DMAx;
7941 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
7942 == DMA_CCR_USEIE) ? 1UL : 0UL);
7943 }
7944
7945 /**
7946 * @brief Check if update link transfer error interrupt is enabled.
7947 * @note This API is used for all available DMA channels.
7948 * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
7949 * @param DMAx DMAx Instance
7950 * @param Channel This parameter can be one of the following values:
7951 * @arg @ref LL_DMA_CHANNEL_0
7952 * @arg @ref LL_DMA_CHANNEL_1
7953 * @arg @ref LL_DMA_CHANNEL_2
7954 * @arg @ref LL_DMA_CHANNEL_3
7955 * @arg @ref LL_DMA_CHANNEL_4
7956 * @arg @ref LL_DMA_CHANNEL_5
7957 * @arg @ref LL_DMA_CHANNEL_6
7958 * @arg @ref LL_DMA_CHANNEL_7
7959 * @arg @ref LL_DMA_CHANNEL_8
7960 * @arg @ref LL_DMA_CHANNEL_9
7961 * @arg @ref LL_DMA_CHANNEL_10
7962 * @arg @ref LL_DMA_CHANNEL_11
7963 * @arg @ref LL_DMA_CHANNEL_12
7964 * @arg @ref LL_DMA_CHANNEL_13
7965 * @arg @ref LL_DMA_CHANNEL_14
7966 * @arg @ref LL_DMA_CHANNEL_15
7967 * @retval State of bit (1 or 0).
7968 */
LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)7969 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
7970 {
7971 uint32_t dma_base_addr = (uint32_t)DMAx;
7972 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
7973 == DMA_CCR_ULEIE) ? 1UL : 0UL);
7974 }
7975
7976 /**
7977 * @brief Check if data transfer error interrupt is enabled.
7978 * @note This API is used for all available DMA channels.
7979 * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
7980 * @param DMAx DMAx Instance
7981 * @param Channel This parameter can be one of the following values:
7982 * @arg @ref LL_DMA_CHANNEL_0
7983 * @arg @ref LL_DMA_CHANNEL_1
7984 * @arg @ref LL_DMA_CHANNEL_2
7985 * @arg @ref LL_DMA_CHANNEL_3
7986 * @arg @ref LL_DMA_CHANNEL_4
7987 * @arg @ref LL_DMA_CHANNEL_5
7988 * @arg @ref LL_DMA_CHANNEL_6
7989 * @arg @ref LL_DMA_CHANNEL_7
7990 * @arg @ref LL_DMA_CHANNEL_8
7991 * @arg @ref LL_DMA_CHANNEL_9
7992 * @arg @ref LL_DMA_CHANNEL_10
7993 * @arg @ref LL_DMA_CHANNEL_11
7994 * @arg @ref LL_DMA_CHANNEL_12
7995 * @arg @ref LL_DMA_CHANNEL_13
7996 * @arg @ref LL_DMA_CHANNEL_14
7997 * @arg @ref LL_DMA_CHANNEL_15
7998 * @retval State of bit (1 or 0).
7999 */
LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)8000 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
8001 {
8002 uint32_t dma_base_addr = (uint32_t)DMAx;
8003 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
8004 == DMA_CCR_DTEIE) ? 1UL : 0UL);
8005 }
8006
8007 /**
8008 * @brief Check if half transfer complete interrupt is enabled.
8009 * @note This API is used for all available DMA channels.
8010 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
8011 * @param DMAx DMAx Instance
8012 * @param Channel This parameter can be one of the following values:
8013 * @arg @ref LL_DMA_CHANNEL_0
8014 * @arg @ref LL_DMA_CHANNEL_1
8015 * @arg @ref LL_DMA_CHANNEL_2
8016 * @arg @ref LL_DMA_CHANNEL_3
8017 * @arg @ref LL_DMA_CHANNEL_4
8018 * @arg @ref LL_DMA_CHANNEL_5
8019 * @arg @ref LL_DMA_CHANNEL_6
8020 * @arg @ref LL_DMA_CHANNEL_7
8021 * @arg @ref LL_DMA_CHANNEL_8
8022 * @arg @ref LL_DMA_CHANNEL_9
8023 * @arg @ref LL_DMA_CHANNEL_10
8024 * @arg @ref LL_DMA_CHANNEL_11
8025 * @arg @ref LL_DMA_CHANNEL_12
8026 * @arg @ref LL_DMA_CHANNEL_13
8027 * @arg @ref LL_DMA_CHANNEL_14
8028 * @arg @ref LL_DMA_CHANNEL_15
8029 * @retval State of bit (1 or 0).
8030 */
LL_DMA_IsEnabledIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)8031 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
8032 {
8033 uint32_t dma_base_addr = (uint32_t)DMAx;
8034 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
8035 == DMA_CCR_HTIE) ? 1UL : 0UL);
8036 }
8037
8038 /**
8039 * @brief Check if transfer complete interrupt is enabled.
8040 * @note This API is used for all available DMA channels.
8041 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
8042 * @param DMAx DMAx Instance
8043 * @param Channel This parameter can be one of the following values:
8044 * @arg @ref LL_DMA_CHANNEL_0
8045 * @arg @ref LL_DMA_CHANNEL_1
8046 * @arg @ref LL_DMA_CHANNEL_2
8047 * @arg @ref LL_DMA_CHANNEL_3
8048 * @arg @ref LL_DMA_CHANNEL_4
8049 * @arg @ref LL_DMA_CHANNEL_5
8050 * @arg @ref LL_DMA_CHANNEL_6
8051 * @arg @ref LL_DMA_CHANNEL_7
8052 * @arg @ref LL_DMA_CHANNEL_8
8053 * @arg @ref LL_DMA_CHANNEL_9
8054 * @arg @ref LL_DMA_CHANNEL_10
8055 * @arg @ref LL_DMA_CHANNEL_11
8056 * @arg @ref LL_DMA_CHANNEL_12
8057 * @arg @ref LL_DMA_CHANNEL_13
8058 * @arg @ref LL_DMA_CHANNEL_14
8059 * @arg @ref LL_DMA_CHANNEL_15
8060 * @retval State of bit (1 or 0).
8061 */
LL_DMA_IsEnabledIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)8062 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
8063 {
8064 uint32_t dma_base_addr = (uint32_t)DMAx;
8065 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
8066 == DMA_CCR_TCIE) ? 1UL : 0UL);
8067 }
8068 /**
8069 * @}
8070 */
8071
8072 #if defined (USE_FULL_LL_DRIVER)
8073 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
8074 * @{
8075 */
8076 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
8077 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
8078
8079 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
8080 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
8081 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
8082
8083 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
8084 LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
8085 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
8086
8087 uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
8088 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
8089 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
8090 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
8091 /**
8092 * @}
8093 */
8094 #endif /* USE_FULL_LL_DRIVER */
8095
8096 /**
8097 * @}
8098 */
8099
8100 /**
8101 * @}
8102 */
8103
8104 #endif /* GPDMA1 || HPDMA1 */
8105
8106 /**
8107 * @}
8108 */
8109
8110 #ifdef __cplusplus
8111 }
8112 #endif /* __cplusplus */
8113
8114 #endif /* STM32N6xx_LL_DMA_H */
8115
8116
