1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32H5xx_LL_DMA_H
41 #define STM32H5xx_LL_DMA_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif /* __cplusplus */
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32h5xx.h"
49
50 /** @addtogroup STM32H5xx_LL_Driver
51 * @{
52 */
53
54 #if defined (GPDMA1)
55
56 /** @defgroup DMA_LL DMA
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62
63 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
64 * @{
65 */
66 #define DMA_CHANNEL0_OFFSET (0x00000050UL)
67 #define DMA_CHANNEL1_OFFSET (0x000000D0UL)
68 #define DMA_CHANNEL2_OFFSET (0x00000150UL)
69 #define DMA_CHANNEL3_OFFSET (0x000001D0UL)
70 #define DMA_CHANNEL4_OFFSET (0x00000250UL)
71 #define DMA_CHANNEL5_OFFSET (0x000002D0UL)
72 #define DMA_CHANNEL6_OFFSET (0x00000350UL)
73 #define DMA_CHANNEL7_OFFSET (0x000003D0UL)
74
75
76 /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
77 static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
78 {
79 DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
80 DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
81 };
82
83 /**
84 * @}
85 */
86
87 /* Private constants ---------------------------------------------------------*/
88 /* Private macros ------------------------------------------------------------*/
89 /* Exported types ------------------------------------------------------------*/
90
91 #if defined (USE_FULL_LL_DRIVER)
92 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
93 * @{
94 */
95
96 /**
97 * @brief LL DMA init structure definition.
98 */
99 typedef struct
100 {
101 uint32_t SrcAddress; /*!< This field specify the data transfer source address.
102 Programming this field is mandatory for all available DMA channels.
103 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
104 This feature can be modified afterwards using unitary function
105 @ref LL_DMA_SetSrcAddress(). */
106
107 uint32_t DestAddress; /*!< This field specify the data transfer destination address.
108 Programming this field is mandatory for all available DMA channels.
109 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
110 This feature can be modified afterwards using unitary function
111 @ref LL_DMA_SetDestAddress(). */
112
113 uint32_t Direction; /*!< This field specify the data transfer direction.
114 Programming this field is mandatory for all available DMA channels.
115 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
116 This feature can be modified afterwards using unitary function
117 @ref LL_DMA_SetDataTransferDirection(). */
118
119 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
120 Programming this field is mandatory for all available DMA channels.
121 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
122 This feature can be modified afterwards using unitary function
123 @ref LL_DMA_SetBlkHWRequest(). */
124
125 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
126 Programming this field is mandatory for all available DMA channels.
127 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
128 This feature can be modified afterwards using unitary function
129 @ref LL_DMA_SetDataAlignment(). */
130
131 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
132 Programming this field is mandatory for all available DMA channels.
133 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
134 This feature can be modified afterwards using unitary function
135 @ref LL_DMA_SetSrcBurstLength(). */
136
137 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
138 Programming this field is mandatory for all available DMA channels.
139 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
140 This feature can be modified afterwards using unitary function
141 @ref LL_DMA_SetDestBurstLength(). */
142
143 uint32_t SrcDataWidth; /*!< This field specify the source data width.
144 Programming this field is mandatory for all available DMA channels.
145 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
146 This feature can be modified afterwards using unitary function
147 @ref LL_DMA_SetSrcDataWidth(). */
148
149 uint32_t DestDataWidth; /*!< This field specify the destination data width.
150 Programming this field is mandatory for all available DMA channels.
151 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
152 This feature can be modified afterwards using unitary function
153 @ref LL_DMA_SetDestDataWidth(). */
154
155 uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
156 Programming this field is mandatory for all available DMA channels.
157 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
158 This feature can be modified afterwards using unitary function
159 @ref LL_DMA_SetSrcIncMode(). */
160
161 uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
162 Programming this field is mandatory for all available DMA channels.
163 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
164 This feature can be modified afterwards using unitary function
165 @ref LL_DMA_SetDestIncMode(). */
166
167 uint32_t Priority; /*!< This field specify the channel priority level.
168 Programming this field is mandatory for all available DMA channels.
169 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
170 This feature can be modified afterwards using unitary function
171 @ref LL_DMA_SetChannelPriorityLevel(). */
172
173 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
174 Programming this field is mandatory for all available DMA channels.
175 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
176 This feature can be modified afterwards using unitary function
177 @ref LL_DMA_SetBlkDataLength(). */
178
179 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
180 Programming this field is mandatory only for 2D addressing channels.
181 This parameter can be a value between 1 and 2048 Min_Data = 0
182 and Max_Data = 0x000007FF.
183 This feature can be modified afterwards using unitary function
184 @ref LL_DMA_SetBlkRptCount(). */
185
186 uint32_t TriggerMode; /*!< This field specify the trigger mode.
187 Programming this field is mandatory for all available DMA channels.
188 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
189 This feature can be modified afterwards using unitary function
190 @ref LL_DMA_SetTriggerMode(). */
191
192 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
193 Programming this field is mandatory for all available DMA channels.
194 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
195 This feature can be modified afterwards using unitary function
196 @ref LL_DMA_SetTriggerPolarity(). */
197
198 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
199 Programming this field is mandatory for all available DMA channels.
200 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
201 This feature can be modified afterwards using unitary function
202 @ref LL_DMA_SetHWTrigger(). */
203
204 uint32_t Request; /*!< This field specify the peripheral request selection.
205 Programming this field is mandatory for all available DMA channels.
206 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
207 This feature can be modified afterwards using unitary function
208 @ref LL_DMA_SetPeriphRequest(). */
209
210 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
211 Programming this field is mandatory for all available DMA channels.
212 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
213 This feature can be modified afterwards using unitary function
214 @ref LL_DMA_SetTransferEventMode(). */
215
216 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
217 Programming this field is mandatory for all available DMA channels.
218 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
219 This feature can be modified afterwards using unitary function
220 @ref LL_DMA_SetDestHWordExchange(). */
221
222 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
223 Programming this field is mandatory for all available DMA channels.
224 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
225 This feature can be modified afterwards using unitary function
226 @ref LL_DMA_SetDestByteExchange(). */
227
228 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
229 Programming this field is mandatory for all available DMA channels.
230 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
231 This feature can be modified afterwards using unitary function
232 @ref LL_DMA_SetSrcByteExchange(). */
233
234 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
235 Programming this field is mandatory for all available DMA channels.
236 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
237 This feature can be modified afterwards using unitary function
238 @ref LL_DMA_SetSrcAllocatedPort(). */
239
240 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
241 Programming this field is mandatory for all available DMA channels.
242 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
243 This feature can be modified afterwards using unitary function
244 @ref LL_DMA_SetDestAllocatedPort(). */
245
246 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
247 Programming this field is mandatory for all available DMA channels.
248 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
249 This feature can be modified afterwards using unitary function
250 @ref LL_DMA_SetLinkAllocatedPort(). */
251
252 uint32_t LinkStepMode; /*!< This field specify the link step mode.
253 Programming this field is mandatory for all available DMA channels.
254 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
255 This feature can be modified afterwards using unitary function
256 @ref LL_DMA_SetLinkStepMode(). */
257
258 uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode.
259 Programming this field is mandatory only for 2D addressing channels.
260 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.
261 This feature can be modified afterwards using unitary function
262 @ref LL_DMA_SetSrcAddrUpdate(). */
263
264 uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode.
265 Programming this field is mandatory only for 2D addressing channels.
266 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.
267 This feature can be modified afterwards using unitary function
268 @ref LL_DMA_SetDestAddrUpdate(). */
269
270 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
271 Programming this field is mandatory only for 2D addressing channels.
272 This parameter can be a value Between 0 to 0x00001FFF.
273 This feature can be modified afterwards using unitary function
274 @ref LL_DMA_SetSrcAddrUpdateValue(). */
275
276 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
277 Programming this field is mandatory only for 2D addressing channels.
278 This parameter can be a value Between 0 to 0x00001FFF.
279 This feature can be modified afterwards using unitary function
280 @ref LL_DMA_SetDestAddrUpdateValue(). */
281
282 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
283 Programming this field is mandatory only for 2D addressing channels.
284 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.
285 This feature can be modified afterwards using unitary function
286 @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */
287
288 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
289 Programming this field is mandatory only for 2D addressing channels.
290 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.
291 This feature can be modified afterwards using unitary function
292 @ref LL_DMA_SetBlkRptDestAddrUpdate(). */
293
294 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
295 Programming this field is mandatory only for 2D addressing channels.
296 This parameter can be a value Between 0 to 0x0000FFFF.
297 This feature can be modified afterwards using unitary function
298 @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */
299
300 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
301 Programming this field is mandatory only for 2D addressing channels.
302 This parameter can be a value Between 0 to 0x0000FFFF.
303 This feature can be modified afterwards using unitary function
304 @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */
305
306 uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
307 Programming this field is mandatory for all available DMA channels.
308 This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
309 bytes are always forced to 0).
310 This feature can be modified afterwards using unitary function
311 @ref LL_DMA_SetLinkedListBaseAddr(). */
312
313 uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
314 Programming this field is mandatory for all available DMA channels.
315 This parameter can be a value Between 0 to 0x0000FFFC.
316 This feature can be modified afterwards using unitary function
317 @ref LL_DMA_SetLinkedListAddrOffset(). */
318
319 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel.
320 This parameter can be a value of @ref DMA_LL_TRANSFER_MODE */
321 } LL_DMA_InitTypeDef;
322
323
324 /**
325 * @brief LL DMA init linked list structure definition.
326 */
327 typedef struct
328 {
329 uint32_t Priority; /*!< This field specify the channel priority level.
330 Programming this field is mandatory for all available DMA channels.
331 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
332 This feature can be modified afterwards using unitary function
333 @ref LL_DMA_SetChannelPriorityLevel(). */
334
335 uint32_t LinkStepMode; /*!< This field specify the link step mode.
336 Programming this field is mandatory for all available DMA channels.
337 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
338 This feature can be modified afterwards using unitary function
339 @ref LL_DMA_SetLinkStepMode(). */
340
341 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
342 Programming this field is mandatory for all available DMA channels.
343 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
344 This feature can be modified afterwards using unitary function
345 @ref LL_DMA_SetLinkAllocatedPort(). */
346
347 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
348 Programming this field is mandatory for all available DMA channels.
349 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
350 This feature can be modified afterwards using unitary function
351 @ref LL_DMA_SetTransferEventMode(). */
352 } LL_DMA_InitLinkedListTypeDef;
353
354
355 /**
356 * @brief LL DMA node init structure definition.
357 */
358 typedef struct
359 {
360 /* CTR1 register fields ******************************************************
361 If any CTR1 fields need to be updated comparing to previous node, it is
362 mandatory to update the new value in CTR1 register fields and enable update
363 CTR1 register in UpdateRegisters fields if it is not enabled in the
364 previous node.
365
366 */
367 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
368 uint32_t DestSecure; /*!< This field specify the destination secure.
369 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
370 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
371
372 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
373 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
374
375 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
376 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
377
378 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
379 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
380
381 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
382 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
383
384 uint32_t DestIncMode; /*!< This field specify the destination increment mode.
385 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
386
387 uint32_t DestDataWidth; /*!< This field specify the destination data width.
388 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
389
390 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
391 uint32_t SrcSecure; /*!< This field specify the source secure.
392 This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */
393 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
394
395 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
396 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
397
398 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
399 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
400
401 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
402 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
403
404 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
405 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
406
407 uint32_t SrcIncMode; /*!< This field specify the source increment mode.
408 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
409
410 uint32_t SrcDataWidth; /*!< This field specify the source data width.
411 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
412
413
414 /* CTR2 register fields ******************************************************
415 If any CTR2 fields need to be updated comparing to previous node, it is
416 mandatory to update the new value in CTR2 register fields and enable update
417 CTR2 register in UpdateRegisters fields if it is not enabled in the
418 previous node.
419
420 For all node created, filling all fields is mandatory.
421 */
422 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
423 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
424
425 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
426 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
427
428 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
429 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
430
431 uint32_t TriggerMode; /*!< This field specify the trigger mode.
432 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
433
434 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
435 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
436
437 uint32_t Direction; /*!< This field specify the transfer direction.
438 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
439
440 uint32_t Request; /*!< This field specify the peripheral request selection.
441 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
442
443 uint32_t Mode; /*!< This field DMA Transfer Mode.
444 This parameter can be a value of @ref DMA_LL_TRANSFER_MODE. */
445
446 /* CBR1 register fields ******************************************************
447 If any CBR1 fields need to be updated comparing to previous node, it is
448 mandatory to update the new value in CBR1 register fields and enable update
449 CBR1 register in UpdateRegisters fields if it is not enabled in the
450 previous node.
451
452 If the node to be created is not for 2D addressing channels, there is no
453 need to fill the following fields for CBR1 register :
454 - BlkReptDestAddrUpdate.
455 - BlkRptSrcAddrUpdate.
456 - DestAddrUpdate.
457 - SrcAddrUpdate.
458 - BlkRptCount.
459 */
460 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
461 This parameter can be a value of
462 @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */
463
464 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
465 This parameter can be a value of
466 @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */
467
468 uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode.
469 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */
470
471 uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode.
472 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */
473
474 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
475 This parameter can be a value between 1 and 2048 Min_Data = 0
476 and Max_Data = 0x000007FF. */
477
478 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
479 This parameter must be a value between Min_Data = 0
480 and Max_Data = 0x0000FFFF. */
481
482 /* CSAR register fields ******************************************************
483 If any CSAR fields need to be updated comparing to previous node, it is
484 mandatory to update the new value in CSAR register fields and enable update
485 CSAR register in UpdateRegisters fields if it is not enabled in the
486 previous node.
487
488 For all node created, filling all fields is mandatory.
489 */
490 uint32_t SrcAddress; /*!< This field specify the transfer source address.
491 This parameter must be a value between Min_Data = 0
492 and Max_Data = 0xFFFFFFFF. */
493
494
495 /* CDAR register fields ******************************************************
496 If any CDAR fields need to be updated comparing to previous node, it is
497 mandatory to update the new value in CDAR register fields and enable update
498 CDAR register in UpdateRegisters fields if it is not enabled in the
499 previous node.
500
501 For all node created, filling all fields is mandatory.
502 */
503 uint32_t DestAddress; /*!< This field specify the transfer destination address.
504 This parameter must be a value between Min_Data = 0
505 and Max_Data = 0xFFFFFFFF. */
506
507 /* CTR3 register fields ******************************************************
508 If any CTR3 fields need to be updated comparing to previous node, it is
509 mandatory to update the new value in CTR3 register fields and enable update
510 CTR3 register in UpdateRegisters fields if it is not enabled in the
511 previous node.
512
513 This register is used only for 2D addressing channels.
514 If used channel is linear addressing, this register will be overwritten by
515 CLLR register in memory.
516 When this register is enabled on UpdateRegisters and the selected channel
517 is linear addressing, LL APIs will discard this register update in memory.
518 */
519 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
520 This parameter can be a value Between 0 to 0x00001FFF. */
521
522 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
523 This parameter can be a value Between 0 to 0x00001FFF. */
524
525
526 /* CBR2 register fields ******************************************************
527 If any CBR2 fields need to be updated comparing to previous node, it is
528 mandatory to update the new value in CBR2 register fields and enable update
529 CBR2 register in UpdateRegisters fields if it is not enabled in the
530 previous node.
531
532 This register is used only for 2D addressing channels.
533 If used channel is linear addressing, this register will be discarded in
534 memory. When this register is enabled on UpdateRegisters and the selected
535 channel is linear addressing, LL APIs will discard this register update in
536 memory.
537 */
538 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
539 This parameter can be a value Between 0 to 0x0000FFFF. */
540
541 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
542 This parameter can be a value Between 0 to 0x0000FFFF. */
543
544 /* CLLR register fields ******************************************************
545 If any CLLR fields need to be updated comparing to previous node, it is
546 mandatory to update the new value in CLLR register fields and enable update
547 CLLR register in UpdateRegisters fields if it is not enabled in the
548 previous node.
549
550 If used channel is linear addressing, there is no need to enable/disable
551 CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded
552 by LL APIs.
553 */
554 uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
555 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
556
557 /* DMA Node type field *******************************************************
558 This parameter defines node types as node size and node content varies
559 between channels.
560 Thanks to this fields, linked list queue could be created independently
561 from channel selection. So, one queue could be executed by all DMA channels.
562 */
563 uint32_t NodeType; /*!< Specifies the node type to be created.
564 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
565 } LL_DMA_InitNodeTypeDef;
566
567 /**
568 * @brief LL DMA linked list node structure definition.
569 * @note For 2D addressing channels, the maximum node size is :
570 * (4 Bytes * 8 registers = 32 Bytes).
571 * For GPDMA linear addressing channels, the maximum node size is :
572 * (4 Bytes * 6 registers = 24 Bytes).
573 */
574 typedef struct
575 {
576 __IO uint32_t LinkRegisters[8U];
577
578 } LL_DMA_LinkNodeTypeDef;
579 /**
580 * @}
581 */
582
583 #endif /* USE_FULL_LL_DRIVER */
584
585 /* Exported constants --------------------------------------------------------*/
586
587 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
588 * @{
589 */
590
591 /** @defgroup DMA_LL_EC_CHANNEL Channel
592 * @{
593 */
594 #define LL_DMA_CHANNEL_0 (0x00U)
595 #define LL_DMA_CHANNEL_1 (0x01U)
596 #define LL_DMA_CHANNEL_2 (0x02U)
597 #define LL_DMA_CHANNEL_3 (0x03U)
598 #define LL_DMA_CHANNEL_4 (0x04U)
599 #define LL_DMA_CHANNEL_5 (0x05U)
600 #define LL_DMA_CHANNEL_6 (0x06U)
601 #define LL_DMA_CHANNEL_7 (0x07U)
602 #define LL_DMA_CHANNEL_8 (0x08U)
603 #define LL_DMA_CHANNEL_9 (0x09U)
604 #define LL_DMA_CHANNEL_10 (0x0AU)
605 #define LL_DMA_CHANNEL_11 (0x0BU)
606 #define LL_DMA_CHANNEL_12 (0x0CU)
607 #define LL_DMA_CHANNEL_13 (0x0DU)
608 #define LL_DMA_CHANNEL_14 (0x0EU)
609 #define LL_DMA_CHANNEL_15 (0x0FU)
610 #if defined (USE_FULL_LL_DRIVER)
611 #define LL_DMA_CHANNEL_ALL (0x10U)
612 #endif /* USE_FULL_LL_DRIVER */
613 /**
614 * @}
615 */
616
617 #if defined (USE_FULL_LL_DRIVER)
618 /** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
619 * @{
620 */
621 #define LL_DMA_CLLR_OFFSET0 (0x00U)
622 #define LL_DMA_CLLR_OFFSET1 (0x01U)
623 #define LL_DMA_CLLR_OFFSET2 (0x02U)
624 #define LL_DMA_CLLR_OFFSET3 (0x03U)
625 #define LL_DMA_CLLR_OFFSET4 (0x04U)
626 #define LL_DMA_CLLR_OFFSET5 (0x05U)
627 #define LL_DMA_CLLR_OFFSET6 (0x06U)
628 #define LL_DMA_CLLR_OFFSET7 (0x07U)
629 /**
630 * @}
631 */
632 #endif /* USE_FULL_LL_DRIVER */
633
634 /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level
635 * @{
636 */
637 #define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
638 #define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
639 #define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
640 #define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
641 /**
642 * @}
643 */
644
645 /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
646 * @{
647 */
648 #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
649 #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
650 /**
651 * @}
652 */
653
654 /** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
655 * @{
656 */
657 #define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
658 #define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
659 /**
660 * @}
661 */
662
663 /** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
664 * @{
665 */
666 #define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width
667 is word */
668 #define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width
669 is word */
670 /**
671 * @}
672 */
673
674 /** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
675 * @{
676 */
677 #define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
678 #define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
679 /**
680 * @}
681 */
682
683 /** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
684 * @{
685 */
686 #define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
687 #define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
688 /**
689 * @}
690 */
691
692 /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
693 * @{
694 */
695 #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
696 #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
697 /**
698 * @}
699 */
700
701 /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
702 * @{
703 */
704 #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
705 #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
706 /**
707 * @}
708 */
709
710 /** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
711 * @{
712 */
713 #define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
714 #define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
715 /**
716 * @}
717 */
718
719 /** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
720 * @{
721 */
722 #define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
723 #define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
724 #define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
725 /**
726 * @}
727 */
728
729 /** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
730 * @{
731 */
732 #define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
733 => Right Aligned padded with 0 up to destination
734 data width.
735 If src data width > dest data width :
736 => Right Aligned Left Truncated down to destination
737 data width. */
738 #define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
739 => Right Aligned padded with sign extended up to destination
740 data width.
741 If src data width > dest data width :
742 => Left Aligned Right Truncated down to the destination
743 data width */
744 #define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
745 => Packed at the destination data width
746 If src data width > dest data width :
747 => Unpacked at the destination data width */
748 /**
749 * @}
750 */
751
752 /** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
753 * @{
754 */
755 #define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
756 #define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
757 /**
758 * @}
759 */
760
761 /** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
762 * @{
763 */
764 #define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
765 #define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
766 #define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
767 /**
768 * @}
769 */
770
771 /** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
772 * @{
773 */
774 #define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
775 request/acknowledge protocol at a burst level */
776 #define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
777 request/acknowledge protocol at a block level */
778 /**
779 * @}
780 */
781
782 /** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
783 * @{
784 */
785 #define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
786 (respectively half) end of each block */
787 #define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
788 (respectively half) end of the repeated block */
789 #define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
790 (respectively half) end of each linked-list item */
791 #define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
792 (respectively half) end of the last linked-list item */
793 /**
794 * @}
795 */
796
797 /** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
798 * @{
799 */
800 #define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
801 Masked trigger event */
802 #define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
803 edge of the selected trigger event input */
804 #define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
805 edge of the selected trigger event input */
806 /**
807 * @}
808 */
809
810 /** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
811 * @{
812 */
813 #define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
814 one hit trigger */
815 #define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
816 one hit trigger */
817 #define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
818 one hit trigger */
819 #define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
820 one hit trigger */
821 /**
822 * @}
823 */
824
825 /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
826 * @{
827 */
828 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
829 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
830 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
831 /**
832 * @}
833 */
834
835 /** @defgroup DMA_LL_TRANSFER_MODE Transfer Mode
836 * @{
837 */
838 #define LL_DMA_NORMAL 0x00000000U /*!< Normal DMA transfer */
839 #define LL_DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */
840 /**
841 * @}
842 */
843
844 /** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode
845 * @{
846 */
847 #define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block
848 transfer by source update value */
849 #define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block
850 transfer by source update value */
851 /**
852 * @}
853 */
854
855 /** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode
856 * @{
857 */
858 #define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block
859 transfer by destination update value */
860 #define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block
861 transfer by destination update value */
862 /**
863 * @}
864 */
865
866 /** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode
867 * @{
868 */
869 #define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst
870 transfer by source update value */
871 #define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst
872 transfer by source update value */
873 /**
874 * @}
875 */
876
877 /** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode
878 * @{
879 */
880 #define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each
881 burst transfer by destination update value */
882 #define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each
883 burst transfer by destination update value */
884 /**
885 * @}
886 */
887
888 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
889 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
890 * @{
891 */
892 #define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
893 #define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */
894 /**
895 * @}
896 */
897
898 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
899 * @{
900 */
901 #define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */
902 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
903 /**
904 * @}
905 */
906
907 /** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
908 * @{
909 */
910 #define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */
911 #define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */
912 /**
913 * @}
914 */
915 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
916
917 /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
918 * @{
919 */
920 #define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
921 #define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */
922
923 /**
924 * @}
925 */
926
927 /** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
928 * @{
929 */
930 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
931 available for all DMA channels */
932 #define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
933 available for all DMA channels */
934 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
935 available for all DMA channels */
936 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
937 available for all DMA channels */
938 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
939 available for all DMA channels */
940 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
941 available only for 2D addressing DMA channels */
942 #define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory :
943 available only for 2D addressing DMA channels */
944 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
945 available for all DMA channels */
946 /**
947 * @}
948 */
949
950 /** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
951 * @{
952 */
953 /* GPDMA1 Hardware Requests */
954 #define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */
955 #if defined (ADC2)
956 #define LL_GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */
957 #endif /* ADC2 */
958 #define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */
959 #define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */
960 #define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */
961 #define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */
962 #define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */
963 #define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */
964 #define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */
965 #define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */
966 #define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */
967 #define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */
968 #define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */
969 #define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */
970 #define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */
971 #define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */
972 #if defined (I2C3)
973 #define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */
974 #define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */
975 #endif /* I2C3 */
976 #define LL_GPDMA1_REQUEST_USART1_RX 21U /*!< GPDMA1 HW request is USART1_RX */
977 #define LL_GPDMA1_REQUEST_USART1_TX 22U /*!< GPDMA1 HW request is USART1_TX */
978 #define LL_GPDMA1_REQUEST_USART2_RX 23U /*!< GPDMA1 HW request is USART2_RX */
979 #define LL_GPDMA1_REQUEST_USART2_TX 24U /*!< GPDMA1 HW request is USART2_TX */
980 #define LL_GPDMA1_REQUEST_USART3_RX 25U /*!< GPDMA1 HW request is USART3_RX */
981 #define LL_GPDMA1_REQUEST_USART3_TX 26U /*!< GPDMA1 HW request is USART3_TX */
982 #if defined (UART4)
983 #define LL_GPDMA1_REQUEST_UART4_RX 27U /*!< GPDMA1 HW request is UART4_RX */
984 #define LL_GPDMA1_REQUEST_UART4_TX 28U /*!< GPDMA1 HW request is UART4_TX */
985 #endif /* UART4 */
986 #if defined (UART4)
987 #define LL_GPDMA1_REQUEST_UART5_RX 29U /*!< GPDMA1 HW request is UART5_RX */
988 #define LL_GPDMA1_REQUEST_UART5_TX 30U /*!< GPDMA1 HW request is UART5_TX */
989 #endif /* UART5 */
990 #if defined (UART4)
991 #define LL_GPDMA1_REQUEST_USART6_RX 31U /*!< GPDMA1 HW request is USART6_RX */
992 #define LL_GPDMA1_REQUEST_USART6_TX 32U /*!< GPDMA1 HW request is USART6_TX */
993 #endif /* USART6 */
994 #if defined (UART7)
995 #define LL_GPDMA1_REQUEST_UART7_RX 33U /*!< GPDMA1 HW request is UART7_RX */
996 #define LL_GPDMA1_REQUEST_UART7_TX 34U /*!< GPDMA1 HW request is UART7_TX */
997 #endif /* UART7 */
998 #if defined (UART8)
999 #define LL_GPDMA1_REQUEST_UART8_RX 35U /*!< GPDMA1 HW request is UART8_RX */
1000 #define LL_GPDMA1_REQUEST_UART8_TX 36U /*!< GPDMA1 HW request is UART8_TX */
1001 #endif /* UART8 */
1002 #if defined (UART9)
1003 #define LL_GPDMA1_REQUEST_UART9_RX 37U /*!< GPDMA1 HW request is UART9_RX */
1004 #define LL_GPDMA1_REQUEST_UART9_TX 38U /*!< GPDMA1 HW request is UART9_TX */
1005 #endif /* UART9 */
1006 #if defined (USART10)
1007 #define LL_GPDMA1_REQUEST_USART10_RX 39U /*!< GPDMA1 HW request is USART10_RX */
1008 #define LL_GPDMA1_REQUEST_USART10_TX 40U /*!< GPDMA1 HW request is USART10_TX */
1009 #endif /* USART10 */
1010 #if defined (USART11)
1011 #define LL_GPDMA1_REQUEST_USART11_RX 41U /*!< GPDMA1 HW request is USART11_RX */
1012 #define LL_GPDMA1_REQUEST_USART11_TX 42U /*!< GPDMA1 HW request is USART11_TX */
1013 #endif /* USART11 */
1014 #if defined (UART12)
1015 #define LL_GPDMA1_REQUEST_UART12_RX 43U /*!< GPDMA1 HW request is UART12_RX */
1016 #define LL_GPDMA1_REQUEST_UART12_TX 44U /*!< GPDMA1 HW request is UART12_TX */
1017 #endif /* UART12 */
1018 #define LL_GPDMA1_REQUEST_LPUART1_RX 45U /*!< GPDMA1 HW request is LPUART1_RX */
1019 #define LL_GPDMA1_REQUEST_LPUART1_TX 46U /*!< GPDMA1 HW request is LPUART1_TX */
1020 #if defined (SPI4)
1021 #define LL_GPDMA1_REQUEST_SPI4_RX 47U /*!< GPDMA1 HW request is SPI4_RX */
1022 #define LL_GPDMA1_REQUEST_SPI4_TX 48U /*!< GPDMA1 HW request is SPI4_TX */
1023 #endif /* SPI4 */
1024 #if defined (SPI5)
1025 #define LL_GPDMA1_REQUEST_SPI5_RX 49U /*!< GPDMA1 HW request is SPI5_RX */
1026 #define LL_GPDMA1_REQUEST_SPI5_TX 50U /*!< GPDMA1 HW request is SPI5_TX */
1027 #endif /* SPI5 */
1028 #if defined (SPI6)
1029 #define LL_GPDMA1_REQUEST_SPI6_RX 51U /*!< GPDMA1 HW request is SPI6_RX */
1030 #define LL_GPDMA1_REQUEST_SPI6_TX 52U /*!< GPDMA1 HW request is SPI6_TX */
1031 #endif /* SPI6 */
1032 #if defined (SAI1)
1033 #define LL_GPDMA1_REQUEST_SAI1_A 53U /*!< GPDMA1 HW request is SAI1_A */
1034 #define LL_GPDMA1_REQUEST_SAI1_B 54U /*!< GPDMA1 HW request is SAI1_B */
1035 #endif /* SAI1 */
1036 #if defined (SAI2)
1037 #define LL_GPDMA1_REQUEST_SAI2_A 55U /*!< GPDMA1 HW request is SAI2_A */
1038 #define LL_GPDMA1_REQUEST_SAI2_B 56U /*!< GPDMA1 HW request is SAI2_B */
1039 #endif /* SAI2 */
1040 #if defined (OCTOSPI1)
1041 #define LL_GPDMA1_REQUEST_OCTOSPI1 57U /*!< GPDMA1 HW request is OCTOSPI1 */
1042 #endif /* OCTOSPI1 */
1043 #define LL_GPDMA1_REQUEST_TIM1_CH1 58U /*!< GPDMA1 HW request is TIM1_CH1 */
1044 #define LL_GPDMA1_REQUEST_TIM1_CH2 59U /*!< GPDMA1 HW request is TIM1_CH2 */
1045 #define LL_GPDMA1_REQUEST_TIM1_CH3 60U /*!< GPDMA1 HW request is TIM1_CH3 */
1046 #define LL_GPDMA1_REQUEST_TIM1_CH4 61U /*!< GPDMA1 HW request is TIM1_CH4 */
1047 #define LL_GPDMA1_REQUEST_TIM1_UP 62U /*!< GPDMA1 HW request is TIM1_UP */
1048 #define LL_GPDMA1_REQUEST_TIM1_TRIG 63U /*!< GPDMA1 HW request is TIM1_TRIG */
1049 #define LL_GPDMA1_REQUEST_TIM1_COM 64U /*!< GPDMA1 HW request is TIM1_COM */
1050 #if defined (TIM8)
1051 #define LL_GPDMA1_REQUEST_TIM8_CH1 65U /*!< GPDMA1 HW request is TIM8_CH1 */
1052 #define LL_GPDMA1_REQUEST_TIM8_CH2 66U /*!< GPDMA1 HW request is TIM8_CH2 */
1053 #define LL_GPDMA1_REQUEST_TIM8_CH3 67U /*!< GPDMA1 HW request is TIM8_CH3 */
1054 #define LL_GPDMA1_REQUEST_TIM8_CH4 68U /*!< GPDMA1 HW request is TIM8_CH4 */
1055 #define LL_GPDMA1_REQUEST_TIM8_UP 69U /*!< GPDMA1 HW request is TIM8_UP */
1056 #define LL_GPDMA1_REQUEST_TIM8_TRIG 70U /*!< GPDMA1 HW request is TIM8_TRIG */
1057 #define LL_GPDMA1_REQUEST_TIM8_COM 71U /*!< GPDMA1 HW request is TIM8_COM */
1058 #endif /* TIM8 */
1059 #define LL_GPDMA1_REQUEST_TIM2_CH1 72U /*!< GPDMA1 HW request is TIM2_CH1 */
1060 #define LL_GPDMA1_REQUEST_TIM2_CH2 73U /*!< GPDMA1 HW request is TIM2_CH2 */
1061 #define LL_GPDMA1_REQUEST_TIM2_CH3 74U /*!< GPDMA1 HW request is TIM2_CH3 */
1062 #define LL_GPDMA1_REQUEST_TIM2_CH4 75U /*!< GPDMA1 HW request is TIM2_CH4 */
1063 #define LL_GPDMA1_REQUEST_TIM2_UP 76U /*!< GPDMA1 HW request is TIM2_UP */
1064 #define LL_GPDMA1_REQUEST_TIM3_CH1 77U /*!< GPDMA1 HW request is TIM3_CH1 */
1065 #define LL_GPDMA1_REQUEST_TIM3_CH2 78U /*!< GPDMA1 HW request is TIM3_CH2 */
1066 #define LL_GPDMA1_REQUEST_TIM3_CH3 79U /*!< GPDMA1 HW request is TIM3_CH3 */
1067 #define LL_GPDMA1_REQUEST_TIM3_CH4 80U /*!< GPDMA1 HW request is TIM3_CH4 */
1068 #define LL_GPDMA1_REQUEST_TIM3_UP 81U /*!< GPDMA1 HW request is TIM3_UP */
1069 #define LL_GPDMA1_REQUEST_TIM3_TRIG 82U /*!< GPDMA1 HW request is TIM3_TRIG */
1070 #if defined (TIM4)
1071 #define LL_GPDMA1_REQUEST_TIM4_CH1 83U /*!< GPDMA1 HW request is TIM4_CH1 */
1072 #define LL_GPDMA1_REQUEST_TIM4_CH2 84U /*!< GPDMA1 HW request is TIM4_CH2 */
1073 #define LL_GPDMA1_REQUEST_TIM4_CH3 85U /*!< GPDMA1 HW request is TIM4_CH3 */
1074 #define LL_GPDMA1_REQUEST_TIM4_CH4 86U /*!< GPDMA1 HW request is TIM4_CH4 */
1075 #define LL_GPDMA1_REQUEST_TIM4_UP 87U /*!< GPDMA1 HW request is TIM4_UP */
1076 #endif /* TIM4 */
1077 #if defined (TIM5)
1078 #define LL_GPDMA1_REQUEST_TIM5_CH1 88U /*!< GPDMA1 HW request is TIM5_CH1 */
1079 #define LL_GPDMA1_REQUEST_TIM5_CH2 89U /*!< GPDMA1 HW request is TIM5_CH2 */
1080 #define LL_GPDMA1_REQUEST_TIM5_CH3 90U /*!< GPDMA1 HW request is TIM5_CH3 */
1081 #define LL_GPDMA1_REQUEST_TIM5_CH4 91U /*!< GPDMA1 HW request is TIM5_CH4 */
1082 #define LL_GPDMA1_REQUEST_TIM5_UP 92U /*!< GPDMA1 HW request is TIM5_UP */
1083 #define LL_GPDMA1_REQUEST_TIM5_TRIG 93U /*!< GPDMA1 HW request is TIM5_TRIG */
1084 #endif /* TIM5 */
1085 #if defined (TIM15)
1086 #define LL_GPDMA1_REQUEST_TIM15_CH1 94U /*!< GPDMA1 HW request is TIM15_CH1 */
1087 #define LL_GPDMA1_REQUEST_TIM15_UP 95U /*!< GPDMA1 HW request is TIM15_UP */
1088 #define LL_GPDMA1_REQUEST_TIM15_TRIG 96U /*!< GPDMA1 HW request is TIM15_TRIG */
1089 #define LL_GPDMA1_REQUEST_TIM15_COM 97U /*!< GPDMA1 HW request is TIM15_COM */
1090 #endif /* TIM15 */
1091 #if defined (TIM16)
1092 #define LL_GPDMA1_REQUEST_TIM16_CH1 98U /*!< GPDMA1 HW request is TIM16_CH1 */
1093 #define LL_GPDMA1_REQUEST_TIM16_UP 99U /*!< GPDMA1 HW request is TIM16_UP */
1094 #endif /* TIM16 */
1095 #if defined (TIM17)
1096 #define LL_GPDMA1_REQUEST_TIM17_CH1 100U /*!< GPDMA1 HW request is TIM17_CH1 */
1097 #define LL_GPDMA1_REQUEST_TIM17_UP 101U /*!< GPDMA1 HW request is TIM17_UP */
1098 #endif /* TIM17 */
1099 #define LL_GPDMA1_REQUEST_LPTIM1_IC1 102U /*!< GPDMA1 HW request is LPTIM1_IC1 */
1100 #define LL_GPDMA1_REQUEST_LPTIM1_IC2 103U /*!< GPDMA1 HW request is LPTIM1_IC2 */
1101 #define LL_GPDMA1_REQUEST_LPTIM1_UE 104U /*!< GPDMA1 HW request is LPTIM1_UE */
1102 #define LL_GPDMA1_REQUEST_LPTIM2_IC1 105U /*!< GPDMA1 HW request is LPTIM2_IC1 */
1103 #define LL_GPDMA1_REQUEST_LPTIM2_IC2 106U /*!< GPDMA1 HW request is LPTIM2_IC2 */
1104 #define LL_GPDMA1_REQUEST_LPTIM2_UE 107U /*!< GPDMA1 HW request is LPTIM2_UE */
1105 #if defined (DCMI)
1106 #define LL_GPDMA1_REQUEST_DCMI 108U /*!< GPDMA1 HW request is DCMI */
1107 #endif /* DCMI */
1108 #if defined (AES)
1109 #define LL_GPDMA1_REQUEST_AES_OUT 109U /*!< GPDMA1 HW request is AES_OUT */
1110 #define LL_GPDMA1_REQUEST_AES_IN 110U /*!< GPDMA1 HW request is AES_IN */
1111 #endif /* AES */
1112 #define LL_GPDMA1_REQUEST_HASH_IN 111U /*!< GPDMA1 HW request is HASH_IN */
1113 #if defined (UCPD1)
1114 #define LL_GPDMA1_REQUEST_UCPD1_RX 112U /*!< GPDMA1 HW request is UCPD1_RX */
1115 #define LL_GPDMA1_REQUEST_UCPD1_TX 113U /*!< GPDMA1 HW request is UCPD1_TX */
1116 #endif /* UCPD1 */
1117 #if defined (CORDIC)
1118 #define LL_GPDMA1_REQUEST_CORDIC_READ 114U /*!< GPDMA1 HW request is CORDIC_READ */
1119 #define LL_GPDMA1_REQUEST_CORDIC_WRITE 115U /*!< GPDMA1 HW request is CORDIC_WRITE */
1120 #endif /* CORDIC */
1121 #if defined (FMAC)
1122 #define LL_GPDMA1_REQUEST_FMAC_READ 116U /*!< GPDMA1 HW request is FMAC_READ */
1123 #define LL_GPDMA1_REQUEST_FMAC_WRITE 117U /*!< GPDMA1 HW request is FMAC_WRITE */
1124 #endif /* FMAC */
1125 #if defined (SAES)
1126 #define LL_GPDMA1_REQUEST_SAES_OUT 118U /*!< GPDMA1 HW request is SAES_OUT */
1127 #define LL_GPDMA1_REQUEST_SAES_IN 119U /*!< GPDMA1 HW request is SAES_IN */
1128 #endif /* SAES */
1129 #define LL_GPDMA1_REQUEST_I3C1_RX 120U /*!< GPDMA1 HW request is I3C1_RX */
1130 #define LL_GPDMA1_REQUEST_I3C1_TX 121U /*!< GPDMA1 HW request is I3C1_TX */
1131 #define LL_GPDMA1_REQUEST_I3C1_TC 122U /*!< GPDMA1 HW request is I3C1_TC */
1132 #define LL_GPDMA1_REQUEST_I3C1_RS 123U /*!< GPDMA1 HW request is I3C1_RS */
1133 #if defined (I2C4)
1134 #define LL_GPDMA1_REQUEST_I2C4_RX 124U /*!< GPDMA1 HW request is I2C4_RX */
1135 #define LL_GPDMA1_REQUEST_I2C4_TX 125U /*!< GPDMA1 HW request is I2C4_TX */
1136 #endif /* I2C4 */
1137 #if defined (LPTIM3)
1138 #define LL_GPDMA1_REQUEST_LPTIM3_IC1 127U /*!< GPDMA1 HW request is LPTIM3_IC1 */
1139 #define LL_GPDMA1_REQUEST_LPTIM3_IC2 128U /*!< GPDMA1 HW request is LPTIM3_IC2 */
1140 #define LL_GPDMA1_REQUEST_LPTIM3_UE 129U /*!< GPDMA1 HW request is LPTIM3_UE */
1141 #endif /* LPTIM3 */
1142 #if defined (LPTIM5)
1143 #define LL_GPDMA1_REQUEST_LPTIM5_IC1 130U /*!< GPDMA1 HW request is LPTIM5_IC1 */
1144 #define LL_GPDMA1_REQUEST_LPTIM5_IC2 131U /*!< GPDMA1 HW request is LPTIM5_IC2 */
1145 #define LL_GPDMA1_REQUEST_LPTIM5_UE 132U /*!< GPDMA1 HW request is LPTIM5_UE */
1146 #endif /* LPTIM5 */
1147 #if defined (LPTIM6)
1148 #define LL_GPDMA1_REQUEST_LPTIM6_IC1 133U /*!< GPDMA1 HW request is LPTIM6_IC1 */
1149 #define LL_GPDMA1_REQUEST_LPTIM6_IC2 134U /*!< GPDMA1 HW request is LPTIM6_IC2 */
1150 #define LL_GPDMA1_REQUEST_LPTIM6_UE 135U /*!< GPDMA1 HW request is LPTIM6_UE */
1151 #endif /* LPTIM6 */
1152 #if defined (I3C2)
1153 #define LL_GPDMA1_REQUEST_I3C2_RX 136U /*!< GPDMA1 HW request is I3C2_RX */
1154 #define LL_GPDMA1_REQUEST_I3C2_TX 137U /*!< GPDMA1 HW request is I3C2_TX */
1155 #define LL_GPDMA1_REQUEST_I3C2_TC 138U /*!< GPDMA1 HW request is I3C2_TC */
1156 #define LL_GPDMA1_REQUEST_I3C2_RS 139U /*!< GPDMA1 HW request is I3C2_RS */
1157 #endif /* I3C2 */
1158
1159 /* GPDMA2 Hardware Requests */
1160 #define LL_GPDMA2_REQUEST_ADC1 0U /*!< GPDMA2 HW request is ADC1 */
1161 #if defined (ADC2)
1162 #define LL_GPDMA2_REQUEST_ADC2 1U /*!< GPDMA2 HW request is ADC2 */
1163 #endif /* ADC2 */
1164 #define LL_GPDMA2_REQUEST_DAC1_CH1 2U /*!< GPDMA2 HW request is DAC1_CH1 */
1165 #define LL_GPDMA2_REQUEST_DAC1_CH2 3U /*!< GPDMA2 HW request is DAC1_CH2 */
1166 #define LL_GPDMA2_REQUEST_TIM6_UP 4U /*!< GPDMA2 HW request is TIM6_UP */
1167 #define LL_GPDMA2_REQUEST_TIM7_UP 5U /*!< GPDMA2 HW request is TIM7_UP */
1168 #define LL_GPDMA2_REQUEST_SPI1_RX 6U /*!< GPDMA2 HW request is SPI1_RX */
1169 #define LL_GPDMA2_REQUEST_SPI1_TX 7U /*!< GPDMA2 HW request is SPI1_TX */
1170 #define LL_GPDMA2_REQUEST_SPI2_RX 8U /*!< GPDMA2 HW request is SPI2_RX */
1171 #define LL_GPDMA2_REQUEST_SPI2_TX 9U /*!< GPDMA2 HW request is SPI2_TX */
1172 #define LL_GPDMA2_REQUEST_SPI3_RX 10U /*!< GPDMA2 HW request is SPI3_RX */
1173 #define LL_GPDMA2_REQUEST_SPI3_TX 11U /*!< GPDMA2 HW request is SPI3_TX */
1174 #define LL_GPDMA2_REQUEST_I2C1_RX 12U /*!< GPDMA2 HW request is I2C1_RX */
1175 #define LL_GPDMA2_REQUEST_I2C1_TX 13U /*!< GPDMA2 HW request is I2C1_TX */
1176 #define LL_GPDMA2_REQUEST_I2C2_RX 15U /*!< GPDMA2 HW request is I2C2_RX */
1177 #define LL_GPDMA2_REQUEST_I2C2_TX 16U /*!< GPDMA2 HW request is I2C2_TX */
1178 #if defined (I2C3)
1179 #define LL_GPDMA2_REQUEST_I2C3_RX 18U /*!< GPDMA2 HW request is I2C3_RX */
1180 #define LL_GPDMA2_REQUEST_I2C3_TX 19U /*!< GPDMA2 HW request is I2C3_TX */
1181 #endif /* I2C3 */
1182 #define LL_GPDMA2_REQUEST_USART1_RX 21U /*!< GPDMA2 HW request is USART1_RX */
1183 #define LL_GPDMA2_REQUEST_USART1_TX 22U /*!< GPDMA2 HW request is USART1_TX */
1184 #define LL_GPDMA2_REQUEST_USART2_RX 23U /*!< GPDMA2 HW request is USART2_RX */
1185 #define LL_GPDMA2_REQUEST_USART2_TX 24U /*!< GPDMA2 HW request is USART2_TX */
1186 #define LL_GPDMA2_REQUEST_USART3_RX 25U /*!< GPDMA2 HW request is USART3_RX */
1187 #define LL_GPDMA2_REQUEST_USART3_TX 26U /*!< GPDMA2 HW request is USART3_TX */
1188 #if defined (UART4)
1189 #define LL_GPDMA2_REQUEST_UART4_RX 27U /*!< GPDMA2 HW request is UART4_RX */
1190 #define LL_GPDMA2_REQUEST_UART4_TX 28U /*!< GPDMA2 HW request is UART4_TX */
1191 #endif /* UART4 */
1192 #if defined (UART4)
1193 #define LL_GPDMA2_REQUEST_UART5_RX 29U /*!< GPDMA2 HW request is UART5_RX */
1194 #define LL_GPDMA2_REQUEST_UART5_TX 30U /*!< GPDMA2 HW request is UART5_TX */
1195 #endif /* UART5 */
1196 #if defined (UART4)
1197 #define LL_GPDMA2_REQUEST_USART6_RX 31U /*!< GPDMA2 HW request is USART6_RX */
1198 #define LL_GPDMA2_REQUEST_USART6_TX 32U /*!< GPDMA2 HW request is USART6_TX */
1199 #endif /* USART6 */
1200 #if defined (UART7)
1201 #define LL_GPDMA2_REQUEST_UART7_RX 33U /*!< GPDMA2 HW request is UART7_RX */
1202 #define LL_GPDMA2_REQUEST_UART7_TX 34U /*!< GPDMA2 HW request is UART7_TX */
1203 #endif /* UART7 */
1204 #if defined (UART8)
1205 #define LL_GPDMA2_REQUEST_UART8_RX 35U /*!< GPDMA2 HW request is UART8_RX */
1206 #define LL_GPDMA2_REQUEST_UART8_TX 36U /*!< GPDMA2 HW request is UART8_TX */
1207 #endif /* UART8 */
1208 #if defined (UART9)
1209 #define LL_GPDMA2_REQUEST_UART9_RX 37U /*!< GPDMA2 HW request is UART9_RX */
1210 #define LL_GPDMA2_REQUEST_UART9_TX 38U /*!< GPDMA2 HW request is UART9_TX */
1211 #endif /* UART9 */
1212 #if defined (USART10)
1213 #define LL_GPDMA2_REQUEST_USART10_RX 39U /*!< GPDMA2 HW request is USART10_RX */
1214 #define LL_GPDMA2_REQUEST_USART10_TX 40U /*!< GPDMA2 HW request is USART10_TX */
1215 #endif /* USART10 */
1216 #if defined (USART11)
1217 #define LL_GPDMA2_REQUEST_USART11_RX 41U /*!< GPDMA2 HW request is USART11_RX */
1218 #define LL_GPDMA2_REQUEST_USART11_TX 42U /*!< GPDMA2 HW request is USART11_TX */
1219 #endif /* USART11 */
1220 #if defined (UART12)
1221 #define LL_GPDMA2_REQUEST_UART12_RX 43U /*!< GPDMA2 HW request is UART12_RX */
1222 #define LL_GPDMA2_REQUEST_UART12_TX 44U /*!< GPDMA2 HW request is UART12_TX */
1223 #endif /* UART12 */
1224 #define LL_GPDMA2_REQUEST_LPUART1_RX 45U /*!< GPDMA2 HW request is LPUART1_RX */
1225 #define LL_GPDMA2_REQUEST_LPUART1_TX 46U /*!< GPDMA2 HW request is LPUART1_TX */
1226 #if defined (SPI4)
1227 #define LL_GPDMA2_REQUEST_SPI4_RX 47U /*!< GPDMA2 HW request is SPI4_RX */
1228 #define LL_GPDMA2_REQUEST_SPI4_TX 48U /*!< GPDMA2 HW request is SPI4_TX */
1229 #endif /* SPI4 */
1230 #if defined (SPI5)
1231 #define LL_GPDMA2_REQUEST_SPI5_RX 49U /*!< GPDMA2 HW request is SPI5_RX */
1232 #define LL_GPDMA2_REQUEST_SPI5_TX 50U /*!< GPDMA2 HW request is SPI5_TX */
1233 #endif /* SPI5 */
1234 #if defined (SPI6)
1235 #define LL_GPDMA2_REQUEST_SPI6_RX 51U /*!< GPDMA2 HW request is SPI6_RX */
1236 #define LL_GPDMA2_REQUEST_SPI6_TX 52U /*!< GPDMA2 HW request is SPI6_TX */
1237 #endif /* SPI6 */
1238 #if defined (SAI1)
1239 #define LL_GPDMA2_REQUEST_SAI1_A 53U /*!< GPDMA2 HW request is SAI1_A */
1240 #define LL_GPDMA2_REQUEST_SAI1_B 54U /*!< GPDMA2 HW request is SAI1_B */
1241 #endif /* SAI1 */
1242 #if defined (SAI2)
1243 #define LL_GPDMA2_REQUEST_SAI2_A 55U /*!< GPDMA2 HW request is SAI2_A */
1244 #define LL_GPDMA2_REQUEST_SAI2_B 56U /*!< GPDMA2 HW request is SAI2_B */
1245 #endif /* SAI2 */
1246 #if defined (OCTOSPI1)
1247 #define LL_GPDMA2_REQUEST_OCTOSPI1 57U /*!< GPDMA2 HW request is OCTOSPI1 */
1248 #endif /* OCTOSPI1 */
1249 #define LL_GPDMA2_REQUEST_TIM1_CH1 58U /*!< GPDMA2 HW request is TIM1_CH1 */
1250 #define LL_GPDMA2_REQUEST_TIM1_CH2 59U /*!< GPDMA2 HW request is TIM1_CH2 */
1251 #define LL_GPDMA2_REQUEST_TIM1_CH3 60U /*!< GPDMA2 HW request is TIM1_CH3 */
1252 #define LL_GPDMA2_REQUEST_TIM1_CH4 61U /*!< GPDMA2 HW request is TIM1_CH4 */
1253 #define LL_GPDMA2_REQUEST_TIM1_UP 62U /*!< GPDMA2 HW request is TIM1_UP */
1254 #define LL_GPDMA2_REQUEST_TIM1_TRIG 63U /*!< GPDMA2 HW request is TIM1_TRIG */
1255 #define LL_GPDMA2_REQUEST_TIM1_COM 64U /*!< GPDMA2 HW request is TIM1_COM */
1256 #if defined (TIM8)
1257 #define LL_GPDMA2_REQUEST_TIM8_CH1 65U /*!< GPDMA2 HW request is TIM8_CH1 */
1258 #define LL_GPDMA2_REQUEST_TIM8_CH2 66U /*!< GPDMA2 HW request is TIM8_CH2 */
1259 #define LL_GPDMA2_REQUEST_TIM8_CH3 67U /*!< GPDMA2 HW request is TIM8_CH3 */
1260 #define LL_GPDMA2_REQUEST_TIM8_CH4 68U /*!< GPDMA2 HW request is TIM8_CH4 */
1261 #define LL_GPDMA2_REQUEST_TIM8_UP 69U /*!< GPDMA2 HW request is TIM8_UP */
1262 #define LL_GPDMA2_REQUEST_TIM8_TRIG 70U /*!< GPDMA2 HW request is TIM8_TRIG */
1263 #define LL_GPDMA2_REQUEST_TIM8_COM 71U /*!< GPDMA2 HW request is TIM8_COM */
1264 #endif /* TIM8 */
1265 #define LL_GPDMA2_REQUEST_TIM2_CH1 72U /*!< GPDMA2 HW request is TIM2_CH1 */
1266 #define LL_GPDMA2_REQUEST_TIM2_CH2 73U /*!< GPDMA2 HW request is TIM2_CH2 */
1267 #define LL_GPDMA2_REQUEST_TIM2_CH3 74U /*!< GPDMA2 HW request is TIM2_CH3 */
1268 #define LL_GPDMA2_REQUEST_TIM2_CH4 75U /*!< GPDMA2 HW request is TIM2_CH4 */
1269 #define LL_GPDMA2_REQUEST_TIM2_UP 76U /*!< GPDMA2 HW request is TIM2_UP */
1270 #define LL_GPDMA2_REQUEST_TIM3_CH1 77U /*!< GPDMA2 HW request is TIM3_CH1 */
1271 #define LL_GPDMA2_REQUEST_TIM3_CH2 78U /*!< GPDMA2 HW request is TIM3_CH2 */
1272 #define LL_GPDMA2_REQUEST_TIM3_CH3 79U /*!< GPDMA2 HW request is TIM3_CH3 */
1273 #define LL_GPDMA2_REQUEST_TIM3_CH4 80U /*!< GPDMA2 HW request is TIM3_CH4 */
1274 #define LL_GPDMA2_REQUEST_TIM3_UP 81U /*!< GPDMA2 HW request is TIM3_UP */
1275 #define LL_GPDMA2_REQUEST_TIM3_TRIG 82U /*!< GPDMA2 HW request is TIM3_TRIG */
1276 #if defined (TIM4)
1277 #define LL_GPDMA2_REQUEST_TIM4_CH1 83U /*!< GPDMA2 HW request is TIM4_CH1 */
1278 #define LL_GPDMA2_REQUEST_TIM4_CH2 84U /*!< GPDMA2 HW request is TIM4_CH2 */
1279 #define LL_GPDMA2_REQUEST_TIM4_CH3 85U /*!< GPDMA2 HW request is TIM4_CH3 */
1280 #define LL_GPDMA2_REQUEST_TIM4_CH4 86U /*!< GPDMA2 HW request is TIM4_CH4 */
1281 #define LL_GPDMA2_REQUEST_TIM4_UP 87U /*!< GPDMA2 HW request is TIM4_UP */
1282 #endif /* TIM4 */
1283 #if defined (TIM5)
1284 #define LL_GPDMA2_REQUEST_TIM5_CH1 88U /*!< GPDMA2 HW request is TIM5_CH1 */
1285 #define LL_GPDMA2_REQUEST_TIM5_CH2 89U /*!< GPDMA2 HW request is TIM5_CH2 */
1286 #define LL_GPDMA2_REQUEST_TIM5_CH3 90U /*!< GPDMA2 HW request is TIM5_CH3 */
1287 #define LL_GPDMA2_REQUEST_TIM5_CH4 91U /*!< GPDMA2 HW request is TIM5_CH4 */
1288 #define LL_GPDMA2_REQUEST_TIM5_UP 92U /*!< GPDMA2 HW request is TIM5_UP */
1289 #define LL_GPDMA2_REQUEST_TIM5_TRIG 93U /*!< GPDMA2 HW request is TIM5_TRIG */
1290 #endif /* TIM5 */
1291 #if defined (TIM15)
1292 #define LL_GPDMA2_REQUEST_TIM15_CH1 94U /*!< GPDMA2 HW request is TIM15_CH1 */
1293 #define LL_GPDMA2_REQUEST_TIM15_UP 95U /*!< GPDMA2 HW request is TIM15_UP */
1294 #define LL_GPDMA2_REQUEST_TIM15_TRIG 96U /*!< GPDMA2 HW request is TIM15_TRIG */
1295 #define LL_GPDMA2_REQUEST_TIM15_COM 97U /*!< GPDMA2 HW request is TIM15_COM */
1296 #endif /* TIM15 */
1297 #if defined (TIM16)
1298 #define LL_GPDMA2_REQUEST_TIM16_CH1 98U /*!< GPDMA2 HW request is TIM16_CH1 */
1299 #define LL_GPDMA2_REQUEST_TIM16_UP 99U /*!< GPDMA2 HW request is TIM16_UP */
1300 #endif /* TIM16 */
1301 #if defined (TIM17)
1302 #define LL_GPDMA2_REQUEST_TIM17_CH1 100U /*!< GPDMA2 HW request is TIM17_CH1 */
1303 #define LL_GPDMA2_REQUEST_TIM17_UP 101U /*!< GPDMA2 HW request is TIM17_UP */
1304 #endif /* TIM17 */
1305 #define LL_GPDMA2_REQUEST_LPTIM1_IC1 102U /*!< GPDMA2 HW request is LPTIM1_IC1 */
1306 #define LL_GPDMA2_REQUEST_LPTIM1_IC2 103U /*!< GPDMA2 HW request is LPTIM1_IC2 */
1307 #define LL_GPDMA2_REQUEST_LPTIM1_UE 104U /*!< GPDMA2 HW request is LPTIM1_UE */
1308 #define LL_GPDMA2_REQUEST_LPTIM2_IC1 105U /*!< GPDMA2 HW request is LPTIM2_IC1 */
1309 #define LL_GPDMA2_REQUEST_LPTIM2_IC2 106U /*!< GPDMA2 HW request is LPTIM2_IC2 */
1310 #define LL_GPDMA2_REQUEST_LPTIM2_UE 107U /*!< GPDMA2 HW request is LPTIM2_UE */
1311 #if defined (DCMI)
1312 #define LL_GPDMA2_REQUEST_DCMI 108U /*!< GPDMA2 HW request is DCMI */
1313 #endif /* DCMI */
1314 #if defined (AES)
1315 #define LL_GPDMA2_REQUEST_AES_OUT 109U /*!< GPDMA2 HW request is AES_OUT */
1316 #define LL_GPDMA2_REQUEST_AES_IN 110U /*!< GPDMA2 HW request is AES_IN */
1317 #endif /* AES */
1318 #define LL_GPDMA2_REQUEST_HASH_IN 111U /*!< GPDMA2 HW request is HASH_IN */
1319 #if defined (UCPD1)
1320 #define LL_GPDMA2_REQUEST_UCPD1_RX 112U /*!< GPDMA2 HW request is UCPD1_RX */
1321 #define LL_GPDMA2_REQUEST_UCPD1_TX 113U /*!< GPDMA2 HW request is UCPD1_TX */
1322 #endif /* UCPD1 */
1323 #if defined (CORDIC)
1324 #define LL_GPDMA2_REQUEST_CORDIC_READ 114U /*!< GPDMA2 HW request is CORDIC_READ */
1325 #define LL_GPDMA2_REQUEST_CORDIC_WRITE 115U /*!< GPDMA2 HW request is CORDIC_WRITE */
1326 #endif /* CORDIC */
1327 #if defined (FMAC)
1328 #define LL_GPDMA2_REQUEST_FMAC_READ 116U /*!< GPDMA2 HW request is FMAC_READ */
1329 #define LL_GPDMA2_REQUEST_FMAC_WRITE 117U /*!< GPDMA2 HW request is FMAC_WRITE */
1330 #endif /* FMAC */
1331 #if defined (SAES)
1332 #define LL_GPDMA2_REQUEST_SAES_OUT 118U /*!< GPDMA2 HW request is SAES_OUT */
1333 #define LL_GPDMA2_REQUEST_SAES_IN 119U /*!< GPDMA2 HW request is SAES_IN */
1334 #endif /* SAES */
1335 #define LL_GPDMA2_REQUEST_I3C1_RX 120U /*!< GPDMA2 HW request is I3C1_RX */
1336 #define LL_GPDMA2_REQUEST_I3C1_TX 121U /*!< GPDMA2 HW request is I3C1_TX */
1337 #define LL_GPDMA2_REQUEST_I3C1_TC 122U /*!< GPDMA2 HW request is I3C1_TC */
1338 #define LL_GPDMA2_REQUEST_I3C1_RS 123U /*!< GPDMA2 HW request is I3C1_RS */
1339 #if defined (I2C4)
1340 #define LL_GPDMA2_REQUEST_I2C4_RX 124U /*!< GPDMA2 HW request is I2C4_RX */
1341 #define LL_GPDMA2_REQUEST_I2C4_TX 125U /*!< GPDMA2 HW request is I2C4_TX */
1342 #endif /* I2C4 */
1343 #if defined (LPTIM3)
1344 #define LL_GPDMA2_REQUEST_LPTIM3_IC1 127U /*!< GPDMA2 HW request is LPTIM3_IC1 */
1345 #define LL_GPDMA2_REQUEST_LPTIM3_IC2 128U /*!< GPDMA2 HW request is LPTIM3_IC2 */
1346 #define LL_GPDMA2_REQUEST_LPTIM3_UE 129U /*!< GPDMA2 HW request is LPTIM3_UE */
1347 #endif /* LPTIM3 */
1348 #if defined (LPTIM5)
1349 #define LL_GPDMA2_REQUEST_LPTIM5_IC1 130U /*!< GPDMA2 HW request is LPTIM5_IC1 */
1350 #define LL_GPDMA2_REQUEST_LPTIM5_IC2 131U /*!< GPDMA2 HW request is LPTIM5_IC2 */
1351 #define LL_GPDMA2_REQUEST_LPTIM5_UE 132U /*!< GPDMA2 HW request is LPTIM5_UE */
1352 #endif /* LPTIM5 */
1353 #if defined (LPTIM6)
1354 #define LL_GPDMA2_REQUEST_LPTIM6_IC1 133U /*!< GPDMA2 HW request is LPTIM6_IC1 */
1355 #define LL_GPDMA2_REQUEST_LPTIM6_IC2 134U /*!< GPDMA2 HW request is LPTIM6_IC2 */
1356 #define LL_GPDMA2_REQUEST_LPTIM6_UE 135U /*!< GPDMA2 HW request is LPTIM6_UE */
1357 #endif /* LPTIM6 */
1358 #if defined (I3C2)
1359 #define LL_GPDMA2_REQUEST_I3C2_RX 136U /*!< GPDMA2 HW request is I3C2_RX */
1360 #define LL_GPDMA2_REQUEST_I3C2_TX 137U /*!< GPDMA2 HW request is I3C2_TX */
1361 #define LL_GPDMA2_REQUEST_I3C2_TC 138U /*!< GPDMA2 HW request is I3C2_TC */
1362 #define LL_GPDMA2_REQUEST_I3C2_RS 139U /*!< GPDMA2 HW request is I3C2_RS */
1363 #endif /* I3C2 */
1364
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
1370 * @{
1371 */
1372 /* GPDMA1 Hardware Triggers */
1373 #define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */
1374 #define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */
1375 #define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */
1376 #define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */
1377 #define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */
1378 #define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */
1379 #define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */
1380 #define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */
1381 #define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */
1382 #define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */
1383 #if defined (TAMP_CR1_TAMP3E)
1384 #define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */
1385 #endif /* TAMP_CR1_TAMP3E */
1386 #define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
1387 #define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
1388 #define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
1389 #define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
1390 #define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
1391 #define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
1392 #define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
1393 #define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
1394 #define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
1395 #define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
1396 #define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
1397 #define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
1398 #define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
1399 #define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
1400 #define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
1401 #define LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH0_TCF */
1402 #define LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH1_TCF */
1403 #define LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH2_TCF */
1404 #define LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH3_TCF */
1405 #define LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH4_TCF */
1406 #define LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH5_TCF */
1407 #define LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH6_TCF */
1408 #define LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH7_TCF */
1409 #define LL_GPDMA1_TRIGGER_TIM2_TRGO 34U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
1410 #if defined (TIM15)
1411 #define LL_GPDMA1_TRIGGER_TIM15_TRGO 35U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
1412 #endif /* TIM15 */
1413 #if defined (TIM12)
1414 #define LL_GPDMA1_TRIGGER_TIM12_TRGO 36U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
1415 #endif /* TIM12 */
1416 #if defined (LPTIM3)
1417 #define LL_GPDMA1_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */
1418 #define LL_GPDMA1_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */
1419 #endif /* LPTIM3 */
1420 #if defined (LPTIM4)
1421 #define LL_GPDMA1_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA1 HW Trigger signal is LPTIM4_AIT */
1422 #endif /* LPTIM4 */
1423 #if defined (LPTIM5)
1424 #define LL_GPDMA1_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH1 */
1425 #define LL_GPDMA1_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH2 */
1426 #endif /* LPTIM5 */
1427 #if defined (LPTIM6)
1428 #define LL_GPDMA1_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH1 */
1429 #define LL_GPDMA1_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH2 */
1430 #endif /* LPTIM6 */
1431 #if defined (COMP1)
1432 #define LL_GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
1433 #endif /* COMP1 */
1434 #if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx)
1435 #define LL_GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is EVENTOUT */
1436 #endif /* STM32H503xx || STM32H523xx || STM32H533xx */
1437
1438 /* GPDMA2 Hardware Triggers */
1439 #define LL_GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */
1440 #define LL_GPDMA2_TRIGGER_EXTI_LINE1 1U /*!< GPDMA2 HW Trigger signal is EXTI_LINE1 */
1441 #define LL_GPDMA2_TRIGGER_EXTI_LINE2 2U /*!< GPDMA2 HW Trigger signal is EXTI_LINE2 */
1442 #define LL_GPDMA2_TRIGGER_EXTI_LINE3 3U /*!< GPDMA2 HW Trigger signal is EXTI_LINE3 */
1443 #define LL_GPDMA2_TRIGGER_EXTI_LINE4 4U /*!< GPDMA2 HW Trigger signal is EXTI_LINE4 */
1444 #define LL_GPDMA2_TRIGGER_EXTI_LINE5 5U /*!< GPDMA2 HW Trigger signal is EXTI_LINE5 */
1445 #define LL_GPDMA2_TRIGGER_EXTI_LINE6 6U /*!< GPDMA2 HW Trigger signal is EXTI_LINE6 */
1446 #define LL_GPDMA2_TRIGGER_EXTI_LINE7 7U /*!< GPDMA2 HW Trigger signal is EXTI_LINE7 */
1447 #define LL_GPDMA2_TRIGGER_TAMP_TRG1 8U /*!< GPDMA2 HW Trigger signal is TAMP_TRG1 */
1448 #define LL_GPDMA2_TRIGGER_TAMP_TRG2 9U /*!< GPDMA2 HW Trigger signal is TAMP_TRG2 */
1449 #define LL_GPDMA2_TRIGGER_TAMP_TRG3 10U /*!< GPDMA2 HW Trigger signal is TAMP_TRG3 */
1450 #define LL_GPDMA2_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH1 */
1451 #define LL_GPDMA2_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH2 */
1452 #define LL_GPDMA2_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH1 */
1453 #define LL_GPDMA2_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH2 */
1454 #define LL_GPDMA2_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA2 HW Trigger signal is RTC_ALRA_TRG */
1455 #define LL_GPDMA2_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA2 HW Trigger signal is RTC_ALRB_TRG */
1456 #define LL_GPDMA2_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA2 HW Trigger signal is RTC_WUT_TRG */
1457 #define LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH0_TCF */
1458 #define LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH1_TCF */
1459 #define LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH2_TCF */
1460 #define LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH3_TCF */
1461 #define LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH4_TCF */
1462 #define LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH5_TCF */
1463 #define LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH6_TCF */
1464 #define LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH7_TCF */
1465 #define LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH0_TCF */
1466 #define LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH1_TCF */
1467 #define LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH2_TCF */
1468 #define LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH3_TCF */
1469 #define LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH4_TCF */
1470 #define LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH5_TCF */
1471 #define LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH6_TCF */
1472 #define LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH7_TCF */
1473 #define LL_GPDMA2_TRIGGER_TIM2_TRGO 34U /*!< GPDMA2 HW Trigger signal is TIM2_TRGO */
1474 #if defined (TIM15)
1475 #define LL_GPDMA2_TRIGGER_TIM15_TRGO 35U /*!< GPDMA2 HW Trigger signal is TIM15_TRGO */
1476 #endif /* TIM15 */
1477 #if defined (TIM12)
1478 #define LL_GPDMA2_TRIGGER_TIM12_TRGO 36U /*!< GPDMA2 HW Trigger signal is TIM12_TRGO */
1479 #endif /* TIM12 */
1480 #if defined (LPTIM3)
1481 #define LL_GPDMA2_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH1 */
1482 #define LL_GPDMA2_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH2 */
1483 #endif /* LPTIM3 */
1484 #if defined (LPTIM4)
1485 #define LL_GPDMA2_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA2 HW Trigger signal is LPTIM4_AIT */
1486 #endif /* LPTIM4 */
1487 #if defined (LPTIM5)
1488 #define LL_GPDMA2_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH1 */
1489 #define LL_GPDMA2_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH2 */
1490 #endif /* LPTIM5 */
1491 #if defined (LPTIM6)
1492 #define LL_GPDMA2_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH1 */
1493 #define LL_GPDMA2_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH2 */
1494 #endif /* LPTIM6 */
1495 #if defined (COMP1)
1496 #define LL_GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */
1497 #endif /* COMP1 */
1498 #if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx)
1499 #define LL_GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is EVENTOUT */
1500 #endif /* STM32H503xx || STM32H523xx || STM32H533xx */
1501 /**
1502 * @}
1503 */
1504
1505 /**
1506 * @}
1507 */
1508
1509 /* Exported macro ------------------------------------------------------------*/
1510
1511 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
1512 * @{
1513 */
1514
1515 /** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
1516 * @{
1517 */
1518 /**
1519 * @brief Write a value in DMA register.
1520 * @param __INSTANCE__ DMA Instance.
1521 * @param __REG__ Register to be written.
1522 * @param __VALUE__ Value to be written in the register.
1523 * @retval None.
1524 */
1525 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1526
1527 /**
1528 * @brief Read a value in DMA register.
1529 * @param __INSTANCE__ DMA Instance.
1530 * @param __REG__ Register to be read.
1531 * @retval Register value.
1532 */
1533 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1534 /**
1535 * @}
1536 */
1537
1538 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
1539 * @{
1540 */
1541 /**
1542 * @brief Convert DMAx_Channely into DMAx.
1543 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1544 * @retval DMAx.
1545 */
1546 #define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
1547 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel7)) ? GPDMA2 : GPDMA1)
1548
1549 /**
1550 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
1551 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1552 * @retval LL_DMA_CHANNEL_y.
1553 */
1554 #define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
1555 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
1556 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel0)) ? LL_DMA_CHANNEL_0 : \
1557 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
1558 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
1559 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
1560 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
1561 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
1562 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
1563 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
1564 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
1565 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
1566 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
1567 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
1568 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
1569 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
1570 LL_DMA_CHANNEL_7)
1571
1572 /**
1573 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
1574 * @param __DMA_INSTANCE__ DMAx.
1575 * @param __CHANNEL__ LL_DMA_CHANNEL_y.
1576 * @retval DMAx_Channely.
1577 */
1578 #define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
1579 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1580 ? GPDMA1_Channel0 : \
1581 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1582 ? GPDMA1_Channel1 : \
1583 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
1584 ? GPDMA1_Channel2 : \
1585 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
1586 ? GPDMA1_Channel3 : \
1587 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
1588 ? GPDMA1_Channel4 : \
1589 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
1590 ? GPDMA1_Channel5 : \
1591 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
1592 ? GPDMA1_Channel6 : \
1593 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
1594 ? GPDMA1_Channel7 : \
1595 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1596 ? GPDMA2_Channel0 : \
1597 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1598 ? GPDMA2_Channel1 : \
1599 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2)))\
1600 ? GPDMA2_Channel2 : \
1601 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3)))\
1602 ? GPDMA2_Channel3 : \
1603 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4)))\
1604 ? GPDMA2_Channel4 : \
1605 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5)))\
1606 ? GPDMA2_Channel5 : \
1607 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6)))\
1608 ? GPDMA2_Channel6 : GPDMA2_Channel7)
1609
1610 /**
1611 * @}
1612 */
1613
1614 /**
1615 * @}
1616 */
1617
1618 /* Exported functions --------------------------------------------------------*/
1619
1620 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
1621 * @{
1622 */
1623
1624 /** @defgroup DMA_LL_EF_Configuration Configuration
1625 * @{
1626 */
1627 /**
1628 * @brief Enable channel.
1629 * @note This API is used for all available DMA channels.
1630 * @rmtoll CCR EN LL_DMA_EnableChannel
1631 * @param DMAx DMAx Instance.
1632 * @param Channel This parameter can be one of the following values:
1633 * @arg @ref LL_DMA_CHANNEL_0
1634 * @arg @ref LL_DMA_CHANNEL_1
1635 * @arg @ref LL_DMA_CHANNEL_2
1636 * @arg @ref LL_DMA_CHANNEL_3
1637 * @arg @ref LL_DMA_CHANNEL_4
1638 * @arg @ref LL_DMA_CHANNEL_5
1639 * @arg @ref LL_DMA_CHANNEL_6
1640 * @arg @ref LL_DMA_CHANNEL_7
1641 * @retval None.
1642 */
LL_DMA_EnableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1643 __STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1644 {
1645 uint32_t dma_base_addr = (uint32_t)DMAx;
1646 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
1647 }
1648
1649 /**
1650 * @brief Disable channel.
1651 * @note This API is used for all available DMA channels.
1652 * @rmtoll CCR EN LL_DMA_DisableChannel
1653 * @param DMAx DMAx Instance.
1654 * @param Channel This parameter can be one of the following values:
1655 * @arg @ref LL_DMA_CHANNEL_0
1656 * @arg @ref LL_DMA_CHANNEL_1
1657 * @arg @ref LL_DMA_CHANNEL_2
1658 * @arg @ref LL_DMA_CHANNEL_3
1659 * @arg @ref LL_DMA_CHANNEL_4
1660 * @arg @ref LL_DMA_CHANNEL_5
1661 * @arg @ref LL_DMA_CHANNEL_6
1662 * @arg @ref LL_DMA_CHANNEL_7
1663 * @retval None.
1664 */
LL_DMA_DisableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1665 __STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1666 {
1667 uint32_t dma_base_addr = (uint32_t)DMAx;
1668 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1669 (DMA_CCR_SUSP | DMA_CCR_RESET));
1670 }
1671
1672 /**
1673 * @brief Check if channel is enabled or disabled.
1674 * @note This API is used for all available DMA channels.
1675 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
1676 * @param DMAx DMAx Instance
1677 * @param Channel This parameter can be one of the following values:
1678 * @arg @ref LL_DMA_CHANNEL_0
1679 * @arg @ref LL_DMA_CHANNEL_1
1680 * @arg @ref LL_DMA_CHANNEL_2
1681 * @arg @ref LL_DMA_CHANNEL_3
1682 * @arg @ref LL_DMA_CHANNEL_4
1683 * @arg @ref LL_DMA_CHANNEL_5
1684 * @arg @ref LL_DMA_CHANNEL_6
1685 * @arg @ref LL_DMA_CHANNEL_7
1686 * @retval State of bit (1 or 0).
1687 */
LL_DMA_IsEnabledChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1688 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1689 {
1690 uint32_t dma_base_addr = (uint32_t)DMAx;
1691 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
1692 == (DMA_CCR_EN)) ? 1UL : 0UL);
1693 }
1694
1695 /**
1696 * @brief Reset channel.
1697 * @note This API is used for all available DMA channels.
1698 * @rmtoll CCR RESET LL_DMA_ResetChannel
1699 * @param DMAx DMAx Instance
1700 * @param Channel This parameter can be one of the following values:
1701 * @arg @ref LL_DMA_CHANNEL_0
1702 * @arg @ref LL_DMA_CHANNEL_1
1703 * @arg @ref LL_DMA_CHANNEL_2
1704 * @arg @ref LL_DMA_CHANNEL_3
1705 * @arg @ref LL_DMA_CHANNEL_4
1706 * @arg @ref LL_DMA_CHANNEL_5
1707 * @arg @ref LL_DMA_CHANNEL_6
1708 * @arg @ref LL_DMA_CHANNEL_7
1709 * @retval None.
1710 */
LL_DMA_ResetChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1711 __STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1712 {
1713 uint32_t dma_base_addr = (uint32_t)DMAx;
1714 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
1715 }
1716
1717 /**
1718 * @brief Suspend channel.
1719 * @note This API is used for all available DMA channels.
1720 * @rmtoll CCR SUSP LL_DMA_SuspendChannel
1721 * @param DMAx DMAx Instance
1722 * @param Channel This parameter can be one of the following values:
1723 * @arg @ref LL_DMA_CHANNEL_0
1724 * @arg @ref LL_DMA_CHANNEL_1
1725 * @arg @ref LL_DMA_CHANNEL_2
1726 * @arg @ref LL_DMA_CHANNEL_3
1727 * @arg @ref LL_DMA_CHANNEL_4
1728 * @arg @ref LL_DMA_CHANNEL_5
1729 * @arg @ref LL_DMA_CHANNEL_6
1730 * @arg @ref LL_DMA_CHANNEL_7
1731 * @retval None.
1732 */
LL_DMA_SuspendChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1733 __STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1734 {
1735 uint32_t dma_base_addr = (uint32_t)DMAx;
1736 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1737 }
1738
1739 /**
1740 * @brief Resume channel.
1741 * @note This API is used for all available DMA channels.
1742 * @rmtoll CCR SUSP LL_DMA_ResumeChannel
1743 * @param DMAx DMAx Instance
1744 * @param Channel This parameter can be one of the following values:
1745 * @arg @ref LL_DMA_CHANNEL_0
1746 * @arg @ref LL_DMA_CHANNEL_1
1747 * @arg @ref LL_DMA_CHANNEL_2
1748 * @arg @ref LL_DMA_CHANNEL_3
1749 * @arg @ref LL_DMA_CHANNEL_4
1750 * @arg @ref LL_DMA_CHANNEL_5
1751 * @arg @ref LL_DMA_CHANNEL_6
1752 * @arg @ref LL_DMA_CHANNEL_7
1753 * @retval None.
1754 */
LL_DMA_ResumeChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1755 __STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1756 {
1757 uint32_t dma_base_addr = (uint32_t)DMAx;
1758 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1759 }
1760
1761 /**
1762 * @brief Check if channel is suspended.
1763 * @note This API is used for all available DMA channels.
1764 * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
1765 * @param DMAx DMAx Instance
1766 * @param Channel This parameter can be one of the following values:
1767 * @arg @ref LL_DMA_CHANNEL_0
1768 * @arg @ref LL_DMA_CHANNEL_1
1769 * @arg @ref LL_DMA_CHANNEL_2
1770 * @arg @ref LL_DMA_CHANNEL_3
1771 * @arg @ref LL_DMA_CHANNEL_4
1772 * @arg @ref LL_DMA_CHANNEL_5
1773 * @arg @ref LL_DMA_CHANNEL_6
1774 * @arg @ref LL_DMA_CHANNEL_7
1775 * @retval State of bit (1 or 0).
1776 */
LL_DMA_IsSuspendedChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1777 __STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1778 {
1779 uint32_t dma_base_addr = (uint32_t)DMAx;
1780 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
1781 == (DMA_CCR_SUSP)) ? 1UL : 0UL);
1782 }
1783
1784 /**
1785 * @brief Set linked-list base address.
1786 * @note This API is used for all available DMA channels.
1787 * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
1788 * @param DMAx DMAx Instance
1789 * @param Channel This parameter can be one of the following values:
1790 * @arg @ref LL_DMA_CHANNEL_0
1791 * @arg @ref LL_DMA_CHANNEL_1
1792 * @arg @ref LL_DMA_CHANNEL_2
1793 * @arg @ref LL_DMA_CHANNEL_3
1794 * @arg @ref LL_DMA_CHANNEL_4
1795 * @arg @ref LL_DMA_CHANNEL_5
1796 * @arg @ref LL_DMA_CHANNEL_6
1797 * @arg @ref LL_DMA_CHANNEL_7
1798 * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
1799 * are always 0)
1800 * @retval None.
1801 */
LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListBaseAddr)1802 __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel,
1803 uint32_t LinkedListBaseAddr)
1804 {
1805 uint32_t dma_base_addr = (uint32_t)DMAx;
1806 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
1807 (LinkedListBaseAddr & DMA_CLBAR_LBA));
1808 }
1809
1810 /**
1811 * @brief Get linked-list base address.
1812 * @note This API is used for all available DMA channels.
1813 * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
1814 * @param DMAx DMAx Instance
1815 * @param Channel This parameter can be one of the following values:
1816 * @arg @ref LL_DMA_CHANNEL_0
1817 * @arg @ref LL_DMA_CHANNEL_1
1818 * @arg @ref LL_DMA_CHANNEL_2
1819 * @arg @ref LL_DMA_CHANNEL_3
1820 * @arg @ref LL_DMA_CHANNEL_4
1821 * @arg @ref LL_DMA_CHANNEL_5
1822 * @arg @ref LL_DMA_CHANNEL_6
1823 * @arg @ref LL_DMA_CHANNEL_7
1824 * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
1825 */
LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel)1826 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel)
1827 {
1828 uint32_t dma_base_addr = (uint32_t)DMAx;
1829 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
1830 }
1831
1832 /**
1833 * @brief Configure all parameters linked to channel control.
1834 * @note This API is used for all available DMA channels.
1835 * @rmtoll CCR PRIO LL_DMA_ConfigControl\n
1836 * CCR LAP LL_DMA_ConfigControl\n
1837 * CCR LSM LL_DMA_ConfigControl
1838 * @param DMAx DMAx Instance
1839 * @param Channel This parameter can be one of the following values:
1840 * @arg @ref LL_DMA_CHANNEL_0
1841 * @arg @ref LL_DMA_CHANNEL_1
1842 * @arg @ref LL_DMA_CHANNEL_2
1843 * @arg @ref LL_DMA_CHANNEL_3
1844 * @arg @ref LL_DMA_CHANNEL_4
1845 * @arg @ref LL_DMA_CHANNEL_5
1846 * @arg @ref LL_DMA_CHANNEL_6
1847 * @arg @ref LL_DMA_CHANNEL_7
1848 * @param Configuration This parameter must be a combination of all the following values:
1849 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
1850 * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
1851 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
1852 * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
1853 *@retval None.
1854 */
LL_DMA_ConfigControl(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1855 __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1856 {
1857 uint32_t dma_base_addr = (uint32_t)DMAx;
1858 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1859 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
1860 }
1861
1862 /**
1863 * @brief Set priority level.
1864 * @note This API is used for all available DMA channels.
1865 * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
1866 * @param DMAx DMAx Instance
1867 * @param Channel This parameter can be one of the following values:
1868 * @arg @ref LL_DMA_CHANNEL_0
1869 * @arg @ref LL_DMA_CHANNEL_1
1870 * @arg @ref LL_DMA_CHANNEL_2
1871 * @arg @ref LL_DMA_CHANNEL_3
1872 * @arg @ref LL_DMA_CHANNEL_4
1873 * @arg @ref LL_DMA_CHANNEL_5
1874 * @arg @ref LL_DMA_CHANNEL_6
1875 * @arg @ref LL_DMA_CHANNEL_7
1876 * @param Priority This parameter can be one of the following values:
1877 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1878 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1879 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1880 * @arg @ref LL_DMA_HIGH_PRIORITY
1881 * @retval None.
1882 */
LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)1883 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
1884 {
1885 uint32_t dma_base_addr = (uint32_t)DMAx;
1886 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
1887 }
1888
1889 /**
1890 * @brief Get Channel priority level.
1891 * @note This API is used for all available DMA channels.
1892 * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
1893 * @param DMAx DMAx Instance
1894 * @param Channel This parameter can be one of the following values:
1895 * @arg @ref LL_DMA_CHANNEL_0
1896 * @arg @ref LL_DMA_CHANNEL_1
1897 * @arg @ref LL_DMA_CHANNEL_2
1898 * @arg @ref LL_DMA_CHANNEL_3
1899 * @arg @ref LL_DMA_CHANNEL_4
1900 * @arg @ref LL_DMA_CHANNEL_5
1901 * @arg @ref LL_DMA_CHANNEL_6
1902 * @arg @ref LL_DMA_CHANNEL_7
1903 * @retval Returned value can be one of the following values:
1904 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1905 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1906 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1907 * @arg @ref LL_DMA_HIGH_PRIORITY
1908 */
LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel)1909 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
1910 {
1911 uint32_t dma_base_addr = (uint32_t)DMAx;
1912 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
1913 }
1914
1915 /**
1916 * @brief Set linked-list allocated port.
1917 * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
1918 * @param DMAx DMAx Instance
1919 * @param Channel This parameter can be one of the following values:
1920 * @arg @ref LL_DMA_CHANNEL_0
1921 * @arg @ref LL_DMA_CHANNEL_1
1922 * @arg @ref LL_DMA_CHANNEL_2
1923 * @arg @ref LL_DMA_CHANNEL_3
1924 * @arg @ref LL_DMA_CHANNEL_4
1925 * @arg @ref LL_DMA_CHANNEL_5
1926 * @arg @ref LL_DMA_CHANNEL_6
1927 * @arg @ref LL_DMA_CHANNEL_7
1928 * @param LinkAllocatedPort This parameter can be one of the following values:
1929 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1930 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1931 * @retval None.
1932 */
LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkAllocatedPort)1933 __STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
1934 {
1935 uint32_t dma_base_addr = (uint32_t)DMAx;
1936 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1937 DMA_CCR_LAP, LinkAllocatedPort);
1938 }
1939
1940 /**
1941 * @brief Get linked-list allocated port.
1942 * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
1943 * @param DMAx DMAx Instance
1944 * @param Channel This parameter can be one of the following values:
1945 * @arg @ref LL_DMA_CHANNEL_0
1946 * @arg @ref LL_DMA_CHANNEL_1
1947 * @arg @ref LL_DMA_CHANNEL_2
1948 * @arg @ref LL_DMA_CHANNEL_3
1949 * @arg @ref LL_DMA_CHANNEL_4
1950 * @arg @ref LL_DMA_CHANNEL_5
1951 * @arg @ref LL_DMA_CHANNEL_6
1952 * @arg @ref LL_DMA_CHANNEL_7
1953 * @retval Returned value can be one of the following values:
1954 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1955 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1956 */
LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1957 __STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1958 {
1959 uint32_t dma_base_addr = (uint32_t)DMAx;
1960 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
1961 }
1962
1963 /**
1964 * @brief Set link step mode.
1965 * @note This API is used for all available DMA channels.
1966 * @rmtoll CCR LSM LL_DMA_SetLinkStepMode
1967 * @param DMAx DMAx Instance
1968 * @param Channel This parameter can be one of the following values:
1969 * @arg @ref LL_DMA_CHANNEL_0
1970 * @arg @ref LL_DMA_CHANNEL_1
1971 * @arg @ref LL_DMA_CHANNEL_2
1972 * @arg @ref LL_DMA_CHANNEL_3
1973 * @arg @ref LL_DMA_CHANNEL_4
1974 * @arg @ref LL_DMA_CHANNEL_5
1975 * @arg @ref LL_DMA_CHANNEL_6
1976 * @arg @ref LL_DMA_CHANNEL_7
1977 * @param LinkStepMode This parameter can be one of the following values:
1978 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1979 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1980 * @retval None.
1981 */
LL_DMA_SetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkStepMode)1982 __STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
1983 {
1984 uint32_t dma_base_addr = (uint32_t)DMAx;
1985 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
1986 }
1987
1988 /**
1989 * @brief Get Link step mode.
1990 * @note This API is used for all available DMA channels.
1991 * @rmtoll CCR LSM LL_DMA_GetLinkStepMode
1992 * @param DMAx DMAx Instance
1993 * @param Channel This parameter can be one of the following values:
1994 * @arg @ref LL_DMA_CHANNEL_0
1995 * @arg @ref LL_DMA_CHANNEL_1
1996 * @arg @ref LL_DMA_CHANNEL_2
1997 * @arg @ref LL_DMA_CHANNEL_3
1998 * @arg @ref LL_DMA_CHANNEL_4
1999 * @arg @ref LL_DMA_CHANNEL_5
2000 * @arg @ref LL_DMA_CHANNEL_6
2001 * @arg @ref LL_DMA_CHANNEL_7
2002 * @retval Returned value can be one of the following values:
2003 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
2004 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
2005 */
LL_DMA_GetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel)2006 __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2007 {
2008 uint32_t dma_base_addr = (uint32_t)DMAx;
2009 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
2010 }
2011
2012 /**
2013 * @brief Configure data transfer.
2014 * @note This API is used for all available DMA channels.
2015 * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
2016 * CTR1 DHX LL_DMA_ConfigTransfer\n
2017 * CTR1 DBX LL_DMA_ConfigTransfer\n
2018 * CTR1 DINC LL_DMA_ConfigTransfer\n
2019 * CTR1 SAP LL_DMA_ConfigTransfer\n
2020 * CTR1 SBX LL_DMA_ConfigTransfer\n
2021 * CTR1 PAM LL_DMA_ConfigTransfer\n
2022 * CTR1 SINC LL_DMA_ConfigTransfer
2023 * @param DMAx DMAx Instance
2024 * @param Channel This parameter can be one of the following values:
2025 * @arg @ref LL_DMA_CHANNEL_0
2026 * @arg @ref LL_DMA_CHANNEL_1
2027 * @arg @ref LL_DMA_CHANNEL_2
2028 * @arg @ref LL_DMA_CHANNEL_3
2029 * @arg @ref LL_DMA_CHANNEL_4
2030 * @arg @ref LL_DMA_CHANNEL_5
2031 * @arg @ref LL_DMA_CHANNEL_6
2032 * @arg @ref LL_DMA_CHANNEL_7
2033 * @param Configuration This parameter must be a combination of all the following values:
2034 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
2035 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2036 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
2037 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
2038 * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
2039 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
2040 * @ref LL_DMA_DEST_DATAWIDTH_WORD
2041 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
2042 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
2043 * @ref LL_DMA_DATA_PACK_UNPACK
2044 * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
2045 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
2046 * @ref LL_DMA_SRC_DATAWIDTH_WORD
2047 *@retval None.
2048 */
LL_DMA_ConfigTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2049 __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2050 {
2051 uint32_t dma_base_addr = (uint32_t)DMAx;
2052 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2053 DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \
2054 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
2055 }
2056
2057 /**
2058 * @brief Configure source and destination burst length.
2059 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
2060 * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
2061 * @param DMAx DMAx Instance
2062 * @param Channel This parameter can be one of the following values:
2063 * @arg @ref LL_DMA_CHANNEL_0
2064 * @arg @ref LL_DMA_CHANNEL_1
2065 * @arg @ref LL_DMA_CHANNEL_2
2066 * @arg @ref LL_DMA_CHANNEL_3
2067 * @arg @ref LL_DMA_CHANNEL_4
2068 * @arg @ref LL_DMA_CHANNEL_5
2069 * @arg @ref LL_DMA_CHANNEL_6
2070 * @arg @ref LL_DMA_CHANNEL_7
2071 * @param SrcBurstLength Between 1 to 64
2072 * @param DestBurstLength Between 1 to 64
2073 * @retval None.
2074 */
LL_DMA_ConfigBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength,uint32_t DestBurstLength)2075 __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
2076 uint32_t DestBurstLength)
2077 {
2078 uint32_t dma_base_addr = (uint32_t)DMAx;
2079 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2080 (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
2081 (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
2082 }
2083
2084 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2085 /**
2086 * @brief Configure all secure parameters linked to DMA channel.
2087 * @note This API is used for all available DMA channels.
2088 * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n
2089 * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n
2090 * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure
2091 * @param DMAx DMAx Instance
2092 * @param Channel This parameter can be one of the following values:
2093 * @arg @ref LL_DMA_CHANNEL_0
2094 * @arg @ref LL_DMA_CHANNEL_1
2095 * @arg @ref LL_DMA_CHANNEL_2
2096 * @arg @ref LL_DMA_CHANNEL_3
2097 * @arg @ref LL_DMA_CHANNEL_4
2098 * @arg @ref LL_DMA_CHANNEL_5
2099 * @arg @ref LL_DMA_CHANNEL_6
2100 * @arg @ref LL_DMA_CHANNEL_7
2101 * @param Configuration This parameter must be a combination of all the following values:
2102 * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC
2103 * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC
2104 * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
2105 * @retval None.
2106 */
LL_DMA_ConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2107 __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2108 {
2109 uint32_t dma_base_addr = (uint32_t)DMAx;
2110 MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
2111 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2112 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
2113 }
2114
2115 /**
2116 * @brief Enable security attribute of the DMA transfer to the destination.
2117 * @note This API is used for all available DMA channels.
2118 * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure
2119 * @param DMAx DMAx Instance
2120 * @param Channel This parameter can be one of the following values:
2121 * @arg @ref LL_DMA_CHANNEL_0
2122 * @arg @ref LL_DMA_CHANNEL_1
2123 * @arg @ref LL_DMA_CHANNEL_2
2124 * @arg @ref LL_DMA_CHANNEL_3
2125 * @arg @ref LL_DMA_CHANNEL_4
2126 * @arg @ref LL_DMA_CHANNEL_5
2127 * @arg @ref LL_DMA_CHANNEL_6
2128 * @arg @ref LL_DMA_CHANNEL_7
2129 * @retval None.
2130 */
LL_DMA_EnableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2131 __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2132 {
2133 uint32_t dma_base_addr = (uint32_t)DMAx;
2134 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
2135 }
2136
2137 /**
2138 * @brief Disable security attribute of the DMA transfer to the destination.
2139 * @note This API is used for all available DMA channels.
2140 * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure
2141 * @param DMAx DMAx Instance
2142 * @param Channel This parameter can be one of the following values:
2143 * @arg @ref LL_DMA_CHANNEL_0
2144 * @arg @ref LL_DMA_CHANNEL_1
2145 * @arg @ref LL_DMA_CHANNEL_2
2146 * @arg @ref LL_DMA_CHANNEL_3
2147 * @arg @ref LL_DMA_CHANNEL_4
2148 * @arg @ref LL_DMA_CHANNEL_5
2149 * @arg @ref LL_DMA_CHANNEL_6
2150 * @arg @ref LL_DMA_CHANNEL_7
2151 * @retval None.
2152 */
LL_DMA_DisableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2153 __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2154 {
2155 uint32_t dma_base_addr = (uint32_t)DMAx;
2156 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
2157 }
2158 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2159
2160 #if defined (DMA_SECCFGR_SEC0)
2161 /**
2162 * @brief Check security attribute of the DMA transfer to the destination.
2163 * @note This API is used for all available DMA channels.
2164 * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure
2165 * @param DMAx DMAx Instance
2166 * @param Channel This parameter can be one of the following values:
2167 * @arg @ref LL_DMA_CHANNEL_0
2168 * @arg @ref LL_DMA_CHANNEL_1
2169 * @arg @ref LL_DMA_CHANNEL_2
2170 * @arg @ref LL_DMA_CHANNEL_3
2171 * @arg @ref LL_DMA_CHANNEL_4
2172 * @arg @ref LL_DMA_CHANNEL_5
2173 * @arg @ref LL_DMA_CHANNEL_6
2174 * @arg @ref LL_DMA_CHANNEL_7
2175 * @retval State of bit (1 or 0).
2176 */
LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2177 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2178 {
2179 uint32_t dma_base_addr = (uint32_t)DMAx;
2180 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
2181 == (DMA_CTR1_DSEC)) ? 1UL : 0UL);
2182 }
2183 #endif /* DMA_SECCFGR_SEC0 */
2184
2185 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2186 /**
2187 * @brief Enable security attribute of the DMA transfer from the source.
2188 * @note This API is used for all available DMA channels.
2189 * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure
2190 * @param DMAx DMAx Instance
2191 * @param Channel This parameter can be one of the following values:
2192 * @arg @ref LL_DMA_CHANNEL_0
2193 * @arg @ref LL_DMA_CHANNEL_1
2194 * @arg @ref LL_DMA_CHANNEL_2
2195 * @arg @ref LL_DMA_CHANNEL_3
2196 * @arg @ref LL_DMA_CHANNEL_4
2197 * @arg @ref LL_DMA_CHANNEL_5
2198 * @arg @ref LL_DMA_CHANNEL_6
2199 * @arg @ref LL_DMA_CHANNEL_7
2200 * @retval None.
2201 */
LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2202 __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2203 {
2204 uint32_t dma_base_addr = (uint32_t)DMAx;
2205 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
2206 }
2207
2208 /**
2209 * @brief Disable security attribute of the DMA transfer from the source.
2210 * @note This API is used for all available DMA channels.
2211 * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure
2212 * @param DMAx DMAx Instance
2213 * @param Channel This parameter can be one of the following values:
2214 * @arg @ref LL_DMA_CHANNEL_0
2215 * @arg @ref LL_DMA_CHANNEL_1
2216 * @arg @ref LL_DMA_CHANNEL_2
2217 * @arg @ref LL_DMA_CHANNEL_3
2218 * @arg @ref LL_DMA_CHANNEL_4
2219 * @arg @ref LL_DMA_CHANNEL_5
2220 * @arg @ref LL_DMA_CHANNEL_6
2221 * @arg @ref LL_DMA_CHANNEL_7
2222 * @retval None.
2223 */
LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2224 __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2225 {
2226 uint32_t dma_base_addr = (uint32_t)DMAx;
2227 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
2228 }
2229 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2230
2231 #if defined (DMA_SECCFGR_SEC0)
2232 /**
2233 * @brief Check security attribute of the DMA transfer from the source.
2234 * @note This API is used for all available DMA channels.
2235 * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure
2236 * @param DMAx DMAx Instance
2237 * @param Channel This parameter can be one of the following values:
2238 * @arg @ref LL_DMA_CHANNEL_0
2239 * @arg @ref LL_DMA_CHANNEL_1
2240 * @arg @ref LL_DMA_CHANNEL_2
2241 * @arg @ref LL_DMA_CHANNEL_3
2242 * @arg @ref LL_DMA_CHANNEL_4
2243 * @arg @ref LL_DMA_CHANNEL_5
2244 * @arg @ref LL_DMA_CHANNEL_6
2245 * @arg @ref LL_DMA_CHANNEL_7
2246 * @retval State of bit (1 or 0).
2247 */
LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)2248 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
2249 {
2250 uint32_t dma_base_addr = (uint32_t)DMAx;
2251 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
2252 == (DMA_CTR1_SSEC)) ? 1UL : 0UL);
2253 }
2254 #endif /* DMA_SECCFGR_SEC0 */
2255
2256 /**
2257 * @brief Set destination allocated port.
2258 * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
2259 * @param DMAx DMAx Instance
2260 * @param Channel This parameter can be one of the following values:
2261 * @arg @ref LL_DMA_CHANNEL_0
2262 * @arg @ref LL_DMA_CHANNEL_1
2263 * @arg @ref LL_DMA_CHANNEL_2
2264 * @arg @ref LL_DMA_CHANNEL_3
2265 * @arg @ref LL_DMA_CHANNEL_4
2266 * @arg @ref LL_DMA_CHANNEL_5
2267 * @arg @ref LL_DMA_CHANNEL_6
2268 * @arg @ref LL_DMA_CHANNEL_7
2269 * @param DestAllocatedPort This parameter can be one of the following values:
2270 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2271 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2272 * @retval None.
2273 */
LL_DMA_SetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAllocatedPort)2274 __STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
2275 {
2276 uint32_t dma_base_addr = (uint32_t)DMAx;
2277 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
2278 DestAllocatedPort);
2279 }
2280
2281 /**
2282 * @brief Get destination allocated port.
2283 * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
2284 * @param DMAx DMAx Instance
2285 * @param Channel This parameter can be one of the following values:
2286 * @arg @ref LL_DMA_CHANNEL_0
2287 * @arg @ref LL_DMA_CHANNEL_1
2288 * @arg @ref LL_DMA_CHANNEL_2
2289 * @arg @ref LL_DMA_CHANNEL_3
2290 * @arg @ref LL_DMA_CHANNEL_4
2291 * @arg @ref LL_DMA_CHANNEL_5
2292 * @arg @ref LL_DMA_CHANNEL_6
2293 * @arg @ref LL_DMA_CHANNEL_7
2294 * @retval Returned value can be one of the following values:
2295 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2296 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2297 */
LL_DMA_GetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)2298 __STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
2299 {
2300 uint32_t dma_base_addr = (uint32_t)DMAx;
2301 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
2302 }
2303
2304 /**
2305 * @brief Set destination half-word exchange.
2306 * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
2307 * @param DMAx DMAx Instance
2308 * @param Channel This parameter can be one of the following values:
2309 * @arg @ref LL_DMA_CHANNEL_0
2310 * @arg @ref LL_DMA_CHANNEL_1
2311 * @arg @ref LL_DMA_CHANNEL_2
2312 * @arg @ref LL_DMA_CHANNEL_3
2313 * @arg @ref LL_DMA_CHANNEL_4
2314 * @arg @ref LL_DMA_CHANNEL_5
2315 * @arg @ref LL_DMA_CHANNEL_6
2316 * @arg @ref LL_DMA_CHANNEL_7
2317 * @param DestHWordExchange This parameter can be one of the following values:
2318 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2319 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2320 * @retval None.
2321 */
LL_DMA_SetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestHWordExchange)2322 __STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
2323 {
2324 uint32_t dma_base_addr = (uint32_t)DMAx;
2325 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
2326 DestHWordExchange);
2327 }
2328
2329 /**
2330 * @brief Get destination half-word exchange.
2331 * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
2332 * @param DMAx DMAx Instance
2333 * @param Channel This parameter can be one of the following values:
2334 * @arg @ref LL_DMA_CHANNEL_0
2335 * @arg @ref LL_DMA_CHANNEL_1
2336 * @arg @ref LL_DMA_CHANNEL_2
2337 * @arg @ref LL_DMA_CHANNEL_3
2338 * @arg @ref LL_DMA_CHANNEL_4
2339 * @arg @ref LL_DMA_CHANNEL_5
2340 * @arg @ref LL_DMA_CHANNEL_6
2341 * @arg @ref LL_DMA_CHANNEL_7
2342 * @retval Returned value can be one of the following values:
2343 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2344 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2345 */
LL_DMA_GetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2346 __STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2347 {
2348 uint32_t dma_base_addr = (uint32_t)DMAx;
2349 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
2350 }
2351
2352 /**
2353 * @brief Set destination byte exchange.
2354 * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
2355 * @param DMAx DMAx Instance
2356 * @param Channel This parameter can be one of the following values:
2357 * @arg @ref LL_DMA_CHANNEL_0
2358 * @arg @ref LL_DMA_CHANNEL_1
2359 * @arg @ref LL_DMA_CHANNEL_2
2360 * @arg @ref LL_DMA_CHANNEL_3
2361 * @arg @ref LL_DMA_CHANNEL_4
2362 * @arg @ref LL_DMA_CHANNEL_5
2363 * @arg @ref LL_DMA_CHANNEL_6
2364 * @arg @ref LL_DMA_CHANNEL_7
2365 * @param DestByteExchange This parameter can be one of the following values:
2366 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
2367 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
2368 * @retval None.
2369 */
LL_DMA_SetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestByteExchange)2370 __STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
2371 {
2372 uint32_t dma_base_addr = (uint32_t)DMAx;
2373 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
2374 DestByteExchange);
2375 }
2376
2377 /**
2378 * @brief Get destination byte exchange.
2379 * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
2380 * @param DMAx DMAx Instance
2381 * @param Channel This parameter can be one of the following values:
2382 * @arg @ref LL_DMA_CHANNEL_0
2383 * @arg @ref LL_DMA_CHANNEL_1
2384 * @arg @ref LL_DMA_CHANNEL_2
2385 * @arg @ref LL_DMA_CHANNEL_3
2386 * @arg @ref LL_DMA_CHANNEL_4
2387 * @arg @ref LL_DMA_CHANNEL_5
2388 * @arg @ref LL_DMA_CHANNEL_6
2389 * @arg @ref LL_DMA_CHANNEL_7
2390 * @retval Returned value can be one of the following values:
2391 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
2392 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
2393 */
LL_DMA_GetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2394 __STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2395 {
2396 uint32_t dma_base_addr = (uint32_t)DMAx;
2397 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
2398 }
2399
2400 /**
2401 * @brief Set source byte exchange.
2402 * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
2403 * @param DMAx DMAx Instance
2404 * @param Channel This parameter can be one of the following values:
2405 * @arg @ref LL_DMA_CHANNEL_0
2406 * @arg @ref LL_DMA_CHANNEL_1
2407 * @arg @ref LL_DMA_CHANNEL_2
2408 * @arg @ref LL_DMA_CHANNEL_3
2409 * @arg @ref LL_DMA_CHANNEL_4
2410 * @arg @ref LL_DMA_CHANNEL_5
2411 * @arg @ref LL_DMA_CHANNEL_6
2412 * @arg @ref LL_DMA_CHANNEL_7
2413 * @param SrcByteExchange This parameter can be one of the following values:
2414 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
2415 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
2416 * @retval None.
2417 */
LL_DMA_SetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcByteExchange)2418 __STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
2419 {
2420 uint32_t dma_base_addr = (uint32_t)DMAx;
2421 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
2422 SrcByteExchange);
2423 }
2424
2425 /**
2426 * @brief Get source byte exchange.
2427 * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
2428 * @param DMAx DMAx Instance
2429 * @param Channel This parameter can be one of the following values:
2430 * @arg @ref LL_DMA_CHANNEL_0
2431 * @arg @ref LL_DMA_CHANNEL_1
2432 * @arg @ref LL_DMA_CHANNEL_2
2433 * @arg @ref LL_DMA_CHANNEL_3
2434 * @arg @ref LL_DMA_CHANNEL_4
2435 * @arg @ref LL_DMA_CHANNEL_5
2436 * @arg @ref LL_DMA_CHANNEL_6
2437 * @arg @ref LL_DMA_CHANNEL_7
2438 * @retval Returned value can be one of the following values:
2439 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
2440 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
2441 */
LL_DMA_GetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2442 __STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2443 {
2444 uint32_t dma_base_addr = (uint32_t)DMAx;
2445 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
2446 }
2447
2448 /**
2449 * @brief Set destination burst length.
2450 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
2451 * @param DMAx DMAx Instance
2452 * @param Channel This parameter can be one of the following values:
2453 * @arg @ref LL_DMA_CHANNEL_0
2454 * @arg @ref LL_DMA_CHANNEL_1
2455 * @arg @ref LL_DMA_CHANNEL_2
2456 * @arg @ref LL_DMA_CHANNEL_3
2457 * @arg @ref LL_DMA_CHANNEL_4
2458 * @arg @ref LL_DMA_CHANNEL_5
2459 * @arg @ref LL_DMA_CHANNEL_6
2460 * @arg @ref LL_DMA_CHANNEL_7
2461 * @param DestBurstLength Between 1 to 64
2462 * @retval None.
2463 */
LL_DMA_SetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestBurstLength)2464 __STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
2465 {
2466 uint32_t dma_base_addr = (uint32_t)DMAx;
2467 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
2468 ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
2469 }
2470
2471 /**
2472 * @brief Get destination burst length.
2473 * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
2474 * @param DMAx DMAx Instance
2475 * @param Channel This parameter can be one of the following values:
2476 * @arg @ref LL_DMA_CHANNEL_0
2477 * @arg @ref LL_DMA_CHANNEL_1
2478 * @arg @ref LL_DMA_CHANNEL_2
2479 * @arg @ref LL_DMA_CHANNEL_3
2480 * @arg @ref LL_DMA_CHANNEL_4
2481 * @arg @ref LL_DMA_CHANNEL_5
2482 * @arg @ref LL_DMA_CHANNEL_6
2483 * @arg @ref LL_DMA_CHANNEL_7
2484 * @retval Between 1 to 64.
2485 */
LL_DMA_GetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)2486 __STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2487 {
2488 uint32_t dma_base_addr = (uint32_t)DMAx;
2489 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2490 DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
2491 }
2492
2493 /**
2494 * @brief Set destination increment mode.
2495 * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
2496 * @param DMAx DMAx Instance
2497 * @param Channel This parameter can be one of the following values:
2498 * @arg @ref LL_DMA_CHANNEL_0
2499 * @arg @ref LL_DMA_CHANNEL_1
2500 * @arg @ref LL_DMA_CHANNEL_2
2501 * @arg @ref LL_DMA_CHANNEL_3
2502 * @arg @ref LL_DMA_CHANNEL_4
2503 * @arg @ref LL_DMA_CHANNEL_5
2504 * @arg @ref LL_DMA_CHANNEL_6
2505 * @arg @ref LL_DMA_CHANNEL_7
2506 * @param DestInc This parameter can be one of the following values:
2507 * @arg @ref LL_DMA_DEST_FIXED
2508 * @arg @ref LL_DMA_DEST_INCREMENT
2509 * @retval None.
2510 */
LL_DMA_SetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestInc)2511 __STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
2512 {
2513 uint32_t dma_base_addr = (uint32_t)DMAx;
2514 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
2515 }
2516
2517 /**
2518 * @brief Get destination increment mode.
2519 * @note This API is used for all available DMA channels.
2520 * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode
2521 * @param DMAx DMAx Instance
2522 * @param Channel This parameter can be one of the following values:
2523 * @arg @ref LL_DMA_CHANNEL_0
2524 * @arg @ref LL_DMA_CHANNEL_1
2525 * @arg @ref LL_DMA_CHANNEL_2
2526 * @arg @ref LL_DMA_CHANNEL_3
2527 * @arg @ref LL_DMA_CHANNEL_4
2528 * @arg @ref LL_DMA_CHANNEL_5
2529 * @arg @ref LL_DMA_CHANNEL_6
2530 * @arg @ref LL_DMA_CHANNEL_7
2531 * @retval Returned value can be one of the following values:
2532 * @arg @ref LL_DMA_DEST_FIXED
2533 * @arg @ref LL_DMA_DEST_INCREMENT
2534 */
LL_DMA_GetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)2535 __STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2536 {
2537 uint32_t dma_base_addr = (uint32_t)DMAx;
2538 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
2539 }
2540
2541 /**
2542 * @brief Set destination data width.
2543 * @note This API is used for all available DMA channels.
2544 * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
2545 * @param DMAx DMAx Instance
2546 * @param Channel This parameter can be one of the following values:
2547 * @arg @ref LL_DMA_CHANNEL_0
2548 * @arg @ref LL_DMA_CHANNEL_1
2549 * @arg @ref LL_DMA_CHANNEL_2
2550 * @arg @ref LL_DMA_CHANNEL_3
2551 * @arg @ref LL_DMA_CHANNEL_4
2552 * @arg @ref LL_DMA_CHANNEL_5
2553 * @arg @ref LL_DMA_CHANNEL_6
2554 * @arg @ref LL_DMA_CHANNEL_7
2555 * @param DestDataWidth This parameter can be one of the following values:
2556 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
2557 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
2558 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
2559 * @retval None.
2560 */
LL_DMA_SetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestDataWidth)2561 __STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
2562 {
2563 uint32_t dma_base_addr = (uint32_t)DMAx;
2564 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
2565 DestDataWidth);
2566 }
2567
2568 /**
2569 * @brief Get destination data width.
2570 * @note This API is used for all available DMA channels.
2571 * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
2572 * @param DMAx DMAx Instance
2573 * @param Channel This parameter can be one of the following values:
2574 * @arg @ref LL_DMA_CHANNEL_0
2575 * @arg @ref LL_DMA_CHANNEL_1
2576 * @arg @ref LL_DMA_CHANNEL_2
2577 * @arg @ref LL_DMA_CHANNEL_3
2578 * @arg @ref LL_DMA_CHANNEL_4
2579 * @arg @ref LL_DMA_CHANNEL_5
2580 * @arg @ref LL_DMA_CHANNEL_6
2581 * @arg @ref LL_DMA_CHANNEL_7
2582 * @retval Returned value can be one of the following values:
2583 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
2584 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
2585 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
2586 */
LL_DMA_GetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)2587 __STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
2588 {
2589 uint32_t dma_base_addr = (uint32_t)DMAx;
2590 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
2591 }
2592
2593 /**
2594 * @brief Set source allocated port.
2595 * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
2596 * @param DMAx DMAx Instance
2597 * @param Channel This parameter can be one of the following values:
2598 * @arg @ref LL_DMA_CHANNEL_0
2599 * @arg @ref LL_DMA_CHANNEL_1
2600 * @arg @ref LL_DMA_CHANNEL_2
2601 * @arg @ref LL_DMA_CHANNEL_3
2602 * @arg @ref LL_DMA_CHANNEL_4
2603 * @arg @ref LL_DMA_CHANNEL_5
2604 * @arg @ref LL_DMA_CHANNEL_6
2605 * @arg @ref LL_DMA_CHANNEL_7
2606 * @param SrcAllocatedPort This parameter can be one of the following values:
2607 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
2608 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
2609 * @retval None.
2610 */
LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAllocatedPort)2611 __STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
2612 {
2613 uint32_t dma_base_addr = (uint32_t)DMAx;
2614 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
2615 SrcAllocatedPort);
2616 }
2617
2618 /**
2619 * @brief Get source allocated port.
2620 * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
2621 * @param DMAx DMAx Instance
2622 * @param Channel This parameter can be one of the following values:
2623 * @arg @ref LL_DMA_CHANNEL_0
2624 * @arg @ref LL_DMA_CHANNEL_1
2625 * @arg @ref LL_DMA_CHANNEL_2
2626 * @arg @ref LL_DMA_CHANNEL_3
2627 * @arg @ref LL_DMA_CHANNEL_4
2628 * @arg @ref LL_DMA_CHANNEL_5
2629 * @arg @ref LL_DMA_CHANNEL_6
2630 * @arg @ref LL_DMA_CHANNEL_7
2631 * @retval Returned value can be one of the following values:
2632 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
2633 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
2634 */
LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)2635 __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
2636 {
2637 uint32_t dma_base_addr = (uint32_t)DMAx;
2638 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
2639 }
2640
2641 /**
2642 * @brief Set data alignment mode.
2643 * @note This API is used for all available DMA channels.
2644 * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
2645 * @param DMAx DMAx Instance
2646 * @param Channel This parameter can be one of the following values:
2647 * @arg @ref LL_DMA_CHANNEL_0
2648 * @arg @ref LL_DMA_CHANNEL_1
2649 * @arg @ref LL_DMA_CHANNEL_2
2650 * @arg @ref LL_DMA_CHANNEL_3
2651 * @arg @ref LL_DMA_CHANNEL_4
2652 * @arg @ref LL_DMA_CHANNEL_5
2653 * @arg @ref LL_DMA_CHANNEL_6
2654 * @arg @ref LL_DMA_CHANNEL_7
2655 * @param DataAlignment This parameter can be one of the following values:
2656 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2657 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2658 * @arg @ref LL_DMA_DATA_PACK_UNPACK
2659 * @retval None.
2660 */
LL_DMA_SetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DataAlignment)2661 __STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
2662 {
2663 uint32_t dma_base_addr = (uint32_t)DMAx;
2664 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
2665 DataAlignment);
2666 }
2667
2668 /**
2669 * @brief Get data alignment mode.
2670 * @note This API is used for all available DMA channels.
2671 * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
2672 * @param DMAx DMAx Instance
2673 * @param Channel This parameter can be one of the following values:
2674 * @arg @ref LL_DMA_CHANNEL_0
2675 * @arg @ref LL_DMA_CHANNEL_1
2676 * @arg @ref LL_DMA_CHANNEL_2
2677 * @arg @ref LL_DMA_CHANNEL_3
2678 * @arg @ref LL_DMA_CHANNEL_4
2679 * @arg @ref LL_DMA_CHANNEL_5
2680 * @arg @ref LL_DMA_CHANNEL_6
2681 * @arg @ref LL_DMA_CHANNEL_7
2682 * @retval Returned value can be one of the following values:
2683 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2684 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2685 * @arg @ref LL_DMA_DATA_PACK_UNPACK
2686 */
LL_DMA_GetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel)2687 __STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel)
2688 {
2689 uint32_t dma_base_addr = (uint32_t)DMAx;
2690 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
2691 }
2692
2693 /**
2694 * @brief Set source burst length.
2695 * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
2696 * @param DMAx DMAx Instance
2697 * @param Channel This parameter can be one of the following values:
2698 * @arg @ref LL_DMA_CHANNEL_0
2699 * @arg @ref LL_DMA_CHANNEL_1
2700 * @arg @ref LL_DMA_CHANNEL_2
2701 * @arg @ref LL_DMA_CHANNEL_3
2702 * @arg @ref LL_DMA_CHANNEL_4
2703 * @arg @ref LL_DMA_CHANNEL_5
2704 * @arg @ref LL_DMA_CHANNEL_6
2705 * @arg @ref LL_DMA_CHANNEL_7
2706 * @param SrcBurstLength Between 1 to 64
2707 * @retval None.
2708 */
LL_DMA_SetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength)2709 __STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
2710 {
2711 uint32_t dma_base_addr = (uint32_t)DMAx;
2712 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
2713 ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
2714 }
2715
2716 /**
2717 * @brief Get source burst length.
2718 * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
2719 * @param DMAx DMAx Instance
2720 * @param Channel This parameter can be one of the following values:
2721 * @arg @ref LL_DMA_CHANNEL_0
2722 * @arg @ref LL_DMA_CHANNEL_1
2723 * @arg @ref LL_DMA_CHANNEL_2
2724 * @arg @ref LL_DMA_CHANNEL_3
2725 * @arg @ref LL_DMA_CHANNEL_4
2726 * @arg @ref LL_DMA_CHANNEL_5
2727 * @arg @ref LL_DMA_CHANNEL_6
2728 * @arg @ref LL_DMA_CHANNEL_7
2729 * @retval Between 1 to 64
2730 * @retval None.
2731 */
LL_DMA_GetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)2732 __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2733 {
2734 uint32_t dma_base_addr = (uint32_t)DMAx;
2735 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2736 DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
2737 }
2738
2739 /**
2740 * @brief Set source increment mode.
2741 * @note This API is used for all available DMA channels.
2742 * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
2743 * @param DMAx DMAx Instance
2744 * @param Channel This parameter can be one of the following values:
2745 * @arg @ref LL_DMA_CHANNEL_0
2746 * @arg @ref LL_DMA_CHANNEL_1
2747 * @arg @ref LL_DMA_CHANNEL_2
2748 * @arg @ref LL_DMA_CHANNEL_3
2749 * @arg @ref LL_DMA_CHANNEL_4
2750 * @arg @ref LL_DMA_CHANNEL_5
2751 * @arg @ref LL_DMA_CHANNEL_6
2752 * @arg @ref LL_DMA_CHANNEL_7
2753 * @param SrcInc This parameter can be one of the following values:
2754 * @arg @ref LL_DMA_SRC_FIXED
2755 * @arg @ref LL_DMA_SRC_INCREMENT
2756 * @retval None.
2757 */
LL_DMA_SetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcInc)2758 __STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
2759 {
2760 uint32_t dma_base_addr = (uint32_t)DMAx;
2761 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
2762 }
2763
2764 /**
2765 * @brief Get source increment mode.
2766 * @note This API is used for all available DMA channels.
2767 * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
2768 * @param DMAx DMAx Instance
2769 * @param Channel This parameter can be one of the following values:
2770 * @arg @ref LL_DMA_CHANNEL_0
2771 * @arg @ref LL_DMA_CHANNEL_1
2772 * @arg @ref LL_DMA_CHANNEL_2
2773 * @arg @ref LL_DMA_CHANNEL_3
2774 * @arg @ref LL_DMA_CHANNEL_4
2775 * @arg @ref LL_DMA_CHANNEL_5
2776 * @arg @ref LL_DMA_CHANNEL_6
2777 * @arg @ref LL_DMA_CHANNEL_7
2778 * @retval Returned value can be one of the following values:
2779 * @arg @ref LL_DMA_SRC_FIXED
2780 * @arg @ref LL_DMA_SRC_INCREMENT
2781 */
LL_DMA_GetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)2782 __STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2783 {
2784 uint32_t dma_base_addr = (uint32_t)DMAx;
2785 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
2786 }
2787
2788 /**
2789 * @brief Set source data width.
2790 * @note This API is used for all available DMA channels.
2791 * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
2792 * @param DMAx DMAx Instance
2793 * @param Channel This parameter can be one of the following values:
2794 * @arg @ref LL_DMA_CHANNEL_0
2795 * @arg @ref LL_DMA_CHANNEL_1
2796 * @arg @ref LL_DMA_CHANNEL_2
2797 * @arg @ref LL_DMA_CHANNEL_3
2798 * @arg @ref LL_DMA_CHANNEL_4
2799 * @arg @ref LL_DMA_CHANNEL_5
2800 * @arg @ref LL_DMA_CHANNEL_6
2801 * @arg @ref LL_DMA_CHANNEL_7
2802 * @param SrcDataWidth This parameter can be one of the following values:
2803 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2804 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2805 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2806 * @retval None.
2807 */
LL_DMA_SetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcDataWidth)2808 __STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
2809 {
2810 uint32_t dma_base_addr = (uint32_t)DMAx;
2811 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
2812 SrcDataWidth);
2813 }
2814
2815 /**
2816 * @brief Get Source Data width.
2817 * @note This API is used for all available DMA channels.
2818 * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
2819 * @param DMAx DMAx Instance
2820 * @param Channel This parameter can be one of the following values:
2821 * @arg @ref LL_DMA_CHANNEL_0
2822 * @arg @ref LL_DMA_CHANNEL_1
2823 * @arg @ref LL_DMA_CHANNEL_2
2824 * @arg @ref LL_DMA_CHANNEL_3
2825 * @arg @ref LL_DMA_CHANNEL_4
2826 * @arg @ref LL_DMA_CHANNEL_5
2827 * @arg @ref LL_DMA_CHANNEL_6
2828 * @arg @ref LL_DMA_CHANNEL_7
2829 * @retval Returned value can be one of the following values:
2830 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2831 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2832 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2833 */
LL_DMA_GetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)2834 __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
2835 {
2836 uint32_t dma_base_addr = (uint32_t)DMAx;
2837 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
2838 }
2839
2840 /**
2841 * @brief Configure channel transfer.
2842 * @note This API is used for all available DMA channels.
2843 * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
2844 * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
2845 * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
2846 * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
2847 * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
2848 * CTR2 SWREQ LL_DMA_ConfigChannelTransfer\n
2849 * CTR2 PFREQ LL_DMA_ConfigChannelTransfer
2850 * @param DMAx DMAx Instance
2851 * @param Channel This parameter can be one of the following values:
2852 * @arg @ref LL_DMA_CHANNEL_0
2853 * @arg @ref LL_DMA_CHANNEL_1
2854 * @arg @ref LL_DMA_CHANNEL_2
2855 * @arg @ref LL_DMA_CHANNEL_3
2856 * @arg @ref LL_DMA_CHANNEL_4
2857 * @arg @ref LL_DMA_CHANNEL_5
2858 * @arg @ref LL_DMA_CHANNEL_6
2859 * @arg @ref LL_DMA_CHANNEL_7
2860 * @param Configuration This parameter must be a combination of all the following values:
2861 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
2862 * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2863 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK
2864 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or
2865 * @ref LL_DMA_TRIG_POLARITY_FALLING
2866 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
2867 * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
2868 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
2869 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
2870 * @arg @ref LL_DMA_NORMAL or @ref LL_DMA_PFCTRL
2871 *@retval None.
2872 */
LL_DMA_ConfigChannelTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2873 __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2874 {
2875 uint32_t dma_base_addr = (uint32_t)DMAx;
2876 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2877 (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ |
2878 DMA_CTR2_PFREQ), Configuration);
2879 }
2880
2881 /**
2882 * @brief Set transfer event mode.
2883 * @note This API is used for all available DMA channels.
2884 * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
2885 * @param DMAx DMAx Instance
2886 * @param Channel This parameter can be one of the following values:
2887 * @arg @ref LL_DMA_CHANNEL_0
2888 * @arg @ref LL_DMA_CHANNEL_1
2889 * @arg @ref LL_DMA_CHANNEL_2
2890 * @arg @ref LL_DMA_CHANNEL_3
2891 * @arg @ref LL_DMA_CHANNEL_4
2892 * @arg @ref LL_DMA_CHANNEL_5
2893 * @arg @ref LL_DMA_CHANNEL_6
2894 * @arg @ref LL_DMA_CHANNEL_7
2895 * @param TransferEventMode This parameter can be one of the following values:
2896 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
2897 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
2898 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
2899 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2900 * @retval None.
2901 */
LL_DMA_SetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TransferEventMode)2902 __STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
2903 {
2904 uint32_t dma_base_addr = (uint32_t)DMAx;
2905 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
2906 TransferEventMode);
2907 }
2908
2909 /**
2910 * @brief Get transfer event mode.
2911 * @note This API is used for all available DMA channels.
2912 * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
2913 * @param DMAx DMAx Instance
2914 * @param Channel This parameter can be one of the following values:
2915 * @arg @ref LL_DMA_CHANNEL_0
2916 * @arg @ref LL_DMA_CHANNEL_1
2917 * @arg @ref LL_DMA_CHANNEL_2
2918 * @arg @ref LL_DMA_CHANNEL_3
2919 * @arg @ref LL_DMA_CHANNEL_4
2920 * @arg @ref LL_DMA_CHANNEL_5
2921 * @arg @ref LL_DMA_CHANNEL_6
2922 * @arg @ref LL_DMA_CHANNEL_7
2923 * @retval Returned value can be one of the following values:
2924 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
2925 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
2926 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
2927 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2928 */
LL_DMA_GetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel)2929 __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2930 {
2931 uint32_t dma_base_addr = (uint32_t)DMAx;
2932 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
2933 }
2934
2935 /**
2936 * @brief Set trigger polarity.
2937 * @note This API is used for all available DMA channels.
2938 * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
2939 * @param DMAx DMAx Instance
2940 * @param Channel This parameter can be one of the following values:
2941 * @arg @ref LL_DMA_CHANNEL_0
2942 * @arg @ref LL_DMA_CHANNEL_1
2943 * @arg @ref LL_DMA_CHANNEL_2
2944 * @arg @ref LL_DMA_CHANNEL_3
2945 * @arg @ref LL_DMA_CHANNEL_4
2946 * @arg @ref LL_DMA_CHANNEL_5
2947 * @arg @ref LL_DMA_CHANNEL_6
2948 * @arg @ref LL_DMA_CHANNEL_7
2949 * @param TriggerPolarity This parameter can be one of the following values:
2950 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
2951 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
2952 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
2953 * @retval None.
2954 */
LL_DMA_SetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerPolarity)2955 __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
2956 {
2957 uint32_t dma_base_addr = (uint32_t)DMAx;
2958 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
2959 TriggerPolarity);
2960 }
2961
2962 /**
2963 * @brief Get trigger polarity.
2964 * @note This API is used for all available DMA channels.
2965 * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
2966 * @param DMAx DMAx Instance
2967 * @param Channel This parameter can be one of the following values:
2968 * @arg @ref LL_DMA_CHANNEL_0
2969 * @arg @ref LL_DMA_CHANNEL_1
2970 * @arg @ref LL_DMA_CHANNEL_2
2971 * @arg @ref LL_DMA_CHANNEL_3
2972 * @arg @ref LL_DMA_CHANNEL_4
2973 * @arg @ref LL_DMA_CHANNEL_5
2974 * @arg @ref LL_DMA_CHANNEL_6
2975 * @arg @ref LL_DMA_CHANNEL_7
2976 * @retval Returned value can be one of the following values:
2977 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
2978 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
2979 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
2980 */
LL_DMA_GetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel)2981 __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel)
2982 {
2983 uint32_t dma_base_addr = (uint32_t)DMAx;
2984 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
2985 }
2986
2987 /**
2988 * @brief Set trigger Mode.
2989 * @note This API is used for all available DMA channels.
2990 * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
2991 * @param DMAx DMAx Instance
2992 * @param Channel This parameter can be one of the following values:
2993 * @arg @ref LL_DMA_CHANNEL_0
2994 * @arg @ref LL_DMA_CHANNEL_1
2995 * @arg @ref LL_DMA_CHANNEL_2
2996 * @arg @ref LL_DMA_CHANNEL_3
2997 * @arg @ref LL_DMA_CHANNEL_4
2998 * @arg @ref LL_DMA_CHANNEL_5
2999 * @arg @ref LL_DMA_CHANNEL_6
3000 * @arg @ref LL_DMA_CHANNEL_7
3001 * @param TriggerMode This parameter can be one of the following values:
3002 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3003 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3004 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3005 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3006 * @retval None.
3007 */
LL_DMA_SetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerMode)3008 __STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
3009 {
3010 uint32_t dma_base_addr = (uint32_t)DMAx;
3011 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
3012 TriggerMode);
3013 }
3014
3015 /**
3016 * @brief Get trigger Mode.
3017 * @note This API is used for all available DMA channels.
3018 * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
3019 * @param DMAx DMAx Instance
3020 * @param Channel This parameter can be one of the following values:
3021 * @arg @ref LL_DMA_CHANNEL_0
3022 * @arg @ref LL_DMA_CHANNEL_1
3023 * @arg @ref LL_DMA_CHANNEL_2
3024 * @arg @ref LL_DMA_CHANNEL_3
3025 * @arg @ref LL_DMA_CHANNEL_4
3026 * @arg @ref LL_DMA_CHANNEL_5
3027 * @arg @ref LL_DMA_CHANNEL_6
3028 * @arg @ref LL_DMA_CHANNEL_7
3029 * @retval Returned value can be one of the following values:
3030 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3031 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3032 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3033 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3034 */
LL_DMA_GetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel)3035 __STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3036 {
3037 uint32_t dma_base_addr = (uint32_t)DMAx;
3038 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
3039 }
3040
3041 /**
3042 * @brief Set destination hardware and software transfer request.
3043 * @note This API is used for all available DMA channels.
3044 * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
3045 * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
3046 * @param DMAx DMAx Instance
3047 * @param Channel This parameter can be one of the following values:
3048 * @arg @ref LL_DMA_CHANNEL_0
3049 * @arg @ref LL_DMA_CHANNEL_1
3050 * @arg @ref LL_DMA_CHANNEL_2
3051 * @arg @ref LL_DMA_CHANNEL_3
3052 * @arg @ref LL_DMA_CHANNEL_4
3053 * @arg @ref LL_DMA_CHANNEL_5
3054 * @arg @ref LL_DMA_CHANNEL_6
3055 * @arg @ref LL_DMA_CHANNEL_7
3056 * @param Direction This parameter can be one of the following values:
3057 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3058 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
3059 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3060 * @retval None.
3061 */
LL_DMA_SetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)3062 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
3063 {
3064 uint32_t dma_base_addr = (uint32_t)DMAx;
3065 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3066 DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
3067 }
3068
3069 /**
3070 * @brief Get destination hardware and software transfer request.
3071 * @note This API is used for all available DMA channels.
3072 * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
3073 * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
3074 * @param DMAx DMAx Instance
3075 * @param Channel This parameter can be one of the following values:
3076 * @arg @ref LL_DMA_CHANNEL_0
3077 * @arg @ref LL_DMA_CHANNEL_1
3078 * @arg @ref LL_DMA_CHANNEL_2
3079 * @arg @ref LL_DMA_CHANNEL_3
3080 * @arg @ref LL_DMA_CHANNEL_4
3081 * @arg @ref LL_DMA_CHANNEL_5
3082 * @arg @ref LL_DMA_CHANNEL_6
3083 * @arg @ref LL_DMA_CHANNEL_7
3084 * @retval Returned value can be one of the following values:
3085 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3086 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
3087 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3088 */
LL_DMA_GetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel)3089 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
3090 {
3091 uint32_t dma_base_addr = (uint32_t)DMAx;
3092 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3093 DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
3094 }
3095
3096 /**
3097 * @brief Set block hardware request.
3098 * @note This API is used for all available DMA channels.
3099 * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
3100 * @param DMAx DMAx Instance
3101 * @param Channel This parameter can be one of the following values:
3102 * @arg @ref LL_DMA_CHANNEL_0
3103 * @arg @ref LL_DMA_CHANNEL_1
3104 * @arg @ref LL_DMA_CHANNEL_2
3105 * @arg @ref LL_DMA_CHANNEL_3
3106 * @arg @ref LL_DMA_CHANNEL_4
3107 * @arg @ref LL_DMA_CHANNEL_5
3108 * @arg @ref LL_DMA_CHANNEL_6
3109 * @arg @ref LL_DMA_CHANNEL_7
3110 * @param BlkHWRequest This parameter can be one of the following values:
3111 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3112 * @arg @ref LL_DMA_HWREQUEST_BLK
3113 * @retval None.
3114 */
LL_DMA_SetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkHWRequest)3115 __STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
3116 {
3117 uint32_t dma_base_addr = (uint32_t)DMAx;
3118 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
3119 BlkHWRequest);
3120 }
3121
3122 /**
3123 * @brief Get block hardware request.
3124 * @note This API is used for all available DMA channels.
3125 * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
3126 * @param DMAx DMAx Instance
3127 * @param Channel This parameter can be one of the following values:
3128 * @arg @ref LL_DMA_CHANNEL_0
3129 * @arg @ref LL_DMA_CHANNEL_1
3130 * @arg @ref LL_DMA_CHANNEL_2
3131 * @arg @ref LL_DMA_CHANNEL_3
3132 * @arg @ref LL_DMA_CHANNEL_4
3133 * @arg @ref LL_DMA_CHANNEL_5
3134 * @arg @ref LL_DMA_CHANNEL_6
3135 * @arg @ref LL_DMA_CHANNEL_7
3136 * @retval Returned value can be one of the following values:
3137 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3138 * @arg @ref LL_DMA_HWREQUEST_BLK
3139 */
LL_DMA_GetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel)3140 __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
3141 {
3142 uint32_t dma_base_addr = (uint32_t)DMAx;
3143 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
3144 }
3145
3146 /**
3147 * @brief Set hardware request.
3148 * @note This API is used for all available DMA channels.
3149 * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
3150 * @param DMAx DMAx Instance
3151 * @param Channel This parameter can be one of the following values:
3152 * @arg @ref LL_DMA_CHANNEL_0
3153 * @arg @ref LL_DMA_CHANNEL_1
3154 * @arg @ref LL_DMA_CHANNEL_2
3155 * @arg @ref LL_DMA_CHANNEL_3
3156 * @arg @ref LL_DMA_CHANNEL_4
3157 * @arg @ref LL_DMA_CHANNEL_5
3158 * @arg @ref LL_DMA_CHANNEL_6
3159 * @arg @ref LL_DMA_CHANNEL_7
3160 * @param Request This parameter can be one of the following values:
3161 * @arg @ref LL_GPDMA1_REQUEST_ADC1
3162 * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*)
3163 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
3164 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
3165 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
3166 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
3167 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
3168 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
3169 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
3170 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
3171 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
3172 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
3173 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
3174 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
3175 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
3176 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
3177 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX (*)
3178 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX (*)
3179 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
3180 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
3181 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
3182 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
3183 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
3184 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
3185 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX (*)
3186 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX (*)
3187 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX (*)
3188 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX (*)
3189 * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*)
3190 * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*)
3191 * @arg @ref LL_GPDMA1_REQUEST_UART7_RX (*)
3192 * @arg @ref LL_GPDMA1_REQUEST_UART7_TX (*)
3193 * @arg @ref LL_GPDMA1_REQUEST_UART8_RX (*)
3194 * @arg @ref LL_GPDMA1_REQUEST_UART8_TX (*)
3195 * @arg @ref LL_GPDMA1_REQUEST_UART9_RX (*)
3196 * @arg @ref LL_GPDMA1_REQUEST_UART9_TX (*)
3197 * @arg @ref LL_GPDMA1_REQUEST_USART10_RX (*)
3198 * @arg @ref LL_GPDMA1_REQUEST_USART10_TX (*)
3199 * @arg @ref LL_GPDMA1_REQUEST_USART11_RX (*)
3200 * @arg @ref LL_GPDMA1_REQUEST_USART11_TX (*)
3201 * @arg @ref LL_GPDMA1_REQUEST_UART12_RX (*)
3202 * @arg @ref LL_GPDMA1_REQUEST_UART12_TX (*)
3203 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
3204 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
3205 * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX (*)
3206 * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX (*)
3207 * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX (*)
3208 * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX (*)
3209 * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX (*)
3210 * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX (*)
3211 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*)
3212 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*)
3213 * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*)
3214 * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*)
3215 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 (*)
3216 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
3217 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
3218 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
3219 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
3220 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
3221 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
3222 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
3223 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 (*)
3224 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 (*)
3225 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 (*)
3226 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 (*)
3227 * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP (*)
3228 * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG (*)
3229 * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM (*)
3230 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
3231 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
3232 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
3233 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
3234 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
3235 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
3236 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
3237 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
3238 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
3239 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
3240 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
3241 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*)
3242 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*)
3243 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*)
3244 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*)
3245 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*)
3246 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 (*)
3247 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 (*)
3248 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 (*)
3249 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 (*)
3250 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP (*)
3251 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG (*)
3252 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 (*)
3253 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP (*)
3254 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG (*)
3255 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM (*)
3256 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 (*)
3257 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP (*)
3258 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*)
3259 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*)
3260 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
3261 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
3262 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
3263 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
3264 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
3265 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
3266 * @arg @ref LL_GPDMA1_REQUEST_DCMI (*)
3267 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*)
3268 * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*)
3269 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
3270 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*)
3271 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*)
3272 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ (*)
3273 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE (*)
3274 * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ (*)
3275 * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE (*)
3276 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*)
3277 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*)
3278 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
3279 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
3280 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
3281 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
3282 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*)
3283 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*)
3284 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 (*)
3285 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 (*)
3286 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE (*)
3287 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC1 (*)
3288 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC2 (*)
3289 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_UE (*)
3290 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC1 (*)
3291 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC2 (*)
3292 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_UE (*)
3293 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX (*)
3294 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX (*)
3295 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC (*)
3296 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS (*)
3297 *
3298 * @arg @ref LL_GPDMA2_REQUEST_ADC1
3299 * @arg @ref LL_GPDMA2_REQUEST_ADC2 (*)
3300 * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH1
3301 * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH2
3302 * @arg @ref LL_GPDMA2_REQUEST_TIM6_UP
3303 * @arg @ref LL_GPDMA2_REQUEST_TIM7_UP
3304 * @arg @ref LL_GPDMA2_REQUEST_SPI1_RX
3305 * @arg @ref LL_GPDMA2_REQUEST_SPI1_TX
3306 * @arg @ref LL_GPDMA2_REQUEST_SPI2_RX
3307 * @arg @ref LL_GPDMA2_REQUEST_SPI2_TX
3308 * @arg @ref LL_GPDMA2_REQUEST_SPI3_RX
3309 * @arg @ref LL_GPDMA2_REQUEST_SPI3_TX
3310 * @arg @ref LL_GPDMA2_REQUEST_I2C1_RX
3311 * @arg @ref LL_GPDMA2_REQUEST_I2C1_TX
3312 * @arg @ref LL_GPDMA2_REQUEST_I2C2_RX
3313 * @arg @ref LL_GPDMA2_REQUEST_I2C2_TX
3314 * @arg @ref LL_GPDMA2_REQUEST_I2C3_RX (*)
3315 * @arg @ref LL_GPDMA2_REQUEST_I2C3_TX (*)
3316 * @arg @ref LL_GPDMA2_REQUEST_USART1_RX
3317 * @arg @ref LL_GPDMA2_REQUEST_USART1_TX
3318 * @arg @ref LL_GPDMA2_REQUEST_USART2_RX
3319 * @arg @ref LL_GPDMA2_REQUEST_USART2_TX
3320 * @arg @ref LL_GPDMA2_REQUEST_USART3_RX
3321 * @arg @ref LL_GPDMA2_REQUEST_USART3_TX
3322 * @arg @ref LL_GPDMA2_REQUEST_UART4_RX (*)
3323 * @arg @ref LL_GPDMA2_REQUEST_UART4_TX (*)
3324 * @arg @ref LL_GPDMA2_REQUEST_UART5_RX (*)
3325 * @arg @ref LL_GPDMA2_REQUEST_UART5_TX (*)
3326 * @arg @ref LL_GPDMA2_REQUEST_USART6_RX (*)
3327 * @arg @ref LL_GPDMA2_REQUEST_USART6_TX (*)
3328 * @arg @ref LL_GPDMA2_REQUEST_UART7_RX (*)
3329 * @arg @ref LL_GPDMA2_REQUEST_UART7_TX (*)
3330 * @arg @ref LL_GPDMA2_REQUEST_UART8_RX (*)
3331 * @arg @ref LL_GPDMA2_REQUEST_UART8_TX (*)
3332 * @arg @ref LL_GPDMA2_REQUEST_UART9_RX (*)
3333 * @arg @ref LL_GPDMA2_REQUEST_UART9_TX (*)
3334 * @arg @ref LL_GPDMA2_REQUEST_USART10_RX (*)
3335 * @arg @ref LL_GPDMA2_REQUEST_USART10_TX (*)
3336 * @arg @ref LL_GPDMA2_REQUEST_USART11_RX (*)
3337 * @arg @ref LL_GPDMA2_REQUEST_USART11_TX (*)
3338 * @arg @ref LL_GPDMA2_REQUEST_UART12_RX (*)
3339 * @arg @ref LL_GPDMA2_REQUEST_UART12_TX (*)
3340 * @arg @ref LL_GPDMA2_REQUEST_LPUART1_RX
3341 * @arg @ref LL_GPDMA2_REQUEST_LPUART1_TX
3342 * @arg @ref LL_GPDMA2_REQUEST_SPI4_RX (*)
3343 * @arg @ref LL_GPDMA2_REQUEST_SPI4_TX (*)
3344 * @arg @ref LL_GPDMA2_REQUEST_SPI5_RX (*)
3345 * @arg @ref LL_GPDMA2_REQUEST_SPI5_TX (*)
3346 * @arg @ref LL_GPDMA2_REQUEST_SPI6_RX (*)
3347 * @arg @ref LL_GPDMA2_REQUEST_SPI6_TX (*)
3348 * @arg @ref LL_GPDMA2_REQUEST_SAI1_A (*)
3349 * @arg @ref LL_GPDMA2_REQUEST_SAI1_B (*)
3350 * @arg @ref LL_GPDMA2_REQUEST_SAI2_A (*)
3351 * @arg @ref LL_GPDMA2_REQUEST_SAI2_B (*)
3352 * @arg @ref LL_GPDMA2_REQUEST_OCTOSPI1 (*)
3353 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH1
3354 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH2
3355 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH3
3356 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH4
3357 * @arg @ref LL_GPDMA2_REQUEST_TIM1_UP
3358 * @arg @ref LL_GPDMA2_REQUEST_TIM1_TRIG
3359 * @arg @ref LL_GPDMA2_REQUEST_TIM1_COM
3360 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH1 (*)
3361 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH2 (*)
3362 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH3 (*)
3363 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH4 (*)
3364 * @arg @ref LL_GPDMA2_REQUEST_TIM8_UP (*)
3365 * @arg @ref LL_GPDMA2_REQUEST_TIM8_TRIG (*)
3366 * @arg @ref LL_GPDMA2_REQUEST_TIM8_COM (*)
3367 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH1
3368 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH2
3369 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH3
3370 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH4
3371 * @arg @ref LL_GPDMA2_REQUEST_TIM2_UP
3372 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH1
3373 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH2
3374 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH3
3375 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH4
3376 * @arg @ref LL_GPDMA2_REQUEST_TIM3_UP
3377 * @arg @ref LL_GPDMA2_REQUEST_TIM3_TRIG
3378 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH1 (*)
3379 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH2 (*)
3380 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH3 (*)
3381 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH4 (*)
3382 * @arg @ref LL_GPDMA2_REQUEST_TIM4_UP (*)
3383 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH1 (*)
3384 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH2 (*)
3385 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH3 (*)
3386 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH4 (*)
3387 * @arg @ref LL_GPDMA2_REQUEST_TIM5_UP (*)
3388 * @arg @ref LL_GPDMA2_REQUEST_TIM5_TRIG (*)
3389 * @arg @ref LL_GPDMA2_REQUEST_TIM15_CH1 (*)
3390 * @arg @ref LL_GPDMA2_REQUEST_TIM15_UP (*)
3391 * @arg @ref LL_GPDMA2_REQUEST_TIM15_TRIG (*)
3392 * @arg @ref LL_GPDMA2_REQUEST_TIM15_COM (*)
3393 * @arg @ref LL_GPDMA2_REQUEST_TIM16_CH1 (*)
3394 * @arg @ref LL_GPDMA2_REQUEST_TIM16_UP (*)
3395 * @arg @ref LL_GPDMA2_REQUEST_TIM17_CH1 (*)
3396 * @arg @ref LL_GPDMA2_REQUEST_TIM17_UP (*)
3397 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC1
3398 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC2
3399 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_UE
3400 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC1
3401 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC2
3402 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_UE
3403 * @arg @ref LL_GPDMA2_REQUEST_DCMI (*)
3404 * @arg @ref LL_GPDMA2_REQUEST_AES_OUT (*)
3405 * @arg @ref LL_GPDMA2_REQUEST_AES_IN (*)
3406 * @arg @ref LL_GPDMA2_REQUEST_HASH_IN
3407 * @arg @ref LL_GPDMA2_REQUEST_UCPD1_RX (*)
3408 * @arg @ref LL_GPDMA2_REQUEST_UCPD1_TX (*)
3409 * @arg @ref LL_GPDMA2_REQUEST_CORDIC_READ (*)
3410 * @arg @ref LL_GPDMA2_REQUEST_CORDIC_WRITE (*)
3411 * @arg @ref LL_GPDMA2_REQUEST_FMAC_READ (*)
3412 * @arg @ref LL_GPDMA2_REQUEST_FMAC_WRITE (*)
3413 * @arg @ref LL_GPDMA2_REQUEST_SAES_OUT (*)
3414 * @arg @ref LL_GPDMA2_REQUEST_SAES_IN (*)
3415 * @arg @ref LL_GPDMA2_REQUEST_I3C1_RX
3416 * @arg @ref LL_GPDMA2_REQUEST_I3C1_TX
3417 * @arg @ref LL_GPDMA2_REQUEST_I3C1_TC
3418 * @arg @ref LL_GPDMA2_REQUEST_I3C1_RS
3419 * @arg @ref LL_GPDMA2_REQUEST_I2C4_RX (*)
3420 * @arg @ref LL_GPDMA2_REQUEST_I2C4_TX (*)
3421 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC1 (*)
3422 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC2 (*)
3423 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_UE (*)
3424 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC1 (*)
3425 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC2 (*)
3426 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_UE (*)
3427 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC1 (*)
3428 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC2 (*)
3429 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_UE (*)
3430 * @arg @ref LL_GPDMA2_REQUEST_I3C2_RX (*)
3431 * @arg @ref LL_GPDMA2_REQUEST_I3C2_TX (*)
3432 * @arg @ref LL_GPDMA2_REQUEST_I3C2_TC (*)
3433 * @arg @ref LL_GPDMA2_REQUEST_I3C2_RS (*)
3434 *
3435 * @note (*) Availability depends on devices.
3436 * @retval None.
3437 */
LL_DMA_SetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)3438 __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
3439 {
3440 uint32_t dma_base_addr = (uint32_t)DMAx;
3441 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
3442 }
3443
3444 /**
3445 * @brief Get hardware request.
3446 * @note This API is used for all available DMA channels.
3447 * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
3448 * @param DMAx DMAx Instance
3449 * @param Channel This parameter can be one of the following values:
3450 * @arg @ref LL_DMA_CHANNEL_0
3451 * @arg @ref LL_DMA_CHANNEL_1
3452 * @arg @ref LL_DMA_CHANNEL_2
3453 * @arg @ref LL_DMA_CHANNEL_3
3454 * @arg @ref LL_DMA_CHANNEL_4
3455 * @arg @ref LL_DMA_CHANNEL_5
3456 * @arg @ref LL_DMA_CHANNEL_6
3457 * @arg @ref LL_DMA_CHANNEL_7
3458 * @retval Returned value can be one of the following values:
3459 * @arg @ref LL_GPDMA1_REQUEST_ADC1
3460 * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*)
3461 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
3462 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
3463 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
3464 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
3465 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
3466 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
3467 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
3468 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
3469 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
3470 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
3471 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
3472 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
3473 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
3474 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
3475 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX (*)
3476 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX (*)
3477 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
3478 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
3479 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
3480 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
3481 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
3482 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
3483 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX (*)
3484 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX (*)
3485 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX (*)
3486 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX (*)
3487 * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*)
3488 * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*)
3489 * @arg @ref LL_GPDMA1_REQUEST_UART7_RX (*)
3490 * @arg @ref LL_GPDMA1_REQUEST_UART7_TX (*)
3491 * @arg @ref LL_GPDMA1_REQUEST_UART8_RX (*)
3492 * @arg @ref LL_GPDMA1_REQUEST_UART8_TX (*)
3493 * @arg @ref LL_GPDMA1_REQUEST_UART9_RX (*)
3494 * @arg @ref LL_GPDMA1_REQUEST_UART9_TX (*)
3495 * @arg @ref LL_GPDMA1_REQUEST_USART10_RX (*)
3496 * @arg @ref LL_GPDMA1_REQUEST_USART10_TX (*)
3497 * @arg @ref LL_GPDMA1_REQUEST_USART11_RX (*)
3498 * @arg @ref LL_GPDMA1_REQUEST_USART11_TX (*)
3499 * @arg @ref LL_GPDMA1_REQUEST_UART12_RX (*)
3500 * @arg @ref LL_GPDMA1_REQUEST_UART12_TX (*)
3501 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
3502 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
3503 * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX (*)
3504 * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX (*)
3505 * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX (*)
3506 * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX (*)
3507 * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX (*)
3508 * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX (*)
3509 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*)
3510 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*)
3511 * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*)
3512 * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*)
3513 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 (*)
3514 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
3515 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
3516 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
3517 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
3518 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
3519 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
3520 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
3521 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 (*)
3522 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 (*)
3523 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 (*)
3524 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 (*)
3525 * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP (*)
3526 * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG (*)
3527 * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM (*)
3528 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
3529 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
3530 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
3531 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
3532 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
3533 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
3534 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
3535 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
3536 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
3537 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
3538 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
3539 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*)
3540 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*)
3541 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*)
3542 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*)
3543 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*)
3544 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 (*)
3545 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 (*)
3546 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 (*)
3547 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 (*)
3548 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP (*)
3549 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG (*)
3550 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 (*)
3551 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP (*)
3552 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG (*)
3553 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM (*)
3554 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 (*)
3555 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP (*)
3556 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*)
3557 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*)
3558 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
3559 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
3560 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
3561 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
3562 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
3563 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
3564 * @arg @ref LL_GPDMA1_REQUEST_DCMI (*)
3565 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*)
3566 * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*)
3567 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
3568 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*)
3569 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*)
3570 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ (*)
3571 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE (*)
3572 * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ (*)
3573 * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE (*)
3574 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*)
3575 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*)
3576 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
3577 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
3578 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
3579 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
3580 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*)
3581 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*)
3582 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 (*)
3583 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 (*)
3584 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE (*)
3585 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC1 (*)
3586 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC2 (*)
3587 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_UE (*)
3588 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC1 (*)
3589 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC2 (*)
3590 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_UE (*)
3591 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX (*)
3592 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX (*)
3593 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC (*)
3594 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS (*)
3595 *
3596 * @arg @ref LL_GPDMA2_REQUEST_ADC1
3597 * @arg @ref LL_GPDMA2_REQUEST_ADC2 (*)
3598 * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH1
3599 * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH2
3600 * @arg @ref LL_GPDMA2_REQUEST_TIM6_UP
3601 * @arg @ref LL_GPDMA2_REQUEST_TIM7_UP
3602 * @arg @ref LL_GPDMA2_REQUEST_SPI1_RX
3603 * @arg @ref LL_GPDMA2_REQUEST_SPI1_TX
3604 * @arg @ref LL_GPDMA2_REQUEST_SPI2_RX
3605 * @arg @ref LL_GPDMA2_REQUEST_SPI2_TX
3606 * @arg @ref LL_GPDMA2_REQUEST_SPI3_RX
3607 * @arg @ref LL_GPDMA2_REQUEST_SPI3_TX
3608 * @arg @ref LL_GPDMA2_REQUEST_I2C1_RX
3609 * @arg @ref LL_GPDMA2_REQUEST_I2C1_TX
3610 * @arg @ref LL_GPDMA2_REQUEST_I2C2_RX
3611 * @arg @ref LL_GPDMA2_REQUEST_I2C2_TX
3612 * @arg @ref LL_GPDMA2_REQUEST_I2C3_RX (*)
3613 * @arg @ref LL_GPDMA2_REQUEST_I2C3_TX (*)
3614 * @arg @ref LL_GPDMA2_REQUEST_USART1_RX
3615 * @arg @ref LL_GPDMA2_REQUEST_USART1_TX
3616 * @arg @ref LL_GPDMA2_REQUEST_USART2_RX
3617 * @arg @ref LL_GPDMA2_REQUEST_USART2_TX
3618 * @arg @ref LL_GPDMA2_REQUEST_USART3_RX
3619 * @arg @ref LL_GPDMA2_REQUEST_USART3_TX
3620 * @arg @ref LL_GPDMA2_REQUEST_UART4_RX (*)
3621 * @arg @ref LL_GPDMA2_REQUEST_UART4_TX (*)
3622 * @arg @ref LL_GPDMA2_REQUEST_UART5_RX (*)
3623 * @arg @ref LL_GPDMA2_REQUEST_UART5_TX (*)
3624 * @arg @ref LL_GPDMA2_REQUEST_USART6_RX (*)
3625 * @arg @ref LL_GPDMA2_REQUEST_USART6_TX (*)
3626 * @arg @ref LL_GPDMA2_REQUEST_UART7_RX (*)
3627 * @arg @ref LL_GPDMA2_REQUEST_UART7_TX (*)
3628 * @arg @ref LL_GPDMA2_REQUEST_UART8_RX (*)
3629 * @arg @ref LL_GPDMA2_REQUEST_UART8_TX (*)
3630 * @arg @ref LL_GPDMA2_REQUEST_UART9_RX (*)
3631 * @arg @ref LL_GPDMA2_REQUEST_UART9_TX (*)
3632 * @arg @ref LL_GPDMA2_REQUEST_USART10_RX (*)
3633 * @arg @ref LL_GPDMA2_REQUEST_USART10_TX (*)
3634 * @arg @ref LL_GPDMA2_REQUEST_USART11_RX (*)
3635 * @arg @ref LL_GPDMA2_REQUEST_USART11_TX (*)
3636 * @arg @ref LL_GPDMA2_REQUEST_UART12_RX (*)
3637 * @arg @ref LL_GPDMA2_REQUEST_UART12_TX (*)
3638 * @arg @ref LL_GPDMA2_REQUEST_LPUART1_RX
3639 * @arg @ref LL_GPDMA2_REQUEST_LPUART1_TX
3640 * @arg @ref LL_GPDMA2_REQUEST_SPI4_RX (*)
3641 * @arg @ref LL_GPDMA2_REQUEST_SPI4_TX (*)
3642 * @arg @ref LL_GPDMA2_REQUEST_SPI5_RX (*)
3643 * @arg @ref LL_GPDMA2_REQUEST_SPI5_TX (*)
3644 * @arg @ref LL_GPDMA2_REQUEST_SPI6_RX (*)
3645 * @arg @ref LL_GPDMA2_REQUEST_SPI6_TX (*)
3646 * @arg @ref LL_GPDMA2_REQUEST_SAI1_A (*)
3647 * @arg @ref LL_GPDMA2_REQUEST_SAI1_B (*)
3648 * @arg @ref LL_GPDMA2_REQUEST_SAI2_A (*)
3649 * @arg @ref LL_GPDMA2_REQUEST_SAI2_B (*)
3650 * @arg @ref LL_GPDMA2_REQUEST_OCTOSPI1 (*)
3651 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH1
3652 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH2
3653 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH3
3654 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH4
3655 * @arg @ref LL_GPDMA2_REQUEST_TIM1_UP
3656 * @arg @ref LL_GPDMA2_REQUEST_TIM1_TRIG
3657 * @arg @ref LL_GPDMA2_REQUEST_TIM1_COM
3658 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH1 (*)
3659 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH2 (*)
3660 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH3 (*)
3661 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH4 (*)
3662 * @arg @ref LL_GPDMA2_REQUEST_TIM8_UP (*)
3663 * @arg @ref LL_GPDMA2_REQUEST_TIM8_TRIG (*)
3664 * @arg @ref LL_GPDMA2_REQUEST_TIM8_COM (*)
3665 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH1
3666 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH2
3667 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH3
3668 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH4
3669 * @arg @ref LL_GPDMA2_REQUEST_TIM2_UP
3670 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH1
3671 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH2
3672 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH3
3673 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH4
3674 * @arg @ref LL_GPDMA2_REQUEST_TIM3_UP
3675 * @arg @ref LL_GPDMA2_REQUEST_TIM3_TRIG
3676 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH1 (*)
3677 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH2 (*)
3678 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH3 (*)
3679 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH4 (*)
3680 * @arg @ref LL_GPDMA2_REQUEST_TIM4_UP (*)
3681 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH1 (*)
3682 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH2 (*)
3683 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH3 (*)
3684 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH4 (*)
3685 * @arg @ref LL_GPDMA2_REQUEST_TIM5_UP (*)
3686 * @arg @ref LL_GPDMA2_REQUEST_TIM5_TRIG (*)
3687 * @arg @ref LL_GPDMA2_REQUEST_TIM15_CH1 (*)
3688 * @arg @ref LL_GPDMA2_REQUEST_TIM15_UP (*)
3689 * @arg @ref LL_GPDMA2_REQUEST_TIM15_TRIG (*)
3690 * @arg @ref LL_GPDMA2_REQUEST_TIM15_COM (*)
3691 * @arg @ref LL_GPDMA2_REQUEST_TIM16_CH1 (*)
3692 * @arg @ref LL_GPDMA2_REQUEST_TIM16_UP (*)
3693 * @arg @ref LL_GPDMA2_REQUEST_TIM17_CH1 (*)
3694 * @arg @ref LL_GPDMA2_REQUEST_TIM17_UP (*)
3695 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC1
3696 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC2
3697 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_UE
3698 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC1
3699 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC2
3700 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_UE
3701 * @arg @ref LL_GPDMA2_REQUEST_DCMI (*)
3702 * @arg @ref LL_GPDMA2_REQUEST_AES_OUT (*)
3703 * @arg @ref LL_GPDMA2_REQUEST_AES_IN (*)
3704 * @arg @ref LL_GPDMA2_REQUEST_HASH_IN
3705 * @arg @ref LL_GPDMA2_REQUEST_UCPD1_RX (*)
3706 * @arg @ref LL_GPDMA2_REQUEST_UCPD1_TX (*)
3707 * @arg @ref LL_GPDMA2_REQUEST_CORDIC_READ (*)
3708 * @arg @ref LL_GPDMA2_REQUEST_CORDIC_WRITE (*)
3709 * @arg @ref LL_GPDMA2_REQUEST_FMAC_READ (*)
3710 * @arg @ref LL_GPDMA2_REQUEST_FMAC_WRITE (*)
3711 * @arg @ref LL_GPDMA2_REQUEST_SAES_OUT (*)
3712 * @arg @ref LL_GPDMA2_REQUEST_SAES_IN (*)
3713 * @arg @ref LL_GPDMA2_REQUEST_I3C1_RX
3714 * @arg @ref LL_GPDMA2_REQUEST_I3C1_TX
3715 * @arg @ref LL_GPDMA2_REQUEST_I3C1_TC
3716 * @arg @ref LL_GPDMA2_REQUEST_I3C1_RS
3717 * @arg @ref LL_GPDMA2_REQUEST_I2C4_RX (*)
3718 * @arg @ref LL_GPDMA2_REQUEST_I2C4_TX (*)
3719 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC1 (*)
3720 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC2 (*)
3721 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_UE (*)
3722 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC1 (*)
3723 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC2 (*)
3724 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_UE (*)
3725 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC1 (*)
3726 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC2 (*)
3727 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_UE (*)
3728 * @arg @ref LL_GPDMA2_REQUEST_I3C2_RX (*)
3729 * @arg @ref LL_GPDMA2_REQUEST_I3C2_TX (*)
3730 * @arg @ref LL_GPDMA2_REQUEST_I3C2_TC (*)
3731 * @arg @ref LL_GPDMA2_REQUEST_I3C2_RS (*)
3732 *
3733 * @note (*) Availability depends on devices.
3734 */
LL_DMA_GetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel)3735 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
3736 {
3737 uint32_t dma_base_addr = (uint32_t)DMAx;
3738 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
3739 }
3740
3741 /**
3742 * @brief Set hardware trigger.
3743 * @note This API is used for all available DMA channels.
3744 * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
3745 * @param DMAx DMAx Instance
3746 * @param Channel This parameter can be one of the following values:
3747 * @arg @ref LL_DMA_CHANNEL_0
3748 * @arg @ref LL_DMA_CHANNEL_1
3749 * @arg @ref LL_DMA_CHANNEL_2
3750 * @arg @ref LL_DMA_CHANNEL_3
3751 * @arg @ref LL_DMA_CHANNEL_4
3752 * @arg @ref LL_DMA_CHANNEL_5
3753 * @arg @ref LL_DMA_CHANNEL_6
3754 * @arg @ref LL_DMA_CHANNEL_7
3755 * @param Trigger This parameter can be one of the following values:
3756 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
3757 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
3758 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
3759 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
3760 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4
3761 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5
3762 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6
3763 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7
3764 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
3765 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
3766 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 (*)
3767 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
3768 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
3769 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
3770 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
3771 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
3772 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
3773 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
3774 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
3775 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
3776 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
3777 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
3778 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
3779 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
3780 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
3781 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
3782 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF
3783 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF
3784 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF
3785 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF
3786 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF
3787 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF
3788 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF
3789 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF
3790 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
3791 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
3792 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
3793 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
3794 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
3795 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT
3796 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1
3797 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2
3798 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1
3799 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2
3800 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO (*)
3801 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO (*)
3802 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 (*)
3803 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 (*)
3804 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT (*)
3805 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1 (*)
3806 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2 (*)
3807 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1 (*)
3808 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2 (*)
3809 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*)
3810 * @arg @ref LL_GPDMA1_TRIGGER_EVENTOUT (*)
3811 *
3812 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE0
3813 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE1
3814 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE2
3815 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE3
3816 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE4
3817 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE5
3818 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE6
3819 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE7
3820 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG1
3821 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG2
3822 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG3 (*)
3823 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH1
3824 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH2
3825 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH1
3826 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH2
3827 * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRA_TRG
3828 * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRB_TRG
3829 * @arg @ref LL_GPDMA2_TRIGGER_RTC_WUT_TRG
3830 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF
3831 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF
3832 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF
3833 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF
3834 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF
3835 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF
3836 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF
3837 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF
3838 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF
3839 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF
3840 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF
3841 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF
3842 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF
3843 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF
3844 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF
3845 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF
3846 * @arg @ref LL_GPDMA2_TRIGGER_TIM2_TRGO
3847 * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO
3848 * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO
3849 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1
3850 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2
3851 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT
3852 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1
3853 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2
3854 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1
3855 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2
3856 * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO (*)
3857 * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO (*)
3858 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1 (*)
3859 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2 (*)
3860 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT (*)
3861 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1 (*)
3862 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2 (*)
3863 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1 (*)
3864 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2 (*)
3865 * @arg @ref LL_GPDMA2_TRIGGER_COMP1_OUT (*)
3866 * @arg @ref LL_GPDMA2_TRIGGER_EVENTOUT (*)
3867 *
3868 * @note (*) Availability depends on devices.
3869 * @retval None.
3870 */
LL_DMA_SetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Trigger)3871 __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
3872 {
3873 uint32_t dma_base_addr = (uint32_t)DMAx;
3874 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
3875 (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
3876 }
3877
3878 /**
3879 * @brief Get hardware triggers.
3880 * @note This API is used for all available DMA channels.
3881 * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
3882 * @param DMAx DMAx Instance
3883 * @param Channel This parameter can be one of the following values:
3884 * @arg @ref LL_DMA_CHANNEL_0
3885 * @arg @ref LL_DMA_CHANNEL_1
3886 * @arg @ref LL_DMA_CHANNEL_2
3887 * @arg @ref LL_DMA_CHANNEL_3
3888 * @arg @ref LL_DMA_CHANNEL_4
3889 * @arg @ref LL_DMA_CHANNEL_5
3890 * @arg @ref LL_DMA_CHANNEL_6
3891 * @arg @ref LL_DMA_CHANNEL_7
3892 * @retval Returned value can be one of the following values:
3893 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
3894 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
3895 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
3896 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
3897 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4
3898 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5
3899 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6
3900 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7
3901 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
3902 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
3903 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 (*)
3904 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
3905 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
3906 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
3907 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
3908 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
3909 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
3910 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
3911 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
3912 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
3913 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
3914 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
3915 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
3916 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
3917 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
3918 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
3919 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF
3920 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF
3921 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF
3922 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF
3923 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF
3924 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF
3925 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF
3926 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF
3927 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
3928 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
3929 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
3930 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
3931 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
3932 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT
3933 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1
3934 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2
3935 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1
3936 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2
3937 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO (*)
3938 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO (*)
3939 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 (*)
3940 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 (*)
3941 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT (*)
3942 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1 (*)
3943 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2 (*)
3944 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1 (*)
3945 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2 (*)
3946 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*)
3947 * @arg @ref LL_GPDMA1_TRIGGER_EVENTOUT (*)
3948 *
3949 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE0
3950 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE1
3951 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE2
3952 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE3
3953 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE4
3954 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE5
3955 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE6
3956 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE7
3957 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG1
3958 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG2
3959 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG3 (*)
3960 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH1
3961 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH2
3962 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH1
3963 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH2
3964 * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRA_TRG
3965 * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRB_TRG
3966 * @arg @ref LL_GPDMA2_TRIGGER_RTC_WUT_TRG
3967 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF
3968 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF
3969 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF
3970 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF
3971 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF
3972 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF
3973 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF
3974 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF
3975 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF
3976 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF
3977 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF
3978 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF
3979 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF
3980 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF
3981 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF
3982 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF
3983 * @arg @ref LL_GPDMA2_TRIGGER_TIM2_TRGO
3984 * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO
3985 * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO
3986 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1
3987 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2
3988 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT
3989 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1
3990 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2
3991 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1
3992 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2
3993 * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO (*)
3994 * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO (*)
3995 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1 (*)
3996 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2 (*)
3997 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT (*)
3998 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1 (*)
3999 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2 (*)
4000 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1 (*)
4001 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2 (*)
4002 * @arg @ref LL_GPDMA2_TRIGGER_COMP1_OUT (*)
4003 * @arg @ref LL_GPDMA2_TRIGGER_EVENTOUT (*)
4004 *
4005 * @note (*) Availability depends on devices.
4006 */
LL_DMA_GetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel)4007 __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel)
4008 {
4009 uint32_t dma_base_addr = (uint32_t)DMAx;
4010 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
4011 DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
4012 }
4013
4014 /**
4015 * @brief Set DMA transfer mode.
4016 * @note This API is used for all available DMA channels.
4017 * @rmtoll CTR2 PFREQ LL_DMA_SetTransferMode
4018 * @param DMAx DMAx Instance
4019 * @param Channel This parameter can be one of the following values:
4020 * @arg @ref LL_DMA_CHANNEL_0
4021 * @arg @ref LL_DMA_CHANNEL_7
4022 * @param Mode This parameter can be one of the following values:
4023 * @arg @ref LL_DMA_NORMAL
4024 * @arg @ref LL_DMA_PFCTRL
4025 * @retval None.
4026 */
LL_DMA_SetTransferMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)4027 __STATIC_INLINE void LL_DMA_SetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
4028 {
4029 uint32_t dma_base_addr = (uint32_t)DMAx;
4030 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_PFREQ,
4031 Mode & DMA_CTR2_PFREQ);
4032 }
4033
4034 /**
4035 * @brief Get DMA transfer mode.
4036 * @note This API is used for all available DMA channels.
4037 * @rmtoll CTR2 TRIGSEL LL_DMA_GetTransferMode
4038 * @param DMAx DMAx Instance
4039 * @param Channel This parameter can be one of the following values:
4040 * @arg @ref LL_DMA_CHANNEL_0
4041 * @arg @ref LL_DMA_CHANNEL_7
4042 * @retval Returned value can be one of the following values:
4043 * @arg @ref LL_DMA_NORMAL
4044 * @arg @ref LL_DMA_PFCTRL
4045 */
LL_DMA_GetTransferMode(const DMA_TypeDef * DMAx,uint32_t Channel)4046 __STATIC_INLINE uint32_t LL_DMA_GetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel)
4047 {
4048 uint32_t dma_base_addr = (uint32_t)DMAx;
4049 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
4050 DMA_CTR2_PFREQ));
4051 }
4052
4053 /**
4054 * @brief Configure addresses update.
4055 * @note This API is used only for 2D addressing channels.
4056 * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4057 * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4058 * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4059 * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate
4060 * @param DMAx DMAx Instance
4061 * @param Channel This parameter can be one of the following values:
4062 * @arg @ref LL_DMA_CHANNEL_6
4063 * @arg @ref LL_DMA_CHANNEL_7
4064 * @param Configuration This parameter must be a combination of all the following values:
4065 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4066 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4067 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4068 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4069 *@retval None.
4070 */
LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)4071 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
4072 {
4073 uint32_t dma_base_addr = (uint32_t)DMAx;
4074 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4075 DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration);
4076 }
4077
4078 /**
4079 * @brief Configure DMA Block number of data and repeat Count.
4080 * @note This API is used only for 2D addressing channels.
4081 * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n
4082 * CBR1 BRC LL_DMA_ConfigBlkCounters
4083 * @param DMAx DMAx Instance
4084 * @param Channel This parameter can be one of the following values:
4085 * @arg @ref LL_DMA_CHANNEL_6
4086 * @arg @ref LL_DMA_CHANNEL_7
4087 * @param BlkDataLength Block transfer length
4088 Value between 0 to 0x0000FFFF
4089 * @param BlkRptCount Block repeat counter
4090 * Value between 0 to 0x000007FF
4091 *@retval None.
4092 */
LL_DMA_ConfigBlkCounters(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength,uint32_t BlkRptCount)4093 __STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength,
4094 uint32_t BlkRptCount)
4095 {
4096 uint32_t dma_base_addr = (uint32_t)DMAx;
4097 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4098 (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos)));
4099 }
4100
4101 /**
4102 * @brief Set block repeat destination address update.
4103 * @note This API is used only for 2D addressing channels.
4104 * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate
4105 * @param DMAx DMAx Instance
4106 * @param Channel This parameter can be one of the following values:
4107 * @arg @ref LL_DMA_CHANNEL_6
4108 * @arg @ref LL_DMA_CHANNEL_7
4109 * @param BlkRptDestAddrUpdate This parameter can be one of the following values:
4110 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
4111 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4112 * @retval None.
4113 */
LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrUpdate)4114 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
4115 uint32_t BlkRptDestAddrUpdate)
4116 {
4117 uint32_t dma_base_addr = (uint32_t)DMAx;
4118 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC,
4119 BlkRptDestAddrUpdate);
4120 }
4121
4122 /**
4123 * @brief Get block repeat destination address update.
4124 * @note This API is used only for 2D addressing channels.
4125 * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate
4126 * @param DMAx DMAx Instance
4127 * @param Channel This parameter can be one of the following values:
4128 * @arg @ref LL_DMA_CHANNEL_6
4129 * @arg @ref LL_DMA_CHANNEL_7
4130 * @retval Returned value can be one of the following values:
4131 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
4132 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4133 */
LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4134 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4135 {
4136 uint32_t dma_base_addr = (uint32_t)DMAx;
4137 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC));
4138 }
4139
4140 /**
4141 * @brief Set block repeat source address update.
4142 * @note This API is used only for 2D addressing channels.
4143 * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate
4144 * @param DMAx DMAx Instance
4145 * @param Channel This parameter can be one of the following values:
4146 * @arg @ref LL_DMA_CHANNEL_6
4147 * @arg @ref LL_DMA_CHANNEL_7
4148 * @param BlkRptSrcAddrUpdate This parameter can be one of the following values:
4149 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
4150 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4151 * @retval None.
4152 */
LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrUpdate)4153 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
4154 uint32_t BlkRptSrcAddrUpdate)
4155 {
4156 uint32_t dma_base_addr = (uint32_t)DMAx;
4157 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC,
4158 BlkRptSrcAddrUpdate);
4159 }
4160
4161 /**
4162 * @brief Get block repeat source address update.
4163 * @note This API is used only for 2D addressing channels.
4164 * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate
4165 * @param DMAx DMAx Instance
4166 * @param Channel This parameter can be one of the following values:
4167 * @arg @ref LL_DMA_CHANNEL_6
4168 * @arg @ref LL_DMA_CHANNEL_7
4169 * @retval Returned value can be one of the following values:
4170 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
4171 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4172 */
LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4173 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4174 {
4175 uint32_t dma_base_addr = (uint32_t)DMAx;
4176 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC));
4177 }
4178
4179 /**
4180 * @brief Set destination address update.
4181 * @note This API is used only for 2D addressing channels.
4182 * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate
4183 * @param DMAx DMAx Instance
4184 * @param Channel This parameter can be one of the following values:
4185 * @arg @ref LL_DMA_CHANNEL_6
4186 * @arg @ref LL_DMA_CHANNEL_7
4187 * @param DestAddrUpdate This parameter can be one of the following values:
4188 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
4189 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4190 * @retval None.
4191 */
LL_DMA_SetDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrUpdate)4192 __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate)
4193 {
4194 uint32_t dma_base_addr = (uint32_t)DMAx;
4195 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC,
4196 DestAddrUpdate);
4197 }
4198
4199 /**
4200 * @brief Get destination address update.
4201 * @note This API is used only for 2D addressing channels.
4202 * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate
4203 * @param DMAx DMAx Instance
4204 * @param Channel This parameter can be one of the following values:
4205 * @arg @ref LL_DMA_CHANNEL_6
4206 * @arg @ref LL_DMA_CHANNEL_7
4207 * @retval Returned value can be one of the following values:
4208 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
4209 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4210 */
LL_DMA_GetDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4211 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4212 {
4213 uint32_t dma_base_addr = (uint32_t)DMAx;
4214 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC));
4215 }
4216
4217 /**
4218 * @brief Set source address update.
4219 * @note This API is used only for 2D addressing channels.
4220 * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate
4221 * @param DMAx DMAx Instance
4222 * @param Channel This parameter can be one of the following values:
4223 * @arg @ref LL_DMA_CHANNEL_6
4224 * @arg @ref LL_DMA_CHANNEL_7
4225 * @param SrcAddrUpdate This parameter can be one of the following values:
4226 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
4227 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4228 * @retval None.
4229 */
LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrUpdate)4230 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate)
4231 {
4232 uint32_t dma_base_addr = (uint32_t)DMAx;
4233 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC,
4234 SrcAddrUpdate);
4235 }
4236
4237 /**
4238 * @brief Get source address update.
4239 * @note This API is used only for 2D addressing channels.
4240 * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate
4241 * @param DMAx DMAx Instance
4242 * @param Channel This parameter can be one of the following values:
4243 * @arg @ref LL_DMA_CHANNEL_6
4244 * @arg @ref LL_DMA_CHANNEL_7
4245 * @retval Returned value can be one of the following values:
4246 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
4247 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4248 */
LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4249 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4250 {
4251 uint32_t dma_base_addr = (uint32_t)DMAx;
4252 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC));
4253 }
4254
4255 /**
4256 * @brief Set block repeat count.
4257 * @note This API is used only for 2D addressing channels.
4258 * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount
4259 * @param DMAx DMAx Instance
4260 * @param Channel This parameter can be one of the following values:
4261 * @arg @ref LL_DMA_CHANNEL_6
4262 * @arg @ref LL_DMA_CHANNEL_7
4263 * @param BlkRptCount Block repeat counter
4264 * Value between 0 to 0x000007FF
4265 * @retval None.
4266 */
LL_DMA_SetBlkRptCount(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptCount)4267 __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount)
4268 {
4269 uint32_t dma_base_addr = (uint32_t)DMAx;
4270 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC,
4271 (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
4272 }
4273
4274 /**
4275 * @brief Get block repeat count.
4276 * @note This API is used only for 2D addressing channels.
4277 * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount
4278 * @param DMAx DMAx Instance
4279 * @param Channel This parameter can be one of the following values:
4280 * @arg @ref LL_DMA_CHANNEL_6
4281 * @arg @ref LL_DMA_CHANNEL_7
4282 * @retval Between 0 to 0x000007FF
4283 */
LL_DMA_GetBlkRptCount(const DMA_TypeDef * DMAx,uint32_t Channel)4284 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel)
4285 {
4286 uint32_t dma_base_addr = (uint32_t)DMAx;
4287 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4288 DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos);
4289 }
4290
4291 /**
4292 * @brief Set block data length in bytes to transfer.
4293 * @note This API is used for all available DMA channels.
4294 * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
4295 * @param DMAx DMAx Instance
4296 * @param Channel This parameter can be one of the following values:
4297 * @arg @ref LL_DMA_CHANNEL_0
4298 * @arg @ref LL_DMA_CHANNEL_1
4299 * @arg @ref LL_DMA_CHANNEL_2
4300 * @arg @ref LL_DMA_CHANNEL_3
4301 * @arg @ref LL_DMA_CHANNEL_4
4302 * @arg @ref LL_DMA_CHANNEL_5
4303 * @arg @ref LL_DMA_CHANNEL_6
4304 * @arg @ref LL_DMA_CHANNEL_7
4305 * @param BlkDataLength Between 0 to 0x0000FFFF
4306 * @retval None.
4307 */
LL_DMA_SetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength)4308 __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
4309 {
4310 uint32_t dma_base_addr = (uint32_t)DMAx;
4311 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
4312 BlkDataLength);
4313 }
4314
4315 /**
4316 * @brief Get block data length in bytes to transfer.
4317 * @note This API is used for all available DMA channels.
4318 * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
4319 * @param DMAx DMAx Instance
4320 * @param Channel This parameter can be one of the following values:
4321 * @arg @ref LL_DMA_CHANNEL_0
4322 * @arg @ref LL_DMA_CHANNEL_1
4323 * @arg @ref LL_DMA_CHANNEL_2
4324 * @arg @ref LL_DMA_CHANNEL_3
4325 * @arg @ref LL_DMA_CHANNEL_4
4326 * @arg @ref LL_DMA_CHANNEL_5
4327 * @arg @ref LL_DMA_CHANNEL_6
4328 * @arg @ref LL_DMA_CHANNEL_7
4329 * @retval Between 0 to 0x0000FFFF
4330 */
LL_DMA_GetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel)4331 __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
4332 {
4333 uint32_t dma_base_addr = (uint32_t)DMAx;
4334 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
4335 }
4336
4337 /**
4338 * @brief Configure the source and destination addresses.
4339 * @note This API is used for all available DMA channels.
4340 * @note This API must not be called when the DMA Channel is enabled.
4341 * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
4342 * CDAR DA LL_DMA_ConfigAddresses
4343 * @param DMAx DMAx Instance
4344 * @param Channel This parameter can be one of the following values:
4345 * @arg @ref LL_DMA_CHANNEL_0
4346 * @arg @ref LL_DMA_CHANNEL_1
4347 * @arg @ref LL_DMA_CHANNEL_2
4348 * @arg @ref LL_DMA_CHANNEL_3
4349 * @arg @ref LL_DMA_CHANNEL_4
4350 * @arg @ref LL_DMA_CHANNEL_5
4351 * @arg @ref LL_DMA_CHANNEL_6
4352 * @arg @ref LL_DMA_CHANNEL_7
4353 * @param SrcAddress Between 0 to 0xFFFFFFFF
4354 * @param DestAddress Between 0 to 0xFFFFFFFF
4355 * @retval None.
4356 */
LL_DMA_ConfigAddresses(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DestAddress)4357 __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
4358 DestAddress)
4359 {
4360 uint32_t dma_base_addr = (uint32_t)DMAx;
4361 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
4362 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
4363 }
4364
4365 /**
4366 * @brief Set source address.
4367 * @note This API is used for all available DMA channels.
4368 * @rmtoll CSAR SA LL_DMA_SetSrcAddress
4369 * @param DMAx DMAx Instance
4370 * @param Channel This parameter can be one of the following values:
4371 * @arg @ref LL_DMA_CHANNEL_0
4372 * @arg @ref LL_DMA_CHANNEL_1
4373 * @arg @ref LL_DMA_CHANNEL_2
4374 * @arg @ref LL_DMA_CHANNEL_3
4375 * @arg @ref LL_DMA_CHANNEL_4
4376 * @arg @ref LL_DMA_CHANNEL_5
4377 * @arg @ref LL_DMA_CHANNEL_6
4378 * @arg @ref LL_DMA_CHANNEL_7
4379 * @param SrcAddress Between 0 to 0xFFFFFFFF
4380 * @retval None.
4381 */
LL_DMA_SetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress)4382 __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
4383 {
4384 uint32_t dma_base_addr = (uint32_t)DMAx;
4385 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
4386 }
4387
4388 /**
4389 * @brief Get source address.
4390 * @note This API is used for all available DMA channels.
4391 * @rmtoll CSAR SA LL_DMA_GetSrcAddress
4392 * @param DMAx DMAx Instance
4393 * @param Channel This parameter can be one of the following values:
4394 * @arg @ref LL_DMA_CHANNEL_0
4395 * @arg @ref LL_DMA_CHANNEL_1
4396 * @arg @ref LL_DMA_CHANNEL_2
4397 * @arg @ref LL_DMA_CHANNEL_3
4398 * @arg @ref LL_DMA_CHANNEL_4
4399 * @arg @ref LL_DMA_CHANNEL_5
4400 * @arg @ref LL_DMA_CHANNEL_6
4401 * @arg @ref LL_DMA_CHANNEL_7
4402 * @retval Between 0 to 0xFFFFFFFF
4403 */
LL_DMA_GetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel)4404 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
4405 {
4406 uint32_t dma_base_addr = (uint32_t)DMAx;
4407 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
4408 }
4409
4410 /**
4411 * @brief Set destination address.
4412 * @note This API is used for all available DMA channels.
4413 * @rmtoll CDAR DA LL_DMA_SetDestAddress
4414 * @param DMAx DMAx Instance
4415 * @param Channel This parameter can be one of the following values:
4416 * @arg @ref LL_DMA_CHANNEL_0
4417 * @arg @ref LL_DMA_CHANNEL_1
4418 * @arg @ref LL_DMA_CHANNEL_2
4419 * @arg @ref LL_DMA_CHANNEL_3
4420 * @arg @ref LL_DMA_CHANNEL_4
4421 * @arg @ref LL_DMA_CHANNEL_5
4422 * @arg @ref LL_DMA_CHANNEL_6
4423 * @arg @ref LL_DMA_CHANNEL_7
4424 * @param DestAddress Between 0 to 0xFFFFFFFF
4425 * @retval None.
4426 */
LL_DMA_SetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddress)4427 __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
4428 {
4429 uint32_t dma_base_addr = (uint32_t)DMAx;
4430 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
4431 }
4432
4433 /**
4434 * @brief Get destination address.
4435 * @note This API is used for all available DMA channels.
4436 * @rmtoll CDAR DA LL_DMA_GetDestAddress
4437 * @param DMAx DMAx Instance
4438 * @param Channel This parameter can be one of the following values:
4439 * @arg @ref LL_DMA_CHANNEL_0
4440 * @arg @ref LL_DMA_CHANNEL_1
4441 * @arg @ref LL_DMA_CHANNEL_2
4442 * @arg @ref LL_DMA_CHANNEL_3
4443 * @arg @ref LL_DMA_CHANNEL_4
4444 * @arg @ref LL_DMA_CHANNEL_5
4445 * @arg @ref LL_DMA_CHANNEL_6
4446 * @arg @ref LL_DMA_CHANNEL_7
4447 * @retval Between 0 to 0xFFFFFFFF
4448 */
LL_DMA_GetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel)4449 __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
4450 {
4451 uint32_t dma_base_addr = (uint32_t)DMAx;
4452 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
4453 }
4454
4455 /**
4456 * @brief Configure source and destination addresses offset.
4457 * @note This API is used only for 2D addressing channels.
4458 * @note This API must not be called when the DMA Channel is enabled.
4459 * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n
4460 * CTR3 SAO LL_DMA_ConfigAddrUpdateValue
4461 * @param DMAx DMAx Instance
4462 * @param Channel This parameter can be one of the following values:
4463 * @arg @ref LL_DMA_CHANNEL_6
4464 * @arg @ref LL_DMA_CHANNEL_7
4465 * @param DestAddrOffset Between 0 to 0x00001FFF
4466 * @param SrcAddrOffset Between 0 to 0x00001FFF
4467 * @retval None.
4468 */
LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset,uint32_t DestAddrOffset)4469 __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset,
4470 uint32_t DestAddrOffset)
4471 {
4472 uint32_t dma_base_addr = (uint32_t)DMAx;
4473 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
4474 (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
4475 }
4476
4477 /**
4478 * @brief Set destination address offset.
4479 * @note This API is used only for 2D addressing channels.
4480 * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue
4481 * @param DMAx DMAx Instance
4482 * @param Channel This parameter can be one of the following values:
4483 * @arg @ref LL_DMA_CHANNEL_6
4484 * @arg @ref LL_DMA_CHANNEL_7
4485 * @param DestAddrOffset Between 0 to 0x00001FFF
4486 * @retval None.
4487 */
LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrOffset)4488 __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset)
4489 {
4490 uint32_t dma_base_addr = (uint32_t)DMAx;
4491 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO,
4492 ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
4493 }
4494
4495 /**
4496 * @brief Get destination address offset.
4497 * @note This API is used only for 2D addressing channels.
4498 * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue
4499 * @param DMAx DMAx Instance
4500 * @param Channel This parameter can be one of the following values:
4501 * @arg @ref LL_DMA_CHANNEL_6
4502 * @arg @ref LL_DMA_CHANNEL_7
4503 * @retval Between 0 to 0x00001FFF
4504 */
LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4505 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4506 {
4507 uint32_t dma_base_addr = (uint32_t)DMAx;
4508 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
4509 DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
4510 }
4511
4512 /**
4513 * @brief Set source address offset.
4514 * @note This API is used only for 2D addressing channels.
4515 * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue
4516 * @param DMAx DMAx Instance
4517 * @param Channel This parameter can be one of the following values:
4518 * @arg @ref LL_DMA_CHANNEL_6
4519 * @arg @ref LL_DMA_CHANNEL_7
4520 * @param SrcAddrOffset Between 0 to 0x00001FFF
4521 * @retval None.
4522 */
LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset)4523 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset)
4524 {
4525 uint32_t dma_base_addr = (uint32_t)DMAx;
4526 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO,
4527 SrcAddrOffset & DMA_CTR3_SAO);
4528 }
4529
4530 /**
4531 * @brief Get source address offset.
4532 * @note This API is used only for 2D addressing channels.
4533 * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue
4534 * @param DMAx DMAx Instance
4535 * @param Channel This parameter can be one of the following values:
4536 * @arg @ref LL_DMA_CHANNEL_6
4537 * @arg @ref LL_DMA_CHANNEL_7
4538 * @retval Between 0 to 0x00001FFF
4539 */
LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4540 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4541 {
4542 uint32_t dma_base_addr = (uint32_t)DMAx;
4543 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO));
4544 }
4545
4546 /**
4547 * @brief Configure the block repeated source and destination addresses offset.
4548 * @note This API is used only for 2D addressing channels.
4549 * @note This API must not be called when the DMA Channel is enabled.
4550 * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n
4551 * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue
4552 * @param DMAx DMAx Instance
4553 * @param Channel This parameter can be one of the following values:
4554 * @arg @ref LL_DMA_CHANNEL_6
4555 * @arg @ref LL_DMA_CHANNEL_7
4556 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
4557 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
4558 * @retval None.
4559 */
LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset,uint32_t BlkRptDestAddrOffset)4560 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4561 uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset)
4562 {
4563 uint32_t dma_base_addr = (uint32_t)DMAx;
4564 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
4565 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO));
4566 }
4567
4568 /**
4569 * @brief Set block repeated destination address offset.
4570 * @note This API is used only for 2D addressing channels.
4571 * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue
4572 * @param DMAx DMAx Instance
4573 * @param Channel This parameter can be one of the following values:
4574 * @arg @ref LL_DMA_CHANNEL_6
4575 * @arg @ref LL_DMA_CHANNEL_7
4576 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
4577 * @retval None.
4578 */
LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrOffset)4579 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4580 uint32_t BlkRptDestAddrOffset)
4581 {
4582 uint32_t dma_base_addr = (uint32_t)DMAx;
4583 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO,
4584 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO));
4585 }
4586
4587 /**
4588 * @brief Get block repeated destination address offset.
4589 * @note This API is used only for 2D addressing channels.
4590 * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue
4591 * @param DMAx DMAx Instance
4592 * @param Channel This parameter can be one of the following values:
4593 * @arg @ref LL_DMA_CHANNEL_6
4594 * @arg @ref LL_DMA_CHANNEL_7
4595 * @retval Between 0 to 0x0000FFFF.
4596 */
LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4597 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4598 {
4599 uint32_t dma_base_addr = (uint32_t)DMAx;
4600 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
4601 DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
4602 }
4603
4604 /**
4605 * @brief Set block repeated source address offset.
4606 * @note This API is used only for 2D addressing channels.
4607 * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue
4608 * @param DMAx DMAx Instance
4609 * @param Channel This parameter can be one of the following values:
4610 * @arg @ref LL_DMA_CHANNEL_6
4611 * @arg @ref LL_DMA_CHANNEL_7
4612 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
4613 * @retval None.
4614 */
LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset)4615 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4616 uint32_t BlkRptSrcAddrOffset)
4617 {
4618 uint32_t dma_base_addr = (uint32_t)DMAx;
4619 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO,
4620 BlkRptSrcAddrOffset);
4621 }
4622
4623 /**
4624 * @brief Get block repeated source address offset.
4625 * @note This API is used only for 2D addressing channels.
4626 * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue
4627 * @param DMAx DMAx Instance
4628 * @param Channel This parameter can be one of the following values:
4629 * @arg @ref LL_DMA_CHANNEL_6
4630 * @arg @ref LL_DMA_CHANNEL_7
4631 * @retval Between 0 to 0x0000FFFF
4632 */
LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4633 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4634 {
4635 uint32_t dma_base_addr = (uint32_t)DMAx;
4636 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO));
4637 }
4638
4639 /**
4640 * @brief Configure registers update and node address offset during the link transfer.
4641 * @note This API is used for all available DMA channels.
4642 * For linear addressing channels, UT3 and UB2 fields are discarded.
4643 * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n
4644 * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n
4645 * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n
4646 * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n
4647 * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n
4648 * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n
4649 * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n
4650 * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate
4651 * @param DMAx DMAx Instance
4652 * @param Channel This parameter can be one of the following values:
4653 * @arg @ref LL_DMA_CHANNEL_0
4654 * @arg @ref LL_DMA_CHANNEL_1
4655 * @arg @ref LL_DMA_CHANNEL_2
4656 * @arg @ref LL_DMA_CHANNEL_3
4657 * @arg @ref LL_DMA_CHANNEL_4
4658 * @arg @ref LL_DMA_CHANNEL_5
4659 * @arg @ref LL_DMA_CHANNEL_6
4660 * @arg @ref LL_DMA_CHANNEL_7
4661 * @param RegistersUpdate This parameter must be a combination of all the following values:
4662 * @arg @ref LL_DMA_UPDATE_CTR1
4663 * @arg @ref LL_DMA_UPDATE_CTR2
4664 * @arg @ref LL_DMA_UPDATE_CBR1
4665 * @arg @ref LL_DMA_UPDATE_CSAR
4666 * @arg @ref LL_DMA_UPDATE_CDAR
4667 * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels)
4668 * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels)
4669 * @arg @ref LL_DMA_UPDATE_CLLR
4670 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
4671 * @retval None.
4672 */
LL_DMA_ConfigLinkUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t RegistersUpdate,uint32_t LinkedListAddrOffset)4673 __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
4674 uint32_t LinkedListAddrOffset)
4675 {
4676 uint32_t dma_base_addr = (uint32_t)DMAx;
4677 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
4678 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \
4679 DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
4680 }
4681
4682 /**
4683 * @brief Enable CTR1 update during the link transfer.
4684 * @note This API is used for all available DMA channels.
4685 * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
4686 * @param DMAx DMAx Instance
4687 * @param Channel This parameter can be one of the following values:
4688 * @arg @ref LL_DMA_CHANNEL_0
4689 * @arg @ref LL_DMA_CHANNEL_1
4690 * @arg @ref LL_DMA_CHANNEL_2
4691 * @arg @ref LL_DMA_CHANNEL_3
4692 * @arg @ref LL_DMA_CHANNEL_4
4693 * @arg @ref LL_DMA_CHANNEL_5
4694 * @arg @ref LL_DMA_CHANNEL_6
4695 * @arg @ref LL_DMA_CHANNEL_7
4696 * @retval None.
4697 */
LL_DMA_EnableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4698 __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4699 {
4700 uint32_t dma_base_addr = (uint32_t)DMAx;
4701 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
4702 }
4703
4704 /**
4705 * @brief Disable CTR1 update during the link transfer.
4706 * @note This API is used for all available DMA channels.
4707 * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
4708 * @param DMAx DMAx Instance
4709 * @param Channel This parameter can be one of the following values:
4710 * @arg @ref LL_DMA_CHANNEL_0
4711 * @arg @ref LL_DMA_CHANNEL_1
4712 * @arg @ref LL_DMA_CHANNEL_2
4713 * @arg @ref LL_DMA_CHANNEL_3
4714 * @arg @ref LL_DMA_CHANNEL_4
4715 * @arg @ref LL_DMA_CHANNEL_5
4716 * @arg @ref LL_DMA_CHANNEL_6
4717 * @arg @ref LL_DMA_CHANNEL_7
4718 * @retval None.
4719 */
LL_DMA_DisableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4720 __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4721 {
4722 uint32_t dma_base_addr = (uint32_t)DMAx;
4723 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
4724 }
4725
4726 /**
4727 * @brief Check if CTR1 update during the link transfer is enabled.
4728 * @note This API is used for all available DMA channels.
4729 * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
4730 * @param DMAx DMAx Instance
4731 * @param Channel This parameter can be one of the following values:
4732 * @arg @ref LL_DMA_CHANNEL_0
4733 * @arg @ref LL_DMA_CHANNEL_1
4734 * @arg @ref LL_DMA_CHANNEL_2
4735 * @arg @ref LL_DMA_CHANNEL_3
4736 * @arg @ref LL_DMA_CHANNEL_4
4737 * @arg @ref LL_DMA_CHANNEL_5
4738 * @arg @ref LL_DMA_CHANNEL_6
4739 * @arg @ref LL_DMA_CHANNEL_7
4740 * @retval State of bit (1 or 0).
4741 */
LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4742 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4743 {
4744 uint32_t dma_base_addr = (uint32_t)DMAx;
4745 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
4746 == (DMA_CLLR_UT1)) ? 1UL : 0UL);
4747 }
4748
4749 /**
4750 * @brief Enable CTR2 update during the link transfer.
4751 * @note This API is used for all available DMA channels.
4752 * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
4753 * @param DMAx DMAx Instance
4754 * @param Channel This parameter can be one of the following values:
4755 * @arg @ref LL_DMA_CHANNEL_0
4756 * @arg @ref LL_DMA_CHANNEL_1
4757 * @arg @ref LL_DMA_CHANNEL_2
4758 * @arg @ref LL_DMA_CHANNEL_3
4759 * @arg @ref LL_DMA_CHANNEL_4
4760 * @arg @ref LL_DMA_CHANNEL_5
4761 * @arg @ref LL_DMA_CHANNEL_6
4762 * @arg @ref LL_DMA_CHANNEL_7
4763 * @retval None.
4764 */
LL_DMA_EnableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4765 __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4766 {
4767 uint32_t dma_base_addr = (uint32_t)DMAx;
4768 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
4769 }
4770
4771 /**
4772 * @brief Disable CTR2 update during the link transfer.
4773 * @note This API is used for all available DMA channels.
4774 * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
4775 * @param DMAx DMAx Instance
4776 * @param Channel This parameter can be one of the following values:
4777 * @arg @ref LL_DMA_CHANNEL_0
4778 * @arg @ref LL_DMA_CHANNEL_1
4779 * @arg @ref LL_DMA_CHANNEL_2
4780 * @arg @ref LL_DMA_CHANNEL_3
4781 * @arg @ref LL_DMA_CHANNEL_4
4782 * @arg @ref LL_DMA_CHANNEL_5
4783 * @arg @ref LL_DMA_CHANNEL_6
4784 * @arg @ref LL_DMA_CHANNEL_7
4785 * @retval None.
4786 */
LL_DMA_DisableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4787 __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4788 {
4789 uint32_t dma_base_addr = (uint32_t)DMAx;
4790 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
4791 }
4792
4793 /**
4794 * @brief Check if CTR2 update during the link transfer is enabled.
4795 * @note This API is used for all available DMA channels.
4796 * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
4797 * @param DMAx DMAx Instance
4798 * @param Channel This parameter can be one of the following values:
4799 * @arg @ref LL_DMA_CHANNEL_0
4800 * @arg @ref LL_DMA_CHANNEL_1
4801 * @arg @ref LL_DMA_CHANNEL_2
4802 * @arg @ref LL_DMA_CHANNEL_3
4803 * @arg @ref LL_DMA_CHANNEL_4
4804 * @arg @ref LL_DMA_CHANNEL_5
4805 * @arg @ref LL_DMA_CHANNEL_6
4806 * @arg @ref LL_DMA_CHANNEL_7
4807 * @retval State of bit (1 or 0).
4808 */
LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4809 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4810 {
4811 uint32_t dma_base_addr = (uint32_t)DMAx;
4812 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
4813 == (DMA_CLLR_UT2)) ? 1UL : 0UL);
4814 }
4815
4816 /**
4817 * @brief Enable CBR1 update during the link transfer.
4818 * @note This API is used for all available DMA channels.
4819 * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
4820 * @param DMAx DMAx Instance
4821 * @param Channel This parameter can be one of the following values:
4822 * @arg @ref LL_DMA_CHANNEL_0
4823 * @arg @ref LL_DMA_CHANNEL_1
4824 * @arg @ref LL_DMA_CHANNEL_2
4825 * @arg @ref LL_DMA_CHANNEL_3
4826 * @arg @ref LL_DMA_CHANNEL_4
4827 * @arg @ref LL_DMA_CHANNEL_5
4828 * @arg @ref LL_DMA_CHANNEL_6
4829 * @arg @ref LL_DMA_CHANNEL_7
4830 * @retval None.
4831 */
LL_DMA_EnableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4832 __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4833 {
4834 uint32_t dma_base_addr = (uint32_t)DMAx;
4835 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
4836 }
4837
4838 /**
4839 * @brief Disable CBR1 update during the link transfer.
4840 * @note This API is used for all available DMA channels.
4841 * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
4842 * @param DMAx DMAx Instance
4843 * @param Channel This parameter can be one of the following values:
4844 * @arg @ref LL_DMA_CHANNEL_0
4845 * @arg @ref LL_DMA_CHANNEL_1
4846 * @arg @ref LL_DMA_CHANNEL_2
4847 * @arg @ref LL_DMA_CHANNEL_3
4848 * @arg @ref LL_DMA_CHANNEL_4
4849 * @arg @ref LL_DMA_CHANNEL_5
4850 * @arg @ref LL_DMA_CHANNEL_6
4851 * @arg @ref LL_DMA_CHANNEL_7
4852 * @retval None.
4853 */
LL_DMA_DisableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4854 __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4855 {
4856 uint32_t dma_base_addr = (uint32_t)DMAx;
4857 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
4858 }
4859
4860 /**
4861 * @brief Check if CBR1 update during the link transfer is enabled.
4862 * @note This API is used for all available DMA channels.
4863 * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
4864 * @param DMAx DMAx Instance
4865 * @param Channel This parameter can be one of the following values:
4866 * @arg @ref LL_DMA_CHANNEL_0
4867 * @arg @ref LL_DMA_CHANNEL_1
4868 * @arg @ref LL_DMA_CHANNEL_2
4869 * @arg @ref LL_DMA_CHANNEL_3
4870 * @arg @ref LL_DMA_CHANNEL_4
4871 * @arg @ref LL_DMA_CHANNEL_5
4872 * @arg @ref LL_DMA_CHANNEL_6
4873 * @arg @ref LL_DMA_CHANNEL_7
4874 * @retval State of bit (1 or 0).
4875 */
LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4876 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4877 {
4878 uint32_t dma_base_addr = (uint32_t)DMAx;
4879 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
4880 == (DMA_CLLR_UB1)) ? 1UL : 0UL);
4881 }
4882
4883 /**
4884 * @brief Enable CSAR update during the link transfer.
4885 * @note This API is used for all available DMA channels.
4886 * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
4887 * @param DMAx DMAx Instance
4888 * @param Channel This parameter can be one of the following values:
4889 * @arg @ref LL_DMA_CHANNEL_0
4890 * @arg @ref LL_DMA_CHANNEL_1
4891 * @arg @ref LL_DMA_CHANNEL_2
4892 * @arg @ref LL_DMA_CHANNEL_3
4893 * @arg @ref LL_DMA_CHANNEL_4
4894 * @arg @ref LL_DMA_CHANNEL_5
4895 * @arg @ref LL_DMA_CHANNEL_6
4896 * @arg @ref LL_DMA_CHANNEL_7
4897 * @retval None.
4898 */
LL_DMA_EnableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4899 __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4900 {
4901 uint32_t dma_base_addr = (uint32_t)DMAx;
4902 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
4903 }
4904
4905 /**
4906 * @brief Disable CSAR update during the link transfer.
4907 * @note This API is used for all available DMA channels.
4908 * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
4909 * @param DMAx DMAx Instance
4910 * @param Channel This parameter can be one of the following values:
4911 * @arg @ref LL_DMA_CHANNEL_0
4912 * @arg @ref LL_DMA_CHANNEL_1
4913 * @arg @ref LL_DMA_CHANNEL_2
4914 * @arg @ref LL_DMA_CHANNEL_3
4915 * @arg @ref LL_DMA_CHANNEL_4
4916 * @arg @ref LL_DMA_CHANNEL_5
4917 * @arg @ref LL_DMA_CHANNEL_6
4918 * @arg @ref LL_DMA_CHANNEL_7
4919 * @retval None.
4920 */
LL_DMA_DisableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4921 __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4922 {
4923 uint32_t dma_base_addr = (uint32_t)DMAx;
4924 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
4925 }
4926
4927 /**
4928 * @brief Check if CSAR update during the link transfer is enabled.
4929 * @note This API is used for all available DMA channels.
4930 * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
4931 * @param DMAx DMAx Instance
4932 * @param Channel This parameter can be one of the following values:
4933 * @arg @ref LL_DMA_CHANNEL_0
4934 * @arg @ref LL_DMA_CHANNEL_1
4935 * @arg @ref LL_DMA_CHANNEL_2
4936 * @arg @ref LL_DMA_CHANNEL_3
4937 * @arg @ref LL_DMA_CHANNEL_4
4938 * @arg @ref LL_DMA_CHANNEL_5
4939 * @arg @ref LL_DMA_CHANNEL_6
4940 * @arg @ref LL_DMA_CHANNEL_7
4941 * @retval State of bit (1 or 0).
4942 */
LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4943 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4944 {
4945 uint32_t dma_base_addr = (uint32_t)DMAx;
4946 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
4947 == (DMA_CLLR_USA)) ? 1UL : 0UL);
4948 }
4949
4950 /**
4951 * @brief Enable CDAR update during the link transfer.
4952 * @note This API is used for all available DMA channels.
4953 * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
4954 * @param DMAx DMAx Instance
4955 * @param Channel This parameter can be one of the following values:
4956 * @arg @ref LL_DMA_CHANNEL_0
4957 * @arg @ref LL_DMA_CHANNEL_1
4958 * @arg @ref LL_DMA_CHANNEL_2
4959 * @arg @ref LL_DMA_CHANNEL_3
4960 * @arg @ref LL_DMA_CHANNEL_4
4961 * @arg @ref LL_DMA_CHANNEL_5
4962 * @arg @ref LL_DMA_CHANNEL_6
4963 * @arg @ref LL_DMA_CHANNEL_7
4964 * @retval None.
4965 */
LL_DMA_EnableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4966 __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4967 {
4968 uint32_t dma_base_addr = (uint32_t)DMAx;
4969 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
4970 }
4971
4972 /**
4973 * @brief Disable CDAR update during the link transfer.
4974 * @note This API is used for all available DMA channels.
4975 * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
4976 * @param DMAx DMAx Instance
4977 * @param Channel This parameter can be one of the following values:
4978 * @arg @ref LL_DMA_CHANNEL_0
4979 * @arg @ref LL_DMA_CHANNEL_1
4980 * @arg @ref LL_DMA_CHANNEL_2
4981 * @arg @ref LL_DMA_CHANNEL_3
4982 * @arg @ref LL_DMA_CHANNEL_4
4983 * @arg @ref LL_DMA_CHANNEL_5
4984 * @arg @ref LL_DMA_CHANNEL_6
4985 * @arg @ref LL_DMA_CHANNEL_7
4986 * @retval None.
4987 */
LL_DMA_DisableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4988 __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4989 {
4990 uint32_t dma_base_addr = (uint32_t)DMAx;
4991 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
4992 }
4993
4994 /**
4995 * @brief Check if CDAR update during the link transfer is enabled.
4996 * @note This API is used for all available DMA channels.
4997 * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
4998 * @param DMAx DMAx Instance
4999 * @param Channel This parameter can be one of the following values:
5000 * @arg @ref LL_DMA_CHANNEL_0
5001 * @arg @ref LL_DMA_CHANNEL_1
5002 * @arg @ref LL_DMA_CHANNEL_2
5003 * @arg @ref LL_DMA_CHANNEL_3
5004 * @arg @ref LL_DMA_CHANNEL_4
5005 * @arg @ref LL_DMA_CHANNEL_5
5006 * @arg @ref LL_DMA_CHANNEL_6
5007 * @arg @ref LL_DMA_CHANNEL_7
5008 * @retval State of bit (1 or 0).
5009 */
LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5010 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5011 {
5012 uint32_t dma_base_addr = (uint32_t)DMAx;
5013 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
5014 == (DMA_CLLR_UDA)) ? 1UL : 0UL);
5015 }
5016
5017 /**
5018 * @brief Enable CTR3 update during the link transfer.
5019 * @note This API is used only for 2D addressing channels.
5020 * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update
5021 * @param DMAx DMAx Instance
5022 * @param Channel This parameter can be one of the following values:
5023 * @arg @ref LL_DMA_CHANNEL_6
5024 * @arg @ref LL_DMA_CHANNEL_7
5025 * @retval None.
5026 */
LL_DMA_EnableCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5027 __STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5028 {
5029 uint32_t dma_base_addr = (uint32_t)DMAx;
5030 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
5031 }
5032
5033 /**
5034 * @brief Disable CTR3 update during the link transfer.
5035 * @note This API is used only for 2D addressing channels.
5036 * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update
5037 * @param DMAx DMAx Instance
5038 * @param Channel This parameter can be one of the following values:
5039 * @arg @ref LL_DMA_CHANNEL_6
5040 * @arg @ref LL_DMA_CHANNEL_7
5041 * @retval None.
5042 */
LL_DMA_DisableCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5043 __STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5044 {
5045 uint32_t dma_base_addr = (uint32_t)DMAx;
5046 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
5047 }
5048
5049 /**
5050 * @brief Check if CTR3 update during the link transfer is enabled.
5051 * @note This API is used only for 2D addressing channels.
5052 * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update
5053 * @param DMAx DMAx Instance
5054 * @param Channel This parameter can be one of the following values:
5055 * @arg @ref LL_DMA_CHANNEL_6
5056 * @arg @ref LL_DMA_CHANNEL_7
5057 * @retval State of bit (1 or 0).
5058 */
LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5059 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5060 {
5061 uint32_t dma_base_addr = (uint32_t)DMAx;
5062 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3)
5063 == (DMA_CLLR_UT3)) ? 1UL : 0UL);
5064 }
5065
5066 /**
5067 * @brief Enable CBR2 update during the link transfer.
5068 * @note This API is used only for 2D addressing channels.
5069 * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update
5070 * @param DMAx DMAx Instance
5071 * @param Channel This parameter can be one of the following values:
5072 * @arg @ref LL_DMA_CHANNEL_6
5073 * @arg @ref LL_DMA_CHANNEL_7
5074 * @retval None.
5075 */
LL_DMA_EnableCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5076 __STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5077 {
5078 uint32_t dma_base_addr = (uint32_t)DMAx;
5079 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
5080 }
5081
5082 /**
5083 * @brief Disable CBR2 update during the link transfer.
5084 * @note This API is used only for 2D addressing channels.
5085 * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update
5086 * @param DMAx DMAx Instance
5087 * @param Channel This parameter can be one of the following values:
5088 * @arg @ref LL_DMA_CHANNEL_6
5089 * @arg @ref LL_DMA_CHANNEL_7
5090 * @retval None.
5091 */
LL_DMA_DisableCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5092 __STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5093 {
5094 uint32_t dma_base_addr = (uint32_t)DMAx;
5095 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
5096 }
5097
5098 /**
5099 * @brief Check if CBR2 update during the link transfer is enabled.
5100 * @note This API is used only for 2D addressing channels.
5101 * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update
5102 * @param DMAx DMAx Instance
5103 * @param Channel This parameter can be one of the following values:
5104 * @arg @ref LL_DMA_CHANNEL_6
5105 * @arg @ref LL_DMA_CHANNEL_7
5106 * @retval State of bit (1 or 0).
5107 */
LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5108 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5109 {
5110 uint32_t dma_base_addr = (uint32_t)DMAx;
5111 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2)
5112 == (DMA_CLLR_UB2)) ? 1UL : 0UL);
5113 }
5114
5115 /**
5116 * @brief Enable CLLR update during the link transfer.
5117 * @note This API is used for all available DMA channels.
5118 * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
5119 * @param DMAx DMAx Instance
5120 * @param Channel This parameter can be one of the following values:
5121 * @arg @ref LL_DMA_CHANNEL_0
5122 * @arg @ref LL_DMA_CHANNEL_1
5123 * @arg @ref LL_DMA_CHANNEL_2
5124 * @arg @ref LL_DMA_CHANNEL_3
5125 * @arg @ref LL_DMA_CHANNEL_4
5126 * @arg @ref LL_DMA_CHANNEL_5
5127 * @arg @ref LL_DMA_CHANNEL_6
5128 * @arg @ref LL_DMA_CHANNEL_7
5129 * @retval None.
5130 */
LL_DMA_EnableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5131 __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5132 {
5133 uint32_t dma_base_addr = (uint32_t)DMAx;
5134 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
5135 }
5136
5137 /**
5138 * @brief Disable CLLR update during the link transfer.
5139 * @note This API is used for all available DMA channels.
5140 * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
5141 * @param DMAx DMAx Instance
5142 * @param Channel This parameter can be one of the following values:
5143 * @arg @ref LL_DMA_CHANNEL_0
5144 * @arg @ref LL_DMA_CHANNEL_1
5145 * @arg @ref LL_DMA_CHANNEL_2
5146 * @arg @ref LL_DMA_CHANNEL_3
5147 * @arg @ref LL_DMA_CHANNEL_4
5148 * @arg @ref LL_DMA_CHANNEL_5
5149 * @arg @ref LL_DMA_CHANNEL_6
5150 * @arg @ref LL_DMA_CHANNEL_7
5151 * @retval None.
5152 */
LL_DMA_DisableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5153 __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5154 {
5155 uint32_t dma_base_addr = (uint32_t)DMAx;
5156 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
5157 }
5158
5159 /**
5160 * @brief Check if CLLR update during the link transfer is enabled.
5161 * @note This API is used for all available DMA channels.
5162 * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
5163 * @param DMAx DMAx Instance
5164 * @param Channel This parameter can be one of the following values:
5165 * @arg @ref LL_DMA_CHANNEL_0
5166 * @arg @ref LL_DMA_CHANNEL_1
5167 * @arg @ref LL_DMA_CHANNEL_2
5168 * @arg @ref LL_DMA_CHANNEL_3
5169 * @arg @ref LL_DMA_CHANNEL_4
5170 * @arg @ref LL_DMA_CHANNEL_5
5171 * @arg @ref LL_DMA_CHANNEL_6
5172 * @arg @ref LL_DMA_CHANNEL_7
5173 * @retval State of bit (1 or 0).
5174 */
LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5175 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5176 {
5177 uint32_t dma_base_addr = (uint32_t)DMAx;
5178 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
5179 == (DMA_CLLR_ULL)) ? 1UL : 0UL);
5180 }
5181
5182 /**
5183 * @brief Set linked list address offset.
5184 * @note This API is used for all available DMA channels.
5185 * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
5186 * @param DMAx DMAx Instance
5187 * @param Channel This parameter can be one of the following values:
5188 * @arg @ref LL_DMA_CHANNEL_0
5189 * @arg @ref LL_DMA_CHANNEL_1
5190 * @arg @ref LL_DMA_CHANNEL_2
5191 * @arg @ref LL_DMA_CHANNEL_3
5192 * @arg @ref LL_DMA_CHANNEL_4
5193 * @arg @ref LL_DMA_CHANNEL_5
5194 * @arg @ref LL_DMA_CHANNEL_6
5195 * @arg @ref LL_DMA_CHANNEL_7
5196 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
5197 * @retval None.
5198 */
LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListAddrOffset)5199 __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel,
5200 uint32_t LinkedListAddrOffset)
5201 {
5202 uint32_t dma_base_addr = (uint32_t)DMAx;
5203 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
5204 (LinkedListAddrOffset & DMA_CLLR_LA));
5205 }
5206
5207 /**
5208 * @brief Get linked list address offset.
5209 * @note This API is used for all available DMA channels.
5210 * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
5211 * @param DMAx DMAx Instance
5212 * @param Channel This parameter can be one of the following values:
5213 * @arg @ref LL_DMA_CHANNEL_0
5214 * @arg @ref LL_DMA_CHANNEL_1
5215 * @arg @ref LL_DMA_CHANNEL_2
5216 * @arg @ref LL_DMA_CHANNEL_3
5217 * @arg @ref LL_DMA_CHANNEL_4
5218 * @arg @ref LL_DMA_CHANNEL_5
5219 * @arg @ref LL_DMA_CHANNEL_6
5220 * @arg @ref LL_DMA_CHANNEL_7
5221 * @retval Between 0 to 0x0000FFFC.
5222 */
LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel)5223 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel)
5224 {
5225 uint32_t dma_base_addr = (uint32_t)DMAx;
5226 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
5227 DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
5228 }
5229
5230 /**
5231 * @brief Get FIFO level.
5232 * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
5233 * @param DMAx DMAx Instance
5234 * @param Channel This parameter can be one of the following values:
5235 * @arg @ref LL_DMA_CHANNEL_0
5236 * @arg @ref LL_DMA_CHANNEL_1
5237 * @arg @ref LL_DMA_CHANNEL_2
5238 * @arg @ref LL_DMA_CHANNEL_3
5239 * @arg @ref LL_DMA_CHANNEL_4
5240 * @arg @ref LL_DMA_CHANNEL_5
5241 * @arg @ref LL_DMA_CHANNEL_6
5242 * @arg @ref LL_DMA_CHANNEL_7
5243 * @retval Between 0 to 0x000000FF.
5244 */
LL_DMA_GetFIFOLevel(const DMA_TypeDef * DMAx,uint32_t Channel)5245 __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
5246 {
5247 uint32_t dma_base_addr = (uint32_t)DMAx;
5248 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
5249 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
5250 }
5251
5252 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5253 /**
5254 * @brief Enable the DMA channel secure attribute.
5255 * @note This API is used for all available DMA channels.
5256 * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure
5257 * @param DMAx DMAx Instance
5258 * @param Channel This parameter can be one of the following values:
5259 * @arg @ref LL_DMA_CHANNEL_0
5260 * @arg @ref LL_DMA_CHANNEL_1
5261 * @arg @ref LL_DMA_CHANNEL_2
5262 * @arg @ref LL_DMA_CHANNEL_3
5263 * @arg @ref LL_DMA_CHANNEL_4
5264 * @arg @ref LL_DMA_CHANNEL_5
5265 * @arg @ref LL_DMA_CHANNEL_6
5266 * @arg @ref LL_DMA_CHANNEL_7
5267 * @retval None.
5268 */
LL_DMA_EnableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)5269 __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
5270 {
5271 SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
5272 }
5273
5274 /**
5275 * @brief Disable the DMA channel secure attribute.
5276 * @note This API is used for all available DMA channels.
5277 * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure
5278 * @param DMAx DMAx Instance
5279 * @param Channel This parameter can be one of the following values:
5280 * @arg @ref LL_DMA_CHANNEL_0
5281 * @arg @ref LL_DMA_CHANNEL_1
5282 * @arg @ref LL_DMA_CHANNEL_2
5283 * @arg @ref LL_DMA_CHANNEL_3
5284 * @arg @ref LL_DMA_CHANNEL_4
5285 * @arg @ref LL_DMA_CHANNEL_5
5286 * @arg @ref LL_DMA_CHANNEL_6
5287 * @arg @ref LL_DMA_CHANNEL_7
5288 * @retval None.
5289 */
LL_DMA_DisableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)5290 __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
5291 {
5292 CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
5293 }
5294 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
5295
5296 #if defined (DMA_SECCFGR_SEC0)
5297 /**
5298 * @brief Check if DMA channel secure is enabled.
5299 * @note This API is used for all available DMA channels.
5300 * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure
5301 * @param DMAx DMAx Instance
5302 * @param Channel This parameter can be one of the following values:
5303 * @arg @ref LL_DMA_CHANNEL_0
5304 * @arg @ref LL_DMA_CHANNEL_1
5305 * @arg @ref LL_DMA_CHANNEL_2
5306 * @arg @ref LL_DMA_CHANNEL_3
5307 * @arg @ref LL_DMA_CHANNEL_4
5308 * @arg @ref LL_DMA_CHANNEL_5
5309 * @arg @ref LL_DMA_CHANNEL_6
5310 * @arg @ref LL_DMA_CHANNEL_7
5311 * @retval State of bit (1 or 0).
5312 */
LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef * DMAx,uint32_t Channel)5313 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
5314 {
5315 return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
5316 == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5317 }
5318 #endif /* DMA_SECCFGR_SEC0 */
5319
5320 /**
5321 * @brief Enable the DMA channel privilege attribute.
5322 * @note This API is used for all available DMA channels.
5323 * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
5324 * @param DMAx DMAx Instance
5325 * @param Channel This parameter can be one of the following values:
5326 * @arg @ref LL_DMA_CHANNEL_0
5327 * @arg @ref LL_DMA_CHANNEL_1
5328 * @arg @ref LL_DMA_CHANNEL_2
5329 * @arg @ref LL_DMA_CHANNEL_3
5330 * @arg @ref LL_DMA_CHANNEL_4
5331 * @arg @ref LL_DMA_CHANNEL_5
5332 * @arg @ref LL_DMA_CHANNEL_6
5333 * @arg @ref LL_DMA_CHANNEL_7
5334 * @retval None.
5335 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)5336 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
5337 {
5338 SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
5339 }
5340
5341 /**
5342 * @brief Disable the DMA channel privilege attribute.
5343 * @note This API is used for all available DMA channels.
5344 * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
5345 * @param DMAx DMAx Instance
5346 * @param Channel This parameter can be one of the following values:
5347 * @arg @ref LL_DMA_CHANNEL_0
5348 * @arg @ref LL_DMA_CHANNEL_1
5349 * @arg @ref LL_DMA_CHANNEL_2
5350 * @arg @ref LL_DMA_CHANNEL_3
5351 * @arg @ref LL_DMA_CHANNEL_4
5352 * @arg @ref LL_DMA_CHANNEL_5
5353 * @arg @ref LL_DMA_CHANNEL_6
5354 * @arg @ref LL_DMA_CHANNEL_7
5355 * @retval None.
5356 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)5357 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
5358 {
5359 CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
5360 }
5361
5362 /**
5363 * @brief Check if DMA Channel privilege is enabled.
5364 * @note This API is used for all available DMA channels.
5365 * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege
5366 * @param DMAx DMAx Instance
5367 * @param Channel This parameter can be one of the following values:
5368 * @arg @ref LL_DMA_CHANNEL_0
5369 * @arg @ref LL_DMA_CHANNEL_1
5370 * @arg @ref LL_DMA_CHANNEL_2
5371 * @arg @ref LL_DMA_CHANNEL_3
5372 * @arg @ref LL_DMA_CHANNEL_4
5373 * @arg @ref LL_DMA_CHANNEL_5
5374 * @arg @ref LL_DMA_CHANNEL_6
5375 * @arg @ref LL_DMA_CHANNEL_7
5376 * @retval State of bit (1 or 0).
5377 */
LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef * DMAx,uint32_t Channel)5378 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel)
5379 {
5380 return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
5381 == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5382 }
5383
5384 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5385 /**
5386 * @brief Enable the DMA channel lock attributes.
5387 * @note This API is used for all available DMA channels.
5388 * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
5389 * @param DMAx DMAx Instance
5390 * @param Channel This parameter can be one of the following values:
5391 * @arg @ref LL_DMA_CHANNEL_0
5392 * @arg @ref LL_DMA_CHANNEL_1
5393 * @arg @ref LL_DMA_CHANNEL_2
5394 * @arg @ref LL_DMA_CHANNEL_3
5395 * @arg @ref LL_DMA_CHANNEL_4
5396 * @arg @ref LL_DMA_CHANNEL_5
5397 * @arg @ref LL_DMA_CHANNEL_6
5398 * @arg @ref LL_DMA_CHANNEL_7
5399 * @retval None.
5400 */
LL_DMA_EnableChannelLockAttribute(DMA_TypeDef * DMAx,uint32_t Channel)5401 __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
5402 {
5403 SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
5404 }
5405 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
5406
5407 #if defined (DMA_RCFGLOCKR_LOCK0)
5408 /**
5409 * @brief Check if DMA channel attributes are locked.
5410 * @note This API is used for all available DMA channels.
5411 * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
5412 * @param DMAx DMAx Instance
5413 * @param Channel This parameter can be one of the following values:
5414 * @arg @ref LL_DMA_CHANNEL_0
5415 * @arg @ref LL_DMA_CHANNEL_1
5416 * @arg @ref LL_DMA_CHANNEL_2
5417 * @arg @ref LL_DMA_CHANNEL_3
5418 * @arg @ref LL_DMA_CHANNEL_4
5419 * @arg @ref LL_DMA_CHANNEL_5
5420 * @arg @ref LL_DMA_CHANNEL_6
5421 * @arg @ref LL_DMA_CHANNEL_7
5422 * @retval State of bit (1 or 0).
5423 */
LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef * DMAx,uint32_t Channel)5424 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel)
5425 {
5426 return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
5427 == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5428 }
5429
5430 #endif /* DMA_RCFGLOCKR_LOCK0 */
5431 /**
5432 * @}
5433 */
5434
5435 /** @defgroup DMA_LL_EF_FLAG_Management Flag Management
5436 * @{
5437 */
5438
5439 /**
5440 * @brief Clear trigger overrun flag.
5441 * @note This API is used for all available DMA channels.
5442 * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
5443 * @param DMAx DMAx Instance
5444 * @param Channel This parameter can be one of the following values:
5445 * @arg @ref LL_DMA_CHANNEL_0
5446 * @arg @ref LL_DMA_CHANNEL_1
5447 * @arg @ref LL_DMA_CHANNEL_2
5448 * @arg @ref LL_DMA_CHANNEL_3
5449 * @arg @ref LL_DMA_CHANNEL_4
5450 * @arg @ref LL_DMA_CHANNEL_5
5451 * @arg @ref LL_DMA_CHANNEL_6
5452 * @arg @ref LL_DMA_CHANNEL_7
5453 * @retval None.
5454 */
LL_DMA_ClearFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)5455 __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
5456 {
5457 uint32_t dma_base_addr = (uint32_t)DMAx;
5458 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
5459 }
5460
5461 /**
5462 * @brief Clear suspension flag.
5463 * @note This API is used for all available DMA channels.
5464 * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
5465 * @param DMAx DMAx Instance
5466 * @param Channel This parameter can be one of the following values:
5467 * @arg @ref LL_DMA_CHANNEL_0
5468 * @arg @ref LL_DMA_CHANNEL_1
5469 * @arg @ref LL_DMA_CHANNEL_2
5470 * @arg @ref LL_DMA_CHANNEL_3
5471 * @arg @ref LL_DMA_CHANNEL_4
5472 * @arg @ref LL_DMA_CHANNEL_5
5473 * @arg @ref LL_DMA_CHANNEL_6
5474 * @arg @ref LL_DMA_CHANNEL_7
5475 * @retval None.
5476 */
LL_DMA_ClearFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)5477 __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
5478 {
5479 uint32_t dma_base_addr = (uint32_t)DMAx;
5480 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
5481 }
5482
5483 /**
5484 * @brief Clear user setting error flag.
5485 * @note This API is used for all available DMA channels.
5486 * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
5487 * @param DMAx DMAx Instance
5488 * @param Channel This parameter can be one of the following values:
5489 * @arg @ref LL_DMA_CHANNEL_0
5490 * @arg @ref LL_DMA_CHANNEL_1
5491 * @arg @ref LL_DMA_CHANNEL_2
5492 * @arg @ref LL_DMA_CHANNEL_3
5493 * @arg @ref LL_DMA_CHANNEL_4
5494 * @arg @ref LL_DMA_CHANNEL_5
5495 * @arg @ref LL_DMA_CHANNEL_6
5496 * @arg @ref LL_DMA_CHANNEL_7
5497 * @retval None.
5498 */
LL_DMA_ClearFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)5499 __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
5500 {
5501 uint32_t dma_base_addr = (uint32_t)DMAx;
5502 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
5503 }
5504
5505 /**
5506 * @brief Clear link transfer error flag.
5507 * @note This API is used for all available DMA channels.
5508 * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
5509 * @param DMAx DMAx Instance
5510 * @param Channel This parameter can be one of the following values:
5511 * @arg @ref LL_DMA_CHANNEL_0
5512 * @arg @ref LL_DMA_CHANNEL_1
5513 * @arg @ref LL_DMA_CHANNEL_2
5514 * @arg @ref LL_DMA_CHANNEL_3
5515 * @arg @ref LL_DMA_CHANNEL_4
5516 * @arg @ref LL_DMA_CHANNEL_5
5517 * @arg @ref LL_DMA_CHANNEL_6
5518 * @arg @ref LL_DMA_CHANNEL_7
5519 * @retval None.
5520 */
LL_DMA_ClearFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)5521 __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
5522 {
5523 uint32_t dma_base_addr = (uint32_t)DMAx;
5524 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
5525 }
5526
5527 /**
5528 * @brief Clear data transfer error flag.
5529 * @note This API is used for all available DMA channels.
5530 * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
5531 * @param DMAx DMAx Instance
5532 * @param Channel This parameter can be one of the following values:
5533 * @arg @ref LL_DMA_CHANNEL_0
5534 * @arg @ref LL_DMA_CHANNEL_1
5535 * @arg @ref LL_DMA_CHANNEL_2
5536 * @arg @ref LL_DMA_CHANNEL_3
5537 * @arg @ref LL_DMA_CHANNEL_4
5538 * @arg @ref LL_DMA_CHANNEL_5
5539 * @arg @ref LL_DMA_CHANNEL_6
5540 * @arg @ref LL_DMA_CHANNEL_7
5541 * @retval None.
5542 */
LL_DMA_ClearFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)5543 __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
5544 {
5545 uint32_t dma_base_addr = (uint32_t)DMAx;
5546 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
5547 }
5548
5549 /**
5550 * @brief Clear half transfer flag.
5551 * @note This API is used for all available DMA channels.
5552 * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
5553 * @param DMAx DMAx Instance
5554 * @param Channel This parameter can be one of the following values:
5555 * @arg @ref LL_DMA_CHANNEL_0
5556 * @arg @ref LL_DMA_CHANNEL_1
5557 * @arg @ref LL_DMA_CHANNEL_2
5558 * @arg @ref LL_DMA_CHANNEL_3
5559 * @arg @ref LL_DMA_CHANNEL_4
5560 * @arg @ref LL_DMA_CHANNEL_5
5561 * @arg @ref LL_DMA_CHANNEL_6
5562 * @arg @ref LL_DMA_CHANNEL_7
5563 * @retval None.
5564 */
LL_DMA_ClearFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)5565 __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
5566 {
5567 uint32_t dma_base_addr = (uint32_t)DMAx;
5568 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
5569 }
5570
5571 /**
5572 * @brief Clear transfer complete flag.
5573 * @note This API is used for all available DMA channels.
5574 * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
5575 * @param DMAx DMAx Instance
5576 * @param Channel This parameter can be one of the following values:
5577 * @arg @ref LL_DMA_CHANNEL_0
5578 * @arg @ref LL_DMA_CHANNEL_1
5579 * @arg @ref LL_DMA_CHANNEL_2
5580 * @arg @ref LL_DMA_CHANNEL_3
5581 * @arg @ref LL_DMA_CHANNEL_4
5582 * @arg @ref LL_DMA_CHANNEL_5
5583 * @arg @ref LL_DMA_CHANNEL_6
5584 * @arg @ref LL_DMA_CHANNEL_7
5585 * @retval None.
5586 */
LL_DMA_ClearFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)5587 __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
5588 {
5589 uint32_t dma_base_addr = (uint32_t)DMAx;
5590 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
5591 }
5592
5593 /**
5594 * @brief Get trigger overrun flag.
5595 * @note This API is used for all available DMA channels.
5596 * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
5597 * @param DMAx DMAx Instance
5598 * @param Channel This parameter can be one of the following values:
5599 * @arg @ref LL_DMA_CHANNEL_0
5600 * @arg @ref LL_DMA_CHANNEL_1
5601 * @arg @ref LL_DMA_CHANNEL_2
5602 * @arg @ref LL_DMA_CHANNEL_3
5603 * @arg @ref LL_DMA_CHANNEL_4
5604 * @arg @ref LL_DMA_CHANNEL_5
5605 * @arg @ref LL_DMA_CHANNEL_6
5606 * @arg @ref LL_DMA_CHANNEL_7
5607 * @retval State of bit (1 or 0).
5608 */
LL_DMA_IsActiveFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)5609 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
5610 {
5611 uint32_t dma_base_addr = (uint32_t)DMAx;
5612 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
5613 == (DMA_CSR_TOF)) ? 1UL : 0UL);
5614 }
5615
5616 /**
5617 * @brief Get suspension flag.
5618 * @note This API is used for all available DMA channels.
5619 * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
5620 * @param DMAx DMAx Instance
5621 * @param Channel This parameter can be one of the following values:
5622 * @arg @ref LL_DMA_CHANNEL_0
5623 * @arg @ref LL_DMA_CHANNEL_1
5624 * @arg @ref LL_DMA_CHANNEL_2
5625 * @arg @ref LL_DMA_CHANNEL_3
5626 * @arg @ref LL_DMA_CHANNEL_4
5627 * @arg @ref LL_DMA_CHANNEL_5
5628 * @arg @ref LL_DMA_CHANNEL_6
5629 * @arg @ref LL_DMA_CHANNEL_7
5630 * @retval State of bit (1 or 0).
5631 */
LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)5632 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
5633 {
5634 uint32_t dma_base_addr = (uint32_t)DMAx;
5635 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
5636 == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
5637 }
5638
5639 /**
5640 * @brief Get user setting error flag.
5641 * @note This API is used for all available DMA channels.
5642 * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
5643 * @param DMAx DMAx Instance
5644 * @param Channel This parameter can be one of the following values:
5645 * @arg @ref LL_DMA_CHANNEL_0
5646 * @arg @ref LL_DMA_CHANNEL_1
5647 * @arg @ref LL_DMA_CHANNEL_2
5648 * @arg @ref LL_DMA_CHANNEL_3
5649 * @arg @ref LL_DMA_CHANNEL_4
5650 * @arg @ref LL_DMA_CHANNEL_5
5651 * @arg @ref LL_DMA_CHANNEL_6
5652 * @arg @ref LL_DMA_CHANNEL_7
5653 * @retval State of bit (1 or 0).
5654 */
LL_DMA_IsActiveFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)5655 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
5656 {
5657 uint32_t dma_base_addr = (uint32_t)DMAx;
5658 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
5659 == (DMA_CSR_USEF)) ? 1UL : 0UL);
5660 }
5661
5662 /**
5663 * @brief Get user setting error flag.
5664 * @note This API is used for all available DMA channels.
5665 * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
5666 * @param DMAx DMAx Instance
5667 * @param Channel This parameter can be one of the following values:
5668 * @arg @ref LL_DMA_CHANNEL_0
5669 * @arg @ref LL_DMA_CHANNEL_1
5670 * @arg @ref LL_DMA_CHANNEL_2
5671 * @arg @ref LL_DMA_CHANNEL_3
5672 * @arg @ref LL_DMA_CHANNEL_4
5673 * @arg @ref LL_DMA_CHANNEL_5
5674 * @arg @ref LL_DMA_CHANNEL_6
5675 * @arg @ref LL_DMA_CHANNEL_7
5676 * @retval State of bit (1 or 0).
5677 */
LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)5678 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
5679 {
5680 uint32_t dma_base_addr = (uint32_t)DMAx;
5681 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
5682 == (DMA_CSR_ULEF)) ? 1UL : 0UL);
5683 }
5684
5685 /**
5686 * @brief Get data transfer error flag.
5687 * @note This API is used for all available DMA channels.
5688 * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
5689 * @param DMAx DMAx Instance
5690 * @param Channel This parameter can be one of the following values:
5691 * @arg @ref LL_DMA_CHANNEL_0
5692 * @arg @ref LL_DMA_CHANNEL_1
5693 * @arg @ref LL_DMA_CHANNEL_2
5694 * @arg @ref LL_DMA_CHANNEL_3
5695 * @arg @ref LL_DMA_CHANNEL_4
5696 * @arg @ref LL_DMA_CHANNEL_5
5697 * @arg @ref LL_DMA_CHANNEL_6
5698 * @arg @ref LL_DMA_CHANNEL_7
5699 * @retval State of bit (1 or 0).
5700 */
LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)5701 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
5702 {
5703 uint32_t dma_base_addr = (uint32_t)DMAx;
5704 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
5705 == (DMA_CSR_DTEF)) ? 1UL : 0UL);
5706 }
5707
5708 /**
5709 * @brief Get half transfer flag.
5710 * @note This API is used for all available DMA channels.
5711 * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
5712 * @param DMAx DMAx Instance
5713 * @param Channel This parameter can be one of the following values:
5714 * @arg @ref LL_DMA_CHANNEL_0
5715 * @arg @ref LL_DMA_CHANNEL_1
5716 * @arg @ref LL_DMA_CHANNEL_2
5717 * @arg @ref LL_DMA_CHANNEL_3
5718 * @arg @ref LL_DMA_CHANNEL_4
5719 * @arg @ref LL_DMA_CHANNEL_5
5720 * @arg @ref LL_DMA_CHANNEL_6
5721 * @arg @ref LL_DMA_CHANNEL_7
5722 * @retval State of bit (1 or 0).
5723 */
LL_DMA_IsActiveFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)5724 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
5725 {
5726 uint32_t dma_base_addr = (uint32_t)DMAx;
5727 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
5728 == (DMA_CSR_HTF)) ? 1UL : 0UL);
5729 }
5730
5731 /**
5732 * @brief Get transfer complete flag.
5733 * @note This API is used for all available DMA channels.
5734 * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
5735 * @param DMAx DMAx Instance
5736 * @param Channel This parameter can be one of the following values:
5737 * @arg @ref LL_DMA_CHANNEL_0
5738 * @arg @ref LL_DMA_CHANNEL_1
5739 * @arg @ref LL_DMA_CHANNEL_2
5740 * @arg @ref LL_DMA_CHANNEL_3
5741 * @arg @ref LL_DMA_CHANNEL_4
5742 * @arg @ref LL_DMA_CHANNEL_5
5743 * @arg @ref LL_DMA_CHANNEL_6
5744 * @arg @ref LL_DMA_CHANNEL_7
5745 * @retval State of bit (1 or 0).
5746 */
LL_DMA_IsActiveFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)5747 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
5748 {
5749 uint32_t dma_base_addr = (uint32_t)DMAx;
5750 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
5751 == (DMA_CSR_TCF)) ? 1UL : 0UL);
5752 }
5753
5754 /**
5755 * @brief Get idle flag.
5756 * @note This API is used for all available DMA channels.
5757 * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
5758 * @param DMAx DMAx Instance
5759 * @param Channel This parameter can be one of the following values:
5760 * @arg @ref LL_DMA_CHANNEL_0
5761 * @arg @ref LL_DMA_CHANNEL_1
5762 * @arg @ref LL_DMA_CHANNEL_2
5763 * @arg @ref LL_DMA_CHANNEL_3
5764 * @arg @ref LL_DMA_CHANNEL_4
5765 * @arg @ref LL_DMA_CHANNEL_5
5766 * @arg @ref LL_DMA_CHANNEL_6
5767 * @arg @ref LL_DMA_CHANNEL_7
5768 * @retval State of bit (1 or 0).
5769 */
LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef * DMAx,uint32_t Channel)5770 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel)
5771 {
5772 uint32_t dma_base_addr = (uint32_t)DMAx;
5773 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
5774 == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
5775 }
5776
5777 /**
5778 * @brief Check if nsecure masked interrupt is active.
5779 * @note This API is used for all available DMA channels.
5780 * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS
5781 * @param DMAx DMAx Instance
5782 * @param Channel This parameter can be one of the following values:
5783 * @arg @ref LL_DMA_CHANNEL_0
5784 * @arg @ref LL_DMA_CHANNEL_1
5785 * @arg @ref LL_DMA_CHANNEL_2
5786 * @arg @ref LL_DMA_CHANNEL_3
5787 * @arg @ref LL_DMA_CHANNEL_4
5788 * @arg @ref LL_DMA_CHANNEL_5
5789 * @arg @ref LL_DMA_CHANNEL_6
5790 * @arg @ref LL_DMA_CHANNEL_7
5791 * @retval State of bit (1 or 0).
5792 */
LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef * DMAx,uint32_t Channel)5793 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel)
5794 {
5795 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
5796 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
5797 }
5798
5799 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5800 /**
5801 * @brief Check if secure masked interrupt is active.
5802 * @note This API is used for all available DMA channels.
5803 * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS
5804 * @param DMAx DMAx Instance
5805 * @param Channel This parameter can be one of the following values:
5806 * @arg @ref LL_DMA_CHANNEL_0
5807 * @arg @ref LL_DMA_CHANNEL_1
5808 * @arg @ref LL_DMA_CHANNEL_2
5809 * @arg @ref LL_DMA_CHANNEL_3
5810 * @arg @ref LL_DMA_CHANNEL_4
5811 * @arg @ref LL_DMA_CHANNEL_5
5812 * @arg @ref LL_DMA_CHANNEL_6
5813 * @arg @ref LL_DMA_CHANNEL_7
5814 * @retval State of bit (1 or 0).
5815 */
LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef * DMAx,uint32_t Channel)5816 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel)
5817 {
5818 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
5819 == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5820 }
5821 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
5822 /**
5823 * @}
5824 */
5825
5826 /** @defgroup DMA_LL_EF_IT_Management Interrupt Management
5827 * @{
5828 */
5829
5830 /**
5831 * @brief Enable trigger overrun interrupt.
5832 * @note This API is used for all available DMA channels.
5833 * @rmtoll CCR TOIE LL_DMA_EnableIT_TO
5834 * @param DMAx DMAx Instance
5835 * @param Channel This parameter can be one of the following values:
5836 * @arg @ref LL_DMA_CHANNEL_0
5837 * @arg @ref LL_DMA_CHANNEL_1
5838 * @arg @ref LL_DMA_CHANNEL_2
5839 * @arg @ref LL_DMA_CHANNEL_3
5840 * @arg @ref LL_DMA_CHANNEL_4
5841 * @arg @ref LL_DMA_CHANNEL_5
5842 * @arg @ref LL_DMA_CHANNEL_6
5843 * @arg @ref LL_DMA_CHANNEL_7
5844 * @retval None.
5845 */
LL_DMA_EnableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)5846 __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
5847 {
5848 uint32_t dma_base_addr = (uint32_t)DMAx;
5849 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
5850 }
5851
5852 /**
5853 * @brief Enable suspension interrupt.
5854 * @note This API is used for all available DMA channels.
5855 * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
5856 * @param DMAx DMAx Instance
5857 * @param Channel This parameter can be one of the following values:
5858 * @arg @ref LL_DMA_CHANNEL_0
5859 * @arg @ref LL_DMA_CHANNEL_1
5860 * @arg @ref LL_DMA_CHANNEL_2
5861 * @arg @ref LL_DMA_CHANNEL_3
5862 * @arg @ref LL_DMA_CHANNEL_4
5863 * @arg @ref LL_DMA_CHANNEL_5
5864 * @arg @ref LL_DMA_CHANNEL_6
5865 * @arg @ref LL_DMA_CHANNEL_7
5866 * @retval None.
5867 */
LL_DMA_EnableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)5868 __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
5869 {
5870 uint32_t dma_base_addr = (uint32_t)DMAx;
5871 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
5872 }
5873
5874 /**
5875 * @brief Enable user setting error interrupt.
5876 * @note This API is used for all available DMA channels.
5877 * @rmtoll CCR USEIE LL_DMA_EnableIT_USE
5878 * @param DMAx DMAx Instance
5879 * @param Channel This parameter can be one of the following values:
5880 * @arg @ref LL_DMA_CHANNEL_0
5881 * @arg @ref LL_DMA_CHANNEL_1
5882 * @arg @ref LL_DMA_CHANNEL_2
5883 * @arg @ref LL_DMA_CHANNEL_3
5884 * @arg @ref LL_DMA_CHANNEL_4
5885 * @arg @ref LL_DMA_CHANNEL_5
5886 * @arg @ref LL_DMA_CHANNEL_6
5887 * @arg @ref LL_DMA_CHANNEL_7
5888 * @retval None.
5889 */
LL_DMA_EnableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)5890 __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
5891 {
5892 uint32_t dma_base_addr = (uint32_t)DMAx;
5893 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
5894 }
5895
5896 /**
5897 * @brief Enable update link transfer error interrupt.
5898 * @note This API is used for all available DMA channels.
5899 * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
5900 * @param DMAx DMAx Instance
5901 * @param Channel This parameter can be one of the following values:
5902 * @arg @ref LL_DMA_CHANNEL_0
5903 * @arg @ref LL_DMA_CHANNEL_1
5904 * @arg @ref LL_DMA_CHANNEL_2
5905 * @arg @ref LL_DMA_CHANNEL_3
5906 * @arg @ref LL_DMA_CHANNEL_4
5907 * @arg @ref LL_DMA_CHANNEL_5
5908 * @arg @ref LL_DMA_CHANNEL_6
5909 * @arg @ref LL_DMA_CHANNEL_7
5910 * @retval None.
5911 */
LL_DMA_EnableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)5912 __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
5913 {
5914 uint32_t dma_base_addr = (uint32_t)DMAx;
5915 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
5916 }
5917
5918 /**
5919 * @brief Enable data transfer error interrupt.
5920 * @note This API is used for all available DMA channels.
5921 * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
5922 * @param DMAx DMAx Instance
5923 * @param Channel This parameter can be one of the following values:
5924 * @arg @ref LL_DMA_CHANNEL_0
5925 * @arg @ref LL_DMA_CHANNEL_1
5926 * @arg @ref LL_DMA_CHANNEL_2
5927 * @arg @ref LL_DMA_CHANNEL_3
5928 * @arg @ref LL_DMA_CHANNEL_4
5929 * @arg @ref LL_DMA_CHANNEL_5
5930 * @arg @ref LL_DMA_CHANNEL_6
5931 * @arg @ref LL_DMA_CHANNEL_7
5932 * @retval None.
5933 */
LL_DMA_EnableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)5934 __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
5935 {
5936 uint32_t dma_base_addr = (uint32_t)DMAx;
5937 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
5938 }
5939
5940 /**
5941 * @brief Enable half transfer complete interrupt.
5942 * @note This API is used for all available DMA channels.
5943 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
5944 * @param DMAx DMAx Instance
5945 * @param Channel This parameter can be one of the following values:
5946 * @arg @ref LL_DMA_CHANNEL_0
5947 * @arg @ref LL_DMA_CHANNEL_1
5948 * @arg @ref LL_DMA_CHANNEL_2
5949 * @arg @ref LL_DMA_CHANNEL_3
5950 * @arg @ref LL_DMA_CHANNEL_4
5951 * @arg @ref LL_DMA_CHANNEL_5
5952 * @arg @ref LL_DMA_CHANNEL_6
5953 * @arg @ref LL_DMA_CHANNEL_7
5954 * @retval None.
5955 */
LL_DMA_EnableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)5956 __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
5957 {
5958 uint32_t dma_base_addr = (uint32_t)DMAx;
5959 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
5960 }
5961
5962 /**
5963 * @brief Enable transfer complete interrupt.
5964 * @note This API is used for all available DMA channels.
5965 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
5966 * @param DMAx DMAx Instance
5967 * @param Channel This parameter can be one of the following values:
5968 * @arg @ref LL_DMA_CHANNEL_0
5969 * @arg @ref LL_DMA_CHANNEL_1
5970 * @arg @ref LL_DMA_CHANNEL_2
5971 * @arg @ref LL_DMA_CHANNEL_3
5972 * @arg @ref LL_DMA_CHANNEL_4
5973 * @arg @ref LL_DMA_CHANNEL_5
5974 * @arg @ref LL_DMA_CHANNEL_6
5975 * @arg @ref LL_DMA_CHANNEL_7
5976 * @retval None.
5977 */
LL_DMA_EnableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)5978 __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
5979 {
5980 uint32_t dma_base_addr = (uint32_t)DMAx;
5981 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
5982 }
5983
5984 /**
5985 * @brief Disable trigger overrun interrupt.
5986 * @note This API is used for all available DMA channels.
5987 * @rmtoll CCR TOIE LL_DMA_DisableIT_TO
5988 * @param DMAx DMAx Instance
5989 * @param Channel This parameter can be one of the following values:
5990 * @arg @ref LL_DMA_CHANNEL_0
5991 * @arg @ref LL_DMA_CHANNEL_1
5992 * @arg @ref LL_DMA_CHANNEL_2
5993 * @arg @ref LL_DMA_CHANNEL_3
5994 * @arg @ref LL_DMA_CHANNEL_4
5995 * @arg @ref LL_DMA_CHANNEL_5
5996 * @arg @ref LL_DMA_CHANNEL_6
5997 * @arg @ref LL_DMA_CHANNEL_7
5998 * @retval None.
5999 */
LL_DMA_DisableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6000 __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6001 {
6002 uint32_t dma_base_addr = (uint32_t)DMAx;
6003 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
6004 }
6005
6006 /**
6007 * @brief Disable suspension interrupt.
6008 * @note This API is used for all available DMA channels.
6009 * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
6010 * @param DMAx DMAx Instance
6011 * @param Channel This parameter can be one of the following values:
6012 * @arg @ref LL_DMA_CHANNEL_0
6013 * @arg @ref LL_DMA_CHANNEL_1
6014 * @arg @ref LL_DMA_CHANNEL_2
6015 * @arg @ref LL_DMA_CHANNEL_3
6016 * @arg @ref LL_DMA_CHANNEL_4
6017 * @arg @ref LL_DMA_CHANNEL_5
6018 * @arg @ref LL_DMA_CHANNEL_6
6019 * @arg @ref LL_DMA_CHANNEL_7
6020 * @retval None.
6021 */
LL_DMA_DisableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6022 __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6023 {
6024 uint32_t dma_base_addr = (uint32_t)DMAx;
6025 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
6026 }
6027
6028 /**
6029 * @brief Disable user setting error interrupt.
6030 * @note This API is used for all available DMA channels.
6031 * @rmtoll CCR USEIE LL_DMA_DisableIT_USE
6032 * @param DMAx DMAx Instance
6033 * @param Channel This parameter can be one of the following values:
6034 * @arg @ref LL_DMA_CHANNEL_0
6035 * @arg @ref LL_DMA_CHANNEL_1
6036 * @arg @ref LL_DMA_CHANNEL_2
6037 * @arg @ref LL_DMA_CHANNEL_3
6038 * @arg @ref LL_DMA_CHANNEL_4
6039 * @arg @ref LL_DMA_CHANNEL_5
6040 * @arg @ref LL_DMA_CHANNEL_6
6041 * @arg @ref LL_DMA_CHANNEL_7
6042 * @retval None.
6043 */
LL_DMA_DisableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6044 __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6045 {
6046 uint32_t dma_base_addr = (uint32_t)DMAx;
6047 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
6048 }
6049
6050 /**
6051 * @brief Disable update link transfer error interrupt.
6052 * @note This API is used for all available DMA channels.
6053 * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
6054 * @param DMAx DMAx Instance
6055 * @param Channel This parameter can be one of the following values:
6056 * @arg @ref LL_DMA_CHANNEL_0
6057 * @arg @ref LL_DMA_CHANNEL_1
6058 * @arg @ref LL_DMA_CHANNEL_2
6059 * @arg @ref LL_DMA_CHANNEL_3
6060 * @arg @ref LL_DMA_CHANNEL_4
6061 * @arg @ref LL_DMA_CHANNEL_5
6062 * @arg @ref LL_DMA_CHANNEL_6
6063 * @arg @ref LL_DMA_CHANNEL_7
6064 * @retval None.
6065 */
LL_DMA_DisableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6066 __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6067 {
6068 uint32_t dma_base_addr = (uint32_t)DMAx;
6069 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
6070 }
6071
6072 /**
6073 * @brief Disable data transfer error interrupt.
6074 * @note This API is used for all available DMA channels.
6075 * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
6076 * @param DMAx DMAx Instance
6077 * @param Channel This parameter can be one of the following values:
6078 * @arg @ref LL_DMA_CHANNEL_0
6079 * @arg @ref LL_DMA_CHANNEL_1
6080 * @arg @ref LL_DMA_CHANNEL_2
6081 * @arg @ref LL_DMA_CHANNEL_3
6082 * @arg @ref LL_DMA_CHANNEL_4
6083 * @arg @ref LL_DMA_CHANNEL_5
6084 * @arg @ref LL_DMA_CHANNEL_6
6085 * @arg @ref LL_DMA_CHANNEL_7
6086 * @retval None.
6087 */
LL_DMA_DisableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6088 __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6089 {
6090 uint32_t dma_base_addr = (uint32_t)DMAx;
6091 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
6092 }
6093
6094 /**
6095 * @brief Disable half transfer complete interrupt.
6096 * @note This API is used for all available DMA channels.
6097 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
6098 * @param DMAx DMAx Instance
6099 * @param Channel This parameter can be one of the following values:
6100 * @arg @ref LL_DMA_CHANNEL_0
6101 * @arg @ref LL_DMA_CHANNEL_1
6102 * @arg @ref LL_DMA_CHANNEL_2
6103 * @arg @ref LL_DMA_CHANNEL_3
6104 * @arg @ref LL_DMA_CHANNEL_4
6105 * @arg @ref LL_DMA_CHANNEL_5
6106 * @arg @ref LL_DMA_CHANNEL_6
6107 * @arg @ref LL_DMA_CHANNEL_7
6108 * @retval None.
6109 */
LL_DMA_DisableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6110 __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6111 {
6112 uint32_t dma_base_addr = (uint32_t)DMAx;
6113 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
6114 }
6115
6116 /**
6117 * @brief Disable transfer complete interrupt.
6118 * @note This API is used for all available DMA channels.
6119 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
6120 * @param DMAx DMAx Instance
6121 * @param Channel This parameter can be one of the following values:
6122 * @arg @ref LL_DMA_CHANNEL_0
6123 * @arg @ref LL_DMA_CHANNEL_1
6124 * @arg @ref LL_DMA_CHANNEL_2
6125 * @arg @ref LL_DMA_CHANNEL_3
6126 * @arg @ref LL_DMA_CHANNEL_4
6127 * @arg @ref LL_DMA_CHANNEL_5
6128 * @arg @ref LL_DMA_CHANNEL_6
6129 * @arg @ref LL_DMA_CHANNEL_7
6130 * @retval None.
6131 */
LL_DMA_DisableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6132 __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6133 {
6134 uint32_t dma_base_addr = (uint32_t)DMAx;
6135 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
6136 }
6137
6138 /**
6139 * @brief Check if trigger overrun interrupt is enabled.
6140 * @note This API is used for all available DMA channels.
6141 * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
6142 * @param DMAx DMAx Instance
6143 * @param Channel This parameter can be one of the following values:
6144 * @arg @ref LL_DMA_CHANNEL_0
6145 * @arg @ref LL_DMA_CHANNEL_1
6146 * @arg @ref LL_DMA_CHANNEL_2
6147 * @arg @ref LL_DMA_CHANNEL_3
6148 * @arg @ref LL_DMA_CHANNEL_4
6149 * @arg @ref LL_DMA_CHANNEL_5
6150 * @arg @ref LL_DMA_CHANNEL_6
6151 * @arg @ref LL_DMA_CHANNEL_7
6152 * @retval State of bit (1 or 0).
6153 */
LL_DMA_IsEnabledIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6154 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6155 {
6156 uint32_t dma_base_addr = (uint32_t)DMAx;
6157 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
6158 == DMA_CCR_TOIE) ? 1UL : 0UL);
6159 }
6160
6161 /**
6162 * @brief Check if suspension interrupt is enabled.
6163 * @note This API is used for all available DMA channels.
6164 * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
6165 * @param DMAx DMAx Instance
6166 * @param Channel This parameter can be one of the following values:
6167 * @arg @ref LL_DMA_CHANNEL_0
6168 * @arg @ref LL_DMA_CHANNEL_1
6169 * @arg @ref LL_DMA_CHANNEL_2
6170 * @arg @ref LL_DMA_CHANNEL_3
6171 * @arg @ref LL_DMA_CHANNEL_4
6172 * @arg @ref LL_DMA_CHANNEL_5
6173 * @arg @ref LL_DMA_CHANNEL_6
6174 * @arg @ref LL_DMA_CHANNEL_7
6175 * @retval State of bit (1 or 0).
6176 */
LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6177 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6178 {
6179 uint32_t dma_base_addr = (uint32_t)DMAx;
6180 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
6181 == DMA_CCR_SUSPIE) ? 1UL : 0UL);
6182 }
6183
6184 /**
6185 * @brief Check if user setting error interrupt is enabled.
6186 * @note This API is used for all available DMA channels.
6187 * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
6188 * @param DMAx DMAx Instance
6189 * @param Channel This parameter can be one of the following values:
6190 * @arg @ref LL_DMA_CHANNEL_0
6191 * @arg @ref LL_DMA_CHANNEL_1
6192 * @arg @ref LL_DMA_CHANNEL_2
6193 * @arg @ref LL_DMA_CHANNEL_3
6194 * @arg @ref LL_DMA_CHANNEL_4
6195 * @arg @ref LL_DMA_CHANNEL_5
6196 * @arg @ref LL_DMA_CHANNEL_6
6197 * @arg @ref LL_DMA_CHANNEL_7
6198 * @retval State of bit (1 or 0).
6199 */
LL_DMA_IsEnabledIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6200 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6201 {
6202 uint32_t dma_base_addr = (uint32_t)DMAx;
6203 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
6204 == DMA_CCR_USEIE) ? 1UL : 0UL);
6205 }
6206
6207 /**
6208 * @brief Check if update link transfer error interrupt is enabled.
6209 * @note This API is used for all available DMA channels.
6210 * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
6211 * @param DMAx DMAx Instance
6212 * @param Channel This parameter can be one of the following values:
6213 * @arg @ref LL_DMA_CHANNEL_0
6214 * @arg @ref LL_DMA_CHANNEL_1
6215 * @arg @ref LL_DMA_CHANNEL_2
6216 * @arg @ref LL_DMA_CHANNEL_3
6217 * @arg @ref LL_DMA_CHANNEL_4
6218 * @arg @ref LL_DMA_CHANNEL_5
6219 * @arg @ref LL_DMA_CHANNEL_6
6220 * @arg @ref LL_DMA_CHANNEL_7
6221 * @retval State of bit (1 or 0).
6222 */
LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6223 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6224 {
6225 uint32_t dma_base_addr = (uint32_t)DMAx;
6226 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
6227 == DMA_CCR_ULEIE) ? 1UL : 0UL);
6228 }
6229
6230 /**
6231 * @brief Check if data transfer error interrupt is enabled.
6232 * @note This API is used for all available DMA channels.
6233 * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
6234 * @param DMAx DMAx Instance
6235 * @param Channel This parameter can be one of the following values:
6236 * @arg @ref LL_DMA_CHANNEL_0
6237 * @arg @ref LL_DMA_CHANNEL_1
6238 * @arg @ref LL_DMA_CHANNEL_2
6239 * @arg @ref LL_DMA_CHANNEL_3
6240 * @arg @ref LL_DMA_CHANNEL_4
6241 * @arg @ref LL_DMA_CHANNEL_5
6242 * @arg @ref LL_DMA_CHANNEL_6
6243 * @arg @ref LL_DMA_CHANNEL_7
6244 * @retval State of bit (1 or 0).
6245 */
LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6246 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6247 {
6248 uint32_t dma_base_addr = (uint32_t)DMAx;
6249 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
6250 == DMA_CCR_DTEIE) ? 1UL : 0UL);
6251 }
6252
6253 /**
6254 * @brief Check if half transfer complete interrupt is enabled.
6255 * @note This API is used for all available DMA channels.
6256 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
6257 * @param DMAx DMAx Instance
6258 * @param Channel This parameter can be one of the following values:
6259 * @arg @ref LL_DMA_CHANNEL_0
6260 * @arg @ref LL_DMA_CHANNEL_1
6261 * @arg @ref LL_DMA_CHANNEL_2
6262 * @arg @ref LL_DMA_CHANNEL_3
6263 * @arg @ref LL_DMA_CHANNEL_4
6264 * @arg @ref LL_DMA_CHANNEL_5
6265 * @arg @ref LL_DMA_CHANNEL_6
6266 * @arg @ref LL_DMA_CHANNEL_7
6267 * @retval State of bit (1 or 0).
6268 */
LL_DMA_IsEnabledIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6269 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6270 {
6271 uint32_t dma_base_addr = (uint32_t)DMAx;
6272 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
6273 == DMA_CCR_HTIE) ? 1UL : 0UL);
6274 }
6275
6276 /**
6277 * @brief Check if transfer complete interrupt is enabled.
6278 * @note This API is used for all available DMA channels.
6279 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
6280 * @param DMAx DMAx Instance
6281 * @param Channel This parameter can be one of the following values:
6282 * @arg @ref LL_DMA_CHANNEL_0
6283 * @arg @ref LL_DMA_CHANNEL_1
6284 * @arg @ref LL_DMA_CHANNEL_2
6285 * @arg @ref LL_DMA_CHANNEL_3
6286 * @arg @ref LL_DMA_CHANNEL_4
6287 * @arg @ref LL_DMA_CHANNEL_5
6288 * @arg @ref LL_DMA_CHANNEL_6
6289 * @arg @ref LL_DMA_CHANNEL_7
6290 * @retval State of bit (1 or 0).
6291 */
LL_DMA_IsEnabledIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6292 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6293 {
6294 uint32_t dma_base_addr = (uint32_t)DMAx;
6295 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
6296 == DMA_CCR_TCIE) ? 1UL : 0UL);
6297 }
6298 /**
6299 * @}
6300 */
6301
6302 #if defined (USE_FULL_LL_DRIVER)
6303 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
6304 * @{
6305 */
6306 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
6307 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
6308
6309 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
6310 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
6311 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
6312
6313 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
6314 LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
6315 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
6316
6317 uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
6318 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
6319 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
6320 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
6321 /**
6322 * @}
6323 */
6324 #endif /* USE_FULL_LL_DRIVER */
6325
6326 /**
6327 * @}
6328 */
6329
6330 /**
6331 * @}
6332 */
6333
6334 #endif /* GPDMA1 */
6335
6336 /**
6337 * @}
6338 */
6339
6340 #ifdef __cplusplus
6341 }
6342 #endif /* __cplusplus */
6343
6344 #endif /* STM32H5xx_LL_DMA_H */
6345
