1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32H7RSxx_LL_DMA_H
41 #define STM32H7RSxx_LL_DMA_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif /* __cplusplus */
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32h7rsxx.h"
49
50 /** @addtogroup STM32H7RSxx_LL_Driver
51 * @{
52 */
53
54 #if (defined (GPDMA1) || defined (HPDMA1))
55
56 /** @defgroup DMA_LL DMA
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62
63 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
64 * @{
65 */
66 #define DMA_CHANNEL0_OFFSET (0x00000050UL)
67 #define DMA_CHANNEL1_OFFSET (0x000000D0UL)
68 #define DMA_CHANNEL2_OFFSET (0x00000150UL)
69 #define DMA_CHANNEL3_OFFSET (0x000001D0UL)
70 #define DMA_CHANNEL4_OFFSET (0x00000250UL)
71 #define DMA_CHANNEL5_OFFSET (0x000002D0UL)
72 #define DMA_CHANNEL6_OFFSET (0x00000350UL)
73 #define DMA_CHANNEL7_OFFSET (0x000003D0UL)
74 #define DMA_CHANNEL8_OFFSET (0x00000450UL)
75 #define DMA_CHANNEL9_OFFSET (0x000004D0UL)
76 #define DMA_CHANNEL10_OFFSET (0x00000550UL)
77 #define DMA_CHANNEL11_OFFSET (0x000005D0UL)
78 #define DMA_CHANNEL12_OFFSET (0x00000650UL)
79 #define DMA_CHANNEL13_OFFSET (0x000006D0UL)
80 #define DMA_CHANNEL14_OFFSET (0x00000750UL)
81 #define DMA_CHANNEL15_OFFSET (0x000007D0UL)
82
83 /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
84 static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
85 {
86 DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
87 DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
88 DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET,
89 DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET,
90 };
91
92 /**
93 * @}
94 */
95
96 /* Private constants ---------------------------------------------------------*/
97 /* Private macros ------------------------------------------------------------*/
98 /* Exported types ------------------------------------------------------------*/
99
100 #if defined (USE_FULL_LL_DRIVER)
101 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
102 * @{
103 */
104
105 /**
106 * @brief LL DMA init structure definition.
107 */
108 typedef struct
109 {
110 uint32_t SrcAddress; /*!< This field specify the data transfer source address.
111 Programming this field is mandatory for all available DMA channels.
112 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
113 This feature can be modified afterwards using unitary function
114 @ref LL_DMA_SetSrcAddress(). */
115
116 uint32_t DestAddress; /*!< This field specify the data transfer destination address.
117 Programming this field is mandatory for all available DMA channels.
118 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
119 This feature can be modified afterwards using unitary function
120 @ref LL_DMA_SetDestAddress(). */
121
122 uint32_t Direction; /*!< This field specify the data transfer direction.
123 Programming this field is mandatory for all available DMA channels.
124 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
125 This feature can be modified afterwards using unitary function
126 @ref LL_DMA_SetDataTransferDirection(). */
127
128 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
129 Programming this field is mandatory for all available DMA channels.
130 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
131 This feature can be modified afterwards using unitary function
132 @ref LL_DMA_SetBlkHWRequest(). */
133
134 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
135 Programming this field is mandatory for all available DMA channels.
136 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
137 This feature can be modified afterwards using unitary function
138 @ref LL_DMA_SetDataAlignment(). */
139
140 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
141 Programming this field is mandatory for all available DMA channels.
142 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
143 This feature can be modified afterwards using unitary function
144 @ref LL_DMA_SetSrcBurstLength(). */
145
146 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
147 Programming this field is mandatory for all available DMA channels.
148 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
149 This feature can be modified afterwards using unitary function
150 @ref LL_DMA_SetDestBurstLength(). */
151
152 uint32_t SrcDataWidth; /*!< This field specify the source data width.
153 Programming this field is mandatory for all available DMA channels.
154 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
155 This feature can be modified afterwards using unitary function
156 @ref LL_DMA_SetSrcDataWidth(). */
157
158 uint32_t DestDataWidth; /*!< This field specify the destination data width.
159 Programming this field is mandatory for all available DMA channels.
160 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
161 This feature can be modified afterwards using unitary function
162 @ref LL_DMA_SetDestDataWidth(). */
163
164 uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
165 Programming this field is mandatory for all available DMA channels.
166 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
167 This feature can be modified afterwards using unitary function
168 @ref LL_DMA_SetSrcIncMode(). */
169
170 uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
171 Programming this field is mandatory for all available DMA channels.
172 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
173 This feature can be modified afterwards using unitary function
174 @ref LL_DMA_SetDestIncMode(). */
175
176 uint32_t Priority; /*!< This field specify the channel priority level.
177 Programming this field is mandatory for all available DMA channels.
178 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
179 This feature can be modified afterwards using unitary function
180 @ref LL_DMA_SetChannelPriorityLevel(). */
181
182 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
183 Programming this field is mandatory for all available DMA channels.
184 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
185 This feature can be modified afterwards using unitary function
186 @ref LL_DMA_SetBlkDataLength(). */
187
188 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
189 Programming this field is mandatory only for 2D addressing channels.
190 This parameter can be a value between 1 and 2048 Min_Data = 0
191 and Max_Data = 0x000007FF.
192 This feature can be modified afterwards using unitary function
193 @ref LL_DMA_SetBlkRptCount(). */
194
195 uint32_t TriggerMode; /*!< This field specify the trigger mode.
196 Programming this field is mandatory for all available DMA channels.
197 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
198 This feature can be modified afterwards using unitary function
199 @ref LL_DMA_SetTriggerMode(). */
200
201 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
202 Programming this field is mandatory for all available DMA channels.
203 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
204 This feature can be modified afterwards using unitary function
205 @ref LL_DMA_SetTriggerPolarity(). */
206
207 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
208 Programming this field is mandatory for all available DMA channels.
209 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
210 This feature can be modified afterwards using unitary function
211 @ref LL_DMA_SetHWTrigger(). */
212
213 uint32_t Request; /*!< This field specify the peripheral request selection.
214 Programming this field is mandatory for all available DMA channels.
215 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
216 This feature can be modified afterwards using unitary function
217 @ref LL_DMA_SetPeriphRequest(). */
218
219 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
220 Programming this field is mandatory for all available DMA channels.
221 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
222 This feature can be modified afterwards using unitary function
223 @ref LL_DMA_SetTransferEventMode(). */
224
225 uint32_t DestWordExchange; /*!< This field specify the destination word exchange.
226 Programming this field is mandatory for all available HPDMA channels.
227 This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE.
228 This feature can be modified afterwards using unitary function
229 @ref LL_DMA_SetDestWordExchange(). */
230
231 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
232 Programming this field is mandatory for all available DMA channels.
233 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
234 This feature can be modified afterwards using unitary function
235 @ref LL_DMA_SetDestHWordExchange(). */
236
237 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
238 Programming this field is mandatory for all available DMA channels.
239 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
240 This feature can be modified afterwards using unitary function
241 @ref LL_DMA_SetDestByteExchange(). */
242
243 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
244 Programming this field is mandatory for all available DMA channels.
245 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
246 This feature can be modified afterwards using unitary function
247 @ref LL_DMA_SetSrcByteExchange(). */
248
249 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
250 Programming this field is mandatory for all available DMA channels.
251 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
252 This feature can be modified afterwards using unitary function
253 @ref LL_DMA_SetSrcAllocatedPort(). */
254
255 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
256 Programming this field is mandatory for all available DMA channels.
257 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
258 This feature can be modified afterwards using unitary function
259 @ref LL_DMA_SetDestAllocatedPort(). */
260
261 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
262 Programming this field is mandatory for all available DMA channels.
263 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
264 This feature can be modified afterwards using unitary function
265 @ref LL_DMA_SetLinkAllocatedPort(). */
266
267 uint32_t LinkStepMode; /*!< This field specify the link step mode.
268 Programming this field is mandatory for all available DMA channels.
269 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
270 This feature can be modified afterwards using unitary function
271 @ref LL_DMA_SetLinkStepMode(). */
272
273 uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode.
274 Programming this field is mandatory only for 2D addressing channels.
275 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.
276 This feature can be modified afterwards using unitary function
277 @ref LL_DMA_SetSrcAddrUpdate(). */
278
279 uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode.
280 Programming this field is mandatory only for 2D addressing channels.
281 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.
282 This feature can be modified afterwards using unitary function
283 @ref LL_DMA_SetDestAddrUpdate(). */
284
285 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
286 Programming this field is mandatory only for 2D addressing channels.
287 This parameter can be a value Between 0 to 0x00001FFF.
288 This feature can be modified afterwards using unitary function
289 @ref LL_DMA_SetSrcAddrUpdateValue(). */
290
291 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
292 Programming this field is mandatory only for 2D addressing channels.
293 This parameter can be a value Between 0 to 0x00001FFF.
294 This feature can be modified afterwards using unitary function
295 @ref LL_DMA_SetDestAddrUpdateValue(). */
296
297 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
298 Programming this field is mandatory only for 2D addressing channels.
299 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.
300 This feature can be modified afterwards using unitary function
301 @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */
302
303 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
304 Programming this field is mandatory only for 2D addressing channels.
305 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.
306 This feature can be modified afterwards using unitary function
307 @ref LL_DMA_SetBlkRptDestAddrUpdate(). */
308
309 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
310 Programming this field is mandatory only for 2D addressing channels.
311 This parameter can be a value Between 0 to 0x0000FFFF.
312 This feature can be modified afterwards using unitary function
313 @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */
314
315 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
316 Programming this field is mandatory only for 2D addressing channels.
317 This parameter can be a value Between 0 to 0x0000FFFF.
318 This feature can be modified afterwards using unitary function
319 @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */
320
321 uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
322 Programming this field is mandatory for all available DMA channels.
323 This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
324 bytes are always forced to 0).
325 This feature can be modified afterwards using unitary function
326 @ref LL_DMA_SetLinkedListBaseAddr(). */
327
328 uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
329 Programming this field is mandatory for all available DMA channels.
330 This parameter can be a value Between 0 to 0x0000FFFC.
331 This feature can be modified afterwards using unitary function
332 @ref LL_DMA_SetLinkedListAddrOffset(). */
333
334 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel.
335 This parameter can be a value of @ref DMA_LL_TRANSFER_MODE */
336 } LL_DMA_InitTypeDef;
337
338
339 /**
340 * @brief LL DMA init linked list structure definition.
341 */
342 typedef struct
343 {
344 uint32_t Priority; /*!< This field specify the channel priority level.
345 Programming this field is mandatory for all available DMA channels.
346 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
347 This feature can be modified afterwards using unitary function
348 @ref LL_DMA_SetChannelPriorityLevel(). */
349
350 uint32_t LinkStepMode; /*!< This field specify the link step mode.
351 Programming this field is mandatory for all available DMA channels.
352 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
353 This feature can be modified afterwards using unitary function
354 @ref LL_DMA_SetLinkStepMode(). */
355
356 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
357 Programming this field is mandatory for all available DMA channels.
358 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
359 This feature can be modified afterwards using unitary function
360 @ref LL_DMA_SetLinkAllocatedPort(). */
361
362 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
363 Programming this field is mandatory for all available DMA channels.
364 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
365 This feature can be modified afterwards using unitary function
366 @ref LL_DMA_SetTransferEventMode(). */
367 } LL_DMA_InitLinkedListTypeDef;
368
369
370 /**
371 * @brief LL DMA node init structure definition.
372 */
373 typedef struct
374 {
375 /* CTR1 register fields ******************************************************
376 If any CTR1 fields need to be updated comparing to previous node, it is
377 mandatory to update the new value in CTR1 register fields and enable update
378 CTR1 register in UpdateRegisters fields if it is not enabled in the
379 previous node.
380
381 */
382 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
383 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
384
385 uint32_t DestWordExchange; /*!< This field specify the destination word exchange.
386 This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE. */
387
388 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
389 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
390
391 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
392 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
393
394 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
395 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
396
397 uint32_t DestIncMode; /*!< This field specify the destination increment mode.
398 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
399
400 uint32_t DestDataWidth; /*!< This field specify the destination data width.
401 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
402
403 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
404 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
405
406 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
407 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
408
409 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
410 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
411
412 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
413 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
414
415 uint32_t SrcIncMode; /*!< This field specify the source increment mode.
416 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
417
418 uint32_t SrcDataWidth; /*!< This field specify the source data width.
419 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
420
421
422 /* CTR2 register fields ******************************************************
423 If any CTR2 fields need to be updated comparing to previous node, it is
424 mandatory to update the new value in CTR2 register fields and enable update
425 CTR2 register in UpdateRegisters fields if it is not enabled in the
426 previous node.
427
428 For all node created, filling all fields is mandatory.
429 */
430 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
431 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
432
433 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
434 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
435
436 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
437 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
438
439 uint32_t TriggerMode; /*!< This field specify the trigger mode.
440 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
441
442 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
443 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
444
445 uint32_t Direction; /*!< This field specify the transfer direction.
446 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
447
448 uint32_t Request; /*!< This field specify the peripheral request selection.
449 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
450
451 uint32_t Mode; /*!< This field DMA Transfer Mode.
452 This parameter can be a value of @ref DMA_LL_TRANSFER_MODE. */
453
454 /* CBR1 register fields ******************************************************
455 If any CBR1 fields need to be updated comparing to previous node, it is
456 mandatory to update the new value in CBR1 register fields and enable update
457 CBR1 register in UpdateRegisters fields if it is not enabled in the
458 previous node.
459
460 If the node to be created is not for 2D addressing channels, there is no
461 need to fill the following fields for CBR1 register :
462 - BlkReptDestAddrUpdate.
463 - BlkRptSrcAddrUpdate.
464 - DestAddrUpdate.
465 - SrcAddrUpdate.
466 - BlkRptCount.
467 */
468 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
469 This parameter can be a value of
470 @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */
471
472 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
473 This parameter can be a value of
474 @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */
475
476 uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode.
477 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */
478
479 uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode.
480 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */
481
482 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
483 This parameter can be a value between 1 and 2048 Min_Data = 0
484 and Max_Data = 0x000007FF. */
485
486 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
487 This parameter must be a value between Min_Data = 0
488 and Max_Data = 0x0000FFFF. */
489
490 /* CSAR register fields ******************************************************
491 If any CSAR fields need to be updated comparing to previous node, it is
492 mandatory to update the new value in CSAR register fields and enable update
493 CSAR register in UpdateRegisters fields if it is not enabled in the
494 previous node.
495
496 For all node created, filling all fields is mandatory.
497 */
498 uint32_t SrcAddress; /*!< This field specify the transfer source address.
499 This parameter must be a value between Min_Data = 0
500 and Max_Data = 0xFFFFFFFF. */
501
502
503 /* CDAR register fields ******************************************************
504 If any CDAR fields need to be updated comparing to previous node, it is
505 mandatory to update the new value in CDAR register fields and enable update
506 CDAR register in UpdateRegisters fields if it is not enabled in the
507 previous node.
508
509 For all node created, filling all fields is mandatory.
510 */
511 uint32_t DestAddress; /*!< This field specify the transfer destination address.
512 This parameter must be a value between Min_Data = 0
513 and Max_Data = 0xFFFFFFFF. */
514
515 /* CTR3 register fields ******************************************************
516 If any CTR3 fields need to be updated comparing to previous node, it is
517 mandatory to update the new value in CTR3 register fields and enable update
518 CTR3 register in UpdateRegisters fields if it is not enabled in the
519 previous node.
520
521 This register is used only for 2D addressing channels.
522 If used channel is linear addressing, this register will be overwritten by
523 CLLR register in memory.
524 When this register is enabled on UpdateRegisters and the selected channel
525 is linear addressing, LL APIs will discard this register update in memory.
526 */
527 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
528 This parameter can be a value Between 0 to 0x00001FFF. */
529
530 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
531 This parameter can be a value Between 0 to 0x00001FFF. */
532
533
534 /* CBR2 register fields ******************************************************
535 If any CBR2 fields need to be updated comparing to previous node, it is
536 mandatory to update the new value in CBR2 register fields and enable update
537 CBR2 register in UpdateRegisters fields if it is not enabled in the
538 previous node.
539
540 This register is used only for 2D addressing channels.
541 If used channel is linear addressing, this register will be discarded in
542 memory. When this register is enabled on UpdateRegisters and the selected
543 channel is linear addressing, LL APIs will discard this register update in
544 memory.
545 */
546 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
547 This parameter can be a value Between 0 to 0x0000FFFF. */
548
549 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
550 This parameter can be a value Between 0 to 0x0000FFFF. */
551
552 /* CLLR register fields ******************************************************
553 If any CLLR fields need to be updated comparing to previous node, it is
554 mandatory to update the new value in CLLR register fields and enable update
555 CLLR register in UpdateRegisters fields if it is not enabled in the
556 previous node.
557
558 If used channel is linear addressing, there is no need to enable/disable
559 CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded
560 by LL APIs.
561 */
562 uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
563 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
564
565 /* DMA Node type field *******************************************************
566 This parameter defines node types as node size and node content varies
567 between channels.
568 Thanks to this fields, linked list queue could be created independently
569 from channel selection. So, one queue could be executed by all DMA channels.
570 */
571 uint32_t NodeType; /*!< Specifies the node type to be created.
572 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
573 } LL_DMA_InitNodeTypeDef;
574
575 /**
576 * @brief LL DMA linked list node structure definition.
577 * @note For 2D addressing channels, the maximum node size is :
578 * (4 Bytes * 8 registers = 32 Bytes).
579 * For GPDMA & HPDMA linear addressing channels, the maximum node size is :
580 * (4 Bytes * 6 registers = 24 Bytes).
581 */
582 typedef struct
583 {
584 __IO uint32_t LinkRegisters[8U];
585
586 } LL_DMA_LinkNodeTypeDef;
587 /**
588 * @}
589 */
590
591 #endif /* USE_FULL_LL_DRIVER */
592
593 /* Exported constants --------------------------------------------------------*/
594
595 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
596 * @{
597 */
598
599 /** @defgroup DMA_LL_EC_CHANNEL Channel
600 * @{
601 */
602 #define LL_DMA_CHANNEL_0 (0x00U)
603 #define LL_DMA_CHANNEL_1 (0x01U)
604 #define LL_DMA_CHANNEL_2 (0x02U)
605 #define LL_DMA_CHANNEL_3 (0x03U)
606 #define LL_DMA_CHANNEL_4 (0x04U)
607 #define LL_DMA_CHANNEL_5 (0x05U)
608 #define LL_DMA_CHANNEL_6 (0x06U)
609 #define LL_DMA_CHANNEL_7 (0x07U)
610 #define LL_DMA_CHANNEL_8 (0x08U)
611 #define LL_DMA_CHANNEL_9 (0x09U)
612 #define LL_DMA_CHANNEL_10 (0x0AU)
613 #define LL_DMA_CHANNEL_11 (0x0BU)
614 #define LL_DMA_CHANNEL_12 (0x0CU)
615 #define LL_DMA_CHANNEL_13 (0x0DU)
616 #define LL_DMA_CHANNEL_14 (0x0EU)
617 #define LL_DMA_CHANNEL_15 (0x0FU)
618 #if defined (USE_FULL_LL_DRIVER)
619 #define LL_DMA_CHANNEL_ALL (0x10U)
620 #endif /* USE_FULL_LL_DRIVER */
621 /**
622 * @}
623 */
624
625 #if defined (USE_FULL_LL_DRIVER)
626 /** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
627 * @{
628 */
629 #define LL_DMA_CLLR_OFFSET0 (0x00U)
630 #define LL_DMA_CLLR_OFFSET1 (0x01U)
631 #define LL_DMA_CLLR_OFFSET2 (0x02U)
632 #define LL_DMA_CLLR_OFFSET3 (0x03U)
633 #define LL_DMA_CLLR_OFFSET4 (0x04U)
634 #define LL_DMA_CLLR_OFFSET5 (0x05U)
635 #define LL_DMA_CLLR_OFFSET6 (0x06U)
636 #define LL_DMA_CLLR_OFFSET7 (0x07U)
637 /**
638 * @}
639 */
640 #endif /* USE_FULL_LL_DRIVER */
641
642 /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level
643 * @{
644 */
645 #define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
646 #define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
647 #define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
648 #define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
649 /**
650 * @}
651 */
652
653 /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
654 * @{
655 */
656 #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
657 #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
658 /**
659 * @}
660 */
661
662 /** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
663 * @{
664 */
665 #define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
666 #define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
667 /**
668 * @}
669 */
670
671 /** @defgroup DMA_LL_EC_DEST_WORD_EXCHANGE Destination Word Exchange
672 * @{
673 */
674 #define LL_DMA_DEST_WORD_PRESERVE 0x00000000U /*!< No destination Word exchange when destination data width
675 is double-word */
676 #define LL_DMA_DEST_WORD_EXCHANGE DMA_CTR1_DWX /*!< Destination Word exchange when destination data width
677 is double-word */
678 /**
679 * @}
680 */
681
682 /** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
683 * @{
684 */
685 #define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width
686 is word */
687 #define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width
688 is word */
689 /**
690 * @}
691 */
692
693 /** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
694 * @{
695 */
696 #define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
697 #define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
698 /**
699 * @}
700 */
701
702 /** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
703 * @{
704 */
705 #define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
706 #define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
707 /**
708 * @}
709 */
710
711 /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
712 * @{
713 */
714 #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
715 #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
716 /**
717 * @}
718 */
719
720 /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
721 * @{
722 */
723 #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
724 #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
725 /**
726 * @}
727 */
728
729 /** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
730 * @{
731 */
732 #define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
733 #define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
734 /**
735 * @}
736 */
737
738 /** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
739 * @{
740 */
741 #define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
742 #define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
743 #define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
744 #define LL_DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination Data Width : DoubleWord */
745 /**
746 * @}
747 */
748
749 /** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
750 * @{
751 */
752 #define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
753 => Right Aligned padded with 0 up to destination
754 data width.
755 If src data width > dest data width :
756 => Right Aligned Left Truncated down to destination
757 data width. */
758 #define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
759 => Right Aligned padded with sign extended up to destination
760 data width.
761 If src data width > dest data width :
762 => Left Aligned Right Truncated down to the destination
763 data width */
764 #define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
765 => Packed at the destination data width
766 If src data width > dest data width :
767 => Unpacked at the destination data width */
768 /**
769 * @}
770 */
771
772 /** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
773 * @{
774 */
775 #define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
776 #define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
777 /**
778 * @}
779 */
780
781 /** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
782 * @{
783 */
784 #define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
785 #define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
786 #define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
787 #define LL_DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source Data Width : DoubleWord */
788 /**
789 * @}
790 */
791
792 /** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
793 * @{
794 */
795 #define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
796 request/acknowledge protocol at a burst level */
797 #define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
798 request/acknowledge protocol at a block level */
799 /**
800 * @}
801 */
802
803 /** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
804 * @{
805 */
806 #define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
807 (respectively half) end of each block */
808 #define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
809 (respectively half) end of the repeated block */
810 #define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
811 (respectively half) end of each linked-list item */
812 #define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
813 (respectively half) end of the last linked-list item */
814 /**
815 * @}
816 */
817
818 /** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
819 * @{
820 */
821 #define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
822 Masked trigger event */
823 #define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
824 edge of the selected trigger event input */
825 #define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
826 edge of the selected trigger event input */
827 /**
828 * @}
829 */
830
831 /** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
832 * @{
833 */
834 #define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
835 one hit trigger */
836 #define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
837 one hit trigger */
838 #define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
839 one hit trigger */
840 #define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
841 one hit trigger */
842 /**
843 * @}
844 */
845
846 /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
847 * @{
848 */
849 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
850 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
851 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
852 /**
853 * @}
854 */
855
856 /** @defgroup DMA_LL_TRANSFER_MODE Transfer Mode
857 * @{
858 */
859 #define LL_DMA_NORMAL 0x00000000U /*!< Normal DMA transfer */
860 #define LL_DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */
861 /**
862 * @}
863 */
864
865 /** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode
866 * @{
867 */
868 #define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block
869 transfer by source update value */
870 #define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block
871 transfer by source update value */
872 /**
873 * @}
874 */
875
876 /** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode
877 * @{
878 */
879 #define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block
880 transfer by destination update value */
881 #define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block
882 transfer by destination update value */
883 /**
884 * @}
885 */
886
887 /** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode
888 * @{
889 */
890 #define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst
891 transfer by source update value */
892 #define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst
893 transfer by source update value */
894 /**
895 * @}
896 */
897
898 /** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode
899 * @{
900 */
901 #define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each
902 burst transfer by destination update value */
903 #define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each
904 burst transfer by destination update value */
905 /**
906 * @}
907 */
908
909 /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
910 * @{
911 */
912 #define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
913 #define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */
914 #define LL_DMA_HPDMA_LINEAR_NODE 0x04U /*!< HPDMA node : linear addressing node */
915 #define LL_DMA_HPDMA_2D_NODE 0x08U /*!< HPDMA node : 2 dimension addressing node */
916
917 /**
918 * @}
919 */
920
921 /** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
922 * @{
923 */
924 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
925 available for all DMA channels */
926 #define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
927 available for all DMA channels */
928 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
929 available for all DMA channels */
930 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
931 available for all DMA channels */
932 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
933 available for all DMA channels */
934 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
935 available only for 2D addressing DMA channels */
936 #define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory :
937 available only for 2D addressing DMA channels */
938 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
939 available for all DMA channels */
940 /**
941 * @}
942 */
943
944 /** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
945 * @{
946 */
947 /* HPDMA1 requests */
948 #define LL_HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_RX */
949 #define LL_HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_TX */
950 #define LL_HPDMA1_REQUEST_XSPI1 2U /*!< HPDMA1 HW request is XSPI1 */
951 #define LL_HPDMA1_REQUEST_XSPI2 3U /*!< HPDMA1 HW request is XSPI2 */
952 #define LL_HPDMA1_REQUEST_SPI3_RX 4U /*!< HPDMA1 HW request is SPI3_RX */
953 #define LL_HPDMA1_REQUEST_SPI3_TX 5U /*!< HPDMA1 HW request is SPI3_TX */
954 #define LL_HPDMA1_REQUEST_SPI4_RX 6U /*!< HPDMA1 HW request is SPI4_RX */
955 #define LL_HPDMA1_REQUEST_SPI4_TX 7U /*!< HPDMA1 HW request is SPI4_TX */
956 #define LL_HPDMA1_REQUEST_ADC1 8U /*!< HPDMA1 HW request is ADC1 */
957 #define LL_HPDMA1_REQUEST_ADC2 9U /*!< HPDMA1 HW request is ADC2 */
958 #define LL_HPDMA1_REQUEST_ADF1_FLT0 10U /*!< HPDMA1 HW request is ADF1_FLT0 */
959 #define LL_HPDMA1_REQUEST_UART4_RX 11U /*!< HPDMA1 HW request is UART4_RX */
960 #define LL_HPDMA1_REQUEST_UART4_TX 12U /*!< HPDMA1 HW request is UART4_TX */
961 #define LL_HPDMA1_REQUEST_UART5_RX 13U /*!< HPDMA1 HW request is UART5_RX */
962 #define LL_HPDMA1_REQUEST_UART5_TX 14U /*!< HPDMA1 HW request is UART5_TX */
963 #define LL_HPDMA1_REQUEST_UART7_RX 15U /*!< HPDMA1 HW request is UART7_RX */
964 #define LL_HPDMA1_REQUEST_UART7_TX 16U /*!< HPDMA1 HW request is UART7_TX */
965 #define LL_HPDMA1_REQUEST_LPTIM2_IC1 17U /*!< HPDMA1 HW request is LPTIM2_IC1 */
966 #define LL_HPDMA1_REQUEST_LPTIM2_IC2 18U /*!< HPDMA1 HW request is LPTIM2_IC2 */
967 #define LL_HPDMA1_REQUEST_LPTIM2_UE 19U /*!< HPDMA1 HW request is LPTIM2_UE */
968
969 /* GPDMA1 requests */
970 #define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */
971 #define LL_GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */
972 #define LL_GPDMA1_REQUEST_CRYP_IN 2U /*!< GPDMA1 HW request is CRYP_IN */
973 #define LL_GPDMA1_REQUEST_CRYP_OUT 3U /*!< GPDMA1 HW request is CRYP_OUT */
974 #define LL_GPDMA1_REQUEST_SAES_IN 4U /*!< GPDMA1 HW request is SAES_IN */
975 #define LL_GPDMA1_REQUEST_SAES_OUT 5U /*!< GPDMA1 HW request is SAES_OUT */
976 #define LL_GPDMA1_REQUEST_HASH_IN 6U /*!< GPDMA1 HW request is HASH_IN */
977 #define LL_GPDMA1_REQUEST_TIM1_CH1 7U /*!< GPDMA1 HW request is TIM1_CH1 */
978 #define LL_GPDMA1_REQUEST_TIM1_CH2 8U /*!< GPDMA1 HW request is TIM1_CH2 */
979 #define LL_GPDMA1_REQUEST_TIM1_CH3 9U /*!< GPDMA1 HW request is TIM1_CH3 */
980 #define LL_GPDMA1_REQUEST_TIM1_CH4 10U /*!< GPDMA1 HW request is TIM1_CH4 */
981 #define LL_GPDMA1_REQUEST_TIM1_UP 11U /*!< GPDMA1 HW request is TIM1_UP */
982 #define LL_GPDMA1_REQUEST_TIM1_TRIG 12U /*!< GPDMA1 HW request is TIM1_TRIG */
983 #define LL_GPDMA1_REQUEST_TIM1_COM 13U /*!< GPDMA1 HW request is TIM1_COM */
984 #define LL_GPDMA1_REQUEST_TIM2_CH1 14U /*!< GPDMA1 HW request is TIM2_CH1 */
985 #define LL_GPDMA1_REQUEST_TIM2_CH2 15U /*!< GPDMA1 HW request is TIM2_CH2 */
986 #define LL_GPDMA1_REQUEST_TIM2_CH3 16U /*!< GPDMA1 HW request is TIM2_CH3 */
987 #define LL_GPDMA1_REQUEST_TIM2_CH4 17U /*!< GPDMA1 HW request is TIM2_CH4 */
988 #define LL_GPDMA1_REQUEST_TIM2_UP 18U /*!< GPDMA1 HW request is TIM2_UP */
989 #define LL_GPDMA1_REQUEST_TIM2_TRIG 19U /*!< GPDMA1 HW request is TIM2_TRIG */
990 #define LL_GPDMA1_REQUEST_TIM3_CH1 20U /*!< GPDMA1 HW request is TIM3_CH1 */
991 #define LL_GPDMA1_REQUEST_TIM3_CH2 21U /*!< GPDMA1 HW request is TIM3_CH2 */
992 #define LL_GPDMA1_REQUEST_TIM3_CH3 22U /*!< GPDMA1 HW request is TIM3_CH3 */
993 #define LL_GPDMA1_REQUEST_TIM3_CH4 23U /*!< GPDMA1 HW request is TIM3_CH4 */
994 #define LL_GPDMA1_REQUEST_TIM3_UP 24U /*!< GPDMA1 HW request is TIM3_UP */
995 #define LL_GPDMA1_REQUEST_TIM3_TRIG 25U /*!< GPDMA1 HW request is TIM3_TRIG */
996 #define LL_GPDMA1_REQUEST_TIM4_CH1 26U /*!< GPDMA1 HW request is TIM4_CH1 */
997 #define LL_GPDMA1_REQUEST_TIM4_CH2 27U /*!< GPDMA1 HW request is TIM4_CH2 */
998 #define LL_GPDMA1_REQUEST_TIM4_CH3 28U /*!< GPDMA1 HW request is TIM4_CH3 */
999 #define LL_GPDMA1_REQUEST_TIM4_CH4 29U /*!< GPDMA1 HW request is TIM4_CH4 */
1000 #define LL_GPDMA1_REQUEST_TIM4_UP 30U /*!< GPDMA1 HW request is TIM4_UP */
1001 #define LL_GPDMA1_REQUEST_TIM4_TRIG 31U /*!< GPDMA1 HW request is TIM4_TRIG */
1002 #define LL_GPDMA1_REQUEST_TIM5_CH1 32U /*!< GPDMA1 HW request is TIM5_CH1 */
1003 #define LL_GPDMA1_REQUEST_TIM5_CH2 33U /*!< GPDMA1 HW request is TIM5_CH2 */
1004 #define LL_GPDMA1_REQUEST_TIM5_CH3 34U /*!< GPDMA1 HW request is TIM5_CH3 */
1005 #define LL_GPDMA1_REQUEST_TIM5_CH4 35U /*!< GPDMA1 HW request is TIM5_CH4 */
1006 #define LL_GPDMA1_REQUEST_TIM5_UP 36U /*!< GPDMA1 HW request is TIM5_UP */
1007 #define LL_GPDMA1_REQUEST_TIM5_TRIG 37U /*!< GPDMA1 HW request is TIM5_TRIG */
1008 #define LL_GPDMA1_REQUEST_TIM6_UP 38U /*!< GPDMA1 HW request is TIM6_UP */
1009 #define LL_GPDMA1_REQUEST_TIM7_UP 39U /*!< GPDMA1 HW request is TIM7_UP */
1010 #define LL_GPDMA1_REQUEST_TIM15_CH1 40U /*!< GPDMA1 HW request is TIM15_CH1 */
1011 #define LL_GPDMA1_REQUEST_TIM15_CH2 41U /*!< GPDMA1 HW request is TIM15_CH2 */
1012 #define LL_GPDMA1_REQUEST_TIM15_UP 42U /*!< GPDMA1 HW request is TIM15_UP */
1013 #define LL_GPDMA1_REQUEST_TIM15_TRIG 43U /*!< GPDMA1 HW request is TIM15_TRIG */
1014 #define LL_GPDMA1_REQUEST_TIM15_COM 44U /*!< GPDMA1 HW request is TIM15_COM */
1015 #define LL_GPDMA1_REQUEST_TIM16_CH1 45U /*!< GPDMA1 HW request is TIM16_CH1 */
1016 #define LL_GPDMA1_REQUEST_TIM16_UP 46U /*!< GPDMA1 HW request is TIM16_UP */
1017 #define LL_GPDMA1_REQUEST_TIM16_COM 47U /*!< GPDMA1 HW request is TIM16_COM */
1018 #define LL_GPDMA1_REQUEST_TIM17_CH1 48U /*!< GPDMA1 HW request is TIM17_CH1 */
1019 #define LL_GPDMA1_REQUEST_TIM17_UP 49U /*!< GPDMA1 HW request is TIM17_UP */
1020 #define LL_GPDMA1_REQUEST_TIM17_COM 50U /*!< GPDMA1 HW request is TIM17_COM */
1021 #define LL_GPDMA1_REQUEST_SPI1_RX 51U /*!< GPDMA1 HW request is SPI1_RX */
1022 #define LL_GPDMA1_REQUEST_SPI1_TX 52U /*!< GPDMA1 HW request is SPI1_TX */
1023 #define LL_GPDMA1_REQUEST_SPI2_RX 53U /*!< GPDMA1 HW request is SPI2_RX */
1024 #define LL_GPDMA1_REQUEST_SPI2_TX 54U /*!< GPDMA1 HW request is SPI2_TX */
1025 #define LL_GPDMA1_REQUEST_SPI3_RX 55U /*!< GPDMA1 HW request is SPI3_RX */
1026 #define LL_GPDMA1_REQUEST_SPI3_TX 56U /*!< GPDMA1 HW request is SPI3_TX */
1027 #define LL_GPDMA1_REQUEST_SPI4_RX 57U /*!< GPDMA1 HW request is SPI4_RX */
1028 #define LL_GPDMA1_REQUEST_SPI4_TX 58U /*!< GPDMA1 HW request is SPI4_TX */
1029 #define LL_GPDMA1_REQUEST_SPI5_RX 59U /*!< GPDMA1 HW request is SPI5_RX */
1030 #define LL_GPDMA1_REQUEST_SPI5_TX 60U /*!< GPDMA1 HW request is SPI5_TX */
1031 #define LL_GPDMA1_REQUEST_SPI6_RX 61U /*!< GPDMA1 HW request is SPI6_RX */
1032 #define LL_GPDMA1_REQUEST_SPI6_TX 62U /*!< GPDMA1 HW request is SPI6_TX */
1033 #define LL_GPDMA1_REQUEST_SAI1_A 63U /*!< GPDMA1 HW request is SAI1_A */
1034 #define LL_GPDMA1_REQUEST_SAI1_B 64U /*!< GPDMA1 HW request is SAI1_B */
1035 #define LL_GPDMA1_REQUEST_SAI2_A 65U /*!< GPDMA1 HW request is SAI2_A */
1036 #define LL_GPDMA1_REQUEST_SAI2_B 66U /*!< GPDMA1 HW request is SAI2_B */
1037 #define LL_GPDMA1_REQUEST_I2C1_RX 67U /*!< GPDMA1 HW request is I2C1_RX */
1038 #define LL_GPDMA1_REQUEST_I2C1_TX 68U /*!< GPDMA1 HW request is I2C1_TX */
1039 #define LL_GPDMA1_REQUEST_I2C2_RX 69U /*!< GPDMA1 HW request is I2C2_RX */
1040 #define LL_GPDMA1_REQUEST_I2C2_TX 70U /*!< GPDMA1 HW request is I2C2_TX */
1041 #define LL_GPDMA1_REQUEST_I2C3_RX 71U /*!< GPDMA1 HW request is I2C3_RX */
1042 #define LL_GPDMA1_REQUEST_I2C3_TX 72U /*!< GPDMA1 HW request is I2C3_TX */
1043 #define LL_GPDMA1_REQUEST_USART1_RX 73U /*!< GPDMA1 HW request is USART1_RX */
1044 #define LL_GPDMA1_REQUEST_USART1_TX 74U /*!< GPDMA1 HW request is USART1_TX */
1045 #define LL_GPDMA1_REQUEST_USART2_RX 75U /*!< GPDMA1 HW request is USART2_RX */
1046 #define LL_GPDMA1_REQUEST_USART2_TX 76U /*!< GPDMA1 HW request is USART2_TX */
1047 #define LL_GPDMA1_REQUEST_USART3_RX 77U /*!< GPDMA1 HW request is USART3_RX */
1048 #define LL_GPDMA1_REQUEST_USART3_TX 78U /*!< GPDMA1 HW request is USART3_TX */
1049 #define LL_GPDMA1_REQUEST_UART4_RX 79U /*!< GPDMA1 HW request is UART4_RX */
1050 #define LL_GPDMA1_REQUEST_UART4_TX 80U /*!< GPDMA1 HW request is UART4_TX */
1051 #define LL_GPDMA1_REQUEST_UART5_RX 81U /*!< GPDMA1 HW request is UART5_RX */
1052 #define LL_GPDMA1_REQUEST_UART5_TX 82U /*!< GPDMA1 HW request is UART5_TX */
1053 #define LL_GPDMA1_REQUEST_UART7_RX 83U /*!< GPDMA1 HW request is UART7_RX */
1054 #define LL_GPDMA1_REQUEST_UART7_TX 84U /*!< GPDMA1 HW request is UART7_TX */
1055 #define LL_GPDMA1_REQUEST_UART8_RX 85U /*!< GPDMA1 HW request is UART8_RX */
1056 #define LL_GPDMA1_REQUEST_UART8_TX 86U /*!< GPDMA1 HW request is UART8_TX */
1057 #define LL_GPDMA1_REQUEST_CORDIC_READ 87U /*!< GPDMA1 HW request is CORDIC_READ */
1058 #define LL_GPDMA1_REQUEST_CORDIC_WRITE 88U /*!< GPDMA1 HW request is CORDIC_WRITE */
1059 #define LL_GPDMA1_REQUEST_LPTIM1_IC1 89U /*!< GPDMA1 HW request is LPTIM1_IC1 */
1060 #define LL_GPDMA1_REQUEST_LPTIM1_IC2 90U /*!< GPDMA1 HW request is LPTIM1_IC2 */
1061 #define LL_GPDMA1_REQUEST_LPTIM1_UE 91U /*!< GPDMA1 HW request is LPTIM1_UE */
1062 #define LL_GPDMA1_REQUEST_LPTIM2_IC1 92U /*!< GPDMA1 HW request is LPTIM2_IC1 */
1063 #define LL_GPDMA1_REQUEST_LPTIM2_IC2 93U /*!< GPDMA1 HW request is LPTIM2_IC2 */
1064 #define LL_GPDMA1_REQUEST_LPTIM2_UE 94U /*!< GPDMA1 HW request is LPTIM2_UE */
1065 #define LL_GPDMA1_REQUEST_SPDIF_RX_DT 95U /*!< GPDMA1 HW request is SPDIF_RX_DT */
1066 #define LL_GPDMA1_REQUEST_SPDIF_RX_CS 96U /*!< GPDMA1 HW request is SPDIF_RX_CS */
1067 #define LL_GPDMA1_REQUEST_ADF1_FLT0 97U /*!< GPDMA1 HW request is ADF1_FLT0 */
1068 #define LL_GPDMA1_REQUEST_UCPD1_TX 98U /*!< GPDMA1 HW request is UCPD1_TX */
1069 #define LL_GPDMA1_REQUEST_UCPD1_RX 99U /*!< GPDMA1 HW request is USBPD_RX */
1070 #define LL_GPDMA1_REQUEST_PSSI 100U /*!< GPDMA1 HW request is PSSI */
1071 #define LL_GPDMA1_REQUEST_LPUART1_RX 101U /*!< GPDMA1 HW request is LPUART1_RX */
1072 #define LL_GPDMA1_REQUEST_LPUART1_TX 102U /*!< GPDMA1 HW request is LPUART1_TX */
1073 #define LL_GPDMA1_REQUEST_LPTIM3_IC1 103U /*!< GPDMA1 HW request is LPTIM3_IC1 */
1074 #define LL_GPDMA1_REQUEST_LPTIM3_IC2 104U /*!< GPDMA1 HW request is LPTIM3_IC2 */
1075 #define LL_GPDMA1_REQUEST_LPTIM3_UE 105U /*!< GPDMA1 HW request is LPTIM3_UE */
1076 #define LL_GPDMA1_REQUEST_I3C1_RX 106U /*!< GPDMA1 HW request is I3C1_RX */
1077 #define LL_GPDMA1_REQUEST_I3C1_TX 107U /*!< GPDMA1 HW request is I3C1_TX */
1078 #define LL_GPDMA1_REQUEST_I3C1_TC 108U /*!< GPDMA1 HW request is I3C1_TC */
1079 #define LL_GPDMA1_REQUEST_I3C1_RS 109U /*!< GPDMA1 HW request is I3C1_RS */
1080
1081 /**
1082 * @}
1083 */
1084
1085 /** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
1086 * @{
1087 */
1088 /* HPDMA1 triggers */
1089 #define LL_HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_FRAMEEND */
1090 #define LL_HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_HSYNC */
1091 #define LL_HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_LINEEND */
1092 #define LL_HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_VSYNC */
1093 #define LL_HPDMA1_TRIGGER_DMA2D_CTC_FLAG 4U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC_FLAG */
1094 #define LL_HPDMA1_TRIGGER_DMA2D_TC_FLAG 5U /*!< HPDMA1 HW Trigger signal is DMA2D_TC_FLAG */
1095 #define LL_HPDMA1_TRIGGER_DMA2D_TW_FLAG 6U /*!< HPDMA1 HW Trigger signal is DMA2D_TW_FLAG */
1096 #define LL_HPDMA1_TRIGGER_JPEG_EOC_FLAG 7U /*!< HPDMA1 HW Trigger signal is JPEG_EOC_FLAG */
1097 #define LL_HPDMA1_TRIGGER_JPEG_IFNF_FLAG 8U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF_FLAG */
1098 #define LL_HPDMA1_TRIGGER_JPEG_IFT_FLAG 9U /*!< HPDMA1 HW Trigger signal is JPEG_IFT_FLAG */
1099 #define LL_HPDMA1_TRIGGER_JPEG_OFNE_FLAG 10U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE_FLAG */
1100 #define LL_HPDMA1_TRIGGER_JPEG_OFT_FLAG 11U /*!< HPDMA1 HW Trigger signal is JPEG_OFT_FLAG */
1101 #define LL_HPDMA1_TRIGGER_LCD 12U /*!< HPDMA1 HW Trigger signal is LCD */
1102 #define LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG0 13U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG0 */
1103 #define LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG1 14U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG1 */
1104 #define LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG2 15U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG2 */
1105 #define LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG3 16U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG3 */
1106 #define LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_4 17U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_4 */
1107 #define LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_3 18U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_3 */
1108 #define LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_2 19U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_2 */
1109 #define LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_1 20U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_1 */
1110 #define LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF 21U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
1111 #define LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF 22U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
1112 #define LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF 23U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
1113 #define LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF 24U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
1114 #define LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF 25U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
1115 #define LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF 26U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
1116 #define LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF 27U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
1117 #define LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF 28U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
1118 #define LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF 29U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
1119 #define LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF 30U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
1120 #define LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF 31U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
1121 #define LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF 32U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
1122 #define LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF 33U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
1123 #define LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF 34U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
1124 #define LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF 35U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
1125 #define LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF 36U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
1126 #define LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF 37U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */
1127 #define LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF 38U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */
1128 #define LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF 39U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */
1129 #define LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF 40U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */
1130 #define LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF 41U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */
1131 #define LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF 42U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */
1132 #define LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF 43U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */
1133 #define LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF 44U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */
1134 #define LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF 45U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */
1135 #define LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF 46U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */
1136 #define LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF 47U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */
1137 #define LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF 48U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */
1138 #define LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF 49U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */
1139 #define LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF 50U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */
1140 #define LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF 51U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */
1141 #define LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF 52U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */
1142
1143 /* GPDMA1 triggers */
1144 #define LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF 0U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */
1145 #define LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF 1U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */
1146 #define LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF 2U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */
1147 #define LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF 3U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */
1148 #define LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF 4U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */
1149 #define LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF 5U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */
1150 #define LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF 6U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */
1151 #define LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF 7U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */
1152 #define LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF 8U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */
1153 #define LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF 9U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */
1154 #define LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF 10U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */
1155 #define LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF 11U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */
1156 #define LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF 12U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */
1157 #define LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF 13U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */
1158 #define LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF 14U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */
1159 #define LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF 15U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */
1160 #define LL_GPDMA1_TRIGGER_LPTIM1_CH1 16U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
1161 #define LL_GPDMA1_TRIGGER_LPTIM1_CH2 17U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
1162 #define LL_GPDMA1_TRIGGER_LPTIM2_CH1 18U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
1163 #define LL_GPDMA1_TRIGGER_LPTIM2_CH2 19U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
1164 #define LL_GPDMA1_TRIGGER_LPTIM3_CH1 20U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */
1165 #define LL_GPDMA1_TRIGGER_LPTIM3_CH2 21U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */
1166 #define LL_GPDMA1_TRIGGER_LPTIM4_OUT 22U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */
1167 #define LL_GPDMA1_TRIGGER_LPTIM5_OUT 23U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */
1168 #define LL_GPDMA1_TRIGGER_EXTIT0_SYNC 24U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */
1169 #define LL_GPDMA1_TRIGGER_RTC_WKUP 25U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */
1170 #define LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 26U /*!< GPDMA1 HW Trigger signal is R_WUP_ASYNC */
1171 #define LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 27U /*!< GPDMA1 HW Trigger signal is T_WUP_ASYNC */
1172 #define LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 28U /*!< GPDMA1 HW Trigger signal is SPI6_OR_SPI6_AIT_SYNC */
1173 #define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
1174 #define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
1175 #define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
1176 #define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
1177 #define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
1178 #define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
1179 #define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
1180 #define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
1181 #define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
1182 #define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 38U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
1183 #define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 39U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
1184 #define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 40U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
1185 #define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 41U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
1186 #define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 42U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
1187 #define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 43U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
1188 #define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 44U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
1189 #define LL_GPDMA1_TRIGGER_TIM1_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */
1190 #define LL_GPDMA1_TRIGGER_TIM1_TRGO2 46U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */
1191 #define LL_GPDMA1_TRIGGER_TIM2_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
1192 #define LL_GPDMA1_TRIGGER_TIM3_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
1193 #define LL_GPDMA1_TRIGGER_TIM4_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */
1194 #define LL_GPDMA1_TRIGGER_TIM5_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */
1195 #define LL_GPDMA1_TRIGGER_TIM6_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */
1196 #define LL_GPDMA1_TRIGGER_TIM7_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */
1197 #define LL_GPDMA1_TRIGGER_TIM9_TRGO 53U /*!< GPDMA1 HW Trigger signal is TIM9_TRGO */
1198 #define LL_GPDMA1_TRIGGER_TIM12_TRGO 54U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
1199 #define LL_GPDMA1_TRIGGER_TIM15_TRGO 55U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
1200 /**
1201 * @}
1202 */
1203
1204 /**
1205 * @}
1206 */
1207
1208 /* Exported macro ------------------------------------------------------------*/
1209
1210 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
1211 * @{
1212 */
1213
1214 /** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
1215 * @{
1216 */
1217 /**
1218 * @brief Write a value in DMA register.
1219 * @param __INSTANCE__ DMA Instance.
1220 * @param __REG__ Register to be written.
1221 * @param __VALUE__ Value to be written in the register.
1222 * @retval None.
1223 */
1224 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1225
1226 /**
1227 * @brief Read a value in DMA register.
1228 * @param __INSTANCE__ DMA Instance.
1229 * @param __REG__ Register to be read.
1230 * @retval Register value.
1231 */
1232 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
1238 * @{
1239 */
1240 /**
1241 * @brief Convert DMAx_Channely into DMAx.
1242 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1243 * @retval DMAx.
1244 */
1245 #define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
1246 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? HPDMA1 : GPDMA1)
1247
1248 /**
1249 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
1250 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1251 * @retval LL_DMA_CHANNEL_y.
1252 */
1253 #define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
1254 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
1255 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
1256 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
1257 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
1258 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
1259 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
1260 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
1261 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
1262 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
1263 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
1264 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
1265 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
1266 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
1267 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
1268 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
1269 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
1270 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \
1271 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \
1272 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \
1273 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \
1274 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
1275 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
1276 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
1277 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
1278 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
1279 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
1280 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
1281 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
1282 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
1283 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
1284 LL_DMA_CHANNEL_15)
1285
1286 /**
1287 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
1288 * @param __DMA_INSTANCE__ DMAx.
1289 * @param __CHANNEL__ LL_DMA_CHANNEL_y.
1290 * @retval DMAx_Channely.
1291 */
1292 #define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
1293 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1294 ? HPDMA1_Channel0 : \
1295 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1296 ? GPDMA1_Channel0 : \
1297 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1298 ? HPDMA1_Channel1 : \
1299 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1300 ? GPDMA1_Channel1 : \
1301 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
1302 ? HPDMA1_Channel2 : \
1303 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
1304 ? GPDMA1_Channel2 : \
1305 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
1306 ? HPDMA1_Channel3 : \
1307 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
1308 ? GPDMA1_Channel3 : \
1309 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
1310 ? HPDMA1_Channel4 : \
1311 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
1312 ? GPDMA1_Channel4 : \
1313 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
1314 ? HPDMA1_Channel5 : \
1315 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
1316 ? GPDMA1_Channel5 : \
1317 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
1318 ? HPDMA1_Channel6 : \
1319 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
1320 ? GPDMA1_Channel6 : \
1321 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
1322 ? HPDMA1_Channel7 : \
1323 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
1324 ? GPDMA1_Channel7 : \
1325 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
1326 ? HPDMA1_Channel8 : \
1327 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
1328 ? GPDMA1_Channel8 : \
1329 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
1330 ? HPDMA1_Channel9 : \
1331 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
1332 ? GPDMA1_Channel9 : \
1333 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
1334 ? HPDMA1_Channel10 : \
1335 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
1336 ? GPDMA1_Channel10 : \
1337 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
1338 ? HPDMA1_Channel11 : \
1339 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
1340 ? GPDMA1_Channel11 : \
1341 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
1342 ? HPDMA1_Channel12 : \
1343 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
1344 ? GPDMA1_Channel12 : \
1345 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
1346 ? HPDMA1_Channel13 : \
1347 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
1348 ? GPDMA1_Channel13 : \
1349 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
1350 ? HPDMA1_Channel14 : \
1351 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
1352 ? GPDMA1_Channel14 : \
1353 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_15)))\
1354 ? HPDMA1_Channel15 : GPDMA1_Channel15)
1355
1356 /**
1357 * @}
1358 */
1359
1360 /**
1361 * @}
1362 */
1363
1364 /* Exported functions --------------------------------------------------------*/
1365
1366 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
1367 * @{
1368 */
1369
1370 /** @defgroup DMA_LL_EF_Configuration Configuration
1371 * @{
1372 */
1373 /**
1374 * @brief Enable channel.
1375 * @note This API is used for all available DMA channels.
1376 * @rmtoll CCR EN LL_DMA_EnableChannel
1377 * @param DMAx DMAx Instance.
1378 * @param Channel This parameter can be one of the following values:
1379 * @arg @ref LL_DMA_CHANNEL_0
1380 * @arg @ref LL_DMA_CHANNEL_1
1381 * @arg @ref LL_DMA_CHANNEL_2
1382 * @arg @ref LL_DMA_CHANNEL_3
1383 * @arg @ref LL_DMA_CHANNEL_4
1384 * @arg @ref LL_DMA_CHANNEL_5
1385 * @arg @ref LL_DMA_CHANNEL_6
1386 * @arg @ref LL_DMA_CHANNEL_7
1387 * @arg @ref LL_DMA_CHANNEL_8
1388 * @arg @ref LL_DMA_CHANNEL_9
1389 * @arg @ref LL_DMA_CHANNEL_10
1390 * @arg @ref LL_DMA_CHANNEL_11
1391 * @arg @ref LL_DMA_CHANNEL_12
1392 * @arg @ref LL_DMA_CHANNEL_13
1393 * @arg @ref LL_DMA_CHANNEL_14
1394 * @arg @ref LL_DMA_CHANNEL_15
1395 * @retval None.
1396 */
LL_DMA_EnableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1397 __STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1398 {
1399 uint32_t dma_base_addr = (uint32_t)DMAx;
1400 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
1401 }
1402
1403 /**
1404 * @brief Disable channel.
1405 * @note This API is used for all available DMA channels.
1406 * @rmtoll CCR EN LL_DMA_DisableChannel
1407 * @param DMAx DMAx Instance.
1408 * @param Channel This parameter can be one of the following values:
1409 * @arg @ref LL_DMA_CHANNEL_0
1410 * @arg @ref LL_DMA_CHANNEL_1
1411 * @arg @ref LL_DMA_CHANNEL_2
1412 * @arg @ref LL_DMA_CHANNEL_3
1413 * @arg @ref LL_DMA_CHANNEL_4
1414 * @arg @ref LL_DMA_CHANNEL_5
1415 * @arg @ref LL_DMA_CHANNEL_6
1416 * @arg @ref LL_DMA_CHANNEL_7
1417 * @arg @ref LL_DMA_CHANNEL_8
1418 * @arg @ref LL_DMA_CHANNEL_9
1419 * @arg @ref LL_DMA_CHANNEL_10
1420 * @arg @ref LL_DMA_CHANNEL_11
1421 * @arg @ref LL_DMA_CHANNEL_12
1422 * @arg @ref LL_DMA_CHANNEL_13
1423 * @arg @ref LL_DMA_CHANNEL_14
1424 * @arg @ref LL_DMA_CHANNEL_15
1425 * @retval None.
1426 */
LL_DMA_DisableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1427 __STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1428 {
1429 uint32_t dma_base_addr = (uint32_t)DMAx;
1430 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1431 (DMA_CCR_SUSP | DMA_CCR_RESET));
1432 }
1433
1434 /**
1435 * @brief Check if channel is enabled or disabled.
1436 * @note This API is used for all available DMA channels.
1437 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
1438 * @param DMAx DMAx Instance
1439 * @param Channel This parameter can be one of the following values:
1440 * @arg @ref LL_DMA_CHANNEL_0
1441 * @arg @ref LL_DMA_CHANNEL_1
1442 * @arg @ref LL_DMA_CHANNEL_2
1443 * @arg @ref LL_DMA_CHANNEL_3
1444 * @arg @ref LL_DMA_CHANNEL_4
1445 * @arg @ref LL_DMA_CHANNEL_5
1446 * @arg @ref LL_DMA_CHANNEL_6
1447 * @arg @ref LL_DMA_CHANNEL_7
1448 * @arg @ref LL_DMA_CHANNEL_8
1449 * @arg @ref LL_DMA_CHANNEL_9
1450 * @arg @ref LL_DMA_CHANNEL_10
1451 * @arg @ref LL_DMA_CHANNEL_11
1452 * @arg @ref LL_DMA_CHANNEL_12
1453 * @arg @ref LL_DMA_CHANNEL_13
1454 * @arg @ref LL_DMA_CHANNEL_14
1455 * @arg @ref LL_DMA_CHANNEL_15
1456 * @retval State of bit (1 or 0).
1457 */
LL_DMA_IsEnabledChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1458 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1459 {
1460 uint32_t dma_base_addr = (uint32_t)DMAx;
1461 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
1462 == (DMA_CCR_EN)) ? 1UL : 0UL);
1463 }
1464
1465 /**
1466 * @brief Reset channel.
1467 * @note This API is used for all available DMA channels.
1468 * @rmtoll CCR RESET LL_DMA_ResetChannel
1469 * @param DMAx DMAx Instance
1470 * @param Channel This parameter can be one of the following values:
1471 * @arg @ref LL_DMA_CHANNEL_0
1472 * @arg @ref LL_DMA_CHANNEL_1
1473 * @arg @ref LL_DMA_CHANNEL_2
1474 * @arg @ref LL_DMA_CHANNEL_3
1475 * @arg @ref LL_DMA_CHANNEL_4
1476 * @arg @ref LL_DMA_CHANNEL_5
1477 * @arg @ref LL_DMA_CHANNEL_6
1478 * @arg @ref LL_DMA_CHANNEL_7
1479 * @arg @ref LL_DMA_CHANNEL_8
1480 * @arg @ref LL_DMA_CHANNEL_9
1481 * @arg @ref LL_DMA_CHANNEL_10
1482 * @arg @ref LL_DMA_CHANNEL_11
1483 * @arg @ref LL_DMA_CHANNEL_12
1484 * @arg @ref LL_DMA_CHANNEL_13
1485 * @arg @ref LL_DMA_CHANNEL_14
1486 * @arg @ref LL_DMA_CHANNEL_15
1487 * @retval None.
1488 */
LL_DMA_ResetChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1489 __STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1490 {
1491 uint32_t dma_base_addr = (uint32_t)DMAx;
1492 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
1493 }
1494
1495 /**
1496 * @brief Suspend channel.
1497 * @note This API is used for all available DMA channels.
1498 * @rmtoll CCR SUSP LL_DMA_SuspendChannel
1499 * @param DMAx DMAx Instance
1500 * @param Channel This parameter can be one of the following values:
1501 * @arg @ref LL_DMA_CHANNEL_0
1502 * @arg @ref LL_DMA_CHANNEL_1
1503 * @arg @ref LL_DMA_CHANNEL_2
1504 * @arg @ref LL_DMA_CHANNEL_3
1505 * @arg @ref LL_DMA_CHANNEL_4
1506 * @arg @ref LL_DMA_CHANNEL_5
1507 * @arg @ref LL_DMA_CHANNEL_6
1508 * @arg @ref LL_DMA_CHANNEL_7
1509 * @arg @ref LL_DMA_CHANNEL_8
1510 * @arg @ref LL_DMA_CHANNEL_9
1511 * @arg @ref LL_DMA_CHANNEL_10
1512 * @arg @ref LL_DMA_CHANNEL_11
1513 * @arg @ref LL_DMA_CHANNEL_12
1514 * @arg @ref LL_DMA_CHANNEL_13
1515 * @arg @ref LL_DMA_CHANNEL_14
1516 * @arg @ref LL_DMA_CHANNEL_15
1517 * @retval None.
1518 */
LL_DMA_SuspendChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1519 __STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1520 {
1521 uint32_t dma_base_addr = (uint32_t)DMAx;
1522 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1523 }
1524
1525 /**
1526 * @brief Resume channel.
1527 * @note This API is used for all available DMA channels.
1528 * @rmtoll CCR SUSP LL_DMA_ResumeChannel
1529 * @param DMAx DMAx Instance
1530 * @param Channel This parameter can be one of the following values:
1531 * @arg @ref LL_DMA_CHANNEL_0
1532 * @arg @ref LL_DMA_CHANNEL_1
1533 * @arg @ref LL_DMA_CHANNEL_2
1534 * @arg @ref LL_DMA_CHANNEL_3
1535 * @arg @ref LL_DMA_CHANNEL_4
1536 * @arg @ref LL_DMA_CHANNEL_5
1537 * @arg @ref LL_DMA_CHANNEL_6
1538 * @arg @ref LL_DMA_CHANNEL_7
1539 * @arg @ref LL_DMA_CHANNEL_8
1540 * @arg @ref LL_DMA_CHANNEL_9
1541 * @arg @ref LL_DMA_CHANNEL_10
1542 * @arg @ref LL_DMA_CHANNEL_11
1543 * @arg @ref LL_DMA_CHANNEL_12
1544 * @arg @ref LL_DMA_CHANNEL_13
1545 * @arg @ref LL_DMA_CHANNEL_14
1546 * @arg @ref LL_DMA_CHANNEL_15
1547 * @retval None.
1548 */
LL_DMA_ResumeChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1549 __STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1550 {
1551 uint32_t dma_base_addr = (uint32_t)DMAx;
1552 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1553 }
1554
1555 /**
1556 * @brief Check if channel is suspended.
1557 * @note This API is used for all available DMA channels.
1558 * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
1559 * @param DMAx DMAx Instance
1560 * @param Channel This parameter can be one of the following values:
1561 * @arg @ref LL_DMA_CHANNEL_0
1562 * @arg @ref LL_DMA_CHANNEL_1
1563 * @arg @ref LL_DMA_CHANNEL_2
1564 * @arg @ref LL_DMA_CHANNEL_3
1565 * @arg @ref LL_DMA_CHANNEL_4
1566 * @arg @ref LL_DMA_CHANNEL_5
1567 * @arg @ref LL_DMA_CHANNEL_6
1568 * @arg @ref LL_DMA_CHANNEL_7
1569 * @arg @ref LL_DMA_CHANNEL_8
1570 * @arg @ref LL_DMA_CHANNEL_9
1571 * @arg @ref LL_DMA_CHANNEL_10
1572 * @arg @ref LL_DMA_CHANNEL_11
1573 * @arg @ref LL_DMA_CHANNEL_12
1574 * @arg @ref LL_DMA_CHANNEL_13
1575 * @arg @ref LL_DMA_CHANNEL_14
1576 * @arg @ref LL_DMA_CHANNEL_15
1577 * @retval State of bit (1 or 0).
1578 */
LL_DMA_IsSuspendedChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1579 __STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1580 {
1581 uint32_t dma_base_addr = (uint32_t)DMAx;
1582 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
1583 == (DMA_CCR_SUSP)) ? 1UL : 0UL);
1584 }
1585
1586 /**
1587 * @brief Set linked-list base address.
1588 * @note This API is used for all available DMA channels.
1589 * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
1590 * @param DMAx DMAx Instance
1591 * @param Channel This parameter can be one of the following values:
1592 * @arg @ref LL_DMA_CHANNEL_0
1593 * @arg @ref LL_DMA_CHANNEL_1
1594 * @arg @ref LL_DMA_CHANNEL_2
1595 * @arg @ref LL_DMA_CHANNEL_3
1596 * @arg @ref LL_DMA_CHANNEL_4
1597 * @arg @ref LL_DMA_CHANNEL_5
1598 * @arg @ref LL_DMA_CHANNEL_6
1599 * @arg @ref LL_DMA_CHANNEL_7
1600 * @arg @ref LL_DMA_CHANNEL_8
1601 * @arg @ref LL_DMA_CHANNEL_9
1602 * @arg @ref LL_DMA_CHANNEL_10
1603 * @arg @ref LL_DMA_CHANNEL_11
1604 * @arg @ref LL_DMA_CHANNEL_12
1605 * @arg @ref LL_DMA_CHANNEL_13
1606 * @arg @ref LL_DMA_CHANNEL_14
1607 * @arg @ref LL_DMA_CHANNEL_15
1608 * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
1609 * are always 0)
1610 * @retval None.
1611 */
LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListBaseAddr)1612 __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel,
1613 uint32_t LinkedListBaseAddr)
1614 {
1615 uint32_t dma_base_addr = (uint32_t)DMAx;
1616 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
1617 (LinkedListBaseAddr & DMA_CLBAR_LBA));
1618 }
1619
1620 /**
1621 * @brief Get linked-list base address.
1622 * @note This API is used for all available DMA channels.
1623 * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
1624 * @param DMAx DMAx Instance
1625 * @param Channel This parameter can be one of the following values:
1626 * @arg @ref LL_DMA_CHANNEL_0
1627 * @arg @ref LL_DMA_CHANNEL_1
1628 * @arg @ref LL_DMA_CHANNEL_2
1629 * @arg @ref LL_DMA_CHANNEL_3
1630 * @arg @ref LL_DMA_CHANNEL_4
1631 * @arg @ref LL_DMA_CHANNEL_5
1632 * @arg @ref LL_DMA_CHANNEL_6
1633 * @arg @ref LL_DMA_CHANNEL_7
1634 * @arg @ref LL_DMA_CHANNEL_8
1635 * @arg @ref LL_DMA_CHANNEL_9
1636 * @arg @ref LL_DMA_CHANNEL_10
1637 * @arg @ref LL_DMA_CHANNEL_11
1638 * @arg @ref LL_DMA_CHANNEL_12
1639 * @arg @ref LL_DMA_CHANNEL_13
1640 * @arg @ref LL_DMA_CHANNEL_14
1641 * @arg @ref LL_DMA_CHANNEL_15
1642 * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
1643 */
LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel)1644 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel)
1645 {
1646 uint32_t dma_base_addr = (uint32_t)DMAx;
1647 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
1648 }
1649
1650 /**
1651 * @brief Configure all parameters linked to channel control.
1652 * @note This API is used for all available DMA channels.
1653 * @rmtoll CCR PRIO LL_DMA_ConfigControl\n
1654 * CCR LAP LL_DMA_ConfigControl\n
1655 * CCR LSM LL_DMA_ConfigControl
1656 * @param DMAx DMAx Instance
1657 * @param Channel This parameter can be one of the following values:
1658 * @arg @ref LL_DMA_CHANNEL_0
1659 * @arg @ref LL_DMA_CHANNEL_1
1660 * @arg @ref LL_DMA_CHANNEL_2
1661 * @arg @ref LL_DMA_CHANNEL_3
1662 * @arg @ref LL_DMA_CHANNEL_4
1663 * @arg @ref LL_DMA_CHANNEL_5
1664 * @arg @ref LL_DMA_CHANNEL_6
1665 * @arg @ref LL_DMA_CHANNEL_7
1666 * @arg @ref LL_DMA_CHANNEL_8
1667 * @arg @ref LL_DMA_CHANNEL_9
1668 * @arg @ref LL_DMA_CHANNEL_10
1669 * @arg @ref LL_DMA_CHANNEL_11
1670 * @arg @ref LL_DMA_CHANNEL_12
1671 * @arg @ref LL_DMA_CHANNEL_13
1672 * @arg @ref LL_DMA_CHANNEL_14
1673 * @arg @ref LL_DMA_CHANNEL_15
1674 * @param Configuration This parameter must be a combination of all the following values:
1675 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
1676 * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
1677 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
1678 * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
1679 *@retval None.
1680 */
LL_DMA_ConfigControl(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1681 __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1682 {
1683 uint32_t dma_base_addr = (uint32_t)DMAx;
1684 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1685 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
1686 }
1687
1688 /**
1689 * @brief Set priority level.
1690 * @note This API is used for all available DMA channels.
1691 * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
1692 * @param DMAx DMAx Instance
1693 * @param Channel This parameter can be one of the following values:
1694 * @arg @ref LL_DMA_CHANNEL_0
1695 * @arg @ref LL_DMA_CHANNEL_1
1696 * @arg @ref LL_DMA_CHANNEL_2
1697 * @arg @ref LL_DMA_CHANNEL_3
1698 * @arg @ref LL_DMA_CHANNEL_4
1699 * @arg @ref LL_DMA_CHANNEL_5
1700 * @arg @ref LL_DMA_CHANNEL_6
1701 * @arg @ref LL_DMA_CHANNEL_7
1702 * @arg @ref LL_DMA_CHANNEL_8
1703 * @arg @ref LL_DMA_CHANNEL_9
1704 * @arg @ref LL_DMA_CHANNEL_10
1705 * @arg @ref LL_DMA_CHANNEL_11
1706 * @arg @ref LL_DMA_CHANNEL_12
1707 * @arg @ref LL_DMA_CHANNEL_13
1708 * @arg @ref LL_DMA_CHANNEL_14
1709 * @arg @ref LL_DMA_CHANNEL_15
1710 * @param Priority This parameter can be one of the following values:
1711 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1712 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1713 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1714 * @arg @ref LL_DMA_HIGH_PRIORITY
1715 * @retval None.
1716 */
LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)1717 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
1718 {
1719 uint32_t dma_base_addr = (uint32_t)DMAx;
1720 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
1721 }
1722
1723 /**
1724 * @brief Get Channel priority level.
1725 * @note This API is used for all available DMA channels.
1726 * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
1727 * @param DMAx DMAx Instance
1728 * @param Channel This parameter can be one of the following values:
1729 * @arg @ref LL_DMA_CHANNEL_0
1730 * @arg @ref LL_DMA_CHANNEL_1
1731 * @arg @ref LL_DMA_CHANNEL_2
1732 * @arg @ref LL_DMA_CHANNEL_3
1733 * @arg @ref LL_DMA_CHANNEL_4
1734 * @arg @ref LL_DMA_CHANNEL_5
1735 * @arg @ref LL_DMA_CHANNEL_6
1736 * @arg @ref LL_DMA_CHANNEL_7
1737 * @arg @ref LL_DMA_CHANNEL_8
1738 * @arg @ref LL_DMA_CHANNEL_9
1739 * @arg @ref LL_DMA_CHANNEL_10
1740 * @arg @ref LL_DMA_CHANNEL_11
1741 * @arg @ref LL_DMA_CHANNEL_12
1742 * @arg @ref LL_DMA_CHANNEL_13
1743 * @arg @ref LL_DMA_CHANNEL_14
1744 * @arg @ref LL_DMA_CHANNEL_15
1745 * @retval Returned value can be one of the following values:
1746 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1747 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1748 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1749 * @arg @ref LL_DMA_HIGH_PRIORITY
1750 */
LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel)1751 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
1752 {
1753 uint32_t dma_base_addr = (uint32_t)DMAx;
1754 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
1755 }
1756
1757 /**
1758 * @brief Set linked-list allocated port.
1759 * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
1760 * @param DMAx DMAx Instance
1761 * @param Channel This parameter can be one of the following values:
1762 * @arg @ref LL_DMA_CHANNEL_0
1763 * @arg @ref LL_DMA_CHANNEL_1
1764 * @arg @ref LL_DMA_CHANNEL_2
1765 * @arg @ref LL_DMA_CHANNEL_3
1766 * @arg @ref LL_DMA_CHANNEL_4
1767 * @arg @ref LL_DMA_CHANNEL_5
1768 * @arg @ref LL_DMA_CHANNEL_6
1769 * @arg @ref LL_DMA_CHANNEL_7
1770 * @arg @ref LL_DMA_CHANNEL_8
1771 * @arg @ref LL_DMA_CHANNEL_9
1772 * @arg @ref LL_DMA_CHANNEL_10
1773 * @arg @ref LL_DMA_CHANNEL_11
1774 * @arg @ref LL_DMA_CHANNEL_12
1775 * @arg @ref LL_DMA_CHANNEL_13
1776 * @arg @ref LL_DMA_CHANNEL_14
1777 * @arg @ref LL_DMA_CHANNEL_15
1778 * @param LinkAllocatedPort This parameter can be one of the following values:
1779 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1780 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1781 * @retval None.
1782 */
LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkAllocatedPort)1783 __STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
1784 {
1785 uint32_t dma_base_addr = (uint32_t)DMAx;
1786 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1787 DMA_CCR_LAP, LinkAllocatedPort);
1788 }
1789
1790 /**
1791 * @brief Get linked-list allocated port.
1792 * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
1793 * @param DMAx DMAx Instance
1794 * @param Channel This parameter can be one of the following values:
1795 * @arg @ref LL_DMA_CHANNEL_0
1796 * @arg @ref LL_DMA_CHANNEL_1
1797 * @arg @ref LL_DMA_CHANNEL_2
1798 * @arg @ref LL_DMA_CHANNEL_3
1799 * @arg @ref LL_DMA_CHANNEL_4
1800 * @arg @ref LL_DMA_CHANNEL_5
1801 * @arg @ref LL_DMA_CHANNEL_6
1802 * @arg @ref LL_DMA_CHANNEL_7
1803 * @arg @ref LL_DMA_CHANNEL_8
1804 * @arg @ref LL_DMA_CHANNEL_9
1805 * @arg @ref LL_DMA_CHANNEL_10
1806 * @arg @ref LL_DMA_CHANNEL_11
1807 * @arg @ref LL_DMA_CHANNEL_12
1808 * @arg @ref LL_DMA_CHANNEL_13
1809 * @arg @ref LL_DMA_CHANNEL_14
1810 * @arg @ref LL_DMA_CHANNEL_15
1811 * @retval Returned value can be one of the following values:
1812 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1813 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1814 */
LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1815 __STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1816 {
1817 uint32_t dma_base_addr = (uint32_t)DMAx;
1818 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
1819 }
1820
1821 /**
1822 * @brief Set link step mode.
1823 * @note This API is used for all available DMA channels.
1824 * @rmtoll CCR LSM LL_DMA_SetLinkStepMode
1825 * @param DMAx DMAx Instance
1826 * @param Channel This parameter can be one of the following values:
1827 * @arg @ref LL_DMA_CHANNEL_0
1828 * @arg @ref LL_DMA_CHANNEL_1
1829 * @arg @ref LL_DMA_CHANNEL_2
1830 * @arg @ref LL_DMA_CHANNEL_3
1831 * @arg @ref LL_DMA_CHANNEL_4
1832 * @arg @ref LL_DMA_CHANNEL_5
1833 * @arg @ref LL_DMA_CHANNEL_6
1834 * @arg @ref LL_DMA_CHANNEL_7
1835 * @arg @ref LL_DMA_CHANNEL_8
1836 * @arg @ref LL_DMA_CHANNEL_9
1837 * @arg @ref LL_DMA_CHANNEL_10
1838 * @arg @ref LL_DMA_CHANNEL_11
1839 * @arg @ref LL_DMA_CHANNEL_12
1840 * @arg @ref LL_DMA_CHANNEL_13
1841 * @arg @ref LL_DMA_CHANNEL_14
1842 * @arg @ref LL_DMA_CHANNEL_15
1843 * @param LinkStepMode This parameter can be one of the following values:
1844 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1845 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1846 * @retval None.
1847 */
LL_DMA_SetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkStepMode)1848 __STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
1849 {
1850 uint32_t dma_base_addr = (uint32_t)DMAx;
1851 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
1852 }
1853
1854 /**
1855 * @brief Get Link step mode.
1856 * @note This API is used for all available DMA channels.
1857 * @rmtoll CCR LSM LL_DMA_GetLinkStepMode
1858 * @param DMAx DMAx Instance
1859 * @param Channel This parameter can be one of the following values:
1860 * @arg @ref LL_DMA_CHANNEL_0
1861 * @arg @ref LL_DMA_CHANNEL_1
1862 * @arg @ref LL_DMA_CHANNEL_2
1863 * @arg @ref LL_DMA_CHANNEL_3
1864 * @arg @ref LL_DMA_CHANNEL_4
1865 * @arg @ref LL_DMA_CHANNEL_5
1866 * @arg @ref LL_DMA_CHANNEL_6
1867 * @arg @ref LL_DMA_CHANNEL_7
1868 * @arg @ref LL_DMA_CHANNEL_8
1869 * @arg @ref LL_DMA_CHANNEL_9
1870 * @arg @ref LL_DMA_CHANNEL_10
1871 * @arg @ref LL_DMA_CHANNEL_11
1872 * @arg @ref LL_DMA_CHANNEL_12
1873 * @arg @ref LL_DMA_CHANNEL_13
1874 * @arg @ref LL_DMA_CHANNEL_14
1875 * @arg @ref LL_DMA_CHANNEL_15
1876 * @retval Returned value can be one of the following values:
1877 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1878 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1879 */
LL_DMA_GetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel)1880 __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel)
1881 {
1882 uint32_t dma_base_addr = (uint32_t)DMAx;
1883 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
1884 }
1885
1886 /**
1887 * @brief Configure data transfer.
1888 * @note This API is used for all available DMA channels.
1889 * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
1890 * CTR1 DWX LL_DMA_ConfigTransfer\n
1891 * CTR1 DHX LL_DMA_ConfigTransfer\n
1892 * CTR1 DBX LL_DMA_ConfigTransfer\n
1893 * CTR1 DINC LL_DMA_ConfigTransfer\n
1894 * CTR1 SAP LL_DMA_ConfigTransfer\n
1895 * CTR1 SBX LL_DMA_ConfigTransfer\n
1896 * CTR1 PAM LL_DMA_ConfigTransfer\n
1897 * CTR1 SINC LL_DMA_ConfigTransfer
1898 * @param DMAx DMAx Instance
1899 * @param Channel This parameter can be one of the following values:
1900 * @arg @ref LL_DMA_CHANNEL_0
1901 * @arg @ref LL_DMA_CHANNEL_1
1902 * @arg @ref LL_DMA_CHANNEL_2
1903 * @arg @ref LL_DMA_CHANNEL_3
1904 * @arg @ref LL_DMA_CHANNEL_4
1905 * @arg @ref LL_DMA_CHANNEL_5
1906 * @arg @ref LL_DMA_CHANNEL_6
1907 * @arg @ref LL_DMA_CHANNEL_7
1908 * @arg @ref LL_DMA_CHANNEL_8
1909 * @arg @ref LL_DMA_CHANNEL_9
1910 * @arg @ref LL_DMA_CHANNEL_10
1911 * @arg @ref LL_DMA_CHANNEL_11
1912 * @arg @ref LL_DMA_CHANNEL_12
1913 * @arg @ref LL_DMA_CHANNEL_13
1914 * @arg @ref LL_DMA_CHANNEL_14
1915 * @arg @ref LL_DMA_CHANNEL_15
1916 * @param Configuration This parameter must be a combination of all the following values:
1917 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
1918 * @arg @ref LL_DMA_DEST_WORD_PRESERVE or @ref LL_DMA_DEST_WORD_EXCHANGE
1919 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
1920 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
1921 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
1922 * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
1923 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
1924 * @ref LL_DMA_DEST_DATAWIDTH_WORD or @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
1925 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
1926 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
1927 * @ref LL_DMA_DATA_PACK_UNPACK
1928 * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
1929 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
1930 * @ref LL_DMA_SRC_DATAWIDTH_WORD or @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
1931 *@retval None.
1932 */
LL_DMA_ConfigTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1933 __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1934 {
1935 uint32_t dma_base_addr = (uint32_t)DMAx;
1936 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1937 DMA_CTR1_DAP | DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | \
1938 DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
1939 }
1940
1941 /**
1942 * @brief Configure source and destination burst length.
1943 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
1944 * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
1945 * @param DMAx DMAx Instance
1946 * @param Channel This parameter can be one of the following values:
1947 * @arg @ref LL_DMA_CHANNEL_0
1948 * @arg @ref LL_DMA_CHANNEL_1
1949 * @arg @ref LL_DMA_CHANNEL_2
1950 * @arg @ref LL_DMA_CHANNEL_3
1951 * @arg @ref LL_DMA_CHANNEL_4
1952 * @arg @ref LL_DMA_CHANNEL_5
1953 * @arg @ref LL_DMA_CHANNEL_6
1954 * @arg @ref LL_DMA_CHANNEL_7
1955 * @arg @ref LL_DMA_CHANNEL_8
1956 * @arg @ref LL_DMA_CHANNEL_9
1957 * @arg @ref LL_DMA_CHANNEL_10
1958 * @arg @ref LL_DMA_CHANNEL_11
1959 * @arg @ref LL_DMA_CHANNEL_12
1960 * @arg @ref LL_DMA_CHANNEL_13
1961 * @arg @ref LL_DMA_CHANNEL_14
1962 * @arg @ref LL_DMA_CHANNEL_15
1963 * @param SrcBurstLength Between 1 to 64
1964 * @param DestBurstLength Between 1 to 64
1965 * @retval None.
1966 */
LL_DMA_ConfigBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength,uint32_t DestBurstLength)1967 __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
1968 uint32_t DestBurstLength)
1969 {
1970 uint32_t dma_base_addr = (uint32_t)DMAx;
1971 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1972 (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
1973 (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
1974 }
1975
1976 /**
1977 * @brief Set destination allocated port.
1978 * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
1979 * @param DMAx DMAx Instance
1980 * @param Channel This parameter can be one of the following values:
1981 * @arg @ref LL_DMA_CHANNEL_0
1982 * @arg @ref LL_DMA_CHANNEL_1
1983 * @arg @ref LL_DMA_CHANNEL_2
1984 * @arg @ref LL_DMA_CHANNEL_3
1985 * @arg @ref LL_DMA_CHANNEL_4
1986 * @arg @ref LL_DMA_CHANNEL_5
1987 * @arg @ref LL_DMA_CHANNEL_6
1988 * @arg @ref LL_DMA_CHANNEL_7
1989 * @arg @ref LL_DMA_CHANNEL_8
1990 * @arg @ref LL_DMA_CHANNEL_9
1991 * @arg @ref LL_DMA_CHANNEL_10
1992 * @arg @ref LL_DMA_CHANNEL_11
1993 * @arg @ref LL_DMA_CHANNEL_12
1994 * @arg @ref LL_DMA_CHANNEL_13
1995 * @arg @ref LL_DMA_CHANNEL_14
1996 * @arg @ref LL_DMA_CHANNEL_15
1997 * @param DestAllocatedPort This parameter can be one of the following values:
1998 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
1999 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2000 * @retval None.
2001 */
LL_DMA_SetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAllocatedPort)2002 __STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
2003 {
2004 uint32_t dma_base_addr = (uint32_t)DMAx;
2005 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
2006 DestAllocatedPort);
2007 }
2008
2009 /**
2010 * @brief Get destination allocated port.
2011 * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
2012 * @param DMAx DMAx Instance
2013 * @param Channel This parameter can be one of the following values:
2014 * @arg @ref LL_DMA_CHANNEL_0
2015 * @arg @ref LL_DMA_CHANNEL_1
2016 * @arg @ref LL_DMA_CHANNEL_2
2017 * @arg @ref LL_DMA_CHANNEL_3
2018 * @arg @ref LL_DMA_CHANNEL_4
2019 * @arg @ref LL_DMA_CHANNEL_5
2020 * @arg @ref LL_DMA_CHANNEL_6
2021 * @arg @ref LL_DMA_CHANNEL_7
2022 * @arg @ref LL_DMA_CHANNEL_8
2023 * @arg @ref LL_DMA_CHANNEL_9
2024 * @arg @ref LL_DMA_CHANNEL_10
2025 * @arg @ref LL_DMA_CHANNEL_11
2026 * @arg @ref LL_DMA_CHANNEL_12
2027 * @arg @ref LL_DMA_CHANNEL_13
2028 * @arg @ref LL_DMA_CHANNEL_14
2029 * @arg @ref LL_DMA_CHANNEL_15
2030 * @retval Returned value can be one of the following values:
2031 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2032 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2033 */
LL_DMA_GetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)2034 __STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
2035 {
2036 uint32_t dma_base_addr = (uint32_t)DMAx;
2037 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
2038 }
2039
2040 /**
2041 * @brief Set destination word exchange.
2042 * @rmtoll CTR1 DWX LL_DMA_SetDestWordExchange
2043 * @param DMAx DMAx Instance
2044 * @param Channel This parameter can be one of the following values:
2045 * @arg @ref LL_DMA_CHANNEL_0
2046 * @arg @ref LL_DMA_CHANNEL_1
2047 * @arg @ref LL_DMA_CHANNEL_2
2048 * @arg @ref LL_DMA_CHANNEL_3
2049 * @arg @ref LL_DMA_CHANNEL_4
2050 * @arg @ref LL_DMA_CHANNEL_5
2051 * @arg @ref LL_DMA_CHANNEL_6
2052 * @arg @ref LL_DMA_CHANNEL_7
2053 * @arg @ref LL_DMA_CHANNEL_8
2054 * @arg @ref LL_DMA_CHANNEL_9
2055 * @arg @ref LL_DMA_CHANNEL_10
2056 * @arg @ref LL_DMA_CHANNEL_11
2057 * @arg @ref LL_DMA_CHANNEL_12
2058 * @arg @ref LL_DMA_CHANNEL_13
2059 * @arg @ref LL_DMA_CHANNEL_14
2060 * @arg @ref LL_DMA_CHANNEL_15
2061 * @param DestWordExchange This parameter can be one of the following values:
2062 * @arg @ref LL_DMA_DEST_WORD_PRESERVE
2063 * @arg @ref LL_DMA_DEST_WORD_EXCHANGE
2064 * @retval None.
2065 */
LL_DMA_SetDestWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestWordExchange)2066 __STATIC_INLINE void LL_DMA_SetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestWordExchange)
2067 {
2068 uint32_t dma_base_addr = (uint32_t)DMAx;
2069 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX,
2070 DestWordExchange);
2071 }
2072
2073 /**
2074 * @brief Get destination word exchange.
2075 * @rmtoll CTR1 DWX LL_DMA_GetDestWordExchange
2076 * @param DMAx DMAx Instance
2077 * @param Channel This parameter can be one of the following values:
2078 * @arg @ref LL_DMA_CHANNEL_0
2079 * @arg @ref LL_DMA_CHANNEL_1
2080 * @arg @ref LL_DMA_CHANNEL_2
2081 * @arg @ref LL_DMA_CHANNEL_3
2082 * @arg @ref LL_DMA_CHANNEL_4
2083 * @arg @ref LL_DMA_CHANNEL_5
2084 * @arg @ref LL_DMA_CHANNEL_6
2085 * @arg @ref LL_DMA_CHANNEL_7
2086 * @arg @ref LL_DMA_CHANNEL_8
2087 * @arg @ref LL_DMA_CHANNEL_9
2088 * @arg @ref LL_DMA_CHANNEL_10
2089 * @arg @ref LL_DMA_CHANNEL_11
2090 * @arg @ref LL_DMA_CHANNEL_12
2091 * @arg @ref LL_DMA_CHANNEL_13
2092 * @arg @ref LL_DMA_CHANNEL_14
2093 * @arg @ref LL_DMA_CHANNEL_15
2094 * @retval Returned value can be one of the following values:
2095 * @arg @ref LL_DMA_DEST_WORD_PRESERVE
2096 * @arg @ref LL_DMA_DEST_WORD_EXCHANGE
2097 */
LL_DMA_GetDestWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2098 __STATIC_INLINE uint32_t LL_DMA_GetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2099 {
2100 uint32_t dma_base_addr = (uint32_t)DMAx;
2101 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX));
2102 }
2103
2104 /**
2105 * @brief Set destination half-word exchange.
2106 * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
2107 * @param DMAx DMAx Instance
2108 * @param Channel This parameter can be one of the following values:
2109 * @arg @ref LL_DMA_CHANNEL_0
2110 * @arg @ref LL_DMA_CHANNEL_1
2111 * @arg @ref LL_DMA_CHANNEL_2
2112 * @arg @ref LL_DMA_CHANNEL_3
2113 * @arg @ref LL_DMA_CHANNEL_4
2114 * @arg @ref LL_DMA_CHANNEL_5
2115 * @arg @ref LL_DMA_CHANNEL_6
2116 * @arg @ref LL_DMA_CHANNEL_7
2117 * @arg @ref LL_DMA_CHANNEL_8
2118 * @arg @ref LL_DMA_CHANNEL_9
2119 * @arg @ref LL_DMA_CHANNEL_10
2120 * @arg @ref LL_DMA_CHANNEL_11
2121 * @arg @ref LL_DMA_CHANNEL_12
2122 * @arg @ref LL_DMA_CHANNEL_13
2123 * @arg @ref LL_DMA_CHANNEL_14
2124 * @arg @ref LL_DMA_CHANNEL_15
2125 * @param DestHWordExchange This parameter can be one of the following values:
2126 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2127 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2128 * @retval None.
2129 */
LL_DMA_SetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestHWordExchange)2130 __STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
2131 {
2132 uint32_t dma_base_addr = (uint32_t)DMAx;
2133 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
2134 DestHWordExchange);
2135 }
2136
2137 /**
2138 * @brief Get destination half-word exchange.
2139 * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
2140 * @param DMAx DMAx Instance
2141 * @param Channel This parameter can be one of the following values:
2142 * @arg @ref LL_DMA_CHANNEL_0
2143 * @arg @ref LL_DMA_CHANNEL_1
2144 * @arg @ref LL_DMA_CHANNEL_2
2145 * @arg @ref LL_DMA_CHANNEL_3
2146 * @arg @ref LL_DMA_CHANNEL_4
2147 * @arg @ref LL_DMA_CHANNEL_5
2148 * @arg @ref LL_DMA_CHANNEL_6
2149 * @arg @ref LL_DMA_CHANNEL_7
2150 * @arg @ref LL_DMA_CHANNEL_8
2151 * @arg @ref LL_DMA_CHANNEL_9
2152 * @arg @ref LL_DMA_CHANNEL_10
2153 * @arg @ref LL_DMA_CHANNEL_11
2154 * @arg @ref LL_DMA_CHANNEL_12
2155 * @arg @ref LL_DMA_CHANNEL_13
2156 * @arg @ref LL_DMA_CHANNEL_14
2157 * @arg @ref LL_DMA_CHANNEL_15
2158 * @retval Returned value can be one of the following values:
2159 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2160 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2161 */
LL_DMA_GetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2162 __STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2163 {
2164 uint32_t dma_base_addr = (uint32_t)DMAx;
2165 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
2166 }
2167
2168 /**
2169 * @brief Set destination byte exchange.
2170 * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
2171 * @param DMAx DMAx Instance
2172 * @param Channel This parameter can be one of the following values:
2173 * @arg @ref LL_DMA_CHANNEL_0
2174 * @arg @ref LL_DMA_CHANNEL_1
2175 * @arg @ref LL_DMA_CHANNEL_2
2176 * @arg @ref LL_DMA_CHANNEL_3
2177 * @arg @ref LL_DMA_CHANNEL_4
2178 * @arg @ref LL_DMA_CHANNEL_5
2179 * @arg @ref LL_DMA_CHANNEL_6
2180 * @arg @ref LL_DMA_CHANNEL_7
2181 * @arg @ref LL_DMA_CHANNEL_8
2182 * @arg @ref LL_DMA_CHANNEL_9
2183 * @arg @ref LL_DMA_CHANNEL_10
2184 * @arg @ref LL_DMA_CHANNEL_11
2185 * @arg @ref LL_DMA_CHANNEL_12
2186 * @arg @ref LL_DMA_CHANNEL_13
2187 * @arg @ref LL_DMA_CHANNEL_14
2188 * @arg @ref LL_DMA_CHANNEL_15
2189 * @param DestByteExchange This parameter can be one of the following values:
2190 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
2191 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
2192 * @retval None.
2193 */
LL_DMA_SetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestByteExchange)2194 __STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
2195 {
2196 uint32_t dma_base_addr = (uint32_t)DMAx;
2197 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
2198 DestByteExchange);
2199 }
2200
2201 /**
2202 * @brief Get destination byte exchange.
2203 * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
2204 * @param DMAx DMAx Instance
2205 * @param Channel This parameter can be one of the following values:
2206 * @arg @ref LL_DMA_CHANNEL_0
2207 * @arg @ref LL_DMA_CHANNEL_1
2208 * @arg @ref LL_DMA_CHANNEL_2
2209 * @arg @ref LL_DMA_CHANNEL_3
2210 * @arg @ref LL_DMA_CHANNEL_4
2211 * @arg @ref LL_DMA_CHANNEL_5
2212 * @arg @ref LL_DMA_CHANNEL_6
2213 * @arg @ref LL_DMA_CHANNEL_7
2214 * @arg @ref LL_DMA_CHANNEL_8
2215 * @arg @ref LL_DMA_CHANNEL_9
2216 * @arg @ref LL_DMA_CHANNEL_10
2217 * @arg @ref LL_DMA_CHANNEL_11
2218 * @arg @ref LL_DMA_CHANNEL_12
2219 * @arg @ref LL_DMA_CHANNEL_13
2220 * @arg @ref LL_DMA_CHANNEL_14
2221 * @arg @ref LL_DMA_CHANNEL_15
2222 * @retval Returned value can be one of the following values:
2223 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
2224 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
2225 */
LL_DMA_GetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2226 __STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2227 {
2228 uint32_t dma_base_addr = (uint32_t)DMAx;
2229 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
2230 }
2231
2232 /**
2233 * @brief Set source byte exchange.
2234 * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
2235 * @param DMAx DMAx Instance
2236 * @param Channel This parameter can be one of the following values:
2237 * @arg @ref LL_DMA_CHANNEL_0
2238 * @arg @ref LL_DMA_CHANNEL_1
2239 * @arg @ref LL_DMA_CHANNEL_2
2240 * @arg @ref LL_DMA_CHANNEL_3
2241 * @arg @ref LL_DMA_CHANNEL_4
2242 * @arg @ref LL_DMA_CHANNEL_5
2243 * @arg @ref LL_DMA_CHANNEL_6
2244 * @arg @ref LL_DMA_CHANNEL_7
2245 * @arg @ref LL_DMA_CHANNEL_8
2246 * @arg @ref LL_DMA_CHANNEL_9
2247 * @arg @ref LL_DMA_CHANNEL_10
2248 * @arg @ref LL_DMA_CHANNEL_11
2249 * @arg @ref LL_DMA_CHANNEL_12
2250 * @arg @ref LL_DMA_CHANNEL_13
2251 * @arg @ref LL_DMA_CHANNEL_14
2252 * @arg @ref LL_DMA_CHANNEL_15
2253 * @param SrcByteExchange This parameter can be one of the following values:
2254 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
2255 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
2256 * @retval None.
2257 */
LL_DMA_SetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcByteExchange)2258 __STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
2259 {
2260 uint32_t dma_base_addr = (uint32_t)DMAx;
2261 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
2262 SrcByteExchange);
2263 }
2264
2265 /**
2266 * @brief Get source byte exchange.
2267 * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
2268 * @param DMAx DMAx Instance
2269 * @param Channel This parameter can be one of the following values:
2270 * @arg @ref LL_DMA_CHANNEL_0
2271 * @arg @ref LL_DMA_CHANNEL_1
2272 * @arg @ref LL_DMA_CHANNEL_2
2273 * @arg @ref LL_DMA_CHANNEL_3
2274 * @arg @ref LL_DMA_CHANNEL_4
2275 * @arg @ref LL_DMA_CHANNEL_5
2276 * @arg @ref LL_DMA_CHANNEL_6
2277 * @arg @ref LL_DMA_CHANNEL_7
2278 * @arg @ref LL_DMA_CHANNEL_8
2279 * @arg @ref LL_DMA_CHANNEL_9
2280 * @arg @ref LL_DMA_CHANNEL_10
2281 * @arg @ref LL_DMA_CHANNEL_11
2282 * @arg @ref LL_DMA_CHANNEL_12
2283 * @arg @ref LL_DMA_CHANNEL_13
2284 * @arg @ref LL_DMA_CHANNEL_14
2285 * @arg @ref LL_DMA_CHANNEL_15
2286 * @retval Returned value can be one of the following values:
2287 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
2288 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
2289 */
LL_DMA_GetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)2290 __STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
2291 {
2292 uint32_t dma_base_addr = (uint32_t)DMAx;
2293 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
2294 }
2295
2296 /**
2297 * @brief Set destination burst length.
2298 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
2299 * @param DMAx DMAx Instance
2300 * @param Channel This parameter can be one of the following values:
2301 * @arg @ref LL_DMA_CHANNEL_0
2302 * @arg @ref LL_DMA_CHANNEL_1
2303 * @arg @ref LL_DMA_CHANNEL_2
2304 * @arg @ref LL_DMA_CHANNEL_3
2305 * @arg @ref LL_DMA_CHANNEL_4
2306 * @arg @ref LL_DMA_CHANNEL_5
2307 * @arg @ref LL_DMA_CHANNEL_6
2308 * @arg @ref LL_DMA_CHANNEL_7
2309 * @arg @ref LL_DMA_CHANNEL_8
2310 * @arg @ref LL_DMA_CHANNEL_9
2311 * @arg @ref LL_DMA_CHANNEL_10
2312 * @arg @ref LL_DMA_CHANNEL_11
2313 * @arg @ref LL_DMA_CHANNEL_12
2314 * @arg @ref LL_DMA_CHANNEL_13
2315 * @arg @ref LL_DMA_CHANNEL_14
2316 * @arg @ref LL_DMA_CHANNEL_15
2317 * @param DestBurstLength Between 1 to 64
2318 * @retval None.
2319 */
LL_DMA_SetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestBurstLength)2320 __STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
2321 {
2322 uint32_t dma_base_addr = (uint32_t)DMAx;
2323 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
2324 ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
2325 }
2326
2327 /**
2328 * @brief Get destination burst length.
2329 * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
2330 * @param DMAx DMAx Instance
2331 * @param Channel This parameter can be one of the following values:
2332 * @arg @ref LL_DMA_CHANNEL_0
2333 * @arg @ref LL_DMA_CHANNEL_1
2334 * @arg @ref LL_DMA_CHANNEL_2
2335 * @arg @ref LL_DMA_CHANNEL_3
2336 * @arg @ref LL_DMA_CHANNEL_4
2337 * @arg @ref LL_DMA_CHANNEL_5
2338 * @arg @ref LL_DMA_CHANNEL_6
2339 * @arg @ref LL_DMA_CHANNEL_7
2340 * @arg @ref LL_DMA_CHANNEL_8
2341 * @arg @ref LL_DMA_CHANNEL_9
2342 * @arg @ref LL_DMA_CHANNEL_10
2343 * @arg @ref LL_DMA_CHANNEL_11
2344 * @arg @ref LL_DMA_CHANNEL_12
2345 * @arg @ref LL_DMA_CHANNEL_13
2346 * @arg @ref LL_DMA_CHANNEL_14
2347 * @arg @ref LL_DMA_CHANNEL_15
2348 * @retval Between 1 to 64.
2349 */
LL_DMA_GetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)2350 __STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2351 {
2352 uint32_t dma_base_addr = (uint32_t)DMAx;
2353 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2354 DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
2355 }
2356
2357 /**
2358 * @brief Set destination increment mode.
2359 * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
2360 * @param DMAx DMAx Instance
2361 * @param Channel This parameter can be one of the following values:
2362 * @arg @ref LL_DMA_CHANNEL_0
2363 * @arg @ref LL_DMA_CHANNEL_1
2364 * @arg @ref LL_DMA_CHANNEL_2
2365 * @arg @ref LL_DMA_CHANNEL_3
2366 * @arg @ref LL_DMA_CHANNEL_4
2367 * @arg @ref LL_DMA_CHANNEL_5
2368 * @arg @ref LL_DMA_CHANNEL_6
2369 * @arg @ref LL_DMA_CHANNEL_7
2370 * @arg @ref LL_DMA_CHANNEL_8
2371 * @arg @ref LL_DMA_CHANNEL_9
2372 * @arg @ref LL_DMA_CHANNEL_10
2373 * @arg @ref LL_DMA_CHANNEL_11
2374 * @arg @ref LL_DMA_CHANNEL_12
2375 * @arg @ref LL_DMA_CHANNEL_13
2376 * @arg @ref LL_DMA_CHANNEL_14
2377 * @arg @ref LL_DMA_CHANNEL_15
2378 * @param DestInc This parameter can be one of the following values:
2379 * @arg @ref LL_DMA_DEST_FIXED
2380 * @arg @ref LL_DMA_DEST_INCREMENT
2381 * @retval None.
2382 */
LL_DMA_SetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestInc)2383 __STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
2384 {
2385 uint32_t dma_base_addr = (uint32_t)DMAx;
2386 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
2387 }
2388
2389 /**
2390 * @brief Get destination increment mode.
2391 * @note This API is used for all available DMA channels.
2392 * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode
2393 * @param DMAx DMAx Instance
2394 * @param Channel This parameter can be one of the following values:
2395 * @arg @ref LL_DMA_CHANNEL_0
2396 * @arg @ref LL_DMA_CHANNEL_1
2397 * @arg @ref LL_DMA_CHANNEL_2
2398 * @arg @ref LL_DMA_CHANNEL_3
2399 * @arg @ref LL_DMA_CHANNEL_4
2400 * @arg @ref LL_DMA_CHANNEL_5
2401 * @arg @ref LL_DMA_CHANNEL_6
2402 * @arg @ref LL_DMA_CHANNEL_7
2403 * @arg @ref LL_DMA_CHANNEL_8
2404 * @arg @ref LL_DMA_CHANNEL_9
2405 * @arg @ref LL_DMA_CHANNEL_10
2406 * @arg @ref LL_DMA_CHANNEL_11
2407 * @arg @ref LL_DMA_CHANNEL_12
2408 * @arg @ref LL_DMA_CHANNEL_13
2409 * @arg @ref LL_DMA_CHANNEL_14
2410 * @arg @ref LL_DMA_CHANNEL_15
2411 * @retval Returned value can be one of the following values:
2412 * @arg @ref LL_DMA_DEST_FIXED
2413 * @arg @ref LL_DMA_DEST_INCREMENT
2414 */
LL_DMA_GetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)2415 __STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2416 {
2417 uint32_t dma_base_addr = (uint32_t)DMAx;
2418 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
2419 }
2420
2421 /**
2422 * @brief Set destination data width.
2423 * @note This API is used for all available DMA channels.
2424 * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
2425 * @param DMAx DMAx Instance
2426 * @param Channel This parameter can be one of the following values:
2427 * @arg @ref LL_DMA_CHANNEL_0
2428 * @arg @ref LL_DMA_CHANNEL_1
2429 * @arg @ref LL_DMA_CHANNEL_2
2430 * @arg @ref LL_DMA_CHANNEL_3
2431 * @arg @ref LL_DMA_CHANNEL_4
2432 * @arg @ref LL_DMA_CHANNEL_5
2433 * @arg @ref LL_DMA_CHANNEL_6
2434 * @arg @ref LL_DMA_CHANNEL_7
2435 * @arg @ref LL_DMA_CHANNEL_8
2436 * @arg @ref LL_DMA_CHANNEL_9
2437 * @arg @ref LL_DMA_CHANNEL_10
2438 * @arg @ref LL_DMA_CHANNEL_11
2439 * @arg @ref LL_DMA_CHANNEL_12
2440 * @arg @ref LL_DMA_CHANNEL_13
2441 * @arg @ref LL_DMA_CHANNEL_14
2442 * @arg @ref LL_DMA_CHANNEL_15
2443 * @param DestDataWidth This parameter can be one of the following values:
2444 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
2445 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
2446 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
2447 * @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
2448 * @retval None.
2449 */
LL_DMA_SetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestDataWidth)2450 __STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
2451 {
2452 uint32_t dma_base_addr = (uint32_t)DMAx;
2453 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
2454 DestDataWidth);
2455 }
2456
2457 /**
2458 * @brief Get destination data width.
2459 * @note This API is used for all available DMA channels.
2460 * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
2461 * @param DMAx DMAx Instance
2462 * @param Channel This parameter can be one of the following values:
2463 * @arg @ref LL_DMA_CHANNEL_0
2464 * @arg @ref LL_DMA_CHANNEL_1
2465 * @arg @ref LL_DMA_CHANNEL_2
2466 * @arg @ref LL_DMA_CHANNEL_3
2467 * @arg @ref LL_DMA_CHANNEL_4
2468 * @arg @ref LL_DMA_CHANNEL_5
2469 * @arg @ref LL_DMA_CHANNEL_6
2470 * @arg @ref LL_DMA_CHANNEL_7
2471 * @arg @ref LL_DMA_CHANNEL_8
2472 * @arg @ref LL_DMA_CHANNEL_9
2473 * @arg @ref LL_DMA_CHANNEL_10
2474 * @arg @ref LL_DMA_CHANNEL_11
2475 * @arg @ref LL_DMA_CHANNEL_12
2476 * @arg @ref LL_DMA_CHANNEL_13
2477 * @arg @ref LL_DMA_CHANNEL_14
2478 * @arg @ref LL_DMA_CHANNEL_15
2479 * @retval Returned value can be one of the following values:
2480 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
2481 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
2482 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
2483 * @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
2484 */
LL_DMA_GetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)2485 __STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
2486 {
2487 uint32_t dma_base_addr = (uint32_t)DMAx;
2488 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
2489 }
2490
2491 /**
2492 * @brief Set source allocated port.
2493 * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
2494 * @param DMAx DMAx Instance
2495 * @param Channel This parameter can be one of the following values:
2496 * @arg @ref LL_DMA_CHANNEL_0
2497 * @arg @ref LL_DMA_CHANNEL_1
2498 * @arg @ref LL_DMA_CHANNEL_2
2499 * @arg @ref LL_DMA_CHANNEL_3
2500 * @arg @ref LL_DMA_CHANNEL_4
2501 * @arg @ref LL_DMA_CHANNEL_5
2502 * @arg @ref LL_DMA_CHANNEL_6
2503 * @arg @ref LL_DMA_CHANNEL_7
2504 * @arg @ref LL_DMA_CHANNEL_8
2505 * @arg @ref LL_DMA_CHANNEL_9
2506 * @arg @ref LL_DMA_CHANNEL_10
2507 * @arg @ref LL_DMA_CHANNEL_11
2508 * @arg @ref LL_DMA_CHANNEL_12
2509 * @arg @ref LL_DMA_CHANNEL_13
2510 * @arg @ref LL_DMA_CHANNEL_14
2511 * @arg @ref LL_DMA_CHANNEL_15
2512 * @param SrcAllocatedPort This parameter can be one of the following values:
2513 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
2514 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
2515 * @retval None.
2516 */
LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAllocatedPort)2517 __STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
2518 {
2519 uint32_t dma_base_addr = (uint32_t)DMAx;
2520 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
2521 SrcAllocatedPort);
2522 }
2523
2524 /**
2525 * @brief Get source allocated port.
2526 * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
2527 * @param DMAx DMAx Instance
2528 * @param Channel This parameter can be one of the following values:
2529 * @arg @ref LL_DMA_CHANNEL_0
2530 * @arg @ref LL_DMA_CHANNEL_1
2531 * @arg @ref LL_DMA_CHANNEL_2
2532 * @arg @ref LL_DMA_CHANNEL_3
2533 * @arg @ref LL_DMA_CHANNEL_4
2534 * @arg @ref LL_DMA_CHANNEL_5
2535 * @arg @ref LL_DMA_CHANNEL_6
2536 * @arg @ref LL_DMA_CHANNEL_7
2537 * @arg @ref LL_DMA_CHANNEL_8
2538 * @arg @ref LL_DMA_CHANNEL_9
2539 * @arg @ref LL_DMA_CHANNEL_10
2540 * @arg @ref LL_DMA_CHANNEL_11
2541 * @arg @ref LL_DMA_CHANNEL_12
2542 * @arg @ref LL_DMA_CHANNEL_13
2543 * @arg @ref LL_DMA_CHANNEL_14
2544 * @arg @ref LL_DMA_CHANNEL_15
2545 * @retval Returned value can be one of the following values:
2546 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
2547 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
2548 */
LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)2549 __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
2550 {
2551 uint32_t dma_base_addr = (uint32_t)DMAx;
2552 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
2553 }
2554
2555 /**
2556 * @brief Set data alignment mode.
2557 * @note This API is used for all available DMA channels.
2558 * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
2559 * @param DMAx DMAx Instance
2560 * @param Channel This parameter can be one of the following values:
2561 * @arg @ref LL_DMA_CHANNEL_0
2562 * @arg @ref LL_DMA_CHANNEL_1
2563 * @arg @ref LL_DMA_CHANNEL_2
2564 * @arg @ref LL_DMA_CHANNEL_3
2565 * @arg @ref LL_DMA_CHANNEL_4
2566 * @arg @ref LL_DMA_CHANNEL_5
2567 * @arg @ref LL_DMA_CHANNEL_6
2568 * @arg @ref LL_DMA_CHANNEL_7
2569 * @arg @ref LL_DMA_CHANNEL_8
2570 * @arg @ref LL_DMA_CHANNEL_9
2571 * @arg @ref LL_DMA_CHANNEL_10
2572 * @arg @ref LL_DMA_CHANNEL_11
2573 * @arg @ref LL_DMA_CHANNEL_12
2574 * @arg @ref LL_DMA_CHANNEL_13
2575 * @arg @ref LL_DMA_CHANNEL_14
2576 * @arg @ref LL_DMA_CHANNEL_15
2577 * @param DataAlignment This parameter can be one of the following values:
2578 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2579 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2580 * @arg @ref LL_DMA_DATA_PACK_UNPACK
2581 * @retval None.
2582 */
LL_DMA_SetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DataAlignment)2583 __STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
2584 {
2585 uint32_t dma_base_addr = (uint32_t)DMAx;
2586 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
2587 DataAlignment);
2588 }
2589
2590 /**
2591 * @brief Get data alignment mode.
2592 * @note This API is used for all available DMA channels.
2593 * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
2594 * @param DMAx DMAx Instance
2595 * @param Channel This parameter can be one of the following values:
2596 * @arg @ref LL_DMA_CHANNEL_0
2597 * @arg @ref LL_DMA_CHANNEL_1
2598 * @arg @ref LL_DMA_CHANNEL_2
2599 * @arg @ref LL_DMA_CHANNEL_3
2600 * @arg @ref LL_DMA_CHANNEL_4
2601 * @arg @ref LL_DMA_CHANNEL_5
2602 * @arg @ref LL_DMA_CHANNEL_6
2603 * @arg @ref LL_DMA_CHANNEL_7
2604 * @arg @ref LL_DMA_CHANNEL_8
2605 * @arg @ref LL_DMA_CHANNEL_9
2606 * @arg @ref LL_DMA_CHANNEL_10
2607 * @arg @ref LL_DMA_CHANNEL_11
2608 * @arg @ref LL_DMA_CHANNEL_12
2609 * @arg @ref LL_DMA_CHANNEL_13
2610 * @arg @ref LL_DMA_CHANNEL_14
2611 * @arg @ref LL_DMA_CHANNEL_15
2612 * @retval Returned value can be one of the following values:
2613 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2614 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2615 * @arg @ref LL_DMA_DATA_PACK_UNPACK
2616 */
LL_DMA_GetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel)2617 __STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel)
2618 {
2619 uint32_t dma_base_addr = (uint32_t)DMAx;
2620 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
2621 }
2622
2623 /**
2624 * @brief Set source burst length.
2625 * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
2626 * @param DMAx DMAx Instance
2627 * @param Channel This parameter can be one of the following values:
2628 * @arg @ref LL_DMA_CHANNEL_0
2629 * @arg @ref LL_DMA_CHANNEL_1
2630 * @arg @ref LL_DMA_CHANNEL_2
2631 * @arg @ref LL_DMA_CHANNEL_3
2632 * @arg @ref LL_DMA_CHANNEL_4
2633 * @arg @ref LL_DMA_CHANNEL_5
2634 * @arg @ref LL_DMA_CHANNEL_6
2635 * @arg @ref LL_DMA_CHANNEL_7
2636 * @arg @ref LL_DMA_CHANNEL_8
2637 * @arg @ref LL_DMA_CHANNEL_9
2638 * @arg @ref LL_DMA_CHANNEL_10
2639 * @arg @ref LL_DMA_CHANNEL_11
2640 * @arg @ref LL_DMA_CHANNEL_12
2641 * @arg @ref LL_DMA_CHANNEL_13
2642 * @arg @ref LL_DMA_CHANNEL_14
2643 * @arg @ref LL_DMA_CHANNEL_15
2644 * @param SrcBurstLength Between 1 to 64
2645 * @retval None.
2646 */
LL_DMA_SetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength)2647 __STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
2648 {
2649 uint32_t dma_base_addr = (uint32_t)DMAx;
2650 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
2651 ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
2652 }
2653
2654 /**
2655 * @brief Get source burst length.
2656 * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
2657 * @param DMAx DMAx Instance
2658 * @param Channel This parameter can be one of the following values:
2659 * @arg @ref LL_DMA_CHANNEL_0
2660 * @arg @ref LL_DMA_CHANNEL_1
2661 * @arg @ref LL_DMA_CHANNEL_2
2662 * @arg @ref LL_DMA_CHANNEL_3
2663 * @arg @ref LL_DMA_CHANNEL_4
2664 * @arg @ref LL_DMA_CHANNEL_5
2665 * @arg @ref LL_DMA_CHANNEL_6
2666 * @arg @ref LL_DMA_CHANNEL_7
2667 * @arg @ref LL_DMA_CHANNEL_8
2668 * @arg @ref LL_DMA_CHANNEL_9
2669 * @arg @ref LL_DMA_CHANNEL_10
2670 * @arg @ref LL_DMA_CHANNEL_11
2671 * @arg @ref LL_DMA_CHANNEL_12
2672 * @arg @ref LL_DMA_CHANNEL_13
2673 * @arg @ref LL_DMA_CHANNEL_14
2674 * @arg @ref LL_DMA_CHANNEL_15
2675 * @retval Between 1 to 64
2676 * @retval None.
2677 */
LL_DMA_GetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)2678 __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2679 {
2680 uint32_t dma_base_addr = (uint32_t)DMAx;
2681 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2682 DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
2683 }
2684
2685 /**
2686 * @brief Set source increment mode.
2687 * @note This API is used for all available DMA channels.
2688 * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
2689 * @param DMAx DMAx Instance
2690 * @param Channel This parameter can be one of the following values:
2691 * @arg @ref LL_DMA_CHANNEL_0
2692 * @arg @ref LL_DMA_CHANNEL_1
2693 * @arg @ref LL_DMA_CHANNEL_2
2694 * @arg @ref LL_DMA_CHANNEL_3
2695 * @arg @ref LL_DMA_CHANNEL_4
2696 * @arg @ref LL_DMA_CHANNEL_5
2697 * @arg @ref LL_DMA_CHANNEL_6
2698 * @arg @ref LL_DMA_CHANNEL_7
2699 * @arg @ref LL_DMA_CHANNEL_8
2700 * @arg @ref LL_DMA_CHANNEL_9
2701 * @arg @ref LL_DMA_CHANNEL_10
2702 * @arg @ref LL_DMA_CHANNEL_11
2703 * @arg @ref LL_DMA_CHANNEL_12
2704 * @arg @ref LL_DMA_CHANNEL_13
2705 * @arg @ref LL_DMA_CHANNEL_14
2706 * @arg @ref LL_DMA_CHANNEL_15
2707 * @param SrcInc This parameter can be one of the following values:
2708 * @arg @ref LL_DMA_SRC_FIXED
2709 * @arg @ref LL_DMA_SRC_INCREMENT
2710 * @retval None.
2711 */
LL_DMA_SetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcInc)2712 __STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
2713 {
2714 uint32_t dma_base_addr = (uint32_t)DMAx;
2715 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
2716 }
2717
2718 /**
2719 * @brief Get source increment mode.
2720 * @note This API is used for all available DMA channels.
2721 * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
2722 * @param DMAx DMAx Instance
2723 * @param Channel This parameter can be one of the following values:
2724 * @arg @ref LL_DMA_CHANNEL_0
2725 * @arg @ref LL_DMA_CHANNEL_1
2726 * @arg @ref LL_DMA_CHANNEL_2
2727 * @arg @ref LL_DMA_CHANNEL_3
2728 * @arg @ref LL_DMA_CHANNEL_4
2729 * @arg @ref LL_DMA_CHANNEL_5
2730 * @arg @ref LL_DMA_CHANNEL_6
2731 * @arg @ref LL_DMA_CHANNEL_7
2732 * @arg @ref LL_DMA_CHANNEL_8
2733 * @arg @ref LL_DMA_CHANNEL_9
2734 * @arg @ref LL_DMA_CHANNEL_10
2735 * @arg @ref LL_DMA_CHANNEL_11
2736 * @arg @ref LL_DMA_CHANNEL_12
2737 * @arg @ref LL_DMA_CHANNEL_13
2738 * @arg @ref LL_DMA_CHANNEL_14
2739 * @arg @ref LL_DMA_CHANNEL_15
2740 * @retval Returned value can be one of the following values:
2741 * @arg @ref LL_DMA_SRC_FIXED
2742 * @arg @ref LL_DMA_SRC_INCREMENT
2743 */
LL_DMA_GetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)2744 __STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2745 {
2746 uint32_t dma_base_addr = (uint32_t)DMAx;
2747 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
2748 }
2749
2750 /**
2751 * @brief Set source data width.
2752 * @note This API is used for all available DMA channels.
2753 * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
2754 * @param DMAx DMAx Instance
2755 * @param Channel This parameter can be one of the following values:
2756 * @arg @ref LL_DMA_CHANNEL_0
2757 * @arg @ref LL_DMA_CHANNEL_1
2758 * @arg @ref LL_DMA_CHANNEL_2
2759 * @arg @ref LL_DMA_CHANNEL_3
2760 * @arg @ref LL_DMA_CHANNEL_4
2761 * @arg @ref LL_DMA_CHANNEL_5
2762 * @arg @ref LL_DMA_CHANNEL_6
2763 * @arg @ref LL_DMA_CHANNEL_7
2764 * @arg @ref LL_DMA_CHANNEL_8
2765 * @arg @ref LL_DMA_CHANNEL_9
2766 * @arg @ref LL_DMA_CHANNEL_10
2767 * @arg @ref LL_DMA_CHANNEL_11
2768 * @arg @ref LL_DMA_CHANNEL_12
2769 * @arg @ref LL_DMA_CHANNEL_13
2770 * @arg @ref LL_DMA_CHANNEL_14
2771 * @arg @ref LL_DMA_CHANNEL_15
2772 * @param SrcDataWidth This parameter can be one of the following values:
2773 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2774 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2775 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2776 * @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
2777 * @retval None.
2778 */
LL_DMA_SetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcDataWidth)2779 __STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
2780 {
2781 uint32_t dma_base_addr = (uint32_t)DMAx;
2782 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
2783 SrcDataWidth);
2784 }
2785
2786 /**
2787 * @brief Get Source Data width.
2788 * @note This API is used for all available DMA channels.
2789 * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
2790 * @param DMAx DMAx Instance
2791 * @param Channel This parameter can be one of the following values:
2792 * @arg @ref LL_DMA_CHANNEL_0
2793 * @arg @ref LL_DMA_CHANNEL_1
2794 * @arg @ref LL_DMA_CHANNEL_2
2795 * @arg @ref LL_DMA_CHANNEL_3
2796 * @arg @ref LL_DMA_CHANNEL_4
2797 * @arg @ref LL_DMA_CHANNEL_5
2798 * @arg @ref LL_DMA_CHANNEL_6
2799 * @arg @ref LL_DMA_CHANNEL_7
2800 * @arg @ref LL_DMA_CHANNEL_8
2801 * @arg @ref LL_DMA_CHANNEL_9
2802 * @arg @ref LL_DMA_CHANNEL_10
2803 * @arg @ref LL_DMA_CHANNEL_11
2804 * @arg @ref LL_DMA_CHANNEL_12
2805 * @arg @ref LL_DMA_CHANNEL_13
2806 * @arg @ref LL_DMA_CHANNEL_14
2807 * @arg @ref LL_DMA_CHANNEL_15
2808 * @retval Returned value can be one of the following values:
2809 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2810 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2811 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2812 * @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
2813 */
LL_DMA_GetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)2814 __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
2815 {
2816 uint32_t dma_base_addr = (uint32_t)DMAx;
2817 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
2818 }
2819
2820 /**
2821 * @brief Configure channel transfer.
2822 * @note This API is used for all available DMA channels.
2823 * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
2824 * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
2825 * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
2826 * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
2827 * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
2828 * CTR2 SWREQ LL_DMA_ConfigChannelTransfer\n
2829 * CTR2 PFREQ LL_DMA_ConfigChannelTransfer
2830 * @param DMAx DMAx Instance
2831 * @param Channel This parameter can be one of the following values:
2832 * @arg @ref LL_DMA_CHANNEL_0
2833 * @arg @ref LL_DMA_CHANNEL_1
2834 * @arg @ref LL_DMA_CHANNEL_2
2835 * @arg @ref LL_DMA_CHANNEL_3
2836 * @arg @ref LL_DMA_CHANNEL_4
2837 * @arg @ref LL_DMA_CHANNEL_5
2838 * @arg @ref LL_DMA_CHANNEL_6
2839 * @arg @ref LL_DMA_CHANNEL_7
2840 * @arg @ref LL_DMA_CHANNEL_8
2841 * @arg @ref LL_DMA_CHANNEL_9
2842 * @arg @ref LL_DMA_CHANNEL_10
2843 * @arg @ref LL_DMA_CHANNEL_11
2844 * @arg @ref LL_DMA_CHANNEL_12
2845 * @arg @ref LL_DMA_CHANNEL_13
2846 * @arg @ref LL_DMA_CHANNEL_14
2847 * @arg @ref LL_DMA_CHANNEL_15
2848 * @param Configuration This parameter must be a combination of all the following values:
2849 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
2850 * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2851 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK
2852 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or
2853 * @ref LL_DMA_TRIG_POLARITY_FALLING
2854 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
2855 * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
2856 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
2857 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
2858 * @arg @ref LL_DMA_NORMAL or @ref LL_DMA_PFCTRL
2859 *@retval None.
2860 */
LL_DMA_ConfigChannelTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2861 __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2862 {
2863 uint32_t dma_base_addr = (uint32_t)DMAx;
2864 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2865 (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ |
2866 DMA_CTR2_PFREQ), Configuration);
2867 }
2868
2869 /**
2870 * @brief Set transfer event mode.
2871 * @note This API is used for all available DMA channels.
2872 * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
2873 * @param DMAx DMAx Instance
2874 * @param Channel This parameter can be one of the following values:
2875 * @arg @ref LL_DMA_CHANNEL_0
2876 * @arg @ref LL_DMA_CHANNEL_1
2877 * @arg @ref LL_DMA_CHANNEL_2
2878 * @arg @ref LL_DMA_CHANNEL_3
2879 * @arg @ref LL_DMA_CHANNEL_4
2880 * @arg @ref LL_DMA_CHANNEL_5
2881 * @arg @ref LL_DMA_CHANNEL_6
2882 * @arg @ref LL_DMA_CHANNEL_7
2883 * @arg @ref LL_DMA_CHANNEL_8
2884 * @arg @ref LL_DMA_CHANNEL_9
2885 * @arg @ref LL_DMA_CHANNEL_10
2886 * @arg @ref LL_DMA_CHANNEL_11
2887 * @arg @ref LL_DMA_CHANNEL_12
2888 * @arg @ref LL_DMA_CHANNEL_13
2889 * @arg @ref LL_DMA_CHANNEL_14
2890 * @arg @ref LL_DMA_CHANNEL_15
2891 * @param TransferEventMode This parameter can be one of the following values:
2892 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
2893 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
2894 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
2895 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2896 * @retval None.
2897 */
LL_DMA_SetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TransferEventMode)2898 __STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
2899 {
2900 uint32_t dma_base_addr = (uint32_t)DMAx;
2901 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
2902 TransferEventMode);
2903 }
2904
2905 /**
2906 * @brief Get transfer event mode.
2907 * @note This API is used for all available DMA channels.
2908 * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
2909 * @param DMAx DMAx Instance
2910 * @param Channel This parameter can be one of the following values:
2911 * @arg @ref LL_DMA_CHANNEL_0
2912 * @arg @ref LL_DMA_CHANNEL_1
2913 * @arg @ref LL_DMA_CHANNEL_2
2914 * @arg @ref LL_DMA_CHANNEL_3
2915 * @arg @ref LL_DMA_CHANNEL_4
2916 * @arg @ref LL_DMA_CHANNEL_5
2917 * @arg @ref LL_DMA_CHANNEL_6
2918 * @arg @ref LL_DMA_CHANNEL_7
2919 * @arg @ref LL_DMA_CHANNEL_8
2920 * @arg @ref LL_DMA_CHANNEL_9
2921 * @arg @ref LL_DMA_CHANNEL_10
2922 * @arg @ref LL_DMA_CHANNEL_11
2923 * @arg @ref LL_DMA_CHANNEL_12
2924 * @arg @ref LL_DMA_CHANNEL_13
2925 * @arg @ref LL_DMA_CHANNEL_14
2926 * @arg @ref LL_DMA_CHANNEL_15
2927 * @retval Returned value can be one of the following values:
2928 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
2929 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
2930 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
2931 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2932 */
LL_DMA_GetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel)2933 __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2934 {
2935 uint32_t dma_base_addr = (uint32_t)DMAx;
2936 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
2937 }
2938
2939 /**
2940 * @brief Set trigger polarity.
2941 * @note This API is used for all available DMA channels.
2942 * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
2943 * @param DMAx DMAx Instance
2944 * @param Channel This parameter can be one of the following values:
2945 * @arg @ref LL_DMA_CHANNEL_0
2946 * @arg @ref LL_DMA_CHANNEL_1
2947 * @arg @ref LL_DMA_CHANNEL_2
2948 * @arg @ref LL_DMA_CHANNEL_3
2949 * @arg @ref LL_DMA_CHANNEL_4
2950 * @arg @ref LL_DMA_CHANNEL_5
2951 * @arg @ref LL_DMA_CHANNEL_6
2952 * @arg @ref LL_DMA_CHANNEL_7
2953 * @arg @ref LL_DMA_CHANNEL_8
2954 * @arg @ref LL_DMA_CHANNEL_9
2955 * @arg @ref LL_DMA_CHANNEL_10
2956 * @arg @ref LL_DMA_CHANNEL_11
2957 * @arg @ref LL_DMA_CHANNEL_12
2958 * @arg @ref LL_DMA_CHANNEL_13
2959 * @arg @ref LL_DMA_CHANNEL_14
2960 * @arg @ref LL_DMA_CHANNEL_15
2961 * @param TriggerPolarity This parameter can be one of the following values:
2962 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
2963 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
2964 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
2965 * @retval None.
2966 */
LL_DMA_SetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerPolarity)2967 __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
2968 {
2969 uint32_t dma_base_addr = (uint32_t)DMAx;
2970 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
2971 TriggerPolarity);
2972 }
2973
2974 /**
2975 * @brief Get trigger polarity.
2976 * @note This API is used for all available DMA channels.
2977 * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
2978 * @param DMAx DMAx Instance
2979 * @param Channel This parameter can be one of the following values:
2980 * @arg @ref LL_DMA_CHANNEL_0
2981 * @arg @ref LL_DMA_CHANNEL_1
2982 * @arg @ref LL_DMA_CHANNEL_2
2983 * @arg @ref LL_DMA_CHANNEL_3
2984 * @arg @ref LL_DMA_CHANNEL_4
2985 * @arg @ref LL_DMA_CHANNEL_5
2986 * @arg @ref LL_DMA_CHANNEL_6
2987 * @arg @ref LL_DMA_CHANNEL_7
2988 * @arg @ref LL_DMA_CHANNEL_8
2989 * @arg @ref LL_DMA_CHANNEL_9
2990 * @arg @ref LL_DMA_CHANNEL_10
2991 * @arg @ref LL_DMA_CHANNEL_11
2992 * @arg @ref LL_DMA_CHANNEL_12
2993 * @arg @ref LL_DMA_CHANNEL_13
2994 * @arg @ref LL_DMA_CHANNEL_14
2995 * @arg @ref LL_DMA_CHANNEL_15
2996 * @retval Returned value can be one of the following values:
2997 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
2998 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
2999 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
3000 */
LL_DMA_GetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel)3001 __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel)
3002 {
3003 uint32_t dma_base_addr = (uint32_t)DMAx;
3004 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
3005 }
3006
3007 /**
3008 * @brief Set trigger Mode.
3009 * @note This API is used for all available DMA channels.
3010 * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
3011 * @param DMAx DMAx Instance
3012 * @param Channel This parameter can be one of the following values:
3013 * @arg @ref LL_DMA_CHANNEL_0
3014 * @arg @ref LL_DMA_CHANNEL_1
3015 * @arg @ref LL_DMA_CHANNEL_2
3016 * @arg @ref LL_DMA_CHANNEL_3
3017 * @arg @ref LL_DMA_CHANNEL_4
3018 * @arg @ref LL_DMA_CHANNEL_5
3019 * @arg @ref LL_DMA_CHANNEL_6
3020 * @arg @ref LL_DMA_CHANNEL_7
3021 * @arg @ref LL_DMA_CHANNEL_8
3022 * @arg @ref LL_DMA_CHANNEL_9
3023 * @arg @ref LL_DMA_CHANNEL_10
3024 * @arg @ref LL_DMA_CHANNEL_11
3025 * @arg @ref LL_DMA_CHANNEL_12
3026 * @arg @ref LL_DMA_CHANNEL_13
3027 * @arg @ref LL_DMA_CHANNEL_14
3028 * @arg @ref LL_DMA_CHANNEL_15
3029 * @param TriggerMode This parameter can be one of the following values:
3030 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3031 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3032 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3033 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3034 * @retval None.
3035 */
LL_DMA_SetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerMode)3036 __STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
3037 {
3038 uint32_t dma_base_addr = (uint32_t)DMAx;
3039 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
3040 TriggerMode);
3041 }
3042
3043 /**
3044 * @brief Get trigger Mode.
3045 * @note This API is used for all available DMA channels.
3046 * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
3047 * @param DMAx DMAx Instance
3048 * @param Channel This parameter can be one of the following values:
3049 * @arg @ref LL_DMA_CHANNEL_0
3050 * @arg @ref LL_DMA_CHANNEL_1
3051 * @arg @ref LL_DMA_CHANNEL_2
3052 * @arg @ref LL_DMA_CHANNEL_3
3053 * @arg @ref LL_DMA_CHANNEL_4
3054 * @arg @ref LL_DMA_CHANNEL_5
3055 * @arg @ref LL_DMA_CHANNEL_6
3056 * @arg @ref LL_DMA_CHANNEL_7
3057 * @arg @ref LL_DMA_CHANNEL_8
3058 * @arg @ref LL_DMA_CHANNEL_9
3059 * @arg @ref LL_DMA_CHANNEL_10
3060 * @arg @ref LL_DMA_CHANNEL_11
3061 * @arg @ref LL_DMA_CHANNEL_12
3062 * @arg @ref LL_DMA_CHANNEL_13
3063 * @arg @ref LL_DMA_CHANNEL_14
3064 * @arg @ref LL_DMA_CHANNEL_15
3065 * @retval Returned value can be one of the following values:
3066 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3067 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3068 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3069 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3070 */
LL_DMA_GetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel)3071 __STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3072 {
3073 uint32_t dma_base_addr = (uint32_t)DMAx;
3074 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
3075 }
3076
3077 /**
3078 * @brief Set destination hardware and software transfer request.
3079 * @note This API is used for all available DMA channels.
3080 * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
3081 * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
3082 * @param DMAx DMAx Instance
3083 * @param Channel This parameter can be one of the following values:
3084 * @arg @ref LL_DMA_CHANNEL_0
3085 * @arg @ref LL_DMA_CHANNEL_1
3086 * @arg @ref LL_DMA_CHANNEL_2
3087 * @arg @ref LL_DMA_CHANNEL_3
3088 * @arg @ref LL_DMA_CHANNEL_4
3089 * @arg @ref LL_DMA_CHANNEL_5
3090 * @arg @ref LL_DMA_CHANNEL_6
3091 * @arg @ref LL_DMA_CHANNEL_7
3092 * @arg @ref LL_DMA_CHANNEL_8
3093 * @arg @ref LL_DMA_CHANNEL_9
3094 * @arg @ref LL_DMA_CHANNEL_10
3095 * @arg @ref LL_DMA_CHANNEL_11
3096 * @arg @ref LL_DMA_CHANNEL_12
3097 * @arg @ref LL_DMA_CHANNEL_13
3098 * @arg @ref LL_DMA_CHANNEL_14
3099 * @arg @ref LL_DMA_CHANNEL_15
3100 * @param Direction This parameter can be one of the following values:
3101 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3102 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
3103 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3104 * @retval None.
3105 */
LL_DMA_SetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)3106 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
3107 {
3108 uint32_t dma_base_addr = (uint32_t)DMAx;
3109 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3110 DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
3111 }
3112
3113 /**
3114 * @brief Get destination hardware and software transfer request.
3115 * @note This API is used for all available DMA channels.
3116 * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
3117 * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
3118 * @param DMAx DMAx Instance
3119 * @param Channel This parameter can be one of the following values:
3120 * @arg @ref LL_DMA_CHANNEL_0
3121 * @arg @ref LL_DMA_CHANNEL_1
3122 * @arg @ref LL_DMA_CHANNEL_2
3123 * @arg @ref LL_DMA_CHANNEL_3
3124 * @arg @ref LL_DMA_CHANNEL_4
3125 * @arg @ref LL_DMA_CHANNEL_5
3126 * @arg @ref LL_DMA_CHANNEL_6
3127 * @arg @ref LL_DMA_CHANNEL_7
3128 * @arg @ref LL_DMA_CHANNEL_8
3129 * @arg @ref LL_DMA_CHANNEL_9
3130 * @arg @ref LL_DMA_CHANNEL_10
3131 * @arg @ref LL_DMA_CHANNEL_11
3132 * @arg @ref LL_DMA_CHANNEL_12
3133 * @arg @ref LL_DMA_CHANNEL_13
3134 * @arg @ref LL_DMA_CHANNEL_14
3135 * @arg @ref LL_DMA_CHANNEL_15
3136 * @retval Returned value can be one of the following values:
3137 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3138 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
3139 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3140 */
LL_DMA_GetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel)3141 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
3142 {
3143 uint32_t dma_base_addr = (uint32_t)DMAx;
3144 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3145 DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
3146 }
3147
3148 /**
3149 * @brief Set block hardware request.
3150 * @note This API is used for all available DMA channels.
3151 * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
3152 * @param DMAx DMAx Instance
3153 * @param Channel This parameter can be one of the following values:
3154 * @arg @ref LL_DMA_CHANNEL_0
3155 * @arg @ref LL_DMA_CHANNEL_1
3156 * @arg @ref LL_DMA_CHANNEL_2
3157 * @arg @ref LL_DMA_CHANNEL_3
3158 * @arg @ref LL_DMA_CHANNEL_4
3159 * @arg @ref LL_DMA_CHANNEL_5
3160 * @arg @ref LL_DMA_CHANNEL_6
3161 * @arg @ref LL_DMA_CHANNEL_7
3162 * @arg @ref LL_DMA_CHANNEL_8
3163 * @arg @ref LL_DMA_CHANNEL_9
3164 * @arg @ref LL_DMA_CHANNEL_10
3165 * @arg @ref LL_DMA_CHANNEL_11
3166 * @arg @ref LL_DMA_CHANNEL_12
3167 * @arg @ref LL_DMA_CHANNEL_13
3168 * @arg @ref LL_DMA_CHANNEL_14
3169 * @arg @ref LL_DMA_CHANNEL_15
3170 * @param BlkHWRequest This parameter can be one of the following values:
3171 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3172 * @arg @ref LL_DMA_HWREQUEST_BLK
3173 * @retval None.
3174 */
LL_DMA_SetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkHWRequest)3175 __STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
3176 {
3177 uint32_t dma_base_addr = (uint32_t)DMAx;
3178 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
3179 BlkHWRequest);
3180 }
3181
3182 /**
3183 * @brief Get block hardware request.
3184 * @note This API is used for all available DMA channels.
3185 * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
3186 * @param DMAx DMAx Instance
3187 * @param Channel This parameter can be one of the following values:
3188 * @arg @ref LL_DMA_CHANNEL_0
3189 * @arg @ref LL_DMA_CHANNEL_1
3190 * @arg @ref LL_DMA_CHANNEL_2
3191 * @arg @ref LL_DMA_CHANNEL_3
3192 * @arg @ref LL_DMA_CHANNEL_4
3193 * @arg @ref LL_DMA_CHANNEL_5
3194 * @arg @ref LL_DMA_CHANNEL_6
3195 * @arg @ref LL_DMA_CHANNEL_7
3196 * @arg @ref LL_DMA_CHANNEL_8
3197 * @arg @ref LL_DMA_CHANNEL_9
3198 * @arg @ref LL_DMA_CHANNEL_10
3199 * @arg @ref LL_DMA_CHANNEL_11
3200 * @arg @ref LL_DMA_CHANNEL_12
3201 * @arg @ref LL_DMA_CHANNEL_13
3202 * @arg @ref LL_DMA_CHANNEL_14
3203 * @arg @ref LL_DMA_CHANNEL_15
3204 * @retval Returned value can be one of the following values:
3205 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3206 * @arg @ref LL_DMA_HWREQUEST_BLK
3207 */
LL_DMA_GetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel)3208 __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
3209 {
3210 uint32_t dma_base_addr = (uint32_t)DMAx;
3211 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
3212 }
3213
3214 /**
3215 * @brief Set hardware request.
3216 * @note This API is used for all available DMA channels.
3217 * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
3218 * @param DMAx DMAx Instance
3219 * @param Channel This parameter can be one of the following values:
3220 * @arg @ref LL_DMA_CHANNEL_0
3221 * @arg @ref LL_DMA_CHANNEL_1
3222 * @arg @ref LL_DMA_CHANNEL_2
3223 * @arg @ref LL_DMA_CHANNEL_3
3224 * @arg @ref LL_DMA_CHANNEL_4
3225 * @arg @ref LL_DMA_CHANNEL_5
3226 * @arg @ref LL_DMA_CHANNEL_6
3227 * @arg @ref LL_DMA_CHANNEL_7
3228 * @arg @ref LL_DMA_CHANNEL_8
3229 * @arg @ref LL_DMA_CHANNEL_9
3230 * @arg @ref LL_DMA_CHANNEL_10
3231 * @arg @ref LL_DMA_CHANNEL_11
3232 * @arg @ref LL_DMA_CHANNEL_12
3233 * @arg @ref LL_DMA_CHANNEL_13
3234 * @arg @ref LL_DMA_CHANNEL_14
3235 * @arg @ref LL_DMA_CHANNEL_15
3236 * @param Request This parameter can be one of the following values:
3237 * @arg @ref LL_HPDMA1_REQUEST_JPEG_RX
3238 * @arg @ref LL_HPDMA1_REQUEST_JPEG_TX
3239 * @arg @ref LL_HPDMA1_REQUEST_XSPI1
3240 * @arg @ref LL_HPDMA1_REQUEST_XSPI2
3241 * @arg @ref LL_HPDMA1_REQUEST_SPI3_RX
3242 * @arg @ref LL_HPDMA1_REQUEST_SPI3_TX
3243 * @arg @ref LL_HPDMA1_REQUEST_SPI4_RX
3244 * @arg @ref LL_HPDMA1_REQUEST_SPI4_TX
3245 * @arg @ref LL_HPDMA1_REQUEST_ADC1
3246 * @arg @ref LL_HPDMA1_REQUEST_ADC2
3247 * @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0
3248 * @arg @ref LL_HPDMA1_REQUEST_UART4_RX
3249 * @arg @ref LL_HPDMA1_REQUEST_UART4_TX
3250 * @arg @ref LL_HPDMA1_REQUEST_UART5_RX
3251 * @arg @ref LL_HPDMA1_REQUEST_UART5_TX
3252 * @arg @ref LL_HPDMA1_REQUEST_UART7_RX
3253 * @arg @ref LL_HPDMA1_REQUEST_UART7_TX
3254 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1
3255 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2
3256 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE
3257 * @arg @ref LL_GPDMA1_REQUEST_ADC1
3258 * @arg @ref LL_GPDMA1_REQUEST_ADC2
3259 * @arg @ref LL_GPDMA1_REQUEST_CRYP_IN
3260 * @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT
3261 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN
3262 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
3263 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
3264 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
3265 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
3266 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
3267 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
3268 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
3269 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
3270 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
3271 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
3272 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
3273 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
3274 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
3275 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
3276 * @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG
3277 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
3278 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
3279 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
3280 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
3281 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
3282 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
3283 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
3284 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
3285 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
3286 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
3287 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
3288 * @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG
3289 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
3290 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
3291 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
3292 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
3293 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
3294 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
3295 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
3296 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
3297 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
3298 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2
3299 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
3300 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
3301 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
3302 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
3303 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
3304 * @arg @ref LL_GPDMA1_REQUEST_TIM16_COM
3305 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
3306 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
3307 * @arg @ref LL_GPDMA1_REQUEST_TIM17_COM
3308 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
3309 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
3310 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
3311 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
3312 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
3313 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
3314 * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX
3315 * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX
3316 * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX
3317 * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX
3318 * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX
3319 * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX
3320 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
3321 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
3322 * @arg @ref LL_GPDMA1_REQUEST_SAI2_A
3323 * @arg @ref LL_GPDMA1_REQUEST_SAI2_B
3324 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
3325 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
3326 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
3327 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
3328 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
3329 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
3330 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
3331 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
3332 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
3333 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
3334 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
3335 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
3336 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX
3337 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX
3338 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX
3339 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX
3340 * @arg @ref LL_GPDMA1_REQUEST_UART7_RX
3341 * @arg @ref LL_GPDMA1_REQUEST_UART7_TX
3342 * @arg @ref LL_GPDMA1_REQUEST_UART8_RX
3343 * @arg @ref LL_GPDMA1_REQUEST_UART8_TX
3344 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ
3345 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE
3346 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
3347 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
3348 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
3349 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
3350 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
3351 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
3352 * @arg @ref LL_GPDMA1_REQUEST_SPDIF_RX_DT
3353 * @arg @ref LL_GPDMA1_REQUEST_SPDIF_RX_CS
3354 * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
3355 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
3356 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
3357 * @arg @ref LL_GPDMA1_REQUEST_PSSI
3358 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
3359 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
3360 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
3361 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
3362 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
3363 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
3364 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
3365 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
3366 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
3367 * @retval None.
3368 */
LL_DMA_SetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)3369 __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
3370 {
3371 uint32_t dma_base_addr = (uint32_t)DMAx;
3372 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
3373 }
3374
3375 /**
3376 * @brief Get hardware request.
3377 * @note This API is used for all available DMA channels.
3378 * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
3379 * @param DMAx DMAx Instance
3380 * @param Channel This parameter can be one of the following values:
3381 * @arg @ref LL_DMA_CHANNEL_0
3382 * @arg @ref LL_DMA_CHANNEL_1
3383 * @arg @ref LL_DMA_CHANNEL_2
3384 * @arg @ref LL_DMA_CHANNEL_3
3385 * @arg @ref LL_DMA_CHANNEL_4
3386 * @arg @ref LL_DMA_CHANNEL_5
3387 * @arg @ref LL_DMA_CHANNEL_6
3388 * @arg @ref LL_DMA_CHANNEL_7
3389 * @arg @ref LL_DMA_CHANNEL_8
3390 * @arg @ref LL_DMA_CHANNEL_9
3391 * @arg @ref LL_DMA_CHANNEL_10
3392 * @arg @ref LL_DMA_CHANNEL_11
3393 * @arg @ref LL_DMA_CHANNEL_12
3394 * @arg @ref LL_DMA_CHANNEL_13
3395 * @arg @ref LL_DMA_CHANNEL_14
3396 * @arg @ref LL_DMA_CHANNEL_15
3397 * @retval Returned value can be one of the following values:
3398 * @arg @ref LL_HPDMA1_REQUEST_JPEG_RX
3399 * @arg @ref LL_HPDMA1_REQUEST_JPEG_TX
3400 * @arg @ref LL_HPDMA1_REQUEST_XSPI1
3401 * @arg @ref LL_HPDMA1_REQUEST_XSPI2
3402 * @arg @ref LL_HPDMA1_REQUEST_SPI3_RX
3403 * @arg @ref LL_HPDMA1_REQUEST_SPI3_TX
3404 * @arg @ref LL_HPDMA1_REQUEST_SPI4_RX
3405 * @arg @ref LL_HPDMA1_REQUEST_SPI4_TX
3406 * @arg @ref LL_HPDMA1_REQUEST_ADC1
3407 * @arg @ref LL_HPDMA1_REQUEST_ADC2
3408 * @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0
3409 * @arg @ref LL_HPDMA1_REQUEST_UART4_RX
3410 * @arg @ref LL_HPDMA1_REQUEST_UART4_TX
3411 * @arg @ref LL_HPDMA1_REQUEST_UART5_RX
3412 * @arg @ref LL_HPDMA1_REQUEST_UART5_TX
3413 * @arg @ref LL_HPDMA1_REQUEST_UART7_RX
3414 * @arg @ref LL_HPDMA1_REQUEST_UART7_TX
3415 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1
3416 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2
3417 * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE
3418 * @arg @ref LL_GPDMA1_REQUEST_ADC1
3419 * @arg @ref LL_GPDMA1_REQUEST_ADC2
3420 * @arg @ref LL_GPDMA1_REQUEST_CRYP_IN
3421 * @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT
3422 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN
3423 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
3424 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
3425 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
3426 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
3427 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
3428 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
3429 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
3430 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
3431 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
3432 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
3433 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
3434 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
3435 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
3436 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
3437 * @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG
3438 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
3439 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
3440 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
3441 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
3442 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
3443 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
3444 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
3445 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
3446 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
3447 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
3448 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
3449 * @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG
3450 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
3451 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
3452 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
3453 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
3454 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
3455 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
3456 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
3457 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
3458 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
3459 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2
3460 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
3461 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
3462 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
3463 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
3464 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
3465 * @arg @ref LL_GPDMA1_REQUEST_TIM16_COM
3466 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
3467 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
3468 * @arg @ref LL_GPDMA1_REQUEST_TIM17_COM
3469 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
3470 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
3471 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
3472 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
3473 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
3474 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
3475 * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX
3476 * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX
3477 * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX
3478 * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX
3479 * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX
3480 * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX
3481 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A
3482 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B
3483 * @arg @ref LL_GPDMA1_REQUEST_SAI2_A
3484 * @arg @ref LL_GPDMA1_REQUEST_SAI2_B
3485 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
3486 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
3487 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
3488 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
3489 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
3490 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
3491 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
3492 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
3493 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
3494 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
3495 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
3496 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
3497 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX
3498 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX
3499 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX
3500 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX
3501 * @arg @ref LL_GPDMA1_REQUEST_UART7_RX
3502 * @arg @ref LL_GPDMA1_REQUEST_UART7_TX
3503 * @arg @ref LL_GPDMA1_REQUEST_UART8_RX
3504 * @arg @ref LL_GPDMA1_REQUEST_UART8_TX
3505 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ
3506 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE
3507 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
3508 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
3509 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
3510 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
3511 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
3512 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
3513 * @arg @ref LL_GPDMA1_REQUEST_SPDIF_RX_DT
3514 * @arg @ref LL_GPDMA1_REQUEST_SPDIF_RX_CS
3515 * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
3516 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
3517 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
3518 * @arg @ref LL_GPDMA1_REQUEST_PSSI
3519 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
3520 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
3521 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
3522 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
3523 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
3524 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
3525 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
3526 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
3527 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
3528 */
LL_DMA_GetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel)3529 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
3530 {
3531 uint32_t dma_base_addr = (uint32_t)DMAx;
3532 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
3533 }
3534
3535 /**
3536 * @brief Set hardware trigger.
3537 * @note This API is used for all available DMA channels.
3538 * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
3539 * @param DMAx DMAx Instance
3540 * @param Channel This parameter can be one of the following values:
3541 * @arg @ref LL_DMA_CHANNEL_0
3542 * @arg @ref LL_DMA_CHANNEL_1
3543 * @arg @ref LL_DMA_CHANNEL_2
3544 * @arg @ref LL_DMA_CHANNEL_3
3545 * @arg @ref LL_DMA_CHANNEL_4
3546 * @arg @ref LL_DMA_CHANNEL_5
3547 * @arg @ref LL_DMA_CHANNEL_6
3548 * @arg @ref LL_DMA_CHANNEL_7
3549 * @arg @ref LL_DMA_CHANNEL_8
3550 * @arg @ref LL_DMA_CHANNEL_9
3551 * @arg @ref LL_DMA_CHANNEL_10
3552 * @arg @ref LL_DMA_CHANNEL_11
3553 * @arg @ref LL_DMA_CHANNEL_12
3554 * @arg @ref LL_DMA_CHANNEL_13
3555 * @arg @ref LL_DMA_CHANNEL_14
3556 * @arg @ref LL_DMA_CHANNEL_15
3557 * @param Trigger This parameter can be one of the following values:
3558 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND
3559 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC
3560 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND
3561 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC
3562 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC_FLAG
3563 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC_FLAG
3564 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW_FLAG
3565 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC_FLAG
3566 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF_FLAG
3567 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT_FLAG
3568 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE_FLAG
3569 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT_FLAG
3570 * @arg @ref LL_HPDMA1_TRIGGER_LCD
3571 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG0
3572 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG1
3573 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG2
3574 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG3
3575 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_4
3576 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_3
3577 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_2
3578 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_1
3579 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF
3580 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF
3581 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF
3582 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF
3583 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF
3584 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF
3585 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF
3586 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF
3587 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF
3588 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF
3589 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF
3590 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF
3591 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF
3592 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF
3593 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF
3594 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF
3595 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF
3596 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF
3597 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF
3598 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF
3599 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF
3600 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF
3601 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF
3602 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF
3603 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF
3604 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF
3605 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF
3606 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF
3607 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF
3608 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF
3609 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF
3610 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF
3611 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF
3612 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF
3613 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF
3614 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF
3615 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF
3616 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF
3617 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF
3618 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF
3619 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF
3620 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF
3621 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF
3622 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF
3623 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF
3624 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF
3625 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF
3626 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
3627 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
3628 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
3629 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
3630 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
3631 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
3632 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
3633 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT
3634 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC
3635 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP
3636 * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
3637 * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
3638 * @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
3639 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
3640 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
3641 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
3642 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
3643 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
3644 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
3645 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
3646 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
3647 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
3648 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
3649 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
3650 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
3651 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
3652 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
3653 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
3654 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
3655 * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO
3656 * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2
3657 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
3658 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO
3659 * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO
3660 * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO
3661 * @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO
3662 * @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO
3663 * @arg @ref LL_GPDMA1_TRIGGER_TIM9_TRGO
3664 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
3665 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
3666 * @retval None.
3667 */
LL_DMA_SetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Trigger)3668 __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
3669 {
3670 uint32_t dma_base_addr = (uint32_t)DMAx;
3671 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
3672 (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
3673 }
3674
3675 /**
3676 * @brief Get hardware triggers.
3677 * @note This API is used for all available DMA channels.
3678 * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
3679 * @param DMAx DMAx Instance
3680 * @param Channel This parameter can be one of the following values:
3681 * @arg @ref LL_DMA_CHANNEL_0
3682 * @arg @ref LL_DMA_CHANNEL_1
3683 * @arg @ref LL_DMA_CHANNEL_2
3684 * @arg @ref LL_DMA_CHANNEL_3
3685 * @arg @ref LL_DMA_CHANNEL_4
3686 * @arg @ref LL_DMA_CHANNEL_5
3687 * @arg @ref LL_DMA_CHANNEL_6
3688 * @arg @ref LL_DMA_CHANNEL_7
3689 * @arg @ref LL_DMA_CHANNEL_8
3690 * @arg @ref LL_DMA_CHANNEL_9
3691 * @arg @ref LL_DMA_CHANNEL_10
3692 * @arg @ref LL_DMA_CHANNEL_11
3693 * @arg @ref LL_DMA_CHANNEL_12
3694 * @arg @ref LL_DMA_CHANNEL_13
3695 * @arg @ref LL_DMA_CHANNEL_14
3696 * @arg @ref LL_DMA_CHANNEL_15
3697 * @retval Returned value can be one of the following values:
3698 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND
3699 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC
3700 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND
3701 * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC
3702 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC_FLAG
3703 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC_FLAG
3704 * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW_FLAG
3705 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC_FLAG
3706 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF_FLAG
3707 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT_FLAG
3708 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE_FLAG
3709 * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT_FLAG
3710 * @arg @ref LL_HPDMA1_TRIGGER_LCD
3711 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG0
3712 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG1
3713 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG2
3714 * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG3
3715 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_4
3716 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_3
3717 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_2
3718 * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_1
3719 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF
3720 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF
3721 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF
3722 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF
3723 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF
3724 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF
3725 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF
3726 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF
3727 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF
3728 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF
3729 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF
3730 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF
3731 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF
3732 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF
3733 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF
3734 * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF
3735 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF
3736 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF
3737 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF
3738 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF
3739 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF
3740 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF
3741 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF
3742 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF
3743 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF
3744 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF
3745 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF
3746 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF
3747 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF
3748 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF
3749 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF
3750 * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF
3751 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF
3752 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF
3753 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF
3754 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF
3755 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF
3756 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF
3757 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF
3758 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF
3759 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF
3760 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF
3761 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF
3762 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF
3763 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF
3764 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF
3765 * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF
3766 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
3767 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
3768 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
3769 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
3770 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
3771 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
3772 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
3773 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT
3774 * @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC
3775 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP
3776 * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
3777 * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
3778 * @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
3779 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
3780 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
3781 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
3782 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
3783 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
3784 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
3785 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
3786 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
3787 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
3788 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
3789 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
3790 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
3791 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
3792 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
3793 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
3794 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
3795 * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO
3796 * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2
3797 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
3798 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO
3799 * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO
3800 * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO
3801 * @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO
3802 * @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO
3803 * @arg @ref LL_GPDMA1_TRIGGER_TIM9_TRGO
3804 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
3805 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
3806 */
LL_DMA_GetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel)3807 __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel)
3808 {
3809 uint32_t dma_base_addr = (uint32_t)DMAx;
3810 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3811 DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
3812 }
3813
3814 /**
3815 * @brief Set DMA transfer mode.
3816 * @note This API is used for all available DMA channels.
3817 * @rmtoll CTR2 PFREQ LL_DMA_SetTransferMode
3818 * @param DMAx DMAx Instance
3819 * @param Channel This parameter can be one of the following values:
3820 * @arg @ref LL_DMA_CHANNEL_0 (HW request peripheral flow control mode supported on GPDMA1)
3821 * @arg @ref LL_DMA_CHANNEL_15 (HW request peripheral flow control mode supported on GPDMA1 & HPDMA1)
3822 * @param Mode This parameter can be one of the following values:
3823 * @arg @ref LL_DMA_NORMAL
3824 * @arg @ref LL_DMA_PFCTRL
3825 * @retval None.
3826 */
LL_DMA_SetTransferMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)3827 __STATIC_INLINE void LL_DMA_SetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
3828 {
3829 uint32_t dma_base_addr = (uint32_t)DMAx;
3830 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_PFREQ,
3831 Mode & DMA_CTR2_PFREQ);
3832 }
3833
3834 /**
3835 * @brief Get DMA transfer mode.
3836 * @note This API is used for all available DMA channels.
3837 * @rmtoll CTR2 TRIGSEL LL_DMA_GetTransferMode
3838 * @param DMAx DMAx Instance
3839 * @param Channel This parameter can be one of the following values:
3840 * @arg @ref LL_DMA_CHANNEL_0 (HW request peripheral flow control mode supported on GPDMA1)
3841 * @arg @ref LL_DMA_CHANNEL_15 (HW request peripheral flow control mode supported on GPDMA1 & HPDMA1)
3842 * @retval Returned value can be one of the following values:
3843 * @arg @ref LL_DMA_NORMAL
3844 * @arg @ref LL_DMA_PFCTRL
3845 */
LL_DMA_GetTransferMode(const DMA_TypeDef * DMAx,uint32_t Channel)3846 __STATIC_INLINE uint32_t LL_DMA_GetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel)
3847 {
3848 uint32_t dma_base_addr = (uint32_t)DMAx;
3849 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3850 DMA_CTR2_PFREQ));
3851 }
3852
3853 /**
3854 * @brief Configure addresses update.
3855 * @note This API is used only for 2D addressing channels.
3856 * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n
3857 * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n
3858 * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n
3859 * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate
3860 * @param DMAx DMAx Instance
3861 * @param Channel This parameter can be one of the following values:
3862 * @arg @ref LL_DMA_CHANNEL_12
3863 * @arg @ref LL_DMA_CHANNEL_13
3864 * @arg @ref LL_DMA_CHANNEL_14
3865 * @arg @ref LL_DMA_CHANNEL_15
3866 * @param Configuration This parameter must be a combination of all the following values:
3867 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
3868 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
3869 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
3870 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
3871 *@retval None.
3872 */
LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)3873 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
3874 {
3875 uint32_t dma_base_addr = (uint32_t)DMAx;
3876 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
3877 DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration);
3878 }
3879
3880 /**
3881 * @brief Configure DMA Block number of data and repeat Count.
3882 * @note This API is used only for 2D addressing channels.
3883 * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n
3884 * CBR1 BRC LL_DMA_ConfigBlkCounters
3885 * @param DMAx DMAx Instance
3886 * @param Channel This parameter can be one of the following values:
3887 * @arg @ref LL_DMA_CHANNEL_12
3888 * @arg @ref LL_DMA_CHANNEL_13
3889 * @arg @ref LL_DMA_CHANNEL_14
3890 * @arg @ref LL_DMA_CHANNEL_15
3891 * @param BlkDataLength Block transfer length
3892 Value between 0 to 0x0000FFFF
3893 * @param BlkRptCount Block repeat counter
3894 * Value between 0 to 0x000007FF
3895 *@retval None.
3896 */
LL_DMA_ConfigBlkCounters(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength,uint32_t BlkRptCount)3897 __STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength,
3898 uint32_t BlkRptCount)
3899 {
3900 uint32_t dma_base_addr = (uint32_t)DMAx;
3901 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
3902 (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos)));
3903 }
3904
3905 /**
3906 * @brief Set block repeat destination address update.
3907 * @note This API is used only for 2D addressing channels.
3908 * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate
3909 * @param DMAx DMAx Instance
3910 * @param Channel This parameter can be one of the following values:
3911 * @arg @ref LL_DMA_CHANNEL_12
3912 * @arg @ref LL_DMA_CHANNEL_13
3913 * @arg @ref LL_DMA_CHANNEL_14
3914 * @arg @ref LL_DMA_CHANNEL_15
3915 * @param BlkRptDestAddrUpdate This parameter can be one of the following values:
3916 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
3917 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
3918 * @retval None.
3919 */
LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrUpdate)3920 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
3921 uint32_t BlkRptDestAddrUpdate)
3922 {
3923 uint32_t dma_base_addr = (uint32_t)DMAx;
3924 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC,
3925 BlkRptDestAddrUpdate);
3926 }
3927
3928 /**
3929 * @brief Get block repeat destination address update.
3930 * @note This API is used only for 2D addressing channels.
3931 * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate
3932 * @param DMAx DMAx Instance
3933 * @param Channel This parameter can be one of the following values:
3934 * @arg @ref LL_DMA_CHANNEL_12
3935 * @arg @ref LL_DMA_CHANNEL_13
3936 * @arg @ref LL_DMA_CHANNEL_14
3937 * @arg @ref LL_DMA_CHANNEL_15
3938 * @retval Returned value can be one of the following values:
3939 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
3940 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
3941 */
LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3942 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3943 {
3944 uint32_t dma_base_addr = (uint32_t)DMAx;
3945 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC));
3946 }
3947
3948 /**
3949 * @brief Set block repeat source address update.
3950 * @note This API is used only for 2D addressing channels.
3951 * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate
3952 * @param DMAx DMAx Instance
3953 * @param Channel This parameter can be one of the following values:
3954 * @arg @ref LL_DMA_CHANNEL_12
3955 * @arg @ref LL_DMA_CHANNEL_13
3956 * @arg @ref LL_DMA_CHANNEL_14
3957 * @arg @ref LL_DMA_CHANNEL_15
3958 * @param BlkRptSrcAddrUpdate This parameter can be one of the following values:
3959 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
3960 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
3961 * @retval None.
3962 */
LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrUpdate)3963 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
3964 uint32_t BlkRptSrcAddrUpdate)
3965 {
3966 uint32_t dma_base_addr = (uint32_t)DMAx;
3967 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC,
3968 BlkRptSrcAddrUpdate);
3969 }
3970
3971 /**
3972 * @brief Get block repeat source address update.
3973 * @note This API is used only for 2D addressing channels.
3974 * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate
3975 * @param DMAx DMAx Instance
3976 * @param Channel This parameter can be one of the following values:
3977 * @arg @ref LL_DMA_CHANNEL_12
3978 * @arg @ref LL_DMA_CHANNEL_13
3979 * @arg @ref LL_DMA_CHANNEL_14
3980 * @arg @ref LL_DMA_CHANNEL_15
3981 * @retval Returned value can be one of the following values:
3982 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
3983 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
3984 */
LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3985 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3986 {
3987 uint32_t dma_base_addr = (uint32_t)DMAx;
3988 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC));
3989 }
3990
3991 /**
3992 * @brief Set destination address update.
3993 * @note This API is used only for 2D addressing channels.
3994 * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate
3995 * @param DMAx DMAx Instance
3996 * @param Channel This parameter can be one of the following values:
3997 * @arg @ref LL_DMA_CHANNEL_12
3998 * @arg @ref LL_DMA_CHANNEL_13
3999 * @arg @ref LL_DMA_CHANNEL_14
4000 * @arg @ref LL_DMA_CHANNEL_15
4001 * @param DestAddrUpdate This parameter can be one of the following values:
4002 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
4003 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4004 * @retval None.
4005 */
LL_DMA_SetDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrUpdate)4006 __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate)
4007 {
4008 uint32_t dma_base_addr = (uint32_t)DMAx;
4009 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC,
4010 DestAddrUpdate);
4011 }
4012
4013 /**
4014 * @brief Get destination address update.
4015 * @note This API is used only for 2D addressing channels.
4016 * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate
4017 * @param DMAx DMAx Instance
4018 * @param Channel This parameter can be one of the following values:
4019 * @arg @ref LL_DMA_CHANNEL_12
4020 * @arg @ref LL_DMA_CHANNEL_13
4021 * @arg @ref LL_DMA_CHANNEL_14
4022 * @arg @ref LL_DMA_CHANNEL_15
4023 * @retval Returned value can be one of the following values:
4024 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
4025 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4026 */
LL_DMA_GetDestAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4027 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4028 {
4029 uint32_t dma_base_addr = (uint32_t)DMAx;
4030 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC));
4031 }
4032
4033 /**
4034 * @brief Set source address update.
4035 * @note This API is used only for 2D addressing channels.
4036 * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate
4037 * @param DMAx DMAx Instance
4038 * @param Channel This parameter can be one of the following values:
4039 * @arg @ref LL_DMA_CHANNEL_12
4040 * @arg @ref LL_DMA_CHANNEL_13
4041 * @arg @ref LL_DMA_CHANNEL_14
4042 * @arg @ref LL_DMA_CHANNEL_15
4043 * @param SrcAddrUpdate This parameter can be one of the following values:
4044 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
4045 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4046 * @retval None.
4047 */
LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrUpdate)4048 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate)
4049 {
4050 uint32_t dma_base_addr = (uint32_t)DMAx;
4051 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC,
4052 SrcAddrUpdate);
4053 }
4054
4055 /**
4056 * @brief Get source address update.
4057 * @note This API is used only for 2D addressing channels.
4058 * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate
4059 * @param DMAx DMAx Instance
4060 * @param Channel This parameter can be one of the following values:
4061 * @arg @ref LL_DMA_CHANNEL_12
4062 * @arg @ref LL_DMA_CHANNEL_13
4063 * @arg @ref LL_DMA_CHANNEL_14
4064 * @arg @ref LL_DMA_CHANNEL_15
4065 * @retval Returned value can be one of the following values:
4066 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
4067 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4068 */
LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4069 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4070 {
4071 uint32_t dma_base_addr = (uint32_t)DMAx;
4072 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC));
4073 }
4074
4075 /**
4076 * @brief Set block repeat count.
4077 * @note This API is used only for 2D addressing channels.
4078 * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount
4079 * @param DMAx DMAx Instance
4080 * @param Channel This parameter can be one of the following values:
4081 * @arg @ref LL_DMA_CHANNEL_12
4082 * @arg @ref LL_DMA_CHANNEL_13
4083 * @arg @ref LL_DMA_CHANNEL_14
4084 * @arg @ref LL_DMA_CHANNEL_15
4085 * @param BlkRptCount Block repeat counter
4086 * Value between 0 to 0x000007FF
4087 * @retval None.
4088 */
LL_DMA_SetBlkRptCount(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptCount)4089 __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount)
4090 {
4091 uint32_t dma_base_addr = (uint32_t)DMAx;
4092 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC,
4093 (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
4094 }
4095
4096 /**
4097 * @brief Get block repeat count.
4098 * @note This API is used only for 2D addressing channels.
4099 * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount
4100 * @param DMAx DMAx Instance
4101 * @param Channel This parameter can be one of the following values:
4102 * @arg @ref LL_DMA_CHANNEL_12
4103 * @arg @ref LL_DMA_CHANNEL_13
4104 * @arg @ref LL_DMA_CHANNEL_14
4105 * @arg @ref LL_DMA_CHANNEL_15
4106 * @retval Between 0 to 0x000007FF
4107 */
LL_DMA_GetBlkRptCount(const DMA_TypeDef * DMAx,uint32_t Channel)4108 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel)
4109 {
4110 uint32_t dma_base_addr = (uint32_t)DMAx;
4111 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4112 DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos);
4113 }
4114
4115 /**
4116 * @brief Set block data length in bytes to transfer.
4117 * @note This API is used for all available DMA channels.
4118 * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
4119 * @param DMAx DMAx Instance
4120 * @param Channel This parameter can be one of the following values:
4121 * @arg @ref LL_DMA_CHANNEL_0
4122 * @arg @ref LL_DMA_CHANNEL_1
4123 * @arg @ref LL_DMA_CHANNEL_2
4124 * @arg @ref LL_DMA_CHANNEL_3
4125 * @arg @ref LL_DMA_CHANNEL_4
4126 * @arg @ref LL_DMA_CHANNEL_5
4127 * @arg @ref LL_DMA_CHANNEL_6
4128 * @arg @ref LL_DMA_CHANNEL_7
4129 * @arg @ref LL_DMA_CHANNEL_8
4130 * @arg @ref LL_DMA_CHANNEL_9
4131 * @arg @ref LL_DMA_CHANNEL_10
4132 * @arg @ref LL_DMA_CHANNEL_11
4133 * @arg @ref LL_DMA_CHANNEL_12
4134 * @arg @ref LL_DMA_CHANNEL_13
4135 * @arg @ref LL_DMA_CHANNEL_14
4136 * @arg @ref LL_DMA_CHANNEL_15
4137 * @param BlkDataLength Between 0 to 0x0000FFFF
4138 * @retval None.
4139 */
LL_DMA_SetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength)4140 __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
4141 {
4142 uint32_t dma_base_addr = (uint32_t)DMAx;
4143 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
4144 BlkDataLength);
4145 }
4146
4147 /**
4148 * @brief Get block data length in bytes to transfer.
4149 * @note This API is used for all available DMA channels.
4150 * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
4151 * @param DMAx DMAx Instance
4152 * @param Channel This parameter can be one of the following values:
4153 * @arg @ref LL_DMA_CHANNEL_0
4154 * @arg @ref LL_DMA_CHANNEL_1
4155 * @arg @ref LL_DMA_CHANNEL_2
4156 * @arg @ref LL_DMA_CHANNEL_3
4157 * @arg @ref LL_DMA_CHANNEL_4
4158 * @arg @ref LL_DMA_CHANNEL_5
4159 * @arg @ref LL_DMA_CHANNEL_6
4160 * @arg @ref LL_DMA_CHANNEL_7
4161 * @arg @ref LL_DMA_CHANNEL_8
4162 * @arg @ref LL_DMA_CHANNEL_9
4163 * @arg @ref LL_DMA_CHANNEL_10
4164 * @arg @ref LL_DMA_CHANNEL_11
4165 * @arg @ref LL_DMA_CHANNEL_12
4166 * @arg @ref LL_DMA_CHANNEL_13
4167 * @arg @ref LL_DMA_CHANNEL_14
4168 * @arg @ref LL_DMA_CHANNEL_15
4169 * @retval Between 0 to 0x0000FFFF
4170 */
LL_DMA_GetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel)4171 __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
4172 {
4173 uint32_t dma_base_addr = (uint32_t)DMAx;
4174 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
4175 }
4176
4177 /**
4178 * @brief Configure the source and destination addresses.
4179 * @note This API is used for all available DMA channels.
4180 * @note This API must not be called when the DMA Channel is enabled.
4181 * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
4182 * CDAR DA LL_DMA_ConfigAddresses
4183 * @param DMAx DMAx Instance
4184 * @param Channel This parameter can be one of the following values:
4185 * @arg @ref LL_DMA_CHANNEL_0
4186 * @arg @ref LL_DMA_CHANNEL_1
4187 * @arg @ref LL_DMA_CHANNEL_2
4188 * @arg @ref LL_DMA_CHANNEL_3
4189 * @arg @ref LL_DMA_CHANNEL_4
4190 * @arg @ref LL_DMA_CHANNEL_5
4191 * @arg @ref LL_DMA_CHANNEL_6
4192 * @arg @ref LL_DMA_CHANNEL_7
4193 * @arg @ref LL_DMA_CHANNEL_8
4194 * @arg @ref LL_DMA_CHANNEL_9
4195 * @arg @ref LL_DMA_CHANNEL_10
4196 * @arg @ref LL_DMA_CHANNEL_11
4197 * @arg @ref LL_DMA_CHANNEL_12
4198 * @arg @ref LL_DMA_CHANNEL_13
4199 * @arg @ref LL_DMA_CHANNEL_14
4200 * @arg @ref LL_DMA_CHANNEL_15
4201 * @param SrcAddress Between 0 to 0xFFFFFFFF
4202 * @param DestAddress Between 0 to 0xFFFFFFFF
4203 * @retval None.
4204 */
LL_DMA_ConfigAddresses(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DestAddress)4205 __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
4206 DestAddress)
4207 {
4208 uint32_t dma_base_addr = (uint32_t)DMAx;
4209 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
4210 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
4211 }
4212
4213 /**
4214 * @brief Set source address.
4215 * @note This API is used for all available DMA channels.
4216 * @rmtoll CSAR SA LL_DMA_SetSrcAddress
4217 * @param DMAx DMAx Instance
4218 * @param Channel This parameter can be one of the following values:
4219 * @arg @ref LL_DMA_CHANNEL_0
4220 * @arg @ref LL_DMA_CHANNEL_1
4221 * @arg @ref LL_DMA_CHANNEL_2
4222 * @arg @ref LL_DMA_CHANNEL_3
4223 * @arg @ref LL_DMA_CHANNEL_4
4224 * @arg @ref LL_DMA_CHANNEL_5
4225 * @arg @ref LL_DMA_CHANNEL_6
4226 * @arg @ref LL_DMA_CHANNEL_7
4227 * @arg @ref LL_DMA_CHANNEL_8
4228 * @arg @ref LL_DMA_CHANNEL_9
4229 * @arg @ref LL_DMA_CHANNEL_10
4230 * @arg @ref LL_DMA_CHANNEL_11
4231 * @arg @ref LL_DMA_CHANNEL_12
4232 * @arg @ref LL_DMA_CHANNEL_13
4233 * @arg @ref LL_DMA_CHANNEL_14
4234 * @arg @ref LL_DMA_CHANNEL_15
4235 * @param SrcAddress Between 0 to 0xFFFFFFFF
4236 * @retval None.
4237 */
LL_DMA_SetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress)4238 __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
4239 {
4240 uint32_t dma_base_addr = (uint32_t)DMAx;
4241 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
4242 }
4243
4244 /**
4245 * @brief Get source address.
4246 * @note This API is used for all available DMA channels.
4247 * @rmtoll CSAR SA LL_DMA_GetSrcAddress
4248 * @param DMAx DMAx Instance
4249 * @param Channel This parameter can be one of the following values:
4250 * @arg @ref LL_DMA_CHANNEL_0
4251 * @arg @ref LL_DMA_CHANNEL_1
4252 * @arg @ref LL_DMA_CHANNEL_2
4253 * @arg @ref LL_DMA_CHANNEL_3
4254 * @arg @ref LL_DMA_CHANNEL_4
4255 * @arg @ref LL_DMA_CHANNEL_5
4256 * @arg @ref LL_DMA_CHANNEL_6
4257 * @arg @ref LL_DMA_CHANNEL_7
4258 * @arg @ref LL_DMA_CHANNEL_8
4259 * @arg @ref LL_DMA_CHANNEL_9
4260 * @arg @ref LL_DMA_CHANNEL_10
4261 * @arg @ref LL_DMA_CHANNEL_11
4262 * @arg @ref LL_DMA_CHANNEL_12
4263 * @arg @ref LL_DMA_CHANNEL_13
4264 * @arg @ref LL_DMA_CHANNEL_14
4265 * @arg @ref LL_DMA_CHANNEL_15
4266 * @retval Between 0 to 0xFFFFFFFF
4267 */
LL_DMA_GetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel)4268 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
4269 {
4270 uint32_t dma_base_addr = (uint32_t)DMAx;
4271 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
4272 }
4273
4274 /**
4275 * @brief Set destination address.
4276 * @note This API is used for all available DMA channels.
4277 * @rmtoll CDAR DA LL_DMA_SetDestAddress
4278 * @param DMAx DMAx Instance
4279 * @param Channel This parameter can be one of the following values:
4280 * @arg @ref LL_DMA_CHANNEL_0
4281 * @arg @ref LL_DMA_CHANNEL_1
4282 * @arg @ref LL_DMA_CHANNEL_2
4283 * @arg @ref LL_DMA_CHANNEL_3
4284 * @arg @ref LL_DMA_CHANNEL_4
4285 * @arg @ref LL_DMA_CHANNEL_5
4286 * @arg @ref LL_DMA_CHANNEL_6
4287 * @arg @ref LL_DMA_CHANNEL_7
4288 * @arg @ref LL_DMA_CHANNEL_8
4289 * @arg @ref LL_DMA_CHANNEL_9
4290 * @arg @ref LL_DMA_CHANNEL_10
4291 * @arg @ref LL_DMA_CHANNEL_11
4292 * @arg @ref LL_DMA_CHANNEL_12
4293 * @arg @ref LL_DMA_CHANNEL_13
4294 * @arg @ref LL_DMA_CHANNEL_14
4295 * @arg @ref LL_DMA_CHANNEL_15
4296 * @param DestAddress Between 0 to 0xFFFFFFFF
4297 * @retval None.
4298 */
LL_DMA_SetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddress)4299 __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
4300 {
4301 uint32_t dma_base_addr = (uint32_t)DMAx;
4302 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
4303 }
4304
4305 /**
4306 * @brief Get destination address.
4307 * @note This API is used for all available DMA channels.
4308 * @rmtoll CDAR DA LL_DMA_GetDestAddress
4309 * @param DMAx DMAx Instance
4310 * @param Channel This parameter can be one of the following values:
4311 * @arg @ref LL_DMA_CHANNEL_0
4312 * @arg @ref LL_DMA_CHANNEL_1
4313 * @arg @ref LL_DMA_CHANNEL_2
4314 * @arg @ref LL_DMA_CHANNEL_3
4315 * @arg @ref LL_DMA_CHANNEL_4
4316 * @arg @ref LL_DMA_CHANNEL_5
4317 * @arg @ref LL_DMA_CHANNEL_6
4318 * @arg @ref LL_DMA_CHANNEL_7
4319 * @arg @ref LL_DMA_CHANNEL_8
4320 * @arg @ref LL_DMA_CHANNEL_9
4321 * @arg @ref LL_DMA_CHANNEL_10
4322 * @arg @ref LL_DMA_CHANNEL_11
4323 * @arg @ref LL_DMA_CHANNEL_12
4324 * @arg @ref LL_DMA_CHANNEL_13
4325 * @arg @ref LL_DMA_CHANNEL_14
4326 * @arg @ref LL_DMA_CHANNEL_15
4327 * @retval Between 0 to 0xFFFFFFFF
4328 */
LL_DMA_GetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel)4329 __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
4330 {
4331 uint32_t dma_base_addr = (uint32_t)DMAx;
4332 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
4333 }
4334
4335 /**
4336 * @brief Configure source and destination addresses offset.
4337 * @note This API is used only for 2D addressing channels.
4338 * @note This API must not be called when the DMA Channel is enabled.
4339 * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n
4340 * CTR3 SAO LL_DMA_ConfigAddrUpdateValue
4341 * @param DMAx DMAx Instance
4342 * @param Channel This parameter can be one of the following values:
4343 * @arg @ref LL_DMA_CHANNEL_12
4344 * @arg @ref LL_DMA_CHANNEL_13
4345 * @arg @ref LL_DMA_CHANNEL_14
4346 * @arg @ref LL_DMA_CHANNEL_15
4347 * @param DestAddrOffset Between 0 to 0x00001FFF
4348 * @param SrcAddrOffset Between 0 to 0x00001FFF
4349 * @retval None.
4350 */
LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset,uint32_t DestAddrOffset)4351 __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset,
4352 uint32_t DestAddrOffset)
4353 {
4354 uint32_t dma_base_addr = (uint32_t)DMAx;
4355 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
4356 (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
4357 }
4358
4359 /**
4360 * @brief Set destination address offset.
4361 * @note This API is used only for 2D addressing channels.
4362 * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue
4363 * @param DMAx DMAx Instance
4364 * @param Channel This parameter can be one of the following values:
4365 * @arg @ref LL_DMA_CHANNEL_12
4366 * @arg @ref LL_DMA_CHANNEL_13
4367 * @arg @ref LL_DMA_CHANNEL_14
4368 * @arg @ref LL_DMA_CHANNEL_15
4369 * @param DestAddrOffset Between 0 to 0x00001FFF
4370 * @retval None.
4371 */
LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrOffset)4372 __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset)
4373 {
4374 uint32_t dma_base_addr = (uint32_t)DMAx;
4375 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO,
4376 ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
4377 }
4378
4379 /**
4380 * @brief Get destination address offset.
4381 * @note This API is used only for 2D addressing channels.
4382 * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue
4383 * @param DMAx DMAx Instance
4384 * @param Channel This parameter can be one of the following values:
4385 * @arg @ref LL_DMA_CHANNEL_12
4386 * @arg @ref LL_DMA_CHANNEL_13
4387 * @arg @ref LL_DMA_CHANNEL_14
4388 * @arg @ref LL_DMA_CHANNEL_15
4389 * @retval Between 0 to 0x00001FFF
4390 */
LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4391 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4392 {
4393 uint32_t dma_base_addr = (uint32_t)DMAx;
4394 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
4395 DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
4396 }
4397
4398 /**
4399 * @brief Set source address offset.
4400 * @note This API is used only for 2D addressing channels.
4401 * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue
4402 * @param DMAx DMAx Instance
4403 * @param Channel This parameter can be one of the following values:
4404 * @arg @ref LL_DMA_CHANNEL_12
4405 * @arg @ref LL_DMA_CHANNEL_13
4406 * @arg @ref LL_DMA_CHANNEL_14
4407 * @arg @ref LL_DMA_CHANNEL_15
4408 * @param SrcAddrOffset Between 0 to 0x00001FFF
4409 * @retval None.
4410 */
LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset)4411 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset)
4412 {
4413 uint32_t dma_base_addr = (uint32_t)DMAx;
4414 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO,
4415 SrcAddrOffset & DMA_CTR3_SAO);
4416 }
4417
4418 /**
4419 * @brief Get source address offset.
4420 * @note This API is used only for 2D addressing channels.
4421 * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue
4422 * @param DMAx DMAx Instance
4423 * @param Channel This parameter can be one of the following values:
4424 * @arg @ref LL_DMA_CHANNEL_12
4425 * @arg @ref LL_DMA_CHANNEL_13
4426 * @arg @ref LL_DMA_CHANNEL_14
4427 * @arg @ref LL_DMA_CHANNEL_15
4428 * @retval Between 0 to 0x00001FFF
4429 */
LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4430 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4431 {
4432 uint32_t dma_base_addr = (uint32_t)DMAx;
4433 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO));
4434 }
4435
4436 /**
4437 * @brief Configure the block repeated source and destination addresses offset.
4438 * @note This API is used only for 2D addressing channels.
4439 * @note This API must not be called when the DMA Channel is enabled.
4440 * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n
4441 * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue
4442 * @param DMAx DMAx Instance
4443 * @param Channel This parameter can be one of the following values:
4444 * @arg @ref LL_DMA_CHANNEL_12
4445 * @arg @ref LL_DMA_CHANNEL_13
4446 * @arg @ref LL_DMA_CHANNEL_14
4447 * @arg @ref LL_DMA_CHANNEL_15
4448 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
4449 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
4450 * @retval None.
4451 */
LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset,uint32_t BlkRptDestAddrOffset)4452 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4453 uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset)
4454 {
4455 uint32_t dma_base_addr = (uint32_t)DMAx;
4456 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
4457 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO));
4458 }
4459
4460 /**
4461 * @brief Set block repeated destination address offset.
4462 * @note This API is used only for 2D addressing channels.
4463 * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue
4464 * @param DMAx DMAx Instance
4465 * @param Channel This parameter can be one of the following values:
4466 * @arg @ref LL_DMA_CHANNEL_12
4467 * @arg @ref LL_DMA_CHANNEL_13
4468 * @arg @ref LL_DMA_CHANNEL_14
4469 * @arg @ref LL_DMA_CHANNEL_15
4470 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
4471 * @retval None.
4472 */
LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrOffset)4473 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4474 uint32_t BlkRptDestAddrOffset)
4475 {
4476 uint32_t dma_base_addr = (uint32_t)DMAx;
4477 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO,
4478 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO));
4479 }
4480
4481 /**
4482 * @brief Get block repeated destination address offset.
4483 * @note This API is used only for 2D addressing channels.
4484 * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue
4485 * @param DMAx DMAx Instance
4486 * @param Channel This parameter can be one of the following values:
4487 * @arg @ref LL_DMA_CHANNEL_12
4488 * @arg @ref LL_DMA_CHANNEL_13
4489 * @arg @ref LL_DMA_CHANNEL_14
4490 * @arg @ref LL_DMA_CHANNEL_15
4491 * @retval Between 0 to 0x0000FFFF.
4492 */
LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4493 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4494 {
4495 uint32_t dma_base_addr = (uint32_t)DMAx;
4496 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
4497 DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
4498 }
4499
4500 /**
4501 * @brief Set block repeated source address offset.
4502 * @note This API is used only for 2D addressing channels.
4503 * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue
4504 * @param DMAx DMAx Instance
4505 * @param Channel This parameter can be one of the following values:
4506 * @arg @ref LL_DMA_CHANNEL_12
4507 * @arg @ref LL_DMA_CHANNEL_13
4508 * @arg @ref LL_DMA_CHANNEL_14
4509 * @arg @ref LL_DMA_CHANNEL_15
4510 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
4511 * @retval None.
4512 */
LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset)4513 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
4514 uint32_t BlkRptSrcAddrOffset)
4515 {
4516 uint32_t dma_base_addr = (uint32_t)DMAx;
4517 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO,
4518 BlkRptSrcAddrOffset);
4519 }
4520
4521 /**
4522 * @brief Get block repeated source address offset.
4523 * @note This API is used only for 2D addressing channels.
4524 * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue
4525 * @param DMAx DMAx Instance
4526 * @param Channel This parameter can be one of the following values:
4527 * @arg @ref LL_DMA_CHANNEL_12
4528 * @arg @ref LL_DMA_CHANNEL_13
4529 * @arg @ref LL_DMA_CHANNEL_14
4530 * @arg @ref LL_DMA_CHANNEL_15
4531 * @retval Between 0 to 0x0000FFFF
4532 */
LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef * DMAx,uint32_t Channel)4533 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
4534 {
4535 uint32_t dma_base_addr = (uint32_t)DMAx;
4536 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO));
4537 }
4538
4539 /**
4540 * @brief Configure registers update and node address offset during the link transfer.
4541 * @note This API is used for all available DMA channels.
4542 * For linear addressing channels, UT3 and UB2 fields are discarded.
4543 * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n
4544 * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n
4545 * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n
4546 * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n
4547 * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n
4548 * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n
4549 * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n
4550 * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate
4551 * @param DMAx DMAx Instance
4552 * @param Channel This parameter can be one of the following values:
4553 * @arg @ref LL_DMA_CHANNEL_0
4554 * @arg @ref LL_DMA_CHANNEL_1
4555 * @arg @ref LL_DMA_CHANNEL_2
4556 * @arg @ref LL_DMA_CHANNEL_3
4557 * @arg @ref LL_DMA_CHANNEL_4
4558 * @arg @ref LL_DMA_CHANNEL_5
4559 * @arg @ref LL_DMA_CHANNEL_6
4560 * @arg @ref LL_DMA_CHANNEL_7
4561 * @arg @ref LL_DMA_CHANNEL_8
4562 * @arg @ref LL_DMA_CHANNEL_9
4563 * @arg @ref LL_DMA_CHANNEL_10
4564 * @arg @ref LL_DMA_CHANNEL_11
4565 * @arg @ref LL_DMA_CHANNEL_12
4566 * @arg @ref LL_DMA_CHANNEL_13
4567 * @arg @ref LL_DMA_CHANNEL_14
4568 * @arg @ref LL_DMA_CHANNEL_15
4569 * @param RegistersUpdate This parameter must be a combination of all the following values:
4570 * @arg @ref LL_DMA_UPDATE_CTR1
4571 * @arg @ref LL_DMA_UPDATE_CTR2
4572 * @arg @ref LL_DMA_UPDATE_CBR1
4573 * @arg @ref LL_DMA_UPDATE_CSAR
4574 * @arg @ref LL_DMA_UPDATE_CDAR
4575 * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels)
4576 * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels)
4577 * @arg @ref LL_DMA_UPDATE_CLLR
4578 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
4579 * @retval None.
4580 */
LL_DMA_ConfigLinkUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t RegistersUpdate,uint32_t LinkedListAddrOffset)4581 __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
4582 uint32_t LinkedListAddrOffset)
4583 {
4584 uint32_t dma_base_addr = (uint32_t)DMAx;
4585 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
4586 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \
4587 DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
4588 }
4589
4590 /**
4591 * @brief Enable CTR1 update during the link transfer.
4592 * @note This API is used for all available DMA channels.
4593 * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
4594 * @param DMAx DMAx Instance
4595 * @param Channel This parameter can be one of the following values:
4596 * @arg @ref LL_DMA_CHANNEL_0
4597 * @arg @ref LL_DMA_CHANNEL_1
4598 * @arg @ref LL_DMA_CHANNEL_2
4599 * @arg @ref LL_DMA_CHANNEL_3
4600 * @arg @ref LL_DMA_CHANNEL_4
4601 * @arg @ref LL_DMA_CHANNEL_5
4602 * @arg @ref LL_DMA_CHANNEL_6
4603 * @arg @ref LL_DMA_CHANNEL_7
4604 * @arg @ref LL_DMA_CHANNEL_8
4605 * @arg @ref LL_DMA_CHANNEL_9
4606 * @arg @ref LL_DMA_CHANNEL_10
4607 * @arg @ref LL_DMA_CHANNEL_11
4608 * @arg @ref LL_DMA_CHANNEL_12
4609 * @arg @ref LL_DMA_CHANNEL_13
4610 * @arg @ref LL_DMA_CHANNEL_14
4611 * @arg @ref LL_DMA_CHANNEL_15
4612 * @retval None.
4613 */
LL_DMA_EnableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4614 __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4615 {
4616 uint32_t dma_base_addr = (uint32_t)DMAx;
4617 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
4618 }
4619
4620 /**
4621 * @brief Disable CTR1 update during the link transfer.
4622 * @note This API is used for all available DMA channels.
4623 * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
4624 * @param DMAx DMAx Instance
4625 * @param Channel This parameter can be one of the following values:
4626 * @arg @ref LL_DMA_CHANNEL_0
4627 * @arg @ref LL_DMA_CHANNEL_1
4628 * @arg @ref LL_DMA_CHANNEL_2
4629 * @arg @ref LL_DMA_CHANNEL_3
4630 * @arg @ref LL_DMA_CHANNEL_4
4631 * @arg @ref LL_DMA_CHANNEL_5
4632 * @arg @ref LL_DMA_CHANNEL_6
4633 * @arg @ref LL_DMA_CHANNEL_7
4634 * @arg @ref LL_DMA_CHANNEL_8
4635 * @arg @ref LL_DMA_CHANNEL_9
4636 * @arg @ref LL_DMA_CHANNEL_10
4637 * @arg @ref LL_DMA_CHANNEL_11
4638 * @arg @ref LL_DMA_CHANNEL_12
4639 * @arg @ref LL_DMA_CHANNEL_13
4640 * @arg @ref LL_DMA_CHANNEL_14
4641 * @arg @ref LL_DMA_CHANNEL_15
4642 * @retval None.
4643 */
LL_DMA_DisableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4644 __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4645 {
4646 uint32_t dma_base_addr = (uint32_t)DMAx;
4647 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
4648 }
4649
4650 /**
4651 * @brief Check if CTR1 update during the link transfer is enabled.
4652 * @note This API is used for all available DMA channels.
4653 * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
4654 * @param DMAx DMAx Instance
4655 * @param Channel This parameter can be one of the following values:
4656 * @arg @ref LL_DMA_CHANNEL_0
4657 * @arg @ref LL_DMA_CHANNEL_1
4658 * @arg @ref LL_DMA_CHANNEL_2
4659 * @arg @ref LL_DMA_CHANNEL_3
4660 * @arg @ref LL_DMA_CHANNEL_4
4661 * @arg @ref LL_DMA_CHANNEL_5
4662 * @arg @ref LL_DMA_CHANNEL_6
4663 * @arg @ref LL_DMA_CHANNEL_7
4664 * @arg @ref LL_DMA_CHANNEL_8
4665 * @arg @ref LL_DMA_CHANNEL_9
4666 * @arg @ref LL_DMA_CHANNEL_10
4667 * @arg @ref LL_DMA_CHANNEL_11
4668 * @arg @ref LL_DMA_CHANNEL_12
4669 * @arg @ref LL_DMA_CHANNEL_13
4670 * @arg @ref LL_DMA_CHANNEL_14
4671 * @arg @ref LL_DMA_CHANNEL_15
4672 * @retval State of bit (1 or 0).
4673 */
LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4674 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4675 {
4676 uint32_t dma_base_addr = (uint32_t)DMAx;
4677 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
4678 == (DMA_CLLR_UT1)) ? 1UL : 0UL);
4679 }
4680
4681 /**
4682 * @brief Enable CTR2 update during the link transfer.
4683 * @note This API is used for all available DMA channels.
4684 * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
4685 * @param DMAx DMAx Instance
4686 * @param Channel This parameter can be one of the following values:
4687 * @arg @ref LL_DMA_CHANNEL_0
4688 * @arg @ref LL_DMA_CHANNEL_1
4689 * @arg @ref LL_DMA_CHANNEL_2
4690 * @arg @ref LL_DMA_CHANNEL_3
4691 * @arg @ref LL_DMA_CHANNEL_4
4692 * @arg @ref LL_DMA_CHANNEL_5
4693 * @arg @ref LL_DMA_CHANNEL_6
4694 * @arg @ref LL_DMA_CHANNEL_7
4695 * @arg @ref LL_DMA_CHANNEL_8
4696 * @arg @ref LL_DMA_CHANNEL_9
4697 * @arg @ref LL_DMA_CHANNEL_10
4698 * @arg @ref LL_DMA_CHANNEL_11
4699 * @arg @ref LL_DMA_CHANNEL_12
4700 * @arg @ref LL_DMA_CHANNEL_13
4701 * @arg @ref LL_DMA_CHANNEL_14
4702 * @arg @ref LL_DMA_CHANNEL_15
4703 * @retval None.
4704 */
LL_DMA_EnableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4705 __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4706 {
4707 uint32_t dma_base_addr = (uint32_t)DMAx;
4708 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
4709 }
4710
4711 /**
4712 * @brief Disable CTR2 update during the link transfer.
4713 * @note This API is used for all available DMA channels.
4714 * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
4715 * @param DMAx DMAx Instance
4716 * @param Channel This parameter can be one of the following values:
4717 * @arg @ref LL_DMA_CHANNEL_0
4718 * @arg @ref LL_DMA_CHANNEL_1
4719 * @arg @ref LL_DMA_CHANNEL_2
4720 * @arg @ref LL_DMA_CHANNEL_3
4721 * @arg @ref LL_DMA_CHANNEL_4
4722 * @arg @ref LL_DMA_CHANNEL_5
4723 * @arg @ref LL_DMA_CHANNEL_6
4724 * @arg @ref LL_DMA_CHANNEL_7
4725 * @arg @ref LL_DMA_CHANNEL_8
4726 * @arg @ref LL_DMA_CHANNEL_9
4727 * @arg @ref LL_DMA_CHANNEL_10
4728 * @arg @ref LL_DMA_CHANNEL_11
4729 * @arg @ref LL_DMA_CHANNEL_12
4730 * @arg @ref LL_DMA_CHANNEL_13
4731 * @arg @ref LL_DMA_CHANNEL_14
4732 * @arg @ref LL_DMA_CHANNEL_15
4733 * @retval None.
4734 */
LL_DMA_DisableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4735 __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4736 {
4737 uint32_t dma_base_addr = (uint32_t)DMAx;
4738 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
4739 }
4740
4741 /**
4742 * @brief Check if CTR2 update during the link transfer is enabled.
4743 * @note This API is used for all available DMA channels.
4744 * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
4745 * @param DMAx DMAx Instance
4746 * @param Channel This parameter can be one of the following values:
4747 * @arg @ref LL_DMA_CHANNEL_0
4748 * @arg @ref LL_DMA_CHANNEL_1
4749 * @arg @ref LL_DMA_CHANNEL_2
4750 * @arg @ref LL_DMA_CHANNEL_3
4751 * @arg @ref LL_DMA_CHANNEL_4
4752 * @arg @ref LL_DMA_CHANNEL_5
4753 * @arg @ref LL_DMA_CHANNEL_6
4754 * @arg @ref LL_DMA_CHANNEL_7
4755 * @arg @ref LL_DMA_CHANNEL_8
4756 * @arg @ref LL_DMA_CHANNEL_9
4757 * @arg @ref LL_DMA_CHANNEL_10
4758 * @arg @ref LL_DMA_CHANNEL_11
4759 * @arg @ref LL_DMA_CHANNEL_12
4760 * @arg @ref LL_DMA_CHANNEL_13
4761 * @arg @ref LL_DMA_CHANNEL_14
4762 * @arg @ref LL_DMA_CHANNEL_15
4763 * @retval State of bit (1 or 0).
4764 */
LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)4765 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4766 {
4767 uint32_t dma_base_addr = (uint32_t)DMAx;
4768 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
4769 == (DMA_CLLR_UT2)) ? 1UL : 0UL);
4770 }
4771
4772 /**
4773 * @brief Enable CBR1 update during the link transfer.
4774 * @note This API is used for all available DMA channels.
4775 * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
4776 * @param DMAx DMAx Instance
4777 * @param Channel This parameter can be one of the following values:
4778 * @arg @ref LL_DMA_CHANNEL_0
4779 * @arg @ref LL_DMA_CHANNEL_1
4780 * @arg @ref LL_DMA_CHANNEL_2
4781 * @arg @ref LL_DMA_CHANNEL_3
4782 * @arg @ref LL_DMA_CHANNEL_4
4783 * @arg @ref LL_DMA_CHANNEL_5
4784 * @arg @ref LL_DMA_CHANNEL_6
4785 * @arg @ref LL_DMA_CHANNEL_7
4786 * @arg @ref LL_DMA_CHANNEL_8
4787 * @arg @ref LL_DMA_CHANNEL_9
4788 * @arg @ref LL_DMA_CHANNEL_10
4789 * @arg @ref LL_DMA_CHANNEL_11
4790 * @arg @ref LL_DMA_CHANNEL_12
4791 * @arg @ref LL_DMA_CHANNEL_13
4792 * @arg @ref LL_DMA_CHANNEL_14
4793 * @arg @ref LL_DMA_CHANNEL_15
4794 * @retval None.
4795 */
LL_DMA_EnableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4796 __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4797 {
4798 uint32_t dma_base_addr = (uint32_t)DMAx;
4799 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
4800 }
4801
4802 /**
4803 * @brief Disable CBR1 update during the link transfer.
4804 * @note This API is used for all available DMA channels.
4805 * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
4806 * @param DMAx DMAx Instance
4807 * @param Channel This parameter can be one of the following values:
4808 * @arg @ref LL_DMA_CHANNEL_0
4809 * @arg @ref LL_DMA_CHANNEL_1
4810 * @arg @ref LL_DMA_CHANNEL_2
4811 * @arg @ref LL_DMA_CHANNEL_3
4812 * @arg @ref LL_DMA_CHANNEL_4
4813 * @arg @ref LL_DMA_CHANNEL_5
4814 * @arg @ref LL_DMA_CHANNEL_6
4815 * @arg @ref LL_DMA_CHANNEL_7
4816 * @arg @ref LL_DMA_CHANNEL_8
4817 * @arg @ref LL_DMA_CHANNEL_9
4818 * @arg @ref LL_DMA_CHANNEL_10
4819 * @arg @ref LL_DMA_CHANNEL_11
4820 * @arg @ref LL_DMA_CHANNEL_12
4821 * @arg @ref LL_DMA_CHANNEL_13
4822 * @arg @ref LL_DMA_CHANNEL_14
4823 * @arg @ref LL_DMA_CHANNEL_15
4824 * @retval None.
4825 */
LL_DMA_DisableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4826 __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4827 {
4828 uint32_t dma_base_addr = (uint32_t)DMAx;
4829 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
4830 }
4831
4832 /**
4833 * @brief Check if CBR1 update during the link transfer is enabled.
4834 * @note This API is used for all available DMA channels.
4835 * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
4836 * @param DMAx DMAx Instance
4837 * @param Channel This parameter can be one of the following values:
4838 * @arg @ref LL_DMA_CHANNEL_0
4839 * @arg @ref LL_DMA_CHANNEL_1
4840 * @arg @ref LL_DMA_CHANNEL_2
4841 * @arg @ref LL_DMA_CHANNEL_3
4842 * @arg @ref LL_DMA_CHANNEL_4
4843 * @arg @ref LL_DMA_CHANNEL_5
4844 * @arg @ref LL_DMA_CHANNEL_6
4845 * @arg @ref LL_DMA_CHANNEL_7
4846 * @arg @ref LL_DMA_CHANNEL_8
4847 * @arg @ref LL_DMA_CHANNEL_9
4848 * @arg @ref LL_DMA_CHANNEL_10
4849 * @arg @ref LL_DMA_CHANNEL_11
4850 * @arg @ref LL_DMA_CHANNEL_12
4851 * @arg @ref LL_DMA_CHANNEL_13
4852 * @arg @ref LL_DMA_CHANNEL_14
4853 * @arg @ref LL_DMA_CHANNEL_15
4854 * @retval State of bit (1 or 0).
4855 */
LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)4856 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
4857 {
4858 uint32_t dma_base_addr = (uint32_t)DMAx;
4859 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
4860 == (DMA_CLLR_UB1)) ? 1UL : 0UL);
4861 }
4862
4863 /**
4864 * @brief Enable CSAR update during the link transfer.
4865 * @note This API is used for all available DMA channels.
4866 * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
4867 * @param DMAx DMAx Instance
4868 * @param Channel This parameter can be one of the following values:
4869 * @arg @ref LL_DMA_CHANNEL_0
4870 * @arg @ref LL_DMA_CHANNEL_1
4871 * @arg @ref LL_DMA_CHANNEL_2
4872 * @arg @ref LL_DMA_CHANNEL_3
4873 * @arg @ref LL_DMA_CHANNEL_4
4874 * @arg @ref LL_DMA_CHANNEL_5
4875 * @arg @ref LL_DMA_CHANNEL_6
4876 * @arg @ref LL_DMA_CHANNEL_7
4877 * @arg @ref LL_DMA_CHANNEL_8
4878 * @arg @ref LL_DMA_CHANNEL_9
4879 * @arg @ref LL_DMA_CHANNEL_10
4880 * @arg @ref LL_DMA_CHANNEL_11
4881 * @arg @ref LL_DMA_CHANNEL_12
4882 * @arg @ref LL_DMA_CHANNEL_13
4883 * @arg @ref LL_DMA_CHANNEL_14
4884 * @arg @ref LL_DMA_CHANNEL_15
4885 * @retval None.
4886 */
LL_DMA_EnableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4887 __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4888 {
4889 uint32_t dma_base_addr = (uint32_t)DMAx;
4890 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
4891 }
4892
4893 /**
4894 * @brief Disable CSAR update during the link transfer.
4895 * @note This API is used for all available DMA channels.
4896 * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
4897 * @param DMAx DMAx Instance
4898 * @param Channel This parameter can be one of the following values:
4899 * @arg @ref LL_DMA_CHANNEL_0
4900 * @arg @ref LL_DMA_CHANNEL_1
4901 * @arg @ref LL_DMA_CHANNEL_2
4902 * @arg @ref LL_DMA_CHANNEL_3
4903 * @arg @ref LL_DMA_CHANNEL_4
4904 * @arg @ref LL_DMA_CHANNEL_5
4905 * @arg @ref LL_DMA_CHANNEL_6
4906 * @arg @ref LL_DMA_CHANNEL_7
4907 * @arg @ref LL_DMA_CHANNEL_8
4908 * @arg @ref LL_DMA_CHANNEL_9
4909 * @arg @ref LL_DMA_CHANNEL_10
4910 * @arg @ref LL_DMA_CHANNEL_11
4911 * @arg @ref LL_DMA_CHANNEL_12
4912 * @arg @ref LL_DMA_CHANNEL_13
4913 * @arg @ref LL_DMA_CHANNEL_14
4914 * @arg @ref LL_DMA_CHANNEL_15
4915 * @retval None.
4916 */
LL_DMA_DisableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4917 __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4918 {
4919 uint32_t dma_base_addr = (uint32_t)DMAx;
4920 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
4921 }
4922
4923 /**
4924 * @brief Check if CSAR update during the link transfer is enabled.
4925 * @note This API is used for all available DMA channels.
4926 * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
4927 * @param DMAx DMAx Instance
4928 * @param Channel This parameter can be one of the following values:
4929 * @arg @ref LL_DMA_CHANNEL_0
4930 * @arg @ref LL_DMA_CHANNEL_1
4931 * @arg @ref LL_DMA_CHANNEL_2
4932 * @arg @ref LL_DMA_CHANNEL_3
4933 * @arg @ref LL_DMA_CHANNEL_4
4934 * @arg @ref LL_DMA_CHANNEL_5
4935 * @arg @ref LL_DMA_CHANNEL_6
4936 * @arg @ref LL_DMA_CHANNEL_7
4937 * @arg @ref LL_DMA_CHANNEL_8
4938 * @arg @ref LL_DMA_CHANNEL_9
4939 * @arg @ref LL_DMA_CHANNEL_10
4940 * @arg @ref LL_DMA_CHANNEL_11
4941 * @arg @ref LL_DMA_CHANNEL_12
4942 * @arg @ref LL_DMA_CHANNEL_13
4943 * @arg @ref LL_DMA_CHANNEL_14
4944 * @arg @ref LL_DMA_CHANNEL_15
4945 * @retval State of bit (1 or 0).
4946 */
LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4947 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4948 {
4949 uint32_t dma_base_addr = (uint32_t)DMAx;
4950 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
4951 == (DMA_CLLR_USA)) ? 1UL : 0UL);
4952 }
4953
4954 /**
4955 * @brief Enable CDAR update during the link transfer.
4956 * @note This API is used for all available DMA channels.
4957 * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
4958 * @param DMAx DMAx Instance
4959 * @param Channel This parameter can be one of the following values:
4960 * @arg @ref LL_DMA_CHANNEL_0
4961 * @arg @ref LL_DMA_CHANNEL_1
4962 * @arg @ref LL_DMA_CHANNEL_2
4963 * @arg @ref LL_DMA_CHANNEL_3
4964 * @arg @ref LL_DMA_CHANNEL_4
4965 * @arg @ref LL_DMA_CHANNEL_5
4966 * @arg @ref LL_DMA_CHANNEL_6
4967 * @arg @ref LL_DMA_CHANNEL_7
4968 * @arg @ref LL_DMA_CHANNEL_8
4969 * @arg @ref LL_DMA_CHANNEL_9
4970 * @arg @ref LL_DMA_CHANNEL_10
4971 * @arg @ref LL_DMA_CHANNEL_11
4972 * @arg @ref LL_DMA_CHANNEL_12
4973 * @arg @ref LL_DMA_CHANNEL_13
4974 * @arg @ref LL_DMA_CHANNEL_14
4975 * @arg @ref LL_DMA_CHANNEL_15
4976 * @retval None.
4977 */
LL_DMA_EnableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)4978 __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
4979 {
4980 uint32_t dma_base_addr = (uint32_t)DMAx;
4981 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
4982 }
4983
4984 /**
4985 * @brief Disable CDAR update during the link transfer.
4986 * @note This API is used for all available DMA channels.
4987 * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
4988 * @param DMAx DMAx Instance
4989 * @param Channel This parameter can be one of the following values:
4990 * @arg @ref LL_DMA_CHANNEL_0
4991 * @arg @ref LL_DMA_CHANNEL_1
4992 * @arg @ref LL_DMA_CHANNEL_2
4993 * @arg @ref LL_DMA_CHANNEL_3
4994 * @arg @ref LL_DMA_CHANNEL_4
4995 * @arg @ref LL_DMA_CHANNEL_5
4996 * @arg @ref LL_DMA_CHANNEL_6
4997 * @arg @ref LL_DMA_CHANNEL_7
4998 * @arg @ref LL_DMA_CHANNEL_8
4999 * @arg @ref LL_DMA_CHANNEL_9
5000 * @arg @ref LL_DMA_CHANNEL_10
5001 * @arg @ref LL_DMA_CHANNEL_11
5002 * @arg @ref LL_DMA_CHANNEL_12
5003 * @arg @ref LL_DMA_CHANNEL_13
5004 * @arg @ref LL_DMA_CHANNEL_14
5005 * @arg @ref LL_DMA_CHANNEL_15
5006 * @retval None.
5007 */
LL_DMA_DisableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5008 __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5009 {
5010 uint32_t dma_base_addr = (uint32_t)DMAx;
5011 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
5012 }
5013
5014 /**
5015 * @brief Check if CDAR update during the link transfer is enabled.
5016 * @note This API is used for all available DMA channels.
5017 * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
5018 * @param DMAx DMAx Instance
5019 * @param Channel This parameter can be one of the following values:
5020 * @arg @ref LL_DMA_CHANNEL_0
5021 * @arg @ref LL_DMA_CHANNEL_1
5022 * @arg @ref LL_DMA_CHANNEL_2
5023 * @arg @ref LL_DMA_CHANNEL_3
5024 * @arg @ref LL_DMA_CHANNEL_4
5025 * @arg @ref LL_DMA_CHANNEL_5
5026 * @arg @ref LL_DMA_CHANNEL_6
5027 * @arg @ref LL_DMA_CHANNEL_7
5028 * @arg @ref LL_DMA_CHANNEL_8
5029 * @arg @ref LL_DMA_CHANNEL_9
5030 * @arg @ref LL_DMA_CHANNEL_10
5031 * @arg @ref LL_DMA_CHANNEL_11
5032 * @arg @ref LL_DMA_CHANNEL_12
5033 * @arg @ref LL_DMA_CHANNEL_13
5034 * @arg @ref LL_DMA_CHANNEL_14
5035 * @arg @ref LL_DMA_CHANNEL_15
5036 * @retval State of bit (1 or 0).
5037 */
LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5038 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5039 {
5040 uint32_t dma_base_addr = (uint32_t)DMAx;
5041 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
5042 == (DMA_CLLR_UDA)) ? 1UL : 0UL);
5043 }
5044
5045 /**
5046 * @brief Enable CTR3 update during the link transfer.
5047 * @note This API is used only for 2D addressing channels.
5048 * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update
5049 * @param DMAx DMAx Instance
5050 * @param Channel This parameter can be one of the following values:
5051 * @arg @ref LL_DMA_CHANNEL_12
5052 * @arg @ref LL_DMA_CHANNEL_13
5053 * @arg @ref LL_DMA_CHANNEL_14
5054 * @arg @ref LL_DMA_CHANNEL_15
5055 * @retval None.
5056 */
LL_DMA_EnableCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5057 __STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5058 {
5059 uint32_t dma_base_addr = (uint32_t)DMAx;
5060 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
5061 }
5062
5063 /**
5064 * @brief Disable CTR3 update during the link transfer.
5065 * @note This API is used only for 2D addressing channels.
5066 * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update
5067 * @param DMAx DMAx Instance
5068 * @param Channel This parameter can be one of the following values:
5069 * @arg @ref LL_DMA_CHANNEL_12
5070 * @arg @ref LL_DMA_CHANNEL_13
5071 * @arg @ref LL_DMA_CHANNEL_14
5072 * @arg @ref LL_DMA_CHANNEL_15
5073 * @retval None.
5074 */
LL_DMA_DisableCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5075 __STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5076 {
5077 uint32_t dma_base_addr = (uint32_t)DMAx;
5078 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
5079 }
5080
5081 /**
5082 * @brief Check if CTR3 update during the link transfer is enabled.
5083 * @note This API is used only for 2D addressing channels.
5084 * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update
5085 * @param DMAx DMAx Instance
5086 * @param Channel This parameter can be one of the following values:
5087 * @arg @ref LL_DMA_CHANNEL_12
5088 * @arg @ref LL_DMA_CHANNEL_13
5089 * @arg @ref LL_DMA_CHANNEL_14
5090 * @arg @ref LL_DMA_CHANNEL_15
5091 * @retval State of bit (1 or 0).
5092 */
LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef * DMAx,uint32_t Channel)5093 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5094 {
5095 uint32_t dma_base_addr = (uint32_t)DMAx;
5096 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3)
5097 == (DMA_CLLR_UT3)) ? 1UL : 0UL);
5098 }
5099
5100 /**
5101 * @brief Enable CBR2 update during the link transfer.
5102 * @note This API is used only for 2D addressing channels.
5103 * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update
5104 * @param DMAx DMAx Instance
5105 * @param Channel This parameter can be one of the following values:
5106 * @arg @ref LL_DMA_CHANNEL_12
5107 * @arg @ref LL_DMA_CHANNEL_13
5108 * @arg @ref LL_DMA_CHANNEL_14
5109 * @arg @ref LL_DMA_CHANNEL_15
5110 * @retval None.
5111 */
LL_DMA_EnableCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5112 __STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5113 {
5114 uint32_t dma_base_addr = (uint32_t)DMAx;
5115 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
5116 }
5117
5118 /**
5119 * @brief Disable CBR2 update during the link transfer.
5120 * @note This API is used only for 2D addressing channels.
5121 * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update
5122 * @param DMAx DMAx Instance
5123 * @param Channel This parameter can be one of the following values:
5124 * @arg @ref LL_DMA_CHANNEL_12
5125 * @arg @ref LL_DMA_CHANNEL_13
5126 * @arg @ref LL_DMA_CHANNEL_14
5127 * @arg @ref LL_DMA_CHANNEL_15
5128 * @retval None.
5129 */
LL_DMA_DisableCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5130 __STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5131 {
5132 uint32_t dma_base_addr = (uint32_t)DMAx;
5133 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
5134 }
5135
5136 /**
5137 * @brief Check if CBR2 update during the link transfer is enabled.
5138 * @note This API is used only for 2D addressing channels.
5139 * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update
5140 * @param DMAx DMAx Instance
5141 * @param Channel This parameter can be one of the following values:
5142 * @arg @ref LL_DMA_CHANNEL_12
5143 * @arg @ref LL_DMA_CHANNEL_13
5144 * @arg @ref LL_DMA_CHANNEL_14
5145 * @arg @ref LL_DMA_CHANNEL_15
5146 * @retval State of bit (1 or 0).
5147 */
LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)5148 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
5149 {
5150 uint32_t dma_base_addr = (uint32_t)DMAx;
5151 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2)
5152 == (DMA_CLLR_UB2)) ? 1UL : 0UL);
5153 }
5154
5155 /**
5156 * @brief Enable CLLR update during the link transfer.
5157 * @note This API is used for all available DMA channels.
5158 * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
5159 * @param DMAx DMAx Instance
5160 * @param Channel This parameter can be one of the following values:
5161 * @arg @ref LL_DMA_CHANNEL_0
5162 * @arg @ref LL_DMA_CHANNEL_1
5163 * @arg @ref LL_DMA_CHANNEL_2
5164 * @arg @ref LL_DMA_CHANNEL_3
5165 * @arg @ref LL_DMA_CHANNEL_4
5166 * @arg @ref LL_DMA_CHANNEL_5
5167 * @arg @ref LL_DMA_CHANNEL_6
5168 * @arg @ref LL_DMA_CHANNEL_7
5169 * @arg @ref LL_DMA_CHANNEL_8
5170 * @arg @ref LL_DMA_CHANNEL_9
5171 * @arg @ref LL_DMA_CHANNEL_10
5172 * @arg @ref LL_DMA_CHANNEL_11
5173 * @arg @ref LL_DMA_CHANNEL_12
5174 * @arg @ref LL_DMA_CHANNEL_13
5175 * @arg @ref LL_DMA_CHANNEL_14
5176 * @arg @ref LL_DMA_CHANNEL_15
5177 * @retval None.
5178 */
LL_DMA_EnableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5179 __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5180 {
5181 uint32_t dma_base_addr = (uint32_t)DMAx;
5182 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
5183 }
5184
5185 /**
5186 * @brief Disable CLLR update during the link transfer.
5187 * @note This API is used for all available DMA channels.
5188 * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
5189 * @param DMAx DMAx Instance
5190 * @param Channel This parameter can be one of the following values:
5191 * @arg @ref LL_DMA_CHANNEL_0
5192 * @arg @ref LL_DMA_CHANNEL_1
5193 * @arg @ref LL_DMA_CHANNEL_2
5194 * @arg @ref LL_DMA_CHANNEL_3
5195 * @arg @ref LL_DMA_CHANNEL_4
5196 * @arg @ref LL_DMA_CHANNEL_5
5197 * @arg @ref LL_DMA_CHANNEL_6
5198 * @arg @ref LL_DMA_CHANNEL_7
5199 * @arg @ref LL_DMA_CHANNEL_8
5200 * @arg @ref LL_DMA_CHANNEL_9
5201 * @arg @ref LL_DMA_CHANNEL_10
5202 * @arg @ref LL_DMA_CHANNEL_11
5203 * @arg @ref LL_DMA_CHANNEL_12
5204 * @arg @ref LL_DMA_CHANNEL_13
5205 * @arg @ref LL_DMA_CHANNEL_14
5206 * @arg @ref LL_DMA_CHANNEL_15
5207 * @retval None.
5208 */
LL_DMA_DisableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5209 __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5210 {
5211 uint32_t dma_base_addr = (uint32_t)DMAx;
5212 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
5213 }
5214
5215 /**
5216 * @brief Check if CLLR update during the link transfer is enabled.
5217 * @note This API is used for all available DMA channels.
5218 * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
5219 * @param DMAx DMAx Instance
5220 * @param Channel This parameter can be one of the following values:
5221 * @arg @ref LL_DMA_CHANNEL_0
5222 * @arg @ref LL_DMA_CHANNEL_1
5223 * @arg @ref LL_DMA_CHANNEL_2
5224 * @arg @ref LL_DMA_CHANNEL_3
5225 * @arg @ref LL_DMA_CHANNEL_4
5226 * @arg @ref LL_DMA_CHANNEL_5
5227 * @arg @ref LL_DMA_CHANNEL_6
5228 * @arg @ref LL_DMA_CHANNEL_7
5229 * @arg @ref LL_DMA_CHANNEL_8
5230 * @arg @ref LL_DMA_CHANNEL_9
5231 * @arg @ref LL_DMA_CHANNEL_10
5232 * @arg @ref LL_DMA_CHANNEL_11
5233 * @arg @ref LL_DMA_CHANNEL_12
5234 * @arg @ref LL_DMA_CHANNEL_13
5235 * @arg @ref LL_DMA_CHANNEL_14
5236 * @arg @ref LL_DMA_CHANNEL_15
5237 * @retval State of bit (1 or 0).
5238 */
LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)5239 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
5240 {
5241 uint32_t dma_base_addr = (uint32_t)DMAx;
5242 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
5243 == (DMA_CLLR_ULL)) ? 1UL : 0UL);
5244 }
5245
5246 /**
5247 * @brief Set linked list address offset.
5248 * @note This API is used for all available DMA channels.
5249 * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
5250 * @param DMAx DMAx Instance
5251 * @param Channel This parameter can be one of the following values:
5252 * @arg @ref LL_DMA_CHANNEL_0
5253 * @arg @ref LL_DMA_CHANNEL_1
5254 * @arg @ref LL_DMA_CHANNEL_2
5255 * @arg @ref LL_DMA_CHANNEL_3
5256 * @arg @ref LL_DMA_CHANNEL_4
5257 * @arg @ref LL_DMA_CHANNEL_5
5258 * @arg @ref LL_DMA_CHANNEL_6
5259 * @arg @ref LL_DMA_CHANNEL_7
5260 * @arg @ref LL_DMA_CHANNEL_8
5261 * @arg @ref LL_DMA_CHANNEL_9
5262 * @arg @ref LL_DMA_CHANNEL_10
5263 * @arg @ref LL_DMA_CHANNEL_11
5264 * @arg @ref LL_DMA_CHANNEL_12
5265 * @arg @ref LL_DMA_CHANNEL_13
5266 * @arg @ref LL_DMA_CHANNEL_14
5267 * @arg @ref LL_DMA_CHANNEL_15
5268 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
5269 * @retval None.
5270 */
LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListAddrOffset)5271 __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel,
5272 uint32_t LinkedListAddrOffset)
5273 {
5274 uint32_t dma_base_addr = (uint32_t)DMAx;
5275 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
5276 (LinkedListAddrOffset & DMA_CLLR_LA));
5277 }
5278
5279 /**
5280 * @brief Get linked list address offset.
5281 * @note This API is used for all available DMA channels.
5282 * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
5283 * @param DMAx DMAx Instance
5284 * @param Channel This parameter can be one of the following values:
5285 * @arg @ref LL_DMA_CHANNEL_0
5286 * @arg @ref LL_DMA_CHANNEL_1
5287 * @arg @ref LL_DMA_CHANNEL_2
5288 * @arg @ref LL_DMA_CHANNEL_3
5289 * @arg @ref LL_DMA_CHANNEL_4
5290 * @arg @ref LL_DMA_CHANNEL_5
5291 * @arg @ref LL_DMA_CHANNEL_6
5292 * @arg @ref LL_DMA_CHANNEL_7
5293 * @arg @ref LL_DMA_CHANNEL_8
5294 * @arg @ref LL_DMA_CHANNEL_9
5295 * @arg @ref LL_DMA_CHANNEL_10
5296 * @arg @ref LL_DMA_CHANNEL_11
5297 * @arg @ref LL_DMA_CHANNEL_12
5298 * @arg @ref LL_DMA_CHANNEL_13
5299 * @arg @ref LL_DMA_CHANNEL_14
5300 * @arg @ref LL_DMA_CHANNEL_15
5301 * @retval Between 0 to 0x0000FFFC.
5302 */
LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel)5303 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel)
5304 {
5305 uint32_t dma_base_addr = (uint32_t)DMAx;
5306 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
5307 DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
5308 }
5309
5310 /**
5311 * @brief Get FIFO level.
5312 * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
5313 * @param DMAx DMAx Instance
5314 * @param Channel This parameter can be one of the following values:
5315 * @arg @ref LL_DMA_CHANNEL_0
5316 * @arg @ref LL_DMA_CHANNEL_1
5317 * @arg @ref LL_DMA_CHANNEL_2
5318 * @arg @ref LL_DMA_CHANNEL_3
5319 * @arg @ref LL_DMA_CHANNEL_4
5320 * @arg @ref LL_DMA_CHANNEL_5
5321 * @arg @ref LL_DMA_CHANNEL_6
5322 * @arg @ref LL_DMA_CHANNEL_7
5323 * @arg @ref LL_DMA_CHANNEL_8
5324 * @arg @ref LL_DMA_CHANNEL_9
5325 * @arg @ref LL_DMA_CHANNEL_10
5326 * @arg @ref LL_DMA_CHANNEL_11
5327 * @arg @ref LL_DMA_CHANNEL_12
5328 * @arg @ref LL_DMA_CHANNEL_13
5329 * @arg @ref LL_DMA_CHANNEL_14
5330 * @arg @ref LL_DMA_CHANNEL_15
5331 * @retval Between 0 to 0x000000FF.
5332 */
LL_DMA_GetFIFOLevel(const DMA_TypeDef * DMAx,uint32_t Channel)5333 __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
5334 {
5335 uint32_t dma_base_addr = (uint32_t)DMAx;
5336 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
5337 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
5338 }
5339
5340
5341 /**
5342 * @brief Enable the DMA channel privilege attribute.
5343 * @note This API is used for all available DMA channels.
5344 * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
5345 * @param DMAx DMAx Instance
5346 * @param Channel This parameter can be one of the following values:
5347 * @arg @ref LL_DMA_CHANNEL_0
5348 * @arg @ref LL_DMA_CHANNEL_1
5349 * @arg @ref LL_DMA_CHANNEL_2
5350 * @arg @ref LL_DMA_CHANNEL_3
5351 * @arg @ref LL_DMA_CHANNEL_4
5352 * @arg @ref LL_DMA_CHANNEL_5
5353 * @arg @ref LL_DMA_CHANNEL_6
5354 * @arg @ref LL_DMA_CHANNEL_7
5355 * @arg @ref LL_DMA_CHANNEL_8
5356 * @arg @ref LL_DMA_CHANNEL_9
5357 * @arg @ref LL_DMA_CHANNEL_10
5358 * @arg @ref LL_DMA_CHANNEL_11
5359 * @arg @ref LL_DMA_CHANNEL_12
5360 * @arg @ref LL_DMA_CHANNEL_13
5361 * @arg @ref LL_DMA_CHANNEL_14
5362 * @arg @ref LL_DMA_CHANNEL_15
5363 * @retval None.
5364 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)5365 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
5366 {
5367 SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
5368 }
5369
5370 /**
5371 * @brief Disable the DMA channel privilege attribute.
5372 * @note This API is used for all available DMA channels.
5373 * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
5374 * @param DMAx DMAx Instance
5375 * @param Channel This parameter can be one of the following values:
5376 * @arg @ref LL_DMA_CHANNEL_0
5377 * @arg @ref LL_DMA_CHANNEL_1
5378 * @arg @ref LL_DMA_CHANNEL_2
5379 * @arg @ref LL_DMA_CHANNEL_3
5380 * @arg @ref LL_DMA_CHANNEL_4
5381 * @arg @ref LL_DMA_CHANNEL_5
5382 * @arg @ref LL_DMA_CHANNEL_6
5383 * @arg @ref LL_DMA_CHANNEL_7
5384 * @arg @ref LL_DMA_CHANNEL_8
5385 * @arg @ref LL_DMA_CHANNEL_9
5386 * @arg @ref LL_DMA_CHANNEL_10
5387 * @arg @ref LL_DMA_CHANNEL_11
5388 * @arg @ref LL_DMA_CHANNEL_12
5389 * @arg @ref LL_DMA_CHANNEL_13
5390 * @arg @ref LL_DMA_CHANNEL_14
5391 * @arg @ref LL_DMA_CHANNEL_15
5392 * @retval None.
5393 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)5394 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
5395 {
5396 CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
5397 }
5398
5399 /**
5400 * @brief Check if DMA Channel privilege is enabled.
5401 * @note This API is used for all available DMA channels.
5402 * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege
5403 * @param DMAx DMAx Instance
5404 * @param Channel This parameter can be one of the following values:
5405 * @arg @ref LL_DMA_CHANNEL_0
5406 * @arg @ref LL_DMA_CHANNEL_1
5407 * @arg @ref LL_DMA_CHANNEL_2
5408 * @arg @ref LL_DMA_CHANNEL_3
5409 * @arg @ref LL_DMA_CHANNEL_4
5410 * @arg @ref LL_DMA_CHANNEL_5
5411 * @arg @ref LL_DMA_CHANNEL_6
5412 * @arg @ref LL_DMA_CHANNEL_7
5413 * @arg @ref LL_DMA_CHANNEL_8
5414 * @arg @ref LL_DMA_CHANNEL_9
5415 * @arg @ref LL_DMA_CHANNEL_10
5416 * @arg @ref LL_DMA_CHANNEL_11
5417 * @arg @ref LL_DMA_CHANNEL_12
5418 * @arg @ref LL_DMA_CHANNEL_13
5419 * @arg @ref LL_DMA_CHANNEL_14
5420 * @arg @ref LL_DMA_CHANNEL_15
5421 * @retval State of bit (1 or 0).
5422 */
LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef * DMAx,uint32_t Channel)5423 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel)
5424 {
5425 return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
5426 == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5427 }
5428
5429
5430 /**
5431 * @brief Enable the DMA channel lock attributes.
5432 * @note This API is used for all available DMA channels.
5433 * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
5434 * @param DMAx DMAx Instance
5435 * @param Channel This parameter can be one of the following values:
5436 * @arg @ref LL_DMA_CHANNEL_0
5437 * @arg @ref LL_DMA_CHANNEL_1
5438 * @arg @ref LL_DMA_CHANNEL_2
5439 * @arg @ref LL_DMA_CHANNEL_3
5440 * @arg @ref LL_DMA_CHANNEL_4
5441 * @arg @ref LL_DMA_CHANNEL_5
5442 * @arg @ref LL_DMA_CHANNEL_6
5443 * @arg @ref LL_DMA_CHANNEL_7
5444 * @arg @ref LL_DMA_CHANNEL_8
5445 * @arg @ref LL_DMA_CHANNEL_9
5446 * @arg @ref LL_DMA_CHANNEL_10
5447 * @arg @ref LL_DMA_CHANNEL_11
5448 * @arg @ref LL_DMA_CHANNEL_12
5449 * @arg @ref LL_DMA_CHANNEL_13
5450 * @arg @ref LL_DMA_CHANNEL_14
5451 * @arg @ref LL_DMA_CHANNEL_15
5452 * @retval None.
5453 */
LL_DMA_EnableChannelLockAttribute(DMA_TypeDef * DMAx,uint32_t Channel)5454 __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
5455 {
5456 SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
5457 }
5458
5459
5460 /**
5461 * @brief Check if DMA channel attributes are locked.
5462 * @note This API is used for all available DMA channels.
5463 * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
5464 * @param DMAx DMAx Instance
5465 * @param Channel This parameter can be one of the following values:
5466 * @arg @ref LL_DMA_CHANNEL_0
5467 * @arg @ref LL_DMA_CHANNEL_1
5468 * @arg @ref LL_DMA_CHANNEL_2
5469 * @arg @ref LL_DMA_CHANNEL_3
5470 * @arg @ref LL_DMA_CHANNEL_4
5471 * @arg @ref LL_DMA_CHANNEL_5
5472 * @arg @ref LL_DMA_CHANNEL_6
5473 * @arg @ref LL_DMA_CHANNEL_7
5474 * @arg @ref LL_DMA_CHANNEL_8
5475 * @arg @ref LL_DMA_CHANNEL_9
5476 * @arg @ref LL_DMA_CHANNEL_10
5477 * @arg @ref LL_DMA_CHANNEL_11
5478 * @arg @ref LL_DMA_CHANNEL_12
5479 * @arg @ref LL_DMA_CHANNEL_13
5480 * @arg @ref LL_DMA_CHANNEL_14
5481 * @arg @ref LL_DMA_CHANNEL_15
5482 * @retval State of bit (1 or 0).
5483 */
LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef * DMAx,uint32_t Channel)5484 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel)
5485 {
5486 return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
5487 == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
5488 }
5489
5490 /**
5491 * @}
5492 */
5493
5494 /** @defgroup DMA_LL_EF_FLAG_Management Flag Management
5495 * @{
5496 */
5497
5498 /**
5499 * @brief Clear trigger overrun flag.
5500 * @note This API is used for all available DMA channels.
5501 * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
5502 * @param DMAx DMAx Instance
5503 * @param Channel This parameter can be one of the following values:
5504 * @arg @ref LL_DMA_CHANNEL_0
5505 * @arg @ref LL_DMA_CHANNEL_1
5506 * @arg @ref LL_DMA_CHANNEL_2
5507 * @arg @ref LL_DMA_CHANNEL_3
5508 * @arg @ref LL_DMA_CHANNEL_4
5509 * @arg @ref LL_DMA_CHANNEL_5
5510 * @arg @ref LL_DMA_CHANNEL_6
5511 * @arg @ref LL_DMA_CHANNEL_7
5512 * @arg @ref LL_DMA_CHANNEL_8
5513 * @arg @ref LL_DMA_CHANNEL_9
5514 * @arg @ref LL_DMA_CHANNEL_10
5515 * @arg @ref LL_DMA_CHANNEL_11
5516 * @arg @ref LL_DMA_CHANNEL_12
5517 * @arg @ref LL_DMA_CHANNEL_13
5518 * @arg @ref LL_DMA_CHANNEL_14
5519 * @arg @ref LL_DMA_CHANNEL_15
5520 * @retval None.
5521 */
LL_DMA_ClearFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)5522 __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
5523 {
5524 uint32_t dma_base_addr = (uint32_t)DMAx;
5525 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
5526 }
5527
5528 /**
5529 * @brief Clear suspension flag.
5530 * @note This API is used for all available DMA channels.
5531 * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
5532 * @param DMAx DMAx Instance
5533 * @param Channel This parameter can be one of the following values:
5534 * @arg @ref LL_DMA_CHANNEL_0
5535 * @arg @ref LL_DMA_CHANNEL_1
5536 * @arg @ref LL_DMA_CHANNEL_2
5537 * @arg @ref LL_DMA_CHANNEL_3
5538 * @arg @ref LL_DMA_CHANNEL_4
5539 * @arg @ref LL_DMA_CHANNEL_5
5540 * @arg @ref LL_DMA_CHANNEL_6
5541 * @arg @ref LL_DMA_CHANNEL_7
5542 * @arg @ref LL_DMA_CHANNEL_8
5543 * @arg @ref LL_DMA_CHANNEL_9
5544 * @arg @ref LL_DMA_CHANNEL_10
5545 * @arg @ref LL_DMA_CHANNEL_11
5546 * @arg @ref LL_DMA_CHANNEL_12
5547 * @arg @ref LL_DMA_CHANNEL_13
5548 * @arg @ref LL_DMA_CHANNEL_14
5549 * @arg @ref LL_DMA_CHANNEL_15
5550 * @retval None.
5551 */
LL_DMA_ClearFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)5552 __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
5553 {
5554 uint32_t dma_base_addr = (uint32_t)DMAx;
5555 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
5556 }
5557
5558 /**
5559 * @brief Clear user setting error flag.
5560 * @note This API is used for all available DMA channels.
5561 * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
5562 * @param DMAx DMAx Instance
5563 * @param Channel This parameter can be one of the following values:
5564 * @arg @ref LL_DMA_CHANNEL_0
5565 * @arg @ref LL_DMA_CHANNEL_1
5566 * @arg @ref LL_DMA_CHANNEL_2
5567 * @arg @ref LL_DMA_CHANNEL_3
5568 * @arg @ref LL_DMA_CHANNEL_4
5569 * @arg @ref LL_DMA_CHANNEL_5
5570 * @arg @ref LL_DMA_CHANNEL_6
5571 * @arg @ref LL_DMA_CHANNEL_7
5572 * @arg @ref LL_DMA_CHANNEL_8
5573 * @arg @ref LL_DMA_CHANNEL_9
5574 * @arg @ref LL_DMA_CHANNEL_10
5575 * @arg @ref LL_DMA_CHANNEL_11
5576 * @arg @ref LL_DMA_CHANNEL_12
5577 * @arg @ref LL_DMA_CHANNEL_13
5578 * @arg @ref LL_DMA_CHANNEL_14
5579 * @arg @ref LL_DMA_CHANNEL_15
5580 * @retval None.
5581 */
LL_DMA_ClearFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)5582 __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
5583 {
5584 uint32_t dma_base_addr = (uint32_t)DMAx;
5585 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
5586 }
5587
5588 /**
5589 * @brief Clear link transfer error flag.
5590 * @note This API is used for all available DMA channels.
5591 * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
5592 * @param DMAx DMAx Instance
5593 * @param Channel This parameter can be one of the following values:
5594 * @arg @ref LL_DMA_CHANNEL_0
5595 * @arg @ref LL_DMA_CHANNEL_1
5596 * @arg @ref LL_DMA_CHANNEL_2
5597 * @arg @ref LL_DMA_CHANNEL_3
5598 * @arg @ref LL_DMA_CHANNEL_4
5599 * @arg @ref LL_DMA_CHANNEL_5
5600 * @arg @ref LL_DMA_CHANNEL_6
5601 * @arg @ref LL_DMA_CHANNEL_7
5602 * @arg @ref LL_DMA_CHANNEL_8
5603 * @arg @ref LL_DMA_CHANNEL_9
5604 * @arg @ref LL_DMA_CHANNEL_10
5605 * @arg @ref LL_DMA_CHANNEL_11
5606 * @arg @ref LL_DMA_CHANNEL_12
5607 * @arg @ref LL_DMA_CHANNEL_13
5608 * @arg @ref LL_DMA_CHANNEL_14
5609 * @arg @ref LL_DMA_CHANNEL_15
5610 * @retval None.
5611 */
LL_DMA_ClearFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)5612 __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
5613 {
5614 uint32_t dma_base_addr = (uint32_t)DMAx;
5615 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
5616 }
5617
5618 /**
5619 * @brief Clear data transfer error flag.
5620 * @note This API is used for all available DMA channels.
5621 * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
5622 * @param DMAx DMAx Instance
5623 * @param Channel This parameter can be one of the following values:
5624 * @arg @ref LL_DMA_CHANNEL_0
5625 * @arg @ref LL_DMA_CHANNEL_1
5626 * @arg @ref LL_DMA_CHANNEL_2
5627 * @arg @ref LL_DMA_CHANNEL_3
5628 * @arg @ref LL_DMA_CHANNEL_4
5629 * @arg @ref LL_DMA_CHANNEL_5
5630 * @arg @ref LL_DMA_CHANNEL_6
5631 * @arg @ref LL_DMA_CHANNEL_7
5632 * @arg @ref LL_DMA_CHANNEL_8
5633 * @arg @ref LL_DMA_CHANNEL_9
5634 * @arg @ref LL_DMA_CHANNEL_10
5635 * @arg @ref LL_DMA_CHANNEL_11
5636 * @arg @ref LL_DMA_CHANNEL_12
5637 * @arg @ref LL_DMA_CHANNEL_13
5638 * @arg @ref LL_DMA_CHANNEL_14
5639 * @arg @ref LL_DMA_CHANNEL_15
5640 * @retval None.
5641 */
LL_DMA_ClearFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)5642 __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
5643 {
5644 uint32_t dma_base_addr = (uint32_t)DMAx;
5645 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
5646 }
5647
5648 /**
5649 * @brief Clear half transfer flag.
5650 * @note This API is used for all available DMA channels.
5651 * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
5652 * @param DMAx DMAx Instance
5653 * @param Channel This parameter can be one of the following values:
5654 * @arg @ref LL_DMA_CHANNEL_0
5655 * @arg @ref LL_DMA_CHANNEL_1
5656 * @arg @ref LL_DMA_CHANNEL_2
5657 * @arg @ref LL_DMA_CHANNEL_3
5658 * @arg @ref LL_DMA_CHANNEL_4
5659 * @arg @ref LL_DMA_CHANNEL_5
5660 * @arg @ref LL_DMA_CHANNEL_6
5661 * @arg @ref LL_DMA_CHANNEL_7
5662 * @arg @ref LL_DMA_CHANNEL_8
5663 * @arg @ref LL_DMA_CHANNEL_9
5664 * @arg @ref LL_DMA_CHANNEL_10
5665 * @arg @ref LL_DMA_CHANNEL_11
5666 * @arg @ref LL_DMA_CHANNEL_12
5667 * @arg @ref LL_DMA_CHANNEL_13
5668 * @arg @ref LL_DMA_CHANNEL_14
5669 * @arg @ref LL_DMA_CHANNEL_15
5670 * @retval None.
5671 */
LL_DMA_ClearFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)5672 __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
5673 {
5674 uint32_t dma_base_addr = (uint32_t)DMAx;
5675 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
5676 }
5677
5678 /**
5679 * @brief Clear transfer complete flag.
5680 * @note This API is used for all available DMA channels.
5681 * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
5682 * @param DMAx DMAx Instance
5683 * @param Channel This parameter can be one of the following values:
5684 * @arg @ref LL_DMA_CHANNEL_0
5685 * @arg @ref LL_DMA_CHANNEL_1
5686 * @arg @ref LL_DMA_CHANNEL_2
5687 * @arg @ref LL_DMA_CHANNEL_3
5688 * @arg @ref LL_DMA_CHANNEL_4
5689 * @arg @ref LL_DMA_CHANNEL_5
5690 * @arg @ref LL_DMA_CHANNEL_6
5691 * @arg @ref LL_DMA_CHANNEL_7
5692 * @arg @ref LL_DMA_CHANNEL_8
5693 * @arg @ref LL_DMA_CHANNEL_9
5694 * @arg @ref LL_DMA_CHANNEL_10
5695 * @arg @ref LL_DMA_CHANNEL_11
5696 * @arg @ref LL_DMA_CHANNEL_12
5697 * @arg @ref LL_DMA_CHANNEL_13
5698 * @arg @ref LL_DMA_CHANNEL_14
5699 * @arg @ref LL_DMA_CHANNEL_15
5700 * @retval None.
5701 */
LL_DMA_ClearFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)5702 __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
5703 {
5704 uint32_t dma_base_addr = (uint32_t)DMAx;
5705 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
5706 }
5707
5708 /**
5709 * @brief Get trigger overrun flag.
5710 * @note This API is used for all available DMA channels.
5711 * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
5712 * @param DMAx DMAx Instance
5713 * @param Channel This parameter can be one of the following values:
5714 * @arg @ref LL_DMA_CHANNEL_0
5715 * @arg @ref LL_DMA_CHANNEL_1
5716 * @arg @ref LL_DMA_CHANNEL_2
5717 * @arg @ref LL_DMA_CHANNEL_3
5718 * @arg @ref LL_DMA_CHANNEL_4
5719 * @arg @ref LL_DMA_CHANNEL_5
5720 * @arg @ref LL_DMA_CHANNEL_6
5721 * @arg @ref LL_DMA_CHANNEL_7
5722 * @arg @ref LL_DMA_CHANNEL_8
5723 * @arg @ref LL_DMA_CHANNEL_9
5724 * @arg @ref LL_DMA_CHANNEL_10
5725 * @arg @ref LL_DMA_CHANNEL_11
5726 * @arg @ref LL_DMA_CHANNEL_12
5727 * @arg @ref LL_DMA_CHANNEL_13
5728 * @arg @ref LL_DMA_CHANNEL_14
5729 * @arg @ref LL_DMA_CHANNEL_15
5730 * @retval State of bit (1 or 0).
5731 */
LL_DMA_IsActiveFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)5732 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
5733 {
5734 uint32_t dma_base_addr = (uint32_t)DMAx;
5735 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
5736 == (DMA_CSR_TOF)) ? 1UL : 0UL);
5737 }
5738
5739 /**
5740 * @brief Get suspension flag.
5741 * @note This API is used for all available DMA channels.
5742 * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
5743 * @param DMAx DMAx Instance
5744 * @param Channel This parameter can be one of the following values:
5745 * @arg @ref LL_DMA_CHANNEL_0
5746 * @arg @ref LL_DMA_CHANNEL_1
5747 * @arg @ref LL_DMA_CHANNEL_2
5748 * @arg @ref LL_DMA_CHANNEL_3
5749 * @arg @ref LL_DMA_CHANNEL_4
5750 * @arg @ref LL_DMA_CHANNEL_5
5751 * @arg @ref LL_DMA_CHANNEL_6
5752 * @arg @ref LL_DMA_CHANNEL_7
5753 * @arg @ref LL_DMA_CHANNEL_8
5754 * @arg @ref LL_DMA_CHANNEL_9
5755 * @arg @ref LL_DMA_CHANNEL_10
5756 * @arg @ref LL_DMA_CHANNEL_11
5757 * @arg @ref LL_DMA_CHANNEL_12
5758 * @arg @ref LL_DMA_CHANNEL_13
5759 * @arg @ref LL_DMA_CHANNEL_14
5760 * @arg @ref LL_DMA_CHANNEL_15
5761 * @retval State of bit (1 or 0).
5762 */
LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)5763 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
5764 {
5765 uint32_t dma_base_addr = (uint32_t)DMAx;
5766 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
5767 == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
5768 }
5769
5770 /**
5771 * @brief Get user setting error flag.
5772 * @note This API is used for all available DMA channels.
5773 * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
5774 * @param DMAx DMAx Instance
5775 * @param Channel This parameter can be one of the following values:
5776 * @arg @ref LL_DMA_CHANNEL_0
5777 * @arg @ref LL_DMA_CHANNEL_1
5778 * @arg @ref LL_DMA_CHANNEL_2
5779 * @arg @ref LL_DMA_CHANNEL_3
5780 * @arg @ref LL_DMA_CHANNEL_4
5781 * @arg @ref LL_DMA_CHANNEL_5
5782 * @arg @ref LL_DMA_CHANNEL_6
5783 * @arg @ref LL_DMA_CHANNEL_7
5784 * @arg @ref LL_DMA_CHANNEL_8
5785 * @arg @ref LL_DMA_CHANNEL_9
5786 * @arg @ref LL_DMA_CHANNEL_10
5787 * @arg @ref LL_DMA_CHANNEL_11
5788 * @arg @ref LL_DMA_CHANNEL_12
5789 * @arg @ref LL_DMA_CHANNEL_13
5790 * @arg @ref LL_DMA_CHANNEL_14
5791 * @arg @ref LL_DMA_CHANNEL_15
5792 * @retval State of bit (1 or 0).
5793 */
LL_DMA_IsActiveFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)5794 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
5795 {
5796 uint32_t dma_base_addr = (uint32_t)DMAx;
5797 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
5798 == (DMA_CSR_USEF)) ? 1UL : 0UL);
5799 }
5800
5801 /**
5802 * @brief Get user setting error flag.
5803 * @note This API is used for all available DMA channels.
5804 * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
5805 * @param DMAx DMAx Instance
5806 * @param Channel This parameter can be one of the following values:
5807 * @arg @ref LL_DMA_CHANNEL_0
5808 * @arg @ref LL_DMA_CHANNEL_1
5809 * @arg @ref LL_DMA_CHANNEL_2
5810 * @arg @ref LL_DMA_CHANNEL_3
5811 * @arg @ref LL_DMA_CHANNEL_4
5812 * @arg @ref LL_DMA_CHANNEL_5
5813 * @arg @ref LL_DMA_CHANNEL_6
5814 * @arg @ref LL_DMA_CHANNEL_7
5815 * @arg @ref LL_DMA_CHANNEL_8
5816 * @arg @ref LL_DMA_CHANNEL_9
5817 * @arg @ref LL_DMA_CHANNEL_10
5818 * @arg @ref LL_DMA_CHANNEL_11
5819 * @arg @ref LL_DMA_CHANNEL_12
5820 * @arg @ref LL_DMA_CHANNEL_13
5821 * @arg @ref LL_DMA_CHANNEL_14
5822 * @arg @ref LL_DMA_CHANNEL_15
5823 * @retval State of bit (1 or 0).
5824 */
LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)5825 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
5826 {
5827 uint32_t dma_base_addr = (uint32_t)DMAx;
5828 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
5829 == (DMA_CSR_ULEF)) ? 1UL : 0UL);
5830 }
5831
5832 /**
5833 * @brief Get data transfer error flag.
5834 * @note This API is used for all available DMA channels.
5835 * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
5836 * @param DMAx DMAx Instance
5837 * @param Channel This parameter can be one of the following values:
5838 * @arg @ref LL_DMA_CHANNEL_0
5839 * @arg @ref LL_DMA_CHANNEL_1
5840 * @arg @ref LL_DMA_CHANNEL_2
5841 * @arg @ref LL_DMA_CHANNEL_3
5842 * @arg @ref LL_DMA_CHANNEL_4
5843 * @arg @ref LL_DMA_CHANNEL_5
5844 * @arg @ref LL_DMA_CHANNEL_6
5845 * @arg @ref LL_DMA_CHANNEL_7
5846 * @arg @ref LL_DMA_CHANNEL_8
5847 * @arg @ref LL_DMA_CHANNEL_9
5848 * @arg @ref LL_DMA_CHANNEL_10
5849 * @arg @ref LL_DMA_CHANNEL_11
5850 * @arg @ref LL_DMA_CHANNEL_12
5851 * @arg @ref LL_DMA_CHANNEL_13
5852 * @arg @ref LL_DMA_CHANNEL_14
5853 * @arg @ref LL_DMA_CHANNEL_15
5854 * @retval State of bit (1 or 0).
5855 */
LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)5856 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
5857 {
5858 uint32_t dma_base_addr = (uint32_t)DMAx;
5859 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
5860 == (DMA_CSR_DTEF)) ? 1UL : 0UL);
5861 }
5862
5863 /**
5864 * @brief Get half transfer flag.
5865 * @note This API is used for all available DMA channels.
5866 * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
5867 * @param DMAx DMAx Instance
5868 * @param Channel This parameter can be one of the following values:
5869 * @arg @ref LL_DMA_CHANNEL_0
5870 * @arg @ref LL_DMA_CHANNEL_1
5871 * @arg @ref LL_DMA_CHANNEL_2
5872 * @arg @ref LL_DMA_CHANNEL_3
5873 * @arg @ref LL_DMA_CHANNEL_4
5874 * @arg @ref LL_DMA_CHANNEL_5
5875 * @arg @ref LL_DMA_CHANNEL_6
5876 * @arg @ref LL_DMA_CHANNEL_7
5877 * @arg @ref LL_DMA_CHANNEL_8
5878 * @arg @ref LL_DMA_CHANNEL_9
5879 * @arg @ref LL_DMA_CHANNEL_10
5880 * @arg @ref LL_DMA_CHANNEL_11
5881 * @arg @ref LL_DMA_CHANNEL_12
5882 * @arg @ref LL_DMA_CHANNEL_13
5883 * @arg @ref LL_DMA_CHANNEL_14
5884 * @arg @ref LL_DMA_CHANNEL_15
5885 * @retval State of bit (1 or 0).
5886 */
LL_DMA_IsActiveFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)5887 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
5888 {
5889 uint32_t dma_base_addr = (uint32_t)DMAx;
5890 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
5891 == (DMA_CSR_HTF)) ? 1UL : 0UL);
5892 }
5893
5894 /**
5895 * @brief Get transfer complete flag.
5896 * @note This API is used for all available DMA channels.
5897 * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
5898 * @param DMAx DMAx Instance
5899 * @param Channel This parameter can be one of the following values:
5900 * @arg @ref LL_DMA_CHANNEL_0
5901 * @arg @ref LL_DMA_CHANNEL_1
5902 * @arg @ref LL_DMA_CHANNEL_2
5903 * @arg @ref LL_DMA_CHANNEL_3
5904 * @arg @ref LL_DMA_CHANNEL_4
5905 * @arg @ref LL_DMA_CHANNEL_5
5906 * @arg @ref LL_DMA_CHANNEL_6
5907 * @arg @ref LL_DMA_CHANNEL_7
5908 * @arg @ref LL_DMA_CHANNEL_8
5909 * @arg @ref LL_DMA_CHANNEL_9
5910 * @arg @ref LL_DMA_CHANNEL_10
5911 * @arg @ref LL_DMA_CHANNEL_11
5912 * @arg @ref LL_DMA_CHANNEL_12
5913 * @arg @ref LL_DMA_CHANNEL_13
5914 * @arg @ref LL_DMA_CHANNEL_14
5915 * @arg @ref LL_DMA_CHANNEL_15
5916 * @retval State of bit (1 or 0).
5917 */
LL_DMA_IsActiveFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)5918 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
5919 {
5920 uint32_t dma_base_addr = (uint32_t)DMAx;
5921 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
5922 == (DMA_CSR_TCF)) ? 1UL : 0UL);
5923 }
5924
5925 /**
5926 * @brief Get idle flag.
5927 * @note This API is used for all available DMA channels.
5928 * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
5929 * @param DMAx DMAx Instance
5930 * @param Channel This parameter can be one of the following values:
5931 * @arg @ref LL_DMA_CHANNEL_0
5932 * @arg @ref LL_DMA_CHANNEL_1
5933 * @arg @ref LL_DMA_CHANNEL_2
5934 * @arg @ref LL_DMA_CHANNEL_3
5935 * @arg @ref LL_DMA_CHANNEL_4
5936 * @arg @ref LL_DMA_CHANNEL_5
5937 * @arg @ref LL_DMA_CHANNEL_6
5938 * @arg @ref LL_DMA_CHANNEL_7
5939 * @arg @ref LL_DMA_CHANNEL_8
5940 * @arg @ref LL_DMA_CHANNEL_9
5941 * @arg @ref LL_DMA_CHANNEL_10
5942 * @arg @ref LL_DMA_CHANNEL_11
5943 * @arg @ref LL_DMA_CHANNEL_12
5944 * @arg @ref LL_DMA_CHANNEL_13
5945 * @arg @ref LL_DMA_CHANNEL_14
5946 * @arg @ref LL_DMA_CHANNEL_15
5947 * @retval State of bit (1 or 0).
5948 */
LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef * DMAx,uint32_t Channel)5949 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel)
5950 {
5951 uint32_t dma_base_addr = (uint32_t)DMAx;
5952 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
5953 == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
5954 }
5955
5956 /**
5957 * @brief Check if masked interrupt is active.
5958 * @note This API is used for all available DMA channels.
5959 * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS
5960 * @param DMAx DMAx Instance
5961 * @param Channel This parameter can be one of the following values:
5962 * @arg @ref LL_DMA_CHANNEL_0
5963 * @arg @ref LL_DMA_CHANNEL_1
5964 * @arg @ref LL_DMA_CHANNEL_2
5965 * @arg @ref LL_DMA_CHANNEL_3
5966 * @arg @ref LL_DMA_CHANNEL_4
5967 * @arg @ref LL_DMA_CHANNEL_5
5968 * @arg @ref LL_DMA_CHANNEL_6
5969 * @arg @ref LL_DMA_CHANNEL_7
5970 * @arg @ref LL_DMA_CHANNEL_8
5971 * @arg @ref LL_DMA_CHANNEL_9
5972 * @arg @ref LL_DMA_CHANNEL_10
5973 * @arg @ref LL_DMA_CHANNEL_11
5974 * @arg @ref LL_DMA_CHANNEL_12
5975 * @arg @ref LL_DMA_CHANNEL_13
5976 * @arg @ref LL_DMA_CHANNEL_14
5977 * @arg @ref LL_DMA_CHANNEL_15
5978 * @retval State of bit (1 or 0).
5979 */
LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef * DMAx,uint32_t Channel)5980 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel)
5981 {
5982 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
5983 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
5984 }
5985
5986 /**
5987 * @}
5988 */
5989
5990 /** @defgroup DMA_LL_EF_IT_Management Interrupt Management
5991 * @{
5992 */
5993
5994 /**
5995 * @brief Enable trigger overrun interrupt.
5996 * @note This API is used for all available DMA channels.
5997 * @rmtoll CCR TOIE LL_DMA_EnableIT_TO
5998 * @param DMAx DMAx Instance
5999 * @param Channel This parameter can be one of the following values:
6000 * @arg @ref LL_DMA_CHANNEL_0
6001 * @arg @ref LL_DMA_CHANNEL_1
6002 * @arg @ref LL_DMA_CHANNEL_2
6003 * @arg @ref LL_DMA_CHANNEL_3
6004 * @arg @ref LL_DMA_CHANNEL_4
6005 * @arg @ref LL_DMA_CHANNEL_5
6006 * @arg @ref LL_DMA_CHANNEL_6
6007 * @arg @ref LL_DMA_CHANNEL_7
6008 * @arg @ref LL_DMA_CHANNEL_8
6009 * @arg @ref LL_DMA_CHANNEL_9
6010 * @arg @ref LL_DMA_CHANNEL_10
6011 * @arg @ref LL_DMA_CHANNEL_11
6012 * @arg @ref LL_DMA_CHANNEL_12
6013 * @arg @ref LL_DMA_CHANNEL_13
6014 * @arg @ref LL_DMA_CHANNEL_14
6015 * @arg @ref LL_DMA_CHANNEL_15
6016 * @retval None.
6017 */
LL_DMA_EnableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6018 __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6019 {
6020 uint32_t dma_base_addr = (uint32_t)DMAx;
6021 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
6022 }
6023
6024 /**
6025 * @brief Enable suspension interrupt.
6026 * @note This API is used for all available DMA channels.
6027 * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
6028 * @param DMAx DMAx Instance
6029 * @param Channel This parameter can be one of the following values:
6030 * @arg @ref LL_DMA_CHANNEL_0
6031 * @arg @ref LL_DMA_CHANNEL_1
6032 * @arg @ref LL_DMA_CHANNEL_2
6033 * @arg @ref LL_DMA_CHANNEL_3
6034 * @arg @ref LL_DMA_CHANNEL_4
6035 * @arg @ref LL_DMA_CHANNEL_5
6036 * @arg @ref LL_DMA_CHANNEL_6
6037 * @arg @ref LL_DMA_CHANNEL_7
6038 * @arg @ref LL_DMA_CHANNEL_8
6039 * @arg @ref LL_DMA_CHANNEL_9
6040 * @arg @ref LL_DMA_CHANNEL_10
6041 * @arg @ref LL_DMA_CHANNEL_11
6042 * @arg @ref LL_DMA_CHANNEL_12
6043 * @arg @ref LL_DMA_CHANNEL_13
6044 * @arg @ref LL_DMA_CHANNEL_14
6045 * @arg @ref LL_DMA_CHANNEL_15
6046 * @retval None.
6047 */
LL_DMA_EnableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6048 __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6049 {
6050 uint32_t dma_base_addr = (uint32_t)DMAx;
6051 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
6052 }
6053
6054 /**
6055 * @brief Enable user setting error interrupt.
6056 * @note This API is used for all available DMA channels.
6057 * @rmtoll CCR USEIE LL_DMA_EnableIT_USE
6058 * @param DMAx DMAx Instance
6059 * @param Channel This parameter can be one of the following values:
6060 * @arg @ref LL_DMA_CHANNEL_0
6061 * @arg @ref LL_DMA_CHANNEL_1
6062 * @arg @ref LL_DMA_CHANNEL_2
6063 * @arg @ref LL_DMA_CHANNEL_3
6064 * @arg @ref LL_DMA_CHANNEL_4
6065 * @arg @ref LL_DMA_CHANNEL_5
6066 * @arg @ref LL_DMA_CHANNEL_6
6067 * @arg @ref LL_DMA_CHANNEL_7
6068 * @arg @ref LL_DMA_CHANNEL_8
6069 * @arg @ref LL_DMA_CHANNEL_9
6070 * @arg @ref LL_DMA_CHANNEL_10
6071 * @arg @ref LL_DMA_CHANNEL_11
6072 * @arg @ref LL_DMA_CHANNEL_12
6073 * @arg @ref LL_DMA_CHANNEL_13
6074 * @arg @ref LL_DMA_CHANNEL_14
6075 * @arg @ref LL_DMA_CHANNEL_15
6076 * @retval None.
6077 */
LL_DMA_EnableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6078 __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6079 {
6080 uint32_t dma_base_addr = (uint32_t)DMAx;
6081 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
6082 }
6083
6084 /**
6085 * @brief Enable update link transfer error interrupt.
6086 * @note This API is used for all available DMA channels.
6087 * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
6088 * @param DMAx DMAx Instance
6089 * @param Channel This parameter can be one of the following values:
6090 * @arg @ref LL_DMA_CHANNEL_0
6091 * @arg @ref LL_DMA_CHANNEL_1
6092 * @arg @ref LL_DMA_CHANNEL_2
6093 * @arg @ref LL_DMA_CHANNEL_3
6094 * @arg @ref LL_DMA_CHANNEL_4
6095 * @arg @ref LL_DMA_CHANNEL_5
6096 * @arg @ref LL_DMA_CHANNEL_6
6097 * @arg @ref LL_DMA_CHANNEL_7
6098 * @arg @ref LL_DMA_CHANNEL_8
6099 * @arg @ref LL_DMA_CHANNEL_9
6100 * @arg @ref LL_DMA_CHANNEL_10
6101 * @arg @ref LL_DMA_CHANNEL_11
6102 * @arg @ref LL_DMA_CHANNEL_12
6103 * @arg @ref LL_DMA_CHANNEL_13
6104 * @arg @ref LL_DMA_CHANNEL_14
6105 * @arg @ref LL_DMA_CHANNEL_15
6106 * @retval None.
6107 */
LL_DMA_EnableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6108 __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6109 {
6110 uint32_t dma_base_addr = (uint32_t)DMAx;
6111 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
6112 }
6113
6114 /**
6115 * @brief Enable data transfer error interrupt.
6116 * @note This API is used for all available DMA channels.
6117 * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
6118 * @param DMAx DMAx Instance
6119 * @param Channel This parameter can be one of the following values:
6120 * @arg @ref LL_DMA_CHANNEL_0
6121 * @arg @ref LL_DMA_CHANNEL_1
6122 * @arg @ref LL_DMA_CHANNEL_2
6123 * @arg @ref LL_DMA_CHANNEL_3
6124 * @arg @ref LL_DMA_CHANNEL_4
6125 * @arg @ref LL_DMA_CHANNEL_5
6126 * @arg @ref LL_DMA_CHANNEL_6
6127 * @arg @ref LL_DMA_CHANNEL_7
6128 * @arg @ref LL_DMA_CHANNEL_8
6129 * @arg @ref LL_DMA_CHANNEL_9
6130 * @arg @ref LL_DMA_CHANNEL_10
6131 * @arg @ref LL_DMA_CHANNEL_11
6132 * @arg @ref LL_DMA_CHANNEL_12
6133 * @arg @ref LL_DMA_CHANNEL_13
6134 * @arg @ref LL_DMA_CHANNEL_14
6135 * @arg @ref LL_DMA_CHANNEL_15
6136 * @retval None.
6137 */
LL_DMA_EnableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6138 __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6139 {
6140 uint32_t dma_base_addr = (uint32_t)DMAx;
6141 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
6142 }
6143
6144 /**
6145 * @brief Enable half transfer complete interrupt.
6146 * @note This API is used for all available DMA channels.
6147 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
6148 * @param DMAx DMAx Instance
6149 * @param Channel This parameter can be one of the following values:
6150 * @arg @ref LL_DMA_CHANNEL_0
6151 * @arg @ref LL_DMA_CHANNEL_1
6152 * @arg @ref LL_DMA_CHANNEL_2
6153 * @arg @ref LL_DMA_CHANNEL_3
6154 * @arg @ref LL_DMA_CHANNEL_4
6155 * @arg @ref LL_DMA_CHANNEL_5
6156 * @arg @ref LL_DMA_CHANNEL_6
6157 * @arg @ref LL_DMA_CHANNEL_7
6158 * @arg @ref LL_DMA_CHANNEL_8
6159 * @arg @ref LL_DMA_CHANNEL_9
6160 * @arg @ref LL_DMA_CHANNEL_10
6161 * @arg @ref LL_DMA_CHANNEL_11
6162 * @arg @ref LL_DMA_CHANNEL_12
6163 * @arg @ref LL_DMA_CHANNEL_13
6164 * @arg @ref LL_DMA_CHANNEL_14
6165 * @arg @ref LL_DMA_CHANNEL_15
6166 * @retval None.
6167 */
LL_DMA_EnableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6168 __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6169 {
6170 uint32_t dma_base_addr = (uint32_t)DMAx;
6171 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
6172 }
6173
6174 /**
6175 * @brief Enable transfer complete interrupt.
6176 * @note This API is used for all available DMA channels.
6177 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
6178 * @param DMAx DMAx Instance
6179 * @param Channel This parameter can be one of the following values:
6180 * @arg @ref LL_DMA_CHANNEL_0
6181 * @arg @ref LL_DMA_CHANNEL_1
6182 * @arg @ref LL_DMA_CHANNEL_2
6183 * @arg @ref LL_DMA_CHANNEL_3
6184 * @arg @ref LL_DMA_CHANNEL_4
6185 * @arg @ref LL_DMA_CHANNEL_5
6186 * @arg @ref LL_DMA_CHANNEL_6
6187 * @arg @ref LL_DMA_CHANNEL_7
6188 * @arg @ref LL_DMA_CHANNEL_8
6189 * @arg @ref LL_DMA_CHANNEL_9
6190 * @arg @ref LL_DMA_CHANNEL_10
6191 * @arg @ref LL_DMA_CHANNEL_11
6192 * @arg @ref LL_DMA_CHANNEL_12
6193 * @arg @ref LL_DMA_CHANNEL_13
6194 * @arg @ref LL_DMA_CHANNEL_14
6195 * @arg @ref LL_DMA_CHANNEL_15
6196 * @retval None.
6197 */
LL_DMA_EnableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6198 __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6199 {
6200 uint32_t dma_base_addr = (uint32_t)DMAx;
6201 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
6202 }
6203
6204 /**
6205 * @brief Disable trigger overrun interrupt.
6206 * @note This API is used for all available DMA channels.
6207 * @rmtoll CCR TOIE LL_DMA_DisableIT_TO
6208 * @param DMAx DMAx Instance
6209 * @param Channel This parameter can be one of the following values:
6210 * @arg @ref LL_DMA_CHANNEL_0
6211 * @arg @ref LL_DMA_CHANNEL_1
6212 * @arg @ref LL_DMA_CHANNEL_2
6213 * @arg @ref LL_DMA_CHANNEL_3
6214 * @arg @ref LL_DMA_CHANNEL_4
6215 * @arg @ref LL_DMA_CHANNEL_5
6216 * @arg @ref LL_DMA_CHANNEL_6
6217 * @arg @ref LL_DMA_CHANNEL_7
6218 * @arg @ref LL_DMA_CHANNEL_8
6219 * @arg @ref LL_DMA_CHANNEL_9
6220 * @arg @ref LL_DMA_CHANNEL_10
6221 * @arg @ref LL_DMA_CHANNEL_11
6222 * @arg @ref LL_DMA_CHANNEL_12
6223 * @arg @ref LL_DMA_CHANNEL_13
6224 * @arg @ref LL_DMA_CHANNEL_14
6225 * @arg @ref LL_DMA_CHANNEL_15
6226 * @retval None.
6227 */
LL_DMA_DisableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6228 __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6229 {
6230 uint32_t dma_base_addr = (uint32_t)DMAx;
6231 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
6232 }
6233
6234 /**
6235 * @brief Disable suspension interrupt.
6236 * @note This API is used for all available DMA channels.
6237 * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
6238 * @param DMAx DMAx Instance
6239 * @param Channel This parameter can be one of the following values:
6240 * @arg @ref LL_DMA_CHANNEL_0
6241 * @arg @ref LL_DMA_CHANNEL_1
6242 * @arg @ref LL_DMA_CHANNEL_2
6243 * @arg @ref LL_DMA_CHANNEL_3
6244 * @arg @ref LL_DMA_CHANNEL_4
6245 * @arg @ref LL_DMA_CHANNEL_5
6246 * @arg @ref LL_DMA_CHANNEL_6
6247 * @arg @ref LL_DMA_CHANNEL_7
6248 * @arg @ref LL_DMA_CHANNEL_8
6249 * @arg @ref LL_DMA_CHANNEL_9
6250 * @arg @ref LL_DMA_CHANNEL_10
6251 * @arg @ref LL_DMA_CHANNEL_11
6252 * @arg @ref LL_DMA_CHANNEL_12
6253 * @arg @ref LL_DMA_CHANNEL_13
6254 * @arg @ref LL_DMA_CHANNEL_14
6255 * @arg @ref LL_DMA_CHANNEL_15
6256 * @retval None.
6257 */
LL_DMA_DisableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6258 __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6259 {
6260 uint32_t dma_base_addr = (uint32_t)DMAx;
6261 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
6262 }
6263
6264 /**
6265 * @brief Disable user setting error interrupt.
6266 * @note This API is used for all available DMA channels.
6267 * @rmtoll CCR USEIE LL_DMA_DisableIT_USE
6268 * @param DMAx DMAx Instance
6269 * @param Channel This parameter can be one of the following values:
6270 * @arg @ref LL_DMA_CHANNEL_0
6271 * @arg @ref LL_DMA_CHANNEL_1
6272 * @arg @ref LL_DMA_CHANNEL_2
6273 * @arg @ref LL_DMA_CHANNEL_3
6274 * @arg @ref LL_DMA_CHANNEL_4
6275 * @arg @ref LL_DMA_CHANNEL_5
6276 * @arg @ref LL_DMA_CHANNEL_6
6277 * @arg @ref LL_DMA_CHANNEL_7
6278 * @arg @ref LL_DMA_CHANNEL_8
6279 * @arg @ref LL_DMA_CHANNEL_9
6280 * @arg @ref LL_DMA_CHANNEL_10
6281 * @arg @ref LL_DMA_CHANNEL_11
6282 * @arg @ref LL_DMA_CHANNEL_12
6283 * @arg @ref LL_DMA_CHANNEL_13
6284 * @arg @ref LL_DMA_CHANNEL_14
6285 * @arg @ref LL_DMA_CHANNEL_15
6286 * @retval None.
6287 */
LL_DMA_DisableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6288 __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6289 {
6290 uint32_t dma_base_addr = (uint32_t)DMAx;
6291 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
6292 }
6293
6294 /**
6295 * @brief Disable update link transfer error interrupt.
6296 * @note This API is used for all available DMA channels.
6297 * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
6298 * @param DMAx DMAx Instance
6299 * @param Channel This parameter can be one of the following values:
6300 * @arg @ref LL_DMA_CHANNEL_0
6301 * @arg @ref LL_DMA_CHANNEL_1
6302 * @arg @ref LL_DMA_CHANNEL_2
6303 * @arg @ref LL_DMA_CHANNEL_3
6304 * @arg @ref LL_DMA_CHANNEL_4
6305 * @arg @ref LL_DMA_CHANNEL_5
6306 * @arg @ref LL_DMA_CHANNEL_6
6307 * @arg @ref LL_DMA_CHANNEL_7
6308 * @arg @ref LL_DMA_CHANNEL_8
6309 * @arg @ref LL_DMA_CHANNEL_9
6310 * @arg @ref LL_DMA_CHANNEL_10
6311 * @arg @ref LL_DMA_CHANNEL_11
6312 * @arg @ref LL_DMA_CHANNEL_12
6313 * @arg @ref LL_DMA_CHANNEL_13
6314 * @arg @ref LL_DMA_CHANNEL_14
6315 * @arg @ref LL_DMA_CHANNEL_15
6316 * @retval None.
6317 */
LL_DMA_DisableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6318 __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6319 {
6320 uint32_t dma_base_addr = (uint32_t)DMAx;
6321 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
6322 }
6323
6324 /**
6325 * @brief Disable data transfer error interrupt.
6326 * @note This API is used for all available DMA channels.
6327 * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
6328 * @param DMAx DMAx Instance
6329 * @param Channel This parameter can be one of the following values:
6330 * @arg @ref LL_DMA_CHANNEL_0
6331 * @arg @ref LL_DMA_CHANNEL_1
6332 * @arg @ref LL_DMA_CHANNEL_2
6333 * @arg @ref LL_DMA_CHANNEL_3
6334 * @arg @ref LL_DMA_CHANNEL_4
6335 * @arg @ref LL_DMA_CHANNEL_5
6336 * @arg @ref LL_DMA_CHANNEL_6
6337 * @arg @ref LL_DMA_CHANNEL_7
6338 * @arg @ref LL_DMA_CHANNEL_8
6339 * @arg @ref LL_DMA_CHANNEL_9
6340 * @arg @ref LL_DMA_CHANNEL_10
6341 * @arg @ref LL_DMA_CHANNEL_11
6342 * @arg @ref LL_DMA_CHANNEL_12
6343 * @arg @ref LL_DMA_CHANNEL_13
6344 * @arg @ref LL_DMA_CHANNEL_14
6345 * @arg @ref LL_DMA_CHANNEL_15
6346 * @retval None.
6347 */
LL_DMA_DisableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6348 __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6349 {
6350 uint32_t dma_base_addr = (uint32_t)DMAx;
6351 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
6352 }
6353
6354 /**
6355 * @brief Disable half transfer complete interrupt.
6356 * @note This API is used for all available DMA channels.
6357 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
6358 * @param DMAx DMAx Instance
6359 * @param Channel This parameter can be one of the following values:
6360 * @arg @ref LL_DMA_CHANNEL_0
6361 * @arg @ref LL_DMA_CHANNEL_1
6362 * @arg @ref LL_DMA_CHANNEL_2
6363 * @arg @ref LL_DMA_CHANNEL_3
6364 * @arg @ref LL_DMA_CHANNEL_4
6365 * @arg @ref LL_DMA_CHANNEL_5
6366 * @arg @ref LL_DMA_CHANNEL_6
6367 * @arg @ref LL_DMA_CHANNEL_7
6368 * @arg @ref LL_DMA_CHANNEL_8
6369 * @arg @ref LL_DMA_CHANNEL_9
6370 * @arg @ref LL_DMA_CHANNEL_10
6371 * @arg @ref LL_DMA_CHANNEL_11
6372 * @arg @ref LL_DMA_CHANNEL_12
6373 * @arg @ref LL_DMA_CHANNEL_13
6374 * @arg @ref LL_DMA_CHANNEL_14
6375 * @arg @ref LL_DMA_CHANNEL_15
6376 * @retval None.
6377 */
LL_DMA_DisableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6378 __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6379 {
6380 uint32_t dma_base_addr = (uint32_t)DMAx;
6381 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
6382 }
6383
6384 /**
6385 * @brief Disable transfer complete interrupt.
6386 * @note This API is used for all available DMA channels.
6387 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
6388 * @param DMAx DMAx Instance
6389 * @param Channel This parameter can be one of the following values:
6390 * @arg @ref LL_DMA_CHANNEL_0
6391 * @arg @ref LL_DMA_CHANNEL_1
6392 * @arg @ref LL_DMA_CHANNEL_2
6393 * @arg @ref LL_DMA_CHANNEL_3
6394 * @arg @ref LL_DMA_CHANNEL_4
6395 * @arg @ref LL_DMA_CHANNEL_5
6396 * @arg @ref LL_DMA_CHANNEL_6
6397 * @arg @ref LL_DMA_CHANNEL_7
6398 * @arg @ref LL_DMA_CHANNEL_8
6399 * @arg @ref LL_DMA_CHANNEL_9
6400 * @arg @ref LL_DMA_CHANNEL_10
6401 * @arg @ref LL_DMA_CHANNEL_11
6402 * @arg @ref LL_DMA_CHANNEL_12
6403 * @arg @ref LL_DMA_CHANNEL_13
6404 * @arg @ref LL_DMA_CHANNEL_14
6405 * @arg @ref LL_DMA_CHANNEL_15
6406 * @retval None.
6407 */
LL_DMA_DisableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6408 __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6409 {
6410 uint32_t dma_base_addr = (uint32_t)DMAx;
6411 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
6412 }
6413
6414 /**
6415 * @brief Check if trigger overrun interrupt is enabled.
6416 * @note This API is used for all available DMA channels.
6417 * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
6418 * @param DMAx DMAx Instance
6419 * @param Channel This parameter can be one of the following values:
6420 * @arg @ref LL_DMA_CHANNEL_0
6421 * @arg @ref LL_DMA_CHANNEL_1
6422 * @arg @ref LL_DMA_CHANNEL_2
6423 * @arg @ref LL_DMA_CHANNEL_3
6424 * @arg @ref LL_DMA_CHANNEL_4
6425 * @arg @ref LL_DMA_CHANNEL_5
6426 * @arg @ref LL_DMA_CHANNEL_6
6427 * @arg @ref LL_DMA_CHANNEL_7
6428 * @arg @ref LL_DMA_CHANNEL_8
6429 * @arg @ref LL_DMA_CHANNEL_9
6430 * @arg @ref LL_DMA_CHANNEL_10
6431 * @arg @ref LL_DMA_CHANNEL_11
6432 * @arg @ref LL_DMA_CHANNEL_12
6433 * @arg @ref LL_DMA_CHANNEL_13
6434 * @arg @ref LL_DMA_CHANNEL_14
6435 * @arg @ref LL_DMA_CHANNEL_15
6436 * @retval State of bit (1 or 0).
6437 */
LL_DMA_IsEnabledIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)6438 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
6439 {
6440 uint32_t dma_base_addr = (uint32_t)DMAx;
6441 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
6442 == DMA_CCR_TOIE) ? 1UL : 0UL);
6443 }
6444
6445 /**
6446 * @brief Check if suspension interrupt is enabled.
6447 * @note This API is used for all available DMA channels.
6448 * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
6449 * @param DMAx DMAx Instance
6450 * @param Channel This parameter can be one of the following values:
6451 * @arg @ref LL_DMA_CHANNEL_0
6452 * @arg @ref LL_DMA_CHANNEL_1
6453 * @arg @ref LL_DMA_CHANNEL_2
6454 * @arg @ref LL_DMA_CHANNEL_3
6455 * @arg @ref LL_DMA_CHANNEL_4
6456 * @arg @ref LL_DMA_CHANNEL_5
6457 * @arg @ref LL_DMA_CHANNEL_6
6458 * @arg @ref LL_DMA_CHANNEL_7
6459 * @arg @ref LL_DMA_CHANNEL_8
6460 * @arg @ref LL_DMA_CHANNEL_9
6461 * @arg @ref LL_DMA_CHANNEL_10
6462 * @arg @ref LL_DMA_CHANNEL_11
6463 * @arg @ref LL_DMA_CHANNEL_12
6464 * @arg @ref LL_DMA_CHANNEL_13
6465 * @arg @ref LL_DMA_CHANNEL_14
6466 * @arg @ref LL_DMA_CHANNEL_15
6467 * @retval State of bit (1 or 0).
6468 */
LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)6469 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
6470 {
6471 uint32_t dma_base_addr = (uint32_t)DMAx;
6472 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
6473 == DMA_CCR_SUSPIE) ? 1UL : 0UL);
6474 }
6475
6476 /**
6477 * @brief Check if user setting error interrupt is enabled.
6478 * @note This API is used for all available DMA channels.
6479 * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
6480 * @param DMAx DMAx Instance
6481 * @param Channel This parameter can be one of the following values:
6482 * @arg @ref LL_DMA_CHANNEL_0
6483 * @arg @ref LL_DMA_CHANNEL_1
6484 * @arg @ref LL_DMA_CHANNEL_2
6485 * @arg @ref LL_DMA_CHANNEL_3
6486 * @arg @ref LL_DMA_CHANNEL_4
6487 * @arg @ref LL_DMA_CHANNEL_5
6488 * @arg @ref LL_DMA_CHANNEL_6
6489 * @arg @ref LL_DMA_CHANNEL_7
6490 * @arg @ref LL_DMA_CHANNEL_8
6491 * @arg @ref LL_DMA_CHANNEL_9
6492 * @arg @ref LL_DMA_CHANNEL_10
6493 * @arg @ref LL_DMA_CHANNEL_11
6494 * @arg @ref LL_DMA_CHANNEL_12
6495 * @arg @ref LL_DMA_CHANNEL_13
6496 * @arg @ref LL_DMA_CHANNEL_14
6497 * @arg @ref LL_DMA_CHANNEL_15
6498 * @retval State of bit (1 or 0).
6499 */
LL_DMA_IsEnabledIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)6500 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
6501 {
6502 uint32_t dma_base_addr = (uint32_t)DMAx;
6503 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
6504 == DMA_CCR_USEIE) ? 1UL : 0UL);
6505 }
6506
6507 /**
6508 * @brief Check if update link transfer error interrupt is enabled.
6509 * @note This API is used for all available DMA channels.
6510 * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
6511 * @param DMAx DMAx Instance
6512 * @param Channel This parameter can be one of the following values:
6513 * @arg @ref LL_DMA_CHANNEL_0
6514 * @arg @ref LL_DMA_CHANNEL_1
6515 * @arg @ref LL_DMA_CHANNEL_2
6516 * @arg @ref LL_DMA_CHANNEL_3
6517 * @arg @ref LL_DMA_CHANNEL_4
6518 * @arg @ref LL_DMA_CHANNEL_5
6519 * @arg @ref LL_DMA_CHANNEL_6
6520 * @arg @ref LL_DMA_CHANNEL_7
6521 * @arg @ref LL_DMA_CHANNEL_8
6522 * @arg @ref LL_DMA_CHANNEL_9
6523 * @arg @ref LL_DMA_CHANNEL_10
6524 * @arg @ref LL_DMA_CHANNEL_11
6525 * @arg @ref LL_DMA_CHANNEL_12
6526 * @arg @ref LL_DMA_CHANNEL_13
6527 * @arg @ref LL_DMA_CHANNEL_14
6528 * @arg @ref LL_DMA_CHANNEL_15
6529 * @retval State of bit (1 or 0).
6530 */
LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)6531 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
6532 {
6533 uint32_t dma_base_addr = (uint32_t)DMAx;
6534 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
6535 == DMA_CCR_ULEIE) ? 1UL : 0UL);
6536 }
6537
6538 /**
6539 * @brief Check if data transfer error interrupt is enabled.
6540 * @note This API is used for all available DMA channels.
6541 * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
6542 * @param DMAx DMAx Instance
6543 * @param Channel This parameter can be one of the following values:
6544 * @arg @ref LL_DMA_CHANNEL_0
6545 * @arg @ref LL_DMA_CHANNEL_1
6546 * @arg @ref LL_DMA_CHANNEL_2
6547 * @arg @ref LL_DMA_CHANNEL_3
6548 * @arg @ref LL_DMA_CHANNEL_4
6549 * @arg @ref LL_DMA_CHANNEL_5
6550 * @arg @ref LL_DMA_CHANNEL_6
6551 * @arg @ref LL_DMA_CHANNEL_7
6552 * @arg @ref LL_DMA_CHANNEL_8
6553 * @arg @ref LL_DMA_CHANNEL_9
6554 * @arg @ref LL_DMA_CHANNEL_10
6555 * @arg @ref LL_DMA_CHANNEL_11
6556 * @arg @ref LL_DMA_CHANNEL_12
6557 * @arg @ref LL_DMA_CHANNEL_13
6558 * @arg @ref LL_DMA_CHANNEL_14
6559 * @arg @ref LL_DMA_CHANNEL_15
6560 * @retval State of bit (1 or 0).
6561 */
LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)6562 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
6563 {
6564 uint32_t dma_base_addr = (uint32_t)DMAx;
6565 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
6566 == DMA_CCR_DTEIE) ? 1UL : 0UL);
6567 }
6568
6569 /**
6570 * @brief Check if half transfer complete interrupt is enabled.
6571 * @note This API is used for all available DMA channels.
6572 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
6573 * @param DMAx DMAx Instance
6574 * @param Channel This parameter can be one of the following values:
6575 * @arg @ref LL_DMA_CHANNEL_0
6576 * @arg @ref LL_DMA_CHANNEL_1
6577 * @arg @ref LL_DMA_CHANNEL_2
6578 * @arg @ref LL_DMA_CHANNEL_3
6579 * @arg @ref LL_DMA_CHANNEL_4
6580 * @arg @ref LL_DMA_CHANNEL_5
6581 * @arg @ref LL_DMA_CHANNEL_6
6582 * @arg @ref LL_DMA_CHANNEL_7
6583 * @arg @ref LL_DMA_CHANNEL_8
6584 * @arg @ref LL_DMA_CHANNEL_9
6585 * @arg @ref LL_DMA_CHANNEL_10
6586 * @arg @ref LL_DMA_CHANNEL_11
6587 * @arg @ref LL_DMA_CHANNEL_12
6588 * @arg @ref LL_DMA_CHANNEL_13
6589 * @arg @ref LL_DMA_CHANNEL_14
6590 * @arg @ref LL_DMA_CHANNEL_15
6591 * @retval State of bit (1 or 0).
6592 */
LL_DMA_IsEnabledIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)6593 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
6594 {
6595 uint32_t dma_base_addr = (uint32_t)DMAx;
6596 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
6597 == DMA_CCR_HTIE) ? 1UL : 0UL);
6598 }
6599
6600 /**
6601 * @brief Check if transfer complete interrupt is enabled.
6602 * @note This API is used for all available DMA channels.
6603 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
6604 * @param DMAx DMAx Instance
6605 * @param Channel This parameter can be one of the following values:
6606 * @arg @ref LL_DMA_CHANNEL_0
6607 * @arg @ref LL_DMA_CHANNEL_1
6608 * @arg @ref LL_DMA_CHANNEL_2
6609 * @arg @ref LL_DMA_CHANNEL_3
6610 * @arg @ref LL_DMA_CHANNEL_4
6611 * @arg @ref LL_DMA_CHANNEL_5
6612 * @arg @ref LL_DMA_CHANNEL_6
6613 * @arg @ref LL_DMA_CHANNEL_7
6614 * @arg @ref LL_DMA_CHANNEL_8
6615 * @arg @ref LL_DMA_CHANNEL_9
6616 * @arg @ref LL_DMA_CHANNEL_10
6617 * @arg @ref LL_DMA_CHANNEL_11
6618 * @arg @ref LL_DMA_CHANNEL_12
6619 * @arg @ref LL_DMA_CHANNEL_13
6620 * @arg @ref LL_DMA_CHANNEL_14
6621 * @arg @ref LL_DMA_CHANNEL_15
6622 * @retval State of bit (1 or 0).
6623 */
LL_DMA_IsEnabledIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)6624 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
6625 {
6626 uint32_t dma_base_addr = (uint32_t)DMAx;
6627 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
6628 == DMA_CCR_TCIE) ? 1UL : 0UL);
6629 }
6630 /**
6631 * @}
6632 */
6633
6634 #if defined (USE_FULL_LL_DRIVER)
6635 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
6636 * @{
6637 */
6638 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
6639 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
6640
6641 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
6642 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
6643 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
6644
6645 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
6646 LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
6647 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
6648
6649 uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
6650 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
6651 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
6652 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
6653 /**
6654 * @}
6655 */
6656 #endif /* USE_FULL_LL_DRIVER */
6657
6658 /**
6659 * @}
6660 */
6661
6662 /**
6663 * @}
6664 */
6665
6666 #endif /* GPDMA1 || HPDMA1 */
6667
6668 /**
6669 * @}
6670 */
6671
6672 #ifdef __cplusplus
6673 }
6674 #endif /* __cplusplus */
6675
6676 #endif /* STM32H7RSxx_LL_DMA_H */
6677
