1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 (+) Access to VREFBUF registers (not available on all devices)
28 @endverbatim
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32WBAxx_LL_SYSTEM_H
33 #define STM32WBAxx_LL_SYSTEM_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32wbaxx.h"
41
42 /** @addtogroup STM32WBAxx_LL_Driver
43 * @{
44 */
45
46 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
47
48 /** @defgroup SYSTEM_LL SYSTEM
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM LL Private Constants
57 * @{
58 */
59
60 /**
61 * @brief Power-down in Run mode Flash key
62 */
63 #define FLASH_PDKEY1_1 0x04152637U /*!< Flash power down key1 */
64 #define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEYR
65 to unlock the PDREQ bit in FLASH_ACR */
66 /**
67 * @}
68 */
69
70 /* Private macros ------------------------------------------------------------*/
71
72 /* Exported types ------------------------------------------------------------*/
73 /* Exported constants --------------------------------------------------------*/
74 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
75 * @{
76 */
77
78 /** @defgroup SYSTEM_LL_EC_CS1 SYSCFG SYSCFG Vdd compensation cell Code selection
79 * @{
80 */
81 #define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell (available in the SYSCFG_CCVR)*/
82 #define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/
83 /**
84 * @}
85 */
86
87 #ifdef SYSCFG_CCCSR_EN2
88 /** @defgroup SYSTEM_LL_EC_CS2 SYSCFG SYSCFG VddIO2 compensation cell Code selection
89 * @{
90 */
91 #define LL_SYSCFG_VDDIO2_CELL_CODE 0U /*VDDIO2 I/Os code from the cell (available in the SYSCFG_CCVR)*/
92 #define LL_SYSCFG_VDDIO2_REGISTER_CODE SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/
93 /**
94 * @}
95 */
96 #endif /* SYSCFG_CCCSR_EN2 */
97
98 /** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE
99 * @{
100 */
101 #define LL_SYSCFG_MEMORIES_ERASE_ON_GOING 0U /*Memory erase on going*/
102 #define LL_SYSCFG_MEMORIES_ERASE_ENDED SYSCFG_MESR_MCLR /*Memory erase done */
103 /**
104 * @}
105 */
106
107 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
108 * @{
109 */
110 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */
111 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */
112 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast Mode Plus on PA15 */
113 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast Mode Plus on PB3 */
114 /**
115 * @}
116 */
117
118 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
119 * @{
120 */
121 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
122 with Break Input of TIM1/16/17 */
123 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
124 with TIM1/16/17 Break Input and also
125 the PVDE and PLS bits of the Power Control Interface */
126 #define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal
127 with Break Input of TIM1/16/17 */
128 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33
129 with Break Input of TIM1/16/17 */
130 /**
131 * @}
132 */
133
134 /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
135 * @note Only available when system implements security (TZEN=1)
136 * @{
137 */
138 #define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */
139 #define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */
140 #define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
141 #define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
142 #define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
143 #define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
144 /**
145 * @}
146 */
147
148 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
149 * @{
150 */
151 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
152 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
153 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
154 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
155 #if defined(I2C1)
156 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
157 #endif /* I2C1 */
158 /**
159 * @}
160 */
161
162 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
163 * @{
164 */
165 #if defined(LPTIM2)
166 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
167 #endif /* LPTIM2 */
168 /**
169 * @}
170 */
171
172 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
173 * @{
174 */
175 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
176 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
177 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
178 /**
179 * @}
180 */
181
182 /** @defgroup SYSTEM_LL_EC_APB7_GRP1_STOP_IP DBGMCU APB7 GRP1 STOP IP
183 * @{
184 */
185 #define LL_DBGMCU_APB7_GRP1_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/
186 #define LL_DBGMCU_APB7_GRP1_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
187 #define LL_DBGMCU_APB7_GRP1_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/
188 /**
189 * @}
190 */
191
192 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
193 * @{
194 */
195 #define LL_FLASH_LATENCY_0 0 /*!< FLASH Zero wait state */
196 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */
197 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
198 #define LL_FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Three wait states */
199 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_2 /*!< FLASH Four wait states */
200 #define LL_FLASH_LATENCY_5 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Five wait state */
201 #define LL_FLASH_LATENCY_6 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Six wait state */
202 #define LL_FLASH_LATENCY_7 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Seven wait states */
203 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_3 /*!< FLASH Eight wait states */
204 #define LL_FLASH_LATENCY_9 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_0) /*!< FLASH Nine wait states */
205 #define LL_FLASH_LATENCY_10 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1) /*!< FLASH Ten wait state */
206 #define LL_FLASH_LATENCY_11 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Eleven wait state */
207 #define LL_FLASH_LATENCY_12 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2) /*!< FLASH Twelve wait states */
208 #define LL_FLASH_LATENCY_13 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Thirteen wait states */
209 #define LL_FLASH_LATENCY_14 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Fourteen wait states */
210 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY /*!< FLASH Fifteen wait states */
211 /**
212 * @}
213 */
214
215
216 /**
217 * @}
218 */
219
220 /* Exported macros -----------------------------------------------------------*/
221
222 /* Exported functions --------------------------------------------------------*/
223 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
224 * @{
225 */
226
227 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
228 * @{
229 */
230
231 /**
232 * @brief Enable I/O analog switch voltage booster.
233 * @note When voltage booster is enabled, I/O analog switches are supplied
234 * by a dedicated voltage booster, from VDD power domain. This is
235 * the recommended configuration with low VDDA voltage operation.
236 * @note The I/O analog switch voltage booster is relevant for peripherals
237 * using I/O in analog input: ADC, COMP, OPAMP.
238 * However, COMP and OPAMP inputs have a high impedance and
239 * voltage booster do not impact performance significantly.
240 * Therefore, the voltage booster is mainly intended for
241 * usage with ADC.
242 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
243 * @retval None
244 */
LL_SYSCFG_EnableAnalogBooster(void)245 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
246 {
247 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
248 }
249
250 /**
251 * @brief Disable I/O analog switch voltage booster.
252 * @note When voltage booster is enabled, I/O analog switches are supplied
253 * by a dedicated voltage booster, from VDD power domain. This is
254 * the recommended configuration with low VDDA voltage operation.
255 * @note The I/O analog switch voltage booster is relevant for peripherals
256 * using I/O in analog input: ADC, COMP, OPAMP.
257 * However, COMP and OPAMP inputs have a high impedance and
258 * voltage booster do not impact performance significantly.
259 * Therefore, the voltage booster is mainly intended for
260 * usage with ADC.
261 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
262 * @retval None
263 */
LL_SYSCFG_DisableAnalogBooster(void)264 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
265 {
266 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
267 }
268
269 /**
270 * @brief Enable the I2C fast mode plus driving capability.
271 * @rmtoll SYSCFG_CFGR1 I2C_PABx_FMP LL_SYSCFG_EnableFastModePlus\n
272 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
273 * @param ConfigFastModePlus This parameter can be a combination of the following values:
274 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA6
275 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA7
276 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA15
277 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB3
278 * @retval None
279 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)280 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
281 {
282 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
283 }
284
285 /**
286 * @brief Disable the I2C fast mode plus driving capability.
287 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
288 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
289 * @param ConfigFastModePlus This parameter can be a combination of the following values:
290 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA6
291 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA7
292 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA15
293 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB3
294 * @retval None
295 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)296 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
297 {
298 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
299 }
300
301 /**
302 * @brief Enable Floating Point Unit Invalid operation Interrupt
303 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
304 * @retval None
305 */
LL_SYSCFG_EnableIT_FPU_IOC(void)306 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
307 {
308 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
309 }
310
311 /**
312 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
313 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
314 * @retval None
315 */
LL_SYSCFG_EnableIT_FPU_DZC(void)316 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
317 {
318 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
319 }
320
321 /**
322 * @brief Enable Floating Point Unit Underflow Interrupt
323 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
324 * @retval None
325 */
LL_SYSCFG_EnableIT_FPU_UFC(void)326 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
327 {
328 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
329 }
330
331 /**
332 * @brief Enable Floating Point Unit Overflow Interrupt
333 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
334 * @retval None
335 */
LL_SYSCFG_EnableIT_FPU_OFC(void)336 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
337 {
338 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
339 }
340
341 /**
342 * @brief Enable Floating Point Unit Input denormal Interrupt
343 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
344 * @retval None
345 */
LL_SYSCFG_EnableIT_FPU_IDC(void)346 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
347 {
348 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
349 }
350
351 /**
352 * @brief Enable Floating Point Unit Inexact Interrupt
353 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
354 * @retval None
355 */
LL_SYSCFG_EnableIT_FPU_IXC(void)356 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
357 {
358 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
359 }
360
361 /**
362 * @brief Disable Floating Point Unit Invalid operation Interrupt
363 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
364 * @retval None
365 */
LL_SYSCFG_DisableIT_FPU_IOC(void)366 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
367 {
368 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
369 }
370
371 /**
372 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
373 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
374 * @retval None
375 */
LL_SYSCFG_DisableIT_FPU_DZC(void)376 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
377 {
378 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
379 }
380
381 /**
382 * @brief Disable Floating Point Unit Underflow Interrupt
383 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
384 * @retval None
385 */
LL_SYSCFG_DisableIT_FPU_UFC(void)386 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
387 {
388 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
389 }
390
391 /**
392 * @brief Disable Floating Point Unit Overflow Interrupt
393 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
394 * @retval None
395 */
LL_SYSCFG_DisableIT_FPU_OFC(void)396 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
397 {
398 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
399 }
400
401 /**
402 * @brief Disable Floating Point Unit Input denormal Interrupt
403 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
404 * @retval None
405 */
LL_SYSCFG_DisableIT_FPU_IDC(void)406 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
407 {
408 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
409 }
410
411 /**
412 * @brief Disable Floating Point Unit Inexact Interrupt
413 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
414 * @retval None
415 */
LL_SYSCFG_DisableIT_FPU_IXC(void)416 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
417 {
418 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
419 }
420
421 /**
422 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
423 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
424 * @retval State of bit (1 or 0).
425 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)426 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
427 {
428 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
429 }
430
431 /**
432 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
433 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
434 * @retval State of bit (1 or 0).
435 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)436 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
437 {
438 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
439 }
440
441 /**
442 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
443 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
444 * @retval State of bit (1 or 0).
445 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)446 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
447 {
448 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
449 }
450
451 /**
452 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
453 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
454 * @retval State of bit (1 or 0).
455 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)456 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
457 {
458 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
459 }
460
461 /**
462 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
463 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
464 * @retval State of bit (1 or 0).
465 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)466 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
467 {
468 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
469 }
470
471 /**
472 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
473 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
474 * @retval State of bit (1 or 0).
475 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)476 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
477 {
478 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
479 }
480
481 /**
482 * @brief Set connections to TIM1/8/15/16/17 Break inputs
483 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
484 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
485 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
486 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
487 * @param Break This parameter can be a combination of the following values:
488 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
489 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
490 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
491 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
492 * @retval None
493 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)494 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
495 {
496 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
497 }
498
499 /**
500 * @brief Get connections to TIM1/8/15/16/17 Break inputs
501 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
502 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
503 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
504 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
505 * @retval Returned value can be can be a combination of the following values:
506 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
507 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
508 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
509 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
510 */
LL_SYSCFG_GetTIMBreakInputs(void)511 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
512 {
513 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
514 }
515
516 /**
517 * @}
518 */
519
520 /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management
521 * @{
522 */
523
524 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
525
526 /**
527 * @brief Configure Secure mode
528 * @note Only available from secure state when system implements security (TZEN=1)
529 * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
530 * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
531 * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
532 * @param Configuration This parameter shall be the full combination
533 * of the following values:
534 * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
535 * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
536 * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
537 * @retval None
538 */
LL_SYSCFG_ConfigSecure(uint32_t Configuration)539 __STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration)
540 {
541 WRITE_REG(SYSCFG->SECCFGR, Configuration);
542 }
543
544 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
545
546 /**
547 * @brief Get Secure mode configuration
548 * @note Only available when system implements security (TZEN=1)
549 * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
550 * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
551 * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
552 * @retval Returned value is the combination of the following values:
553 * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
554 * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
555 * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
556 */
LL_SYSCFG_GetConfigSecure(void)557 __STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void)
558 {
559 return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU));
560 }
561
562 /**
563 * @}
564 */
565
566 /** @defgroup SYSTEM_LL_EF_SYSCFG_ERASE_MEMORIE_STATUS SYSCFG ERASE MEMORIE STATUS
567 * @{
568 */
569
570 /**
571 * @brief Clear Status of End of Erase for ICACHE and PKA RAMs
572 * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus
573 * @retval None
574 */
LL_SYSCFG_ClearEraseEndStatus(void)575 __STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void)
576 {
577 SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE);
578 }
579
580 /**
581 * @brief Get Status of End of Erase for ICACHE and PKA RAMs
582 * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus
583 * @retval Returned value can be one of the following values:
584 * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
585 * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
586 */
LL_SYSCFG_GetEraseEndStatus(void)587 __STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void)
588 {
589 return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE));
590 }
591
592
593 /**
594 * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
595 * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus
596 * @retval None
597 */
LL_SYSCFG_ClearEraseAfterResetStatus(void)598 __STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void)
599 {
600 SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR);
601 }
602
603 /**
604 * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
605 * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus
606 * @retval Returned value can be one of the following values:
607 * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
608 * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
609 */
LL_SYSCFG_GetEraseAfterResetStatus(void)610 __STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void)
611 {
612 return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR));
613 }
614 /**
615 * @}
616 */
617
618 /** @defgroup SYSTEM_LL_EF_SYSCFG_COMPENSATION SYSCFG COMPENSATION
619 * @{
620 */
621
622 /**
623 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD
624 * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue
625 * @retval Returned value is the PMOS compensation cell
626 */
LL_SYSCFG_GetPMOSVddCompensationValue(void)627 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void)
628 {
629 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1));
630 }
631
632 /**
633 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD
634 * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue
635 * @retval Returned value is the NMOS compensation cell
636 */
LL_SYSCFG_GetNMOSVddCompensationValue(void)637 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void)
638 {
639 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1));
640 }
641
642
643 /**
644 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD
645 * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode
646 * @param PMOSCode PMOS compensation code
647 * This code is applied to the PMOS compensation cell when the CS1 bit of the
648 * SYSCFG_CCCSR is set
649 * @retval None
650 */
LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)651 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)
652 {
653 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos);
654 }
655
656 /**
657 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD
658 * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode
659 * @retval Returned value is the PMOS compensation cell
660 */
LL_SYSCFG_GetPMOSVddCompensationCode(void)661 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void)
662 {
663 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1));
664 }
665
666 /**
667 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD
668 * @rmtoll CCCR NCC1 LL_SYSCFG_SetNMOSVddCompensationCode
669 * @param NMOSCode NMOS compensation code
670 * This code is applied to the NMOS compensation cell when the CS1 bit of the
671 * SYSCFG_CCCSR is set
672 * @retval None
673 */
LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)674 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)
675 {
676 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos);
677 }
678
679 /**
680 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD
681 * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode
682 * @retval Returned value is the Vdd compensation cell code for NMOS transistors
683 */
LL_SYSCFG_GetNMOSVddCompensationCode(void)684 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void)
685 {
686 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1));
687 }
688
689 /**
690 * @brief Enable the Compensation Cell of GPIO supplied by VDD
691 * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell
692 * @note The vdd compensation cell can be used only when the device supply
693 * voltage ranges from 1.71 to 3.6 V
694 * @retval None
695 */
LL_SYSCFG_EnableVddCompensationCell(void)696 __STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void)
697 {
698 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
699 }
700
701 /**
702 * @brief Disable the Compensation Cell of GPIO supplied by VDD
703 * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell
704 * @note The Vdd compensation cell can be used only when the device supply
705 * voltage ranges from 1.71 to 3.6 V
706 * @retval None
707 */
LL_SYSCFG_DisableVddCompensationCell(void)708 __STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void)
709 {
710 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
711 }
712
713 /**
714 * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable
715 * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell
716 * @retval State of bit (1 or 0).
717 */
LL_SYSCFG_IsEnabled_VddCompensationCell(void)718 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void)
719 {
720 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL);
721 }
722
723 /**
724 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD
725 * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR
726 * @retval State of bit (1 or 0).
727 */
LL_SYSCFG_IsActiveFlag_VddCMPCR(void)728 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void)
729 {
730 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL);
731 }
732
733 /**
734 * @brief Set the compensation cell code selection of GPIO supplied by VDD
735 * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode
736 * @param CompCode: Selects the code to be applied for the Vdd compensation cell
737 * This parameter can be one of the following values:
738 * @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
739 * @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
740 * @retval None
741 */
LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)742 __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)
743 {
744 MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1, CompCode);
745 }
746
747 /**
748 * @brief Get the compensation cell code selection of GPIO supplied by VDD
749 * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode
750 * @retval Returned value can be one of the following values:
751 * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
752 * @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
753 */
LL_SYSCFG_GetVddCellCompensationCode(void)754 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void)
755 {
756 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1));
757 }
758
759 #ifdef SYSCFG_CCCSR_EN2
760 /**
761 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2
762 * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue
763 * @retval Returned value is the PMOS compensation cell
764 */
LL_SYSCFG_GetPMOSVddIO2CompensationValue(void)765 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void)
766 {
767 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2));
768 }
769
770 /**
771 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2
772 * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue
773 * @retval Returned value is the NMOS compensation cell
774 */
LL_SYSCFG_GetNMOSVddIO2CompensationValue(void)775 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void)
776 {
777 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2));
778 }
779
780
781 /**
782 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2
783 * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode
784 * @param PMOSCode PMOS compensation code
785 * This code is applied to the PMOS compensation cell when the CS2 bit of the
786 * SYSCFG_CCCSR is set
787 * @retval None
788 */
LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode)789 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode)
790 {
791 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos);
792 }
793
794 /**
795 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2
796 * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode
797 * @retval Returned value is the PMOS compensation cell
798 */
LL_SYSCFG_GetPMOSVddIO2CompensationCode(void)799 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void)
800 {
801 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2));
802 }
803
804 /**
805 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2
806 * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode
807 * @param NMOSCode NMOS compensation code
808 * This code is applied to the NMOS compensation cell when the CS2 bit of the
809 * SYSCFG_CCCSR is set
810 * @retval None
811 */
LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode)812 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode)
813 {
814 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos);
815 }
816
817 /**
818 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2
819 * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode
820 * @retval Returned value is the VddIO2 compensation cell code for NMOS transistors
821 */
LL_SYSCFG_GetNMOSVddIO2CompensationCode(void)822 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void)
823 {
824 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2));
825 }
826
827 /**
828 * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2
829 * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell
830 * @note The VddIO2 compensation cell can be used only when the device supply
831 * voltage ranges from 1.71 to 3.6 V
832 * @retval None
833 */
LL_SYSCFG_EnableVddIO2CompensationCell(void)834 __STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void)
835 {
836 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
837 }
838
839 /**
840 * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2
841 * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell
842 * @note The VddIO2 compensation cell can be used only when the device supply
843 * voltage ranges from 1.71 to 3.6 V
844 * @retval None
845 */
LL_SYSCFG_DisableVddIO2CompensationCell(void)846 __STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void)
847 {
848 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
849 }
850
851 /**
852 * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable
853 * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell
854 * @retval State of bit (1 or 0).
855 */
LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void)856 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void)
857 {
858 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL);
859 }
860
861 /**
862 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2
863 * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR
864 * @retval State of bit (1 or 0).
865 */
LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void)866 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void)
867 {
868 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL);
869 }
870
871 /**
872 * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2
873 * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode
874 * @param CompCode: Selects the code to be applied for the VddIO2 compensation cell
875 * This parameter can be one of the following values:
876 * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
877 * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
878 * @retval None
879 */
LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode)880 __STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode)
881 {
882 MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2, CompCode);
883 }
884
885 /**
886 * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2
887 * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode
888 * @retval Returned value can be one of the following values:
889 * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
890 * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
891 */
LL_SYSCFG_GetVddIO2CellCompensationCode(void)892 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void)
893 {
894 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2));
895 }
896 #endif /* SYSCFG_CCCSR_EN2 */
897
898 /**
899 * @}
900 */
901
902 /**
903 * @}
904 */
905
906 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
907 * @{
908 */
909
910 /**
911 * @brief Return the device identifier
912 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
913 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
914 */
LL_DBGMCU_GetDeviceID(void)915 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
916 {
917 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
918 }
919
920 /**
921 * @brief Return the device revision identifier
922 * @note This field indicates the revision of the device.
923 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
924 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
925 */
LL_DBGMCU_GetRevisionID(void)926 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
927 {
928 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
929 }
930
931 /**
932 * @brief Enable the Debug Module during STOP mode
933 * @rmtoll DBGMCU_SCR DBG_STOP LL_DBGMCU_EnableDBGStopMode
934 * @retval None
935 */
LL_DBGMCU_EnableDBGStopMode(void)936 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
937 {
938 SET_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STOP);
939 }
940
941 /**
942 * @brief Disable the Debug Module during STOP mode
943 * @rmtoll DBGMCU_SCR DBG_STOP LL_DBGMCU_DisableDBGStopMode
944 * @retval None
945 */
LL_DBGMCU_DisableDBGStopMode(void)946 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
947 {
948 CLEAR_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STOP);
949 }
950
951 /**
952 * @brief Enable the Debug Module during STANDBY mode
953 * @rmtoll DBGMCU_SCR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
954 * @retval None
955 */
LL_DBGMCU_EnableDBGStandbyMode(void)956 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
957 {
958 SET_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STANDBY);
959 }
960
961 /**
962 * @brief Disable the Debug Module during STANDBY mode
963 * @rmtoll DBGMCU_SCR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
964 * @retval None
965 */
LL_DBGMCU_DisableDBGStandbyMode(void)966 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
967 {
968 CLEAR_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STANDBY);
969 }
970
971 /**
972 * @brief Freeze APB1 peripherals (group1 peripherals)
973 * @rmtoll DBGMCU_APB1LFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
974 * @param Periphs This parameter can be a combination of the following values:
975 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
976 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
977 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
978 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
979 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
980 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
981 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
982 *
983 * (*) value not defined in all devices.
984 * @retval None
985 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)986 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
987 {
988 SET_BIT(DBGMCU->APB1LFZR, Periphs);
989 }
990
991 /**
992 * @brief Freeze APB1 peripherals (group2 peripherals)
993 * @rmtoll DBGMCU_APB1HFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
994 * @param Periphs This parameter can be a combination of the following values:
995 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
996 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
997 *
998 * (*) value not defined in all devices.
999 * @retval None
1000 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1001 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1002 {
1003 SET_BIT(DBGMCU->APB1HFZR, Periphs);
1004 }
1005
1006 /**
1007 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1008 * @rmtoll DBGMCU_APB1LFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1009 * @param Periphs This parameter can be a combination of the following values:
1010 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1011 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1012 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1013 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1014 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1015 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1016 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1017 *
1018 * (*) value not defined in all devices.
1019 * @retval None
1020 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1021 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1022 {
1023 CLEAR_BIT(DBGMCU->APB1LFZR, Periphs);
1024 }
1025
1026 /**
1027 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1028 * @rmtoll DBGMCU_APB1HFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1029 * @param Periphs This parameter can be a combination of the following values:
1030 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1031 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1032 *
1033 * (*) value not defined in all devices.
1034 * @retval None
1035 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1036 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1037 {
1038 CLEAR_BIT(DBGMCU->APB1HFZR, Periphs);
1039 }
1040
1041 /**
1042 * @brief Freeze APB2 peripherals
1043 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1044 * @param Periphs This parameter can be a combination of the following values:
1045 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1046 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1047 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1048 * @retval None
1049 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1050 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1051 {
1052 SET_BIT(DBGMCU->APB2FZR, Periphs);
1053 }
1054
1055 /**
1056 * @brief Unfreeze APB2 peripherals
1057 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1058 * @param Periphs This parameter can be a combination of the following values:
1059 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1060 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1061 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1062 * @retval None
1063 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1064 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1065 {
1066 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1067 }
1068
1069 /**
1070 * @brief Freeze APB7 peripherals
1071 * @rmtoll DBGMCU_APB7FZ DBG_TIMx_STOP LL_DBGMCU_APB7_GRP1_FreezePeriph
1072 * @param Periphs This parameter can be a combination of the following values:
1073 * @arg @ref LL_DBGMCU_APB7_GRP1_I2C3_STOP
1074 * @arg @ref LL_DBGMCU_APB7_GRP1_LPTIM1_STOP
1075 * @arg @ref LL_DBGMCU_APB7_GRP1_RTC_STOP
1076 * @retval None
1077 */
LL_DBGMCU_APB7_GRP1_FreezePeriph(uint32_t Periphs)1078 __STATIC_INLINE void LL_DBGMCU_APB7_GRP1_FreezePeriph(uint32_t Periphs)
1079 {
1080 SET_BIT(DBGMCU->APB7FZR, Periphs);
1081 }
1082
1083 /**
1084 * @brief Unfreeze APB7 peripherals
1085 * @rmtoll DBGMCU_APB7FZR DBG_TIMx_STOP LL_DBGMCU_APB7_GRP1_UnFreezePeriph
1086 * @param Periphs This parameter can be a combination of the following values:
1087 * @arg @ref LL_DBGMCU_APB7_GRP1_I2C3_STOP
1088 * @arg @ref LL_DBGMCU_APB7_GRP1_LPTIM1_STOP
1089 * @arg @ref LL_DBGMCU_APB7_GRP1_RTC_STOP
1090 * @retval None
1091 */
LL_DBGMCU_APB7_GRP1_UnFreezePeriph(uint32_t Periphs)1092 __STATIC_INLINE void LL_DBGMCU_APB7_GRP1_UnFreezePeriph(uint32_t Periphs)
1093 {
1094 CLEAR_BIT(DBGMCU->APB7FZR, Periphs);
1095 }
1096
1097 /**
1098 * @}
1099 */
1100
1101
1102
1103 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1104 * @{
1105 */
1106 /**
1107 * @brief Set FLASH Latency
1108 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1109 * @param Latency This parameter can be one of the following values:
1110 * @arg @ref LL_FLASH_LATENCY_0
1111 * @arg @ref LL_FLASH_LATENCY_1
1112 * @arg @ref LL_FLASH_LATENCY_2
1113 * @arg @ref LL_FLASH_LATENCY_3
1114 * @arg @ref LL_FLASH_LATENCY_4
1115 * @arg @ref LL_FLASH_LATENCY_5
1116 * @arg @ref LL_FLASH_LATENCY_6
1117 * @arg @ref LL_FLASH_LATENCY_7
1118 * @arg @ref LL_FLASH_LATENCY_8
1119 * @arg @ref LL_FLASH_LATENCY_9
1120 * @arg @ref LL_FLASH_LATENCY_10
1121 * @arg @ref LL_FLASH_LATENCY_11
1122 * @arg @ref LL_FLASH_LATENCY_12
1123 * @arg @ref LL_FLASH_LATENCY_13
1124 * @arg @ref LL_FLASH_LATENCY_14
1125 * @arg @ref LL_FLASH_LATENCY_15
1126 * @retval None
1127 */
LL_FLASH_SetLatency(uint32_t Latency)1128 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1129 {
1130 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1131 }
1132
1133 /**
1134 * @brief Get FLASH Latency
1135 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1136 * @retval Returned value can be one of the following values:
1137 * @arg @ref LL_FLASH_LATENCY_0
1138 * @arg @ref LL_FLASH_LATENCY_1
1139 * @arg @ref LL_FLASH_LATENCY_2
1140 * @arg @ref LL_FLASH_LATENCY_3
1141 * @arg @ref LL_FLASH_LATENCY_4
1142 * @arg @ref LL_FLASH_LATENCY_5
1143 * @arg @ref LL_FLASH_LATENCY_6
1144 * @arg @ref LL_FLASH_LATENCY_7
1145 * @arg @ref LL_FLASH_LATENCY_8
1146 * @arg @ref LL_FLASH_LATENCY_9
1147 * @arg @ref LL_FLASH_LATENCY_10
1148 * @arg @ref LL_FLASH_LATENCY_11
1149 * @arg @ref LL_FLASH_LATENCY_12
1150 * @arg @ref LL_FLASH_LATENCY_13
1151 * @arg @ref LL_FLASH_LATENCY_14
1152 * @arg @ref LL_FLASH_LATENCY_15
1153 */
LL_FLASH_GetLatency(void)1154 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1155 {
1156 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1157 }
1158
1159 /**
1160 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1161 * @note Flash memory can be put in power-down mode only when the code is executed
1162 * from RAM
1163 * @note Flash must not be accessed when power down is enabled
1164 * @note Flash must not be put in power-down while a program or an erase operation
1165 * is on-going
1166 * @rmtoll FLASH_ACR PDREQ LL_FLASH_EnableRunPowerDown\n
1167 * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n
1168 * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown
1169 * @retval None
1170 */
LL_FLASH_EnableRunPowerDown(void)1171 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1172 {
1173 /* Following values must be written consecutively to unlock the PDREQ bit in
1174 FLASH_ACR */
1175 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_1);
1176 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_2);
1177
1178 /*Request to enter flash in power mode */
1179 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ);
1180 }
1181
1182 /**
1183 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1184 * @note Flash must not be put in power-down while a program or an erase operation
1185 * is on-going
1186 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1187 * @retval None
1188 */
LL_FLASH_EnableSleepPowerDown(void)1189 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1190 {
1191 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1192 }
1193
1194 /**
1195 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1196 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1197 * @retval None
1198 */
LL_FLASH_DisableSleepPowerDown(void)1199 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1200 {
1201 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1202 }
1203
1204 /**
1205 * @brief Return the Unique Device Number
1206 * @retval Values between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1207 */
LL_FLASH_GetUDN(void)1208 __STATIC_INLINE uint32_t LL_FLASH_GetUDN(void)
1209 {
1210 return (READ_REG(*((uint32_t *)UID64_BASE)));
1211 }
1212
1213 /**
1214 * @brief Return the Device ID
1215 * For STM32WBA52xx devices, the device ID is 0x2A
1216 * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x2A)
1217 */
LL_FLASH_GetDeviceID(void)1218 __STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void)
1219 {
1220 return ((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU);
1221 }
1222
1223 /**
1224 * @brief Return the ST Company ID
1225 * @note For STM32WBAxxxx devices, the ST Company ID is 0x0080E1
1226 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Company ID is 0x0080E1)
1227 */
LL_FLASH_GetSTCompanyID(void)1228 __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void)
1229 {
1230 return (((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U) & 0x00FFFFFFU);
1231 }
1232 /**
1233 * @}
1234 */
1235
1236
1237
1238 /**
1239 * @}
1240 */
1241
1242 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1243
1244 /**
1245 * @}
1246 */
1247
1248 #ifdef __cplusplus
1249 }
1250 #endif
1251
1252 #endif /* STM32WBAxx_LL_SYSTEM_H */
1253
1254
