1 /**
2   ******************************************************************************
3   * @file    stm32n6xx_ll_cacheaxi.h
4   * @author  MCD Application Team
5   * @brief   Header file of CACHEAXI LL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2023 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion ------------------------------------*/
20 #ifndef STM32N6xx_LL_CACHEAXI_H
21 #define STM32N6xx_LL_CACHEAXI_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes -----------------------------------------------------------------*/
28 #include "stm32n6xx.h"
29 
30 /** @addtogroup STM32N6xx_LL_Driver
31   * @{
32   */
33 
34 /** @defgroup CACHEAXI_LL CACHEAXI
35   * @{
36   */
37 
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /** @defgroup CACHEAXI_Exported_Constants CACHEAXI Exported Constants
42   * @{
43   */
44 /** @defgroup CACHEAXI_Command_Operation Command Operation
45   * @{
46   */
47 #define LL_CACHEAXI_COMMAND_NO_OPERATION                    (0x00000000)
48 #define LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR                   CACHEAXI_CR2_CACHECMD_0
49 #define LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR        (CACHEAXI_CR2_CACHECMD_0|CACHEAXI_CR2_CACHECMD_1)
50 /**
51   * @}
52   */
53 
54 /** @defgroup CACHEAXI_LL_EC_GET_FLAG Get Flags Defines
55   * @brief    Flags defines which can be used with LL_CACHEAXI_ReadReg function
56   * @{
57   */
58 #define LL_CACHEAXI_SR_ERRF              CACHEAXI_SR_ERRF      /*!< Cache error flag */
59 #define LL_CACHEAXI_SR_BUSYF             CACHEAXI_SR_BUSYF     /*!< Busy flag */
60 #define LL_CACHEAXI_SR_CMDENDF           CACHEAXI_SR_CMDENDF   /*!< Command end flag */
61 #define LL_CACHEAXI_SR_BSYENDF           CACHEAXI_SR_BSYENDF   /*!< Full invalidate busy end flag */
62 #define LL_CACHEAXI_SR_BUSYCMDF          CACHEAXI_SR_BUSYCMDF  /*!< Command busy flag */
63 /**
64   * @}
65   */
66 
67 /** @defgroup CACHEAXI_LL_EC_CLEAR_FLAG Clear Flags Defines
68   * @brief    Flags defines which can be used with LL_CACHEAXI_WriteReg function
69   * @{
70   */
71 #define LL_CACHEAXI_FCR_CERRF            CACHEAXI_FCR_CERRF    /*!< Cache error flag */
72 #define LL_CACHEAXI_FCR_CBSYENDF         CACHEAXI_FCR_CBSYENDF /*!< Full invalidate busy end flag */
73 #define LL_CACHEAXI_FCR_CCMDENDF         CACHEAXI_FCR_CCMDENDF /*!< Command end flag*/
74 /**
75   * @}
76   */
77 
78 /** @defgroup CACHEAXI_LL_EC_IT IT Defines
79   * @brief    IT defines which can be used with LL_CACHEAXI_ReadReg and  LL_CACHEAXI_WriteReg functions
80   * @{
81   */
82 #define LL_CACHEAXI_IER_BSYENDIE         CACHEAXI_IER_BSYENDIE /*!< Busy end interrupt */
83 #define LL_CACHEAXI_IER_ERRIE            CACHEAXI_IER_ERRIE    /*!< Cache error interrupt */
84 #define LL_CACHEAXI_IER_CMDENDIE         CACHEAXI_IER_CMDENDIE /*!< Command end interrupt */
85 /**
86   * @}
87   */
88 
89 /** @defgroup CACHEAXI_Monitor_Type Monitor type
90   * @{
91   */
92 #define LL_CACHEAXI_MONITOR_READ_HIT         CACHEAXI_CR1_RHITMEN   /*!< Read Hit monitoring */
93 #define LL_CACHEAXI_MONITOR_READ_MISS        CACHEAXI_CR1_RMISSMEN  /*!< Read Miss monitoring */
94 #define LL_CACHEAXI_MONITOR_WRITE_HIT        CACHEAXI_CR1_WHITMEN   /*!< Write Hit monitoring */
95 #define LL_CACHEAXI_MONITOR_WRITE_MISS       CACHEAXI_CR1_WMISSMEN  /*!< Write Miss monitoring */
96 #define LL_CACHEAXI_MONITOR_READALLOC_MISS   CACHEAXI_CR1_RAMMEN /*!< Read-alloc Miss monitoring */
97 #define LL_CACHEAXI_MONITOR_WRITEALLOC_MISS  CACHEAXI_CR1_WAMMEN /*!< Write-alloc Miss monitoring */
98 #define LL_CACHEAXI_MONITOR_WRITETHROUGH     CACHEAXI_CR1_WTMEN     /*!< Write-through monitoring */
99 #define LL_CACHEAXI_MONITOR_EVICTION         CACHEAXI_CR1_EVIMEN    /*!< Eviction monitoring */
100 #define LL_CACHEAXI_MONITOR_ALL             (CACHEAXI_CR1_RHITMEN | CACHEAXI_CR1_RMISSMEN   \
101                                              | CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_WMISSMEN \
102                                              | CACHEAXI_CR1_RAMMEN  | CACHEAXI_CR1_WAMMEN   \
103                                              | CACHEAXI_CR1_WTMEN   | CACHEAXI_CR1_EVIMEN)
104 /**
105   * @}
106   */
107 
108 /**
109   * @}
110   */
111 
112 /* Exported macros --------------------------------------------------------*/
113 /** @defgroup CACHEAXI_LL_Exported_Macros CACHEAXI Exported Macros
114   * @{
115   */
116 
117 /** @defgroup CACHEAXI_LL_EM_WRITE_READ Common write and read registers Macros
118   * @{
119   */
120 
121 /**
122   * @brief  Write a value in CACHEAXI register
123   * @param  __INSTANCE__ CACHEAXI Instance
124   * @param  __REG__ Register to be written
125   * @param  __VALUE__ Value to be written in the register
126   * @retval None
127   */
128 #define LL_CACHEAXI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
129 
130 /**
131   * @brief  Read a value in CACHEAXI register
132   * @param  __INSTANCE__ CACHEAXI Instance
133   * @param  __REG__ Register to be read
134   * @retval Register value
135   */
136 #define LL_CACHEAXI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
137 /**
138   * @}
139   */
140 
141 /**
142   * @}
143   */
144 
145 /* Exported functions --------------------------------------------------------*/
146 /** @defgroup CACHEAXI_LL_Exported_Functions CACHEAXI Exported Functions
147   * @{
148   */
149 
150 /** @defgroup CACHEAXI_LL_EF_Configuration Configuration
151   * @{
152   */
153 
154 /**
155   * @brief  Enable the selected CACHEAXI instance.
156   * @rmtoll CR1       EN           LL_CACHEAXI_Enable
157   * @param  CACHEAXIx CACHEAXI instance
158   * @retval None
159   */
LL_CACHEAXI_Enable(CACHEAXI_TypeDef * CACHEAXIx)160 __STATIC_INLINE void LL_CACHEAXI_Enable(CACHEAXI_TypeDef *CACHEAXIx)
161 {
162   SET_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN);
163 }
164 
165 /**
166   * @brief  Disable the selected CACHEAXI instance.
167   * @rmtoll CR1       EN           LL_CACHEAXI_Disable
168   * @param  CACHEAXIx CACHEAXI instance
169   * @retval None
170   */
LL_CACHEAXI_Disable(CACHEAXI_TypeDef * CACHEAXIx)171 __STATIC_INLINE void LL_CACHEAXI_Disable(CACHEAXI_TypeDef *CACHEAXIx)
172 {
173   CLEAR_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN);
174 }
175 
176 /**
177   * @brief  Get the selected CACHEAXI instance enable state.
178   * @rmtoll CR1       EN           LL_CACHEAXI_IsEnabled
179   * @param  CACHEAXIx CACHEAXI instance
180   * @retval 0: CACHEAXI is disabled, 1: CACHEAXI is enabled.
181   */
LL_CACHEAXI_IsEnabled(const CACHEAXI_TypeDef * CACHEAXIx)182 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabled(const CACHEAXI_TypeDef *CACHEAXIx)
183 {
184   return ((READ_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN) == (CACHEAXI_CR1_EN)) ? 1UL : 0UL);
185 }
186 
187 /**
188   * @brief  Set the cacheaxi instance start command address.
189   * @rmtoll CR2       CMDRSADDRR          LL_CACHEAXI_SetStartAddress
190   * @param  addr cacheaxi command start address(Clean, Invalidate or Clean and Invalidate).
191   * @param  CACHEAXIx CACHEAXI instance
192   * @retval None
193   */
LL_CACHEAXI_SetStartAddress(CACHEAXI_TypeDef * CACHEAXIx,uint32_t addr)194 __STATIC_INLINE void LL_CACHEAXI_SetStartAddress(CACHEAXI_TypeDef *CACHEAXIx, uint32_t addr)
195 {
196   WRITE_REG(CACHEAXIx->CMDRSADDRR, addr);
197 }
198 
199 /**
200   * @brief  Get the cacheaxi command start address.
201   * @rmtoll CR2       CMDRSADDRR         LL_CACHEAXI_GetStartAddress
202   * @param  CACHEAXIx CACHEAXI instance
203   * @retval Start address of cacheaxi command
204   */
LL_CACHEAXI_GetStartAddress(const CACHEAXI_TypeDef * CACHEAXIx)205 __STATIC_INLINE uint32_t LL_CACHEAXI_GetStartAddress(const CACHEAXI_TypeDef *CACHEAXIx)
206 {
207   return (uint32_t)(READ_REG(CACHEAXIx->CMDRSADDRR));
208 }
209 
210 /**
211   * @brief  Set the cacheaxi instance End command address.
212   * @rmtoll CR2       CMDREADDRR          LL_CACHEAXI_SetEndAddress
213   * @param  CACHEAXIx CACHEAXI instance
214   * @param  addr cacheaxi command end address(Clean, Invalidate or Clean and Invalidate).
215   * @retval None
216   */
LL_CACHEAXI_SetEndAddress(CACHEAXI_TypeDef * CACHEAXIx,uint32_t addr)217 __STATIC_INLINE void LL_CACHEAXI_SetEndAddress(CACHEAXI_TypeDef *CACHEAXIx, uint32_t addr)
218 {
219   WRITE_REG(CACHEAXIx->CMDREADDRR, addr);
220 }
221 
222 /**
223   * @brief  Get the cacheaxi command End address.
224   * @rmtoll CR2       CMDREADDRR          LL_CACHEAXI_GetEndAddress
225   * @param  CACHEAXIx CACHEAXI instance
226   * @retval End address of cacheaxi command
227   */
LL_CACHEAXI_GetEndAddress(const CACHEAXI_TypeDef * CACHEAXIx)228 __STATIC_INLINE uint32_t LL_CACHEAXI_GetEndAddress(const CACHEAXI_TypeDef *CACHEAXIx)
229 {
230   return (uint32_t)(READ_REG(CACHEAXIx->CMDREADDRR));
231 }
232 
233 /**
234   * @brief  Set Dcache command.
235   * @rmtoll CR2       CACHECMD          LL_CACHEAXI_SetCommand
236   * @param  CACHEAXIx CACHEAXI instance
237   * @param  Command command to be applied for the cacheaxi
238   *         Command can be one of the following values:
239   *         @arg @ref LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR
240   *         @arg @ref LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR
241   *         @arg @ref LL_CACHEAXI_COMMAND_NO_OPERATION
242   * @retval None
243   */
LL_CACHEAXI_SetCommand(CACHEAXI_TypeDef * CACHEAXIx,uint32_t Command)244 __STATIC_INLINE void LL_CACHEAXI_SetCommand(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Command)
245 {
246   /* Set cacheaxi command */
247   MODIFY_REG(CACHEAXIx->CR2, CACHEAXI_CR2_CACHECMD, Command);
248 }
249 
250 /**
251   * @brief  Set Dcache command.
252   * @rmtoll CR2       CACHECMD          LL_CACHEAXI_GetCommand
253   * @param  CACHEAXIx CACHEAXI instance
254   * @retval Returned value can be one of the following values:
255   *         @arg @ref LL_CACHEAXI_COMMAND_NO_OPERATION
256   *         @arg @ref LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR
257   *         @arg @ref LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR
258   */
LL_CACHEAXI_GetCommand(const CACHEAXI_TypeDef * CACHEAXIx)259 __STATIC_INLINE uint32_t LL_CACHEAXI_GetCommand(const CACHEAXI_TypeDef *CACHEAXIx)
260 {
261   /*Get Dcache Command */
262   return (uint32_t)(READ_BIT(CACHEAXIx->CR2, CACHEAXI_CR2_CACHECMD));
263 }
264 
265 /**
266   * @brief  Launch Dcache Command.
267   * @rmtoll CR2       CACHECMD          LL_CACHEAXI_StartCommand
268   * @param  CACHEAXIx CACHEAXI instance
269   * @retval None
270   */
LL_CACHEAXI_StartCommand(CACHEAXI_TypeDef * CACHEAXIx)271 __STATIC_INLINE void LL_CACHEAXI_StartCommand(CACHEAXI_TypeDef *CACHEAXIx)
272 {
273   SET_BIT(CACHEAXIx->CR2, CACHEAXI_CR2_STARTCMD);
274 }
275 
276 /**
277   * @brief  Invalidate the Data cache.
278   * @rmtoll CR1       CACHEINV          LL_CACHEAXI_Invalidate
279   * @param  CACHEAXIx CACHEAXI instance
280   * @retval None
281   */
LL_CACHEAXI_Invalidate(CACHEAXI_TypeDef * CACHEAXIx)282 __STATIC_INLINE void LL_CACHEAXI_Invalidate(CACHEAXI_TypeDef *CACHEAXIx)
283 {
284   SET_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_CACHEINV);
285 }
286 
287 /**
288   * @}
289   */
290 
291 
292 /** @defgroup CACHEAXI_LL_EF_Monitor Monitor
293   * @{
294   */
295 
296 /**
297   * @brief  Enable the hit/miss monitor(s).
298   * @rmtoll CR1  (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN)   LL_CACHEAXI_EnableMonitors
299   * @param  CACHEAXIx CACHEAXI instance
300   * @param  Monitors This parameter can be one or a combination of the following values:
301   *            @arg LL_CACHEAXI_MONITOR_READ_HIT
302   *            @arg LL_CACHEAXI_MONITOR_READ_MISS
303   *            @arg LL_CACHEAXI_MONITOR_WRITE_HIT
304   *            @arg LL_CACHEAXI_MONITOR_WRITE_MISS
305   *            @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
306   *            @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
307   *            @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
308   *            @arg LL_CACHEAXI_MONITOR_EVICTION
309   *            @arg LL_CACHEAXI_MONITOR_ALL
310   * @retval None
311   */
LL_CACHEAXI_EnableMonitors(CACHEAXI_TypeDef * CACHEAXIx,uint32_t Monitors)312 __STATIC_INLINE void LL_CACHEAXI_EnableMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
313 {
314   SET_BIT(CACHEAXIx->CR1, Monitors);
315 }
316 
317 /**
318   * @brief  Disable the hit/miss monitor(s).
319   * @rmtoll CR1  (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN)   LL_CACHEAXI_DisableMonitors
320   * @param  CACHEAXIx CACHEAXI instance
321   * @param  Monitors This parameter can be one or a combination of the following values:
322   *            @arg LL_CACHEAXI_MONITOR_READ_HIT
323   *            @arg LL_CACHEAXI_MONITOR_READ_MISS
324   *            @arg LL_CACHEAXI_MONITOR_WRITE_HIT
325   *            @arg LL_CACHEAXI_MONITOR_WRITE_MISS
326   *            @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
327   *            @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
328   *            @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
329   *            @arg LL_CACHEAXI_MONITOR_EVICTION
330   *            @arg LL_CACHEAXI_MONITOR_ALL
331   * @retval None
332   */
LL_CACHEAXI_DisableMonitors(CACHEAXI_TypeDef * CACHEAXIx,uint32_t Monitors)333 __STATIC_INLINE void LL_CACHEAXI_DisableMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
334 {
335   CLEAR_BIT(CACHEAXIx->CR1, Monitors);
336 }
337 
338 /**
339   * @brief  Return the hit/miss monitor(s) enable state.
340   * @rmtoll CR1  (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN)   LL_CACHEAXI_IsEnabledMonitors
341   * @param  CACHEAXIx CACHEAXI instance
342   * @param  Monitors This parameter can be one or a combination of the following values:
343   *            @arg LL_CACHEAXI_MONITOR_READ_HIT
344   *            @arg LL_CACHEAXI_MONITOR_READ_MISS
345   *            @arg LL_CACHEAXI_MONITOR_WRITE_HIT
346   *            @arg LL_CACHEAXI_MONITOR_WRITE_MISS
347   *            @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
348   *            @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
349   *            @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
350   *            @arg LL_CACHEAXI_MONITOR_EVICTION
351   *            @arg LL_CACHEAXI_MONITOR_ALL
352   * @retval State of parameter value (1 or 0).
353   */
LL_CACHEAXI_IsEnabledMonitors(const CACHEAXI_TypeDef * CACHEAXIx,uint32_t Monitors)354 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledMonitors(const CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
355 {
356   return (((READ_BIT(CACHEAXIx->CR1, (CACHEAXI_CR1_WMISSMEN | CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_RMISSMEN | \
357                                       CACHEAXI_CR1_RHITMEN  | CACHEAXI_CR1_RAMMEN  | CACHEAXI_CR1_WAMMEN   | \
358                                       CACHEAXI_CR1_WTMEN    | CACHEAXI_CR1_EVIMEN))\
359             & Monitors) == (Monitors)) ? 1UL : 0UL);
360 }
361 
362 /**
363   * @brief  Reset the Data Cache performance monitoring.
364   * @rmtoll CR1  (RHITMRST/RMISSMRST/WHITMRST/WMISSMRST/RAMMRST/WAMMRST/WTMRST/EVIMRST)   LL_CACHEAXI_ResetMonitors
365   * @param  CACHEAXIx CACHEAXI instance
366   * @param  Monitors Monitoring type
367   *         This parameter can be a combination of the following values:
368   *            @arg LL_CACHEAXI_MONITOR_READ_HIT
369   *            @arg LL_CACHEAXI_MONITOR_READ_MISS
370   *            @arg LL_CACHEAXI_MONITOR_WRITE_HIT
371   *            @arg LL_CACHEAXI_MONITOR_WRITE_MISS
372   *            @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
373   *            @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
374   *            @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
375   *            @arg LL_CACHEAXI_MONITOR_EVICTION
376   *            @arg LL_CACHEAXI_MONITOR_ALL
377   * @retval None
378   */
LL_CACHEAXI_ResetMonitors(CACHEAXI_TypeDef * CACHEAXIx,uint32_t Monitors)379 __STATIC_INLINE void LL_CACHEAXI_ResetMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
380 {
381   /* Reset */
382   SET_BIT(CACHEAXIx->CR1, (Monitors << 2U));
383 
384   /* Release reset */
385   CLEAR_BIT(CACHEAXIx->CR1, (Monitors << 2U));
386 }
387 
388 /**
389   * @brief  Get the Read Hit monitor Value
390   * @rmtoll RHMONR       LL_CACHEAXI_Monitor_GetReadHitValue
391   * @param  CACHEAXIx CACHEAXI instance
392   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
393   */
LL_CACHEAXI_Monitor_GetReadHitValue(CACHEAXI_TypeDef * CACHEAXIx)394 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadHitValue(CACHEAXI_TypeDef *CACHEAXIx)
395 {
396   return CACHEAXIx->RHMONR;
397 }
398 
399 /**
400   * @brief  Get the Read Miss monitor Value
401   * @rmtoll RMMONR       LL_CACHEAXI_Monitor_GetReadMissValue
402   * @param  CACHEAXIx CACHEAXI instance
403   * @retval Value between Min_Data=0 and Max_Data=0xFFFF
404   */
LL_CACHEAXI_Monitor_GetReadMissValue(CACHEAXI_TypeDef * CACHEAXIx)405 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadMissValue(CACHEAXI_TypeDef *CACHEAXIx)
406 {
407   return CACHEAXIx->RMMONR;
408 }
409 
410 /**
411   * @brief  Get the Write Hit monitor Value
412   * @rmtoll WHMONR       LL_CACHEAXI_Monitor_GetWriteHitValue
413   * @param  CACHEAXIx CACHEAXI instance
414   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
415   */
LL_CACHEAXI_Monitor_GetWriteHitValue(CACHEAXI_TypeDef * CACHEAXIx)416 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteHitValue(CACHEAXI_TypeDef *CACHEAXIx)
417 {
418   return CACHEAXIx->WHMONR;
419 }
420 
421 /**
422   * @brief  Get the Write Miss monitor Value
423   * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetWriteMissValue
424   * @param  CACHEAXIx CACHEAXI instance
425   * @retval Value between Min_Data=0 and Max_Data=0xFFFF
426   */
LL_CACHEAXI_Monitor_GetWriteMissValue(CACHEAXI_TypeDef * CACHEAXIx)427 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteMissValue(CACHEAXI_TypeDef *CACHEAXIx)
428 {
429   return CACHEAXIx->WMMONR;
430 }
431 
432 /**
433   * @brief  Get the Read-allocate Miss monitor Value
434   * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetReadAllocMissValue
435   * @param  CACHEAXIx CACHEAXI instance
436   * @retval Value between Min_Data=0 and Max_Data=0xFFFF
437   */
LL_CACHEAXI_Monitor_GetReadAllocMissValue(CACHEAXI_TypeDef * CACHEAXIx)438 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadAllocMissValue(CACHEAXI_TypeDef *CACHEAXIx)
439 {
440   return CACHEAXIx->RAMMONR;
441 }
442 
443 /**
444   * @brief  Get the Write-allocate Miss monitor Value
445   * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetWriteAllocMissValue
446   * @param  CACHEAXIx CACHEAXI instance
447   * @retval Value between Min_Data=0 and Max_Data=0xFFFF
448   */
LL_CACHEAXI_Monitor_GetWriteAllocMissValue(CACHEAXI_TypeDef * CACHEAXIx)449 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteAllocMissValue(CACHEAXI_TypeDef *CACHEAXIx)
450 {
451   return CACHEAXIx->WAMMONR;
452 }
453 
454 /**
455   * @brief  Get the Write-through monitor Value
456   * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetWriteThroughValue
457   * @param  CACHEAXIx CACHEAXI instance
458   * @retval Value between Min_Data=0 and Max_Data=0xFFFF
459   */
LL_CACHEAXI_Monitor_GetWriteThroughValue(CACHEAXI_TypeDef * CACHEAXIx)460 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteThroughValue(CACHEAXI_TypeDef *CACHEAXIx)
461 {
462   return CACHEAXIx->WTMONR;
463 }
464 
465 /**
466   * @brief  Get the Eviction monitor Value
467   * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetEvictionValue
468   * @param  CACHEAXIx CACHEAXI instance
469   * @retval Value between Min_Data=0 and Max_Data=0xFFFF
470   */
LL_CACHEAXI_Monitor_GetEvictionValue(CACHEAXI_TypeDef * CACHEAXIx)471 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetEvictionValue(CACHEAXI_TypeDef *CACHEAXIx)
472 {
473   return CACHEAXIx->EVIMONR;
474 }
475 
476 /**
477   * @}
478   */
479 
480 /** @defgroup CACHEAXI_LL_EF_IT_Management IT-Management
481   * @{
482   */
483 
484 /**
485   * @brief  Enable BusyEnd interrupt.
486   * @rmtoll IER         BSYENDIE          LL_CACHEAXI_EnableIT_BSYEND
487   * @param  CACHEAXIx CACHEAXI instance
488   * @retval None
489   */
LL_CACHEAXI_EnableIT_BSYEND(CACHEAXI_TypeDef * CACHEAXIx)490 __STATIC_INLINE void LL_CACHEAXI_EnableIT_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
491 {
492   SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE);
493 }
494 
495 /**
496   * @brief  Disable BusyEnd interrupt.
497   * @rmtoll IER         BSYENDIE          LL_CACHEAXI_DisableIT_BSYEND
498   * @param  CACHEAXIx CACHEAXI instance
499   * @retval None
500   */
LL_CACHEAXI_DisableIT_BSYEND(CACHEAXI_TypeDef * CACHEAXIx)501 __STATIC_INLINE void LL_CACHEAXI_DisableIT_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
502 {
503   CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE);
504 }
505 
506 /**
507   * @brief  Indicates whether the Busyend interrupt is enabled.
508   * @rmtoll IER         BSYENDIE          LL_CACHEAXI_IsEnabledIT_BSYEND
509   * @param  CACHEAXIx CACHEAXI instance
510   * @retval State of bit (1 or 0).
511   */
LL_CACHEAXI_IsEnabledIT_BSYEND(const CACHEAXI_TypeDef * CACHEAXIx)512 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_BSYEND(const CACHEAXI_TypeDef *CACHEAXIx)
513 {
514   return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE) == (CACHEAXI_IER_BSYENDIE)) ? 1UL : 0UL);
515 }
516 
517 /**
518   * @brief  Enable Error interrupt.
519   * @rmtoll IER         ERRIE          LL_CACHEAXI_EnableIT_ERR
520   * @param  CACHEAXIx CACHEAXI instance
521   * @retval None
522   */
LL_CACHEAXI_EnableIT_ERR(CACHEAXI_TypeDef * CACHEAXIx)523 __STATIC_INLINE void LL_CACHEAXI_EnableIT_ERR(CACHEAXI_TypeDef *CACHEAXIx)
524 {
525   SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE);
526 }
527 
528 /**
529   * @brief  Disable Error interrupt.
530   * @rmtoll IER         ERRIE          LL_CACHEAXI_DisableIT_ERR
531   * @param  CACHEAXIx CACHEAXI instance
532   * @retval None
533   */
LL_CACHEAXI_DisableIT_ERR(CACHEAXI_TypeDef * CACHEAXIx)534 __STATIC_INLINE void LL_CACHEAXI_DisableIT_ERR(CACHEAXI_TypeDef *CACHEAXIx)
535 {
536   CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE);
537 }
538 
539 /**
540   * @brief  Indicates whether the Error interrupt is enabled.
541   * @rmtoll IER         ERRIE          LL_CACHEAXI_IsEnabledIT_ERR
542   * @param  CACHEAXIx CACHEAXI instance
543   * @retval State of bit (1 or 0).
544   */
LL_CACHEAXI_IsEnabledIT_ERR(const CACHEAXI_TypeDef * CACHEAXIx)545 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_ERR(const CACHEAXI_TypeDef *CACHEAXIx)
546 {
547   return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE) == (CACHEAXI_IER_ERRIE)) ? 1UL : 0UL);
548 }
549 
550 /**
551   * @brief  Enable command end interrupt.
552   * @rmtoll IER         CMDENDIE         LL_CACHEAXI_EnableIT_CMDEND
553   * @param  CACHEAXIx CACHEAXI instance
554   * @retval None
555   */
LL_CACHEAXI_EnableIT_CMDEND(CACHEAXI_TypeDef * CACHEAXIx)556 __STATIC_INLINE void LL_CACHEAXI_EnableIT_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
557 {
558   SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE);
559 }
560 
561 /**
562   * @brief  Disable command end interrupt.
563   * @rmtoll IER         CMDENDIE         LL_CACHEAXI_DisableIT_CMDEND
564   * @param  CACHEAXIx CACHEAXI instance
565   * @retval None
566   */
LL_CACHEAXI_DisableIT_CMDEND(CACHEAXI_TypeDef * CACHEAXIx)567 __STATIC_INLINE void LL_CACHEAXI_DisableIT_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
568 {
569   CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE);
570 }
571 
572 /**
573   * @brief  Indicates whether the command end interrupt is enabled.
574   * @rmtoll IER         CMDENDIE          LL_CACHEAXI_IsEnabledIT_CMDEND
575   * @param  CACHEAXIx CACHEAXI instance
576   * @retval State of bit (1 or 0).
577   */
LL_CACHEAXI_IsEnabledIT_CMDEND(const CACHEAXI_TypeDef * CACHEAXIx)578 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_CMDEND(const CACHEAXI_TypeDef *CACHEAXIx)
579 {
580   return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE) == (CACHEAXI_IER_CMDENDIE)) ? 1UL : 0UL);
581 }
582 
583 /**
584   * @brief  Clear full invalidate busy end flag.
585   * @rmtoll FCR      CBSYENDF         LL_CACHEAXI_ClearFlag_BSYEND
586   * @param  CACHEAXIx CACHEAXI instance
587   * @retval None
588   */
LL_CACHEAXI_ClearFlag_BSYEND(CACHEAXI_TypeDef * CACHEAXIx)589 __STATIC_INLINE void LL_CACHEAXI_ClearFlag_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
590 {
591   WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CBSYENDF);
592 }
593 
594 /**
595   * @brief  Clear cache error flag.
596   * @rmtoll FCR      CERRF        LL_CACHEAXI_ClearFlag_ERR
597   * @param  CACHEAXIx CACHEAXI instance
598   * @retval None
599   */
LL_CACHEAXI_ClearFlag_ERR(CACHEAXI_TypeDef * CACHEAXIx)600 __STATIC_INLINE void LL_CACHEAXI_ClearFlag_ERR(CACHEAXI_TypeDef *CACHEAXIx)
601 {
602   WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CERRF);
603 }
604 
605 /**
606   * @brief  Clear command end flag.
607   * @rmtoll FCR      CCMDENDF        LL_CACHEAXI_ClearFlag_CMDEND
608   * @param  CACHEAXIx CACHEAXI instance
609   * @retval None
610   */
LL_CACHEAXI_ClearFlag_CMDEND(CACHEAXI_TypeDef * CACHEAXIx)611 __STATIC_INLINE void LL_CACHEAXI_ClearFlag_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
612 {
613   WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CCMDENDF);
614 }
615 
616 /**
617   * @brief  Get flag Dcache BUSY.
618   * @rmtoll SR      BUSYF            LL_CACHEAXI_IsActiveFlag_BUSY
619   * @param  CACHEAXIx CACHEAXI instance
620   * @retval State of bit (1 or 0).
621   */
LL_CACHEAXI_IsActiveFlag_BUSY(const CACHEAXI_TypeDef * CACHEAXIx)622 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BUSY(const CACHEAXI_TypeDef *CACHEAXIx)
623 {
624   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BUSYF) == (CACHEAXI_SR_BUSYF)) ? 1UL : 0UL);
625 }
626 
627 /**
628   * @brief  Get flag Dcache Busyend.
629   * @rmtoll SR      BSYENDF            LL_CACHEAXI_IsActiveFlag_BSYEND
630   * @param  CACHEAXIx CACHEAXI instance
631   * @retval State of bit (1 or 0).
632   */
LL_CACHEAXI_IsActiveFlag_BSYEND(const CACHEAXI_TypeDef * CACHEAXIx)633 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BSYEND(const CACHEAXI_TypeDef *CACHEAXIx)
634 {
635   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BSYENDF) == (CACHEAXI_SR_BSYENDF)) ? 1UL : 0UL);
636 }
637 
638 /**
639   * @brief  Get flag Dcache Error.
640   * @rmtoll SR      ERRF            LL_CACHEAXI_IsActiveFlag_ERR
641   * @param  CACHEAXIx CACHEAXI instance
642   * @retval State of bit (1 or 0).
643   */
LL_CACHEAXI_IsActiveFlag_ERR(const CACHEAXI_TypeDef * CACHEAXIx)644 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_ERR(const CACHEAXI_TypeDef *CACHEAXIx)
645 {
646   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_ERRF) == (CACHEAXI_SR_ERRF)) ? 1UL : 0UL);
647 }
648 
649 /**
650   * @brief  Get flag Dcache Busy command.
651   * @rmtoll SR      BUSYCMDF            LL_CACHEAXI_IsActiveFlag_BUSYCMD
652   * @param  CACHEAXIx CACHEAXI instance
653   * @retval State of bit (1 or 0).
654   */
LL_CACHEAXI_IsActiveFlag_BUSYCMD(const CACHEAXI_TypeDef * CACHEAXIx)655 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BUSYCMD(const CACHEAXI_TypeDef *CACHEAXIx)
656 {
657   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BUSYCMDF) == (CACHEAXI_SR_BUSYCMDF)) ? 1UL : 0UL);
658 }
659 
660 /**
661   * @brief  Get flag Dcache command end.
662   * @rmtoll SR      CMDENDF            LL_CACHEAXI_IsActiveFlag_CMDEND
663   * @param  CACHEAXIx CACHEAXI instance
664   * @retval State of bit (1 or 0).
665   */
LL_CACHEAXI_IsActiveFlag_CMDEND(const CACHEAXI_TypeDef * CACHEAXIx)666 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_CMDEND(const CACHEAXI_TypeDef *CACHEAXIx)
667 {
668   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_CMDENDF) == (CACHEAXI_SR_CMDENDF)) ? 1UL : 0UL);
669 }
670 
671 /**
672   * @}
673   */
674 
675 /**
676   * @}
677   */
678 
679 /**
680   * @}
681   */
682 
683 /**
684   * @}
685   */
686 
687 #ifdef __cplusplus
688 }
689 #endif
690 
691 #endif /* STM32N6xx_LL_CACHEAXI_H */
692