1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2021 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ##### RCC Limitations #####
20 ==============================================================================
21 [..]
22 A delay between an RCC peripheral clock enable and the effective peripheral
23 enabling should be taken into account in order to manage the peripheral read/write
24 from/to registers.
25 (+) This delay depends on the peripheral mapping.
26 (++) AHB , APB peripherals, 1 dummy read is necessary
27
28 [..]
29 Workarounds:
30 (#) For AHB , APB peripherals, a dummy read to the peripheral register has been
31 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
32
33 @endverbatim
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32U5xx_LL_BUS_H
39 #define STM32U5xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32u5xx.h"
47
48 /** @addtogroup STM32U5xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60 /* Private constants ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
74 #define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
75 #define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
76 #define LL_AHB1_GRP1_PERIPH_MDF1 RCC_AHB1ENR_MDF1EN
77 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
78 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
79 #if defined(JPEG)
80 #define LL_AHB1_GRP1_PERIPH_JPEG RCC_AHB1ENR_JPEGEN
81 #endif /* defined(JPEG) */
82 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
83 #define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN
84 #if defined(DMA2D)
85 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
86 #endif /* DMA2D */
87 #if defined(GFXMMU)
88 #define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN
89 #endif /* defined(GFXMMU) */
90 #if defined(GPU2D)
91 #define LL_AHB1_GRP1_PERIPH_GPU2D RCC_AHB1ENR_GPU2DEN
92 #endif /* defined(GPU2D) */
93 #if defined(DCACHE2)
94 #define LL_AHB1_GRP1_PERIPH_DCACHE2 RCC_AHB1ENR_DCACHE2EN
95 #endif /* defined(DCACHE2) */
96 #define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN
97 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
98 #define LL_AHB1_GRP1_PERIPH_ICACHE1 RCC_AHB1SMENR_ICACHESMEN
99 #define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN
100 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN
101 /**
102 * @}
103 */
104
105 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
106 * @{
107 */
108 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
109 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR1_GPIOAEN
110 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR1_GPIOBEN
111 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR1_GPIOCEN
112 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR1_GPIODEN
113 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR1_GPIOEEN
114 #if defined(GPIOF)
115 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR1_GPIOFEN
116 #endif /* GPIOF */
117 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR1_GPIOGEN
118 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR1_GPIOHEN
119 #if defined (GPIOI)
120 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR1_GPIOIEN
121 #endif /* GPIOI */
122 #if defined (GPIOJ)
123 #define LL_AHB2_GRP1_PERIPH_GPIOJ RCC_AHB2ENR1_GPIOJEN
124 #endif /* defined (GPIOJ) */
125 #define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR1_ADC12EN
126 #define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR1_DCMI_PSSIEN
127 #if defined(USB_OTG_FS)
128 #define LL_AHB2_GRP1_PERIPH_OTG_FS RCC_AHB2ENR1_OTGEN
129 /* Legacy define */
130 #define LL_AHB2_GRP1_PERIPH_USBFS LL_AHB2_GRP1_PERIPH_OTG_FS
131 #elif defined(USB_OTG_HS)
132 #define LL_AHB2_GRP1_PERIPH_OTG_HS RCC_AHB2ENR1_OTGEN
133 /* Legacy define */
134 #define LL_AHB2_GRP1_PERIPH_USBHS LL_AHB2_GRP1_PERIPH_OTG_HS
135 #endif /* defined(USB_OTG_HS) */
136 #if defined(RCC_AHB2ENR1_USBPHYCEN)
137 #define LL_AHB2_GRP1_PERIPH_USBPHY RCC_AHB2ENR1_USBPHYCEN
138 #endif /* defined(RCC_AHB2ENR1_USBPHYCEN) */
139 #if defined(AES)
140 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR1_AESEN
141 #endif /* AES */
142 #if defined(HASH)
143 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR1_HASHEN
144 #endif /* HASH */
145 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR1_RNGEN
146 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR1_PKAEN
147 #if defined(SAES)
148 #define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR1_SAESEN
149 #endif /* SAES */
150 #if defined(OCTOSPIM)
151 #define LL_AHB2_GRP1_PERIPH_OCTOSPIM RCC_AHB2ENR1_OCTOSPIMEN
152 #endif /* OCTOSPIM */
153 #define LL_AHB2_GRP1_PERIPH_OTFDEC1 RCC_AHB2ENR1_OTFDEC1EN
154 #if defined (OTFDEC2)
155 #define LL_AHB2_GRP1_PERIPH_OTFDEC2 RCC_AHB2ENR1_OTFDEC2EN
156 #endif /* OTFDEC2 */
157 #define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR1_SDMMC1EN
158 #if defined(SDMMC2)
159 #define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR1_SDMMC2EN
160 #endif /* SDMMC2 */
161 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR1_SRAM2EN
162 #if defined(SRAM3_BASE)
163 #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR1_SRAM3EN
164 #endif /* SRAM3_BASE */
165
166 /**
167 * @}
168 */
169
170 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
171 * @{
172 */
173 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
174 #define LL_AHB3_GRP1_PERIPH_LPGPIO1 RCC_AHB3ENR_LPGPIO1EN
175 #define LL_AHB3_GRP1_PERIPH_PWR RCC_AHB3ENR_PWREN
176 #define LL_AHB3_GRP1_PERIPH_ADC4 RCC_AHB3ENR_ADC4EN
177 #define LL_AHB3_GRP1_PERIPH_DAC1 RCC_AHB3ENR_DAC1EN
178 #define LL_AHB3_GRP1_PERIPH_LPDMA1 RCC_AHB3ENR_LPDMA1EN
179 #define LL_AHB3_GRP1_PERIPH_ADF1 RCC_AHB3ENR_ADF1EN
180 #define LL_AHB3_GRP1_PERIPH_GTZC2 RCC_AHB3ENR_GTZC2EN
181 #define LL_AHB3_GRP1_PERIPH_SRAM4 RCC_AHB3ENR_SRAM4EN
182
183 /**
184 * @}
185 */
186
187 /** @defgroup BUS_LL_EC_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH
188 * @{
189 */
190 #define LL_AHB2_GRP2_PERIPH_ALL 0xFFFFFFFFU
191 #if defined(FMC_BASE)
192 #define LL_AHB2_GRP2_PERIPH_FSMC RCC_AHB2ENR2_FSMCEN
193 #endif /* FMC_BASE */
194 #define LL_AHB2_GRP2_PERIPH_OCTOSPI1 RCC_AHB2ENR2_OCTOSPI1EN
195 #if defined(OCTOSPI2)
196 #define LL_AHB2_GRP2_PERIPH_OCTOSPI2 RCC_AHB2ENR2_OCTOSPI2EN
197 #endif /* OCTOSPI2 */
198 #if defined(HSPI1)
199 #define LL_AHB2_GRP2_PERIPH_HSPI1 RCC_AHB2ENR2_HSPI1EN
200 #endif /* defined(HSPI1) */
201 #if defined(SRAM6_BASE)
202 #define LL_AHB2_GRP2_PERIPH_SRAM6 RCC_AHB2ENR2_SRAM6EN
203 #endif /* SRAM6_BASE */
204 #if defined(SRAM5_BASE)
205 #define LL_AHB2_GRP2_PERIPH_SRAM5 RCC_AHB2ENR2_SRAM5EN
206 #endif /* SRAM5_BASE */
207 /**
208 * @}
209 */
210
211 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
212 * @{
213 */
214 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
215 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
216 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
217 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
218 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
219 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
220 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
221 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
222 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
223 #if defined(USART2)
224 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
225 #endif /* USART2 */
226 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
227 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
228 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
229 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
230 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
231 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
232 #if defined(USART6)
233 #define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1ENR1_USART6EN
234 #endif /* defined(USART6) */
235 /**
236 * @}
237 */
238
239
240 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
241 * @{
242 */
243 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
244 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
245 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
246 #define LL_APB1_GRP2_PERIPH_FDCAN1 RCC_APB1ENR2_FDCAN1EN
247 #if defined(UCPD1)
248 #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
249 #endif /* UCPD1 */
250 #if defined(I2C5)
251 #define LL_APB1_GRP2_PERIPH_I2C5 RCC_APB1ENR2_I2C5EN
252 #endif /* defined(I2C5) */
253 #if defined(I2C6)
254 #define LL_APB1_GRP2_PERIPH_I2C6 RCC_APB1ENR2_I2C6EN
255 #endif /* defined(I2C6) */
256 /**
257 * @}
258 */
259
260 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
261 * @{
262 */
263 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
264 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
265 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
266 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
267 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
268 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
269 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
270 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
271 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
272 #if defined(SAI2)
273 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
274 #endif /* SAI2 */
275 #if defined(USB_DRD_FS)
276 #define LL_APB2_GRP1_PERIPH_USB_FS RCC_APB2ENR_USBEN
277 #endif /* USB_DRD_FS */
278 #if defined(GFXTIM)
279 #define LL_APB2_GRP1_PERIPH_GFXTIM RCC_APB2ENR_GFXTIMEN
280 #endif /* GFXTIM */
281 #if defined(LTDC)
282 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
283 #endif /* defined(LTDC) */
284 #if defined(DSI)
285 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIHOSTEN
286 #endif /* defined(DSI) */
287 /**
288 * @}
289 */
290
291 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
292 * @{
293 */
294 #define LL_APB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
295 #define LL_APB3_GRP1_PERIPH_SYSCFG RCC_APB3ENR_SYSCFGEN
296 #define LL_APB3_GRP1_PERIPH_SPI3 RCC_APB3ENR_SPI3EN
297 #define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN
298 #define LL_APB3_GRP1_PERIPH_I2C3 RCC_APB3ENR_I2C3EN
299 #define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN
300 #define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_APB3ENR_LPTIM3EN
301 #define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_APB3ENR_LPTIM4EN
302 #define LL_APB3_GRP1_PERIPH_OPAMP RCC_APB3ENR_OPAMPEN
303 #define LL_APB3_GRP1_PERIPH_COMP RCC_APB3ENR_COMPEN
304 #define LL_APB3_GRP1_PERIPH_VREF RCC_APB3ENR_VREFEN
305 #define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN
306 /**
307 * @}
308 */
309
310 /** @defgroup BUS_LL_EC_SRDAMR_GRP1_PERIPH SRDAMR GRP1 PERIPH
311 * @{
312 */
313 #define LL_SRDAMR_GRP1_PERIPH_ALL 0xFFFFFFFFU
314 #define LL_SRDAMR_GRP1_PERIPH_SPI3 RCC_SRDAMR_SPI3AMEN
315 #define LL_SRDAMR_GRP1_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN
316 #define LL_SRDAMR_GRP1_PERIPH_I2C3 RCC_SRDAMR_I2C3AMEN
317 #define LL_SRDAMR_GRP1_PERIPH_LPTIM1 RCC_SRDAMR_LPTIM1AMEN
318 #define LL_SRDAMR_GRP1_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN
319 #define LL_SRDAMR_GRP1_PERIPH_LPTIM4 RCC_SRDAMR_LPTIM4AMEN
320 #define LL_SRDAMR_GRP1_PERIPH_OPAMP RCC_SRDAMR_OPAMPAMEN
321 #define LL_SRDAMR_GRP1_PERIPH_COMP RCC_SRDAMR_COMPAMEN
322 #define LL_SRDAMR_GRP1_PERIPH_VREF RCC_SRDAMR_VREFAMEN
323 #define LL_SRDAMR_GRP1_PERIPH_RTCAPB RCC_SRDAMR_RTCAPBAMEN
324 #define LL_SRDAMR_GRP1_PERIPH_ADC4 RCC_SRDAMR_ADC4AMEN
325 #define LL_SRDAMR_GRP1_PERIPH_LPGPIO1 RCC_SRDAMR_LPGPIO1AMEN
326 #define LL_SRDAMR_GRP1_PERIPH_DAC1 RCC_SRDAMR_DAC1AMEN
327 #define LL_SRDAMR_GRP1_PERIPH_LPDMA1 RCC_SRDAMR_LPDMA1AMEN
328 #define LL_SRDAMR_GRP1_PERIPH_ADF1 RCC_SRDAMR_ADF1AMEN
329 #define LL_SRDAMR_GRP1_PERIPH_SRAM4 RCC_SRDAMR_SRAM4AMEN
330 /**
331 * @}
332 */
333 /** @defgroup LL_RCC_Aliased_Constants LL RCC Aliased Constants maintained for legacy purpose
334 * @{
335 */
336 #define LL_AHB2_GRP1_PERIPH_ADC1 LL_AHB2_GRP1_PERIPH_ADC12
337 #define LL_SRDAMR_GRP1_PERIPH_SPI3AMEN LL_SRDAMR_GRP1_PERIPH_SPI3
338 #define LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN LL_SRDAMR_GRP1_PERIPH_LPUART1
339 #define LL_SRDAMR_GRP1_PERIPH_I2C3AMEN LL_SRDAMR_GRP1_PERIPH_I2C3
340 #define LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM1
341 #define LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM3
342 #define LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM4
343 #define LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN LL_SRDAMR_GRP1_PERIPH_OPAMP
344 #define LL_SRDAMR_GRP1_PERIPH_COMPAMEN LL_SRDAMR_GRP1_PERIPH_COMP
345 #define LL_SRDAMR_GRP1_PERIPH_VREFAMEN LL_SRDAMR_GRP1_PERIPH_VREF
346 #define LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN LL_SRDAMR_GRP1_PERIPH_RTCAPB
347 #define LL_SRDAMR_GRP1_PERIPH_ADC4AMEN LL_SRDAMR_GRP1_PERIPH_ADC4
348 #define LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN LL_SRDAMR_GRP1_PERIPH_LPGPIO1
349 #define LL_SRDAMR_GRP1_PERIPH_DAC1AMEN LL_SRDAMR_GRP1_PERIPH_DAC1
350 #define LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN LL_SRDAMR_GRP1_PERIPH_LPDMA1
351 #define LL_SRDAMR_GRP1_PERIPH_ADF1AMEN LL_SRDAMR_GRP1_PERIPH_ADF1
352 #define LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN LL_SRDAMR_GRP1_PERIPH_SRAM4
353 /**
354 * @}
355 */
356 /**
357 * @}
358 */
359
360 /* Exported macro ------------------------------------------------------------*/
361 /* Exported functions --------------------------------------------------------*/
362 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
363 * @{
364 */
365
366 /** @defgroup BUS_LL_EF_AHB1 AHB1
367 * @{
368 */
369
370 /**
371 * @brief Enable AHB1 bus clock.
372 * @rmtoll CFGR2 AHB1DIS LL_AHB1_GRP1_EnableBusClock
373 * @retval None
374 */
LL_AHB1_GRP1_EnableBusClock(void)375 __STATIC_INLINE void LL_AHB1_GRP1_EnableBusClock(void)
376 {
377 __IO uint32_t tmpreg;
378 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS);
379 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS);
380 (void)(tmpreg);
381 }
382
383 /**
384 * @brief Enable AHB1 peripherals clock.
385 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n
386 * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
387 * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
388 * AHB1ENR MDF1EN LL_AHB1_GRP1_EnableClock\n
389 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
390 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
391 * AHB1ENR JPEGEN LL_AHB1_GRP1_EnableClock\n
392 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
393 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n
394 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
395 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock\n
396 * AHB1ENR GPU2DEN LL_AHB1_GRP1_EnableClock\n
397 * AHB1ENR DCACHE2EN LL_AHB1_GRP1_EnableClock\n
398 * AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n
399 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
400 * AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n
401 * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock\n
402 * @param Periphs This parameter can be a combination of the following values:
403 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
404 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
405 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
406 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
407 * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
408 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
409 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
410 * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*)
411 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
412 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
413 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
414 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
415 * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
416 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
417 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
418 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
419 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
420 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
421 *
422 * (*) value not defined in all devices.
423 * @retval None
424 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)425 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
426 {
427 __IO uint32_t tmpreg;
428 SET_BIT(RCC->AHB1ENR, Periphs);
429 /* Delay after an RCC peripheral clock enabling */
430 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
431 (void)tmpreg;
432 }
433
434 /**
435 * @brief Check if AHB1 peripheral clock is enabled or not
436 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n
437 * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
438 * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
439 * AHB1ENR MDF1EN LL_AHB1_GRP1_IsEnabledClock\n
440 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
441 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
442 * AHB1ENR JPEGEN LL_AHB1_GRP1_IsEnabledClock\n
443 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
444 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n
445 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
446 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock\n
447 * AHB1ENR GPU2DEN LL_AHB1_GRP1_IsEnabledClock\n
448 * AHB1ENR DCACHE2EN LL_AHB1_GRP1_IsEnabledClock\n
449 * AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n
450 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
451 * AHB1ENR DCACHEEN LL_AHB1_GRP1_IsEnabledClock\n
452 * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock\n
453 * @param Periphs This parameter can be a combination of the following values:
454 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
455 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
456 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
457 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
458 * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
459 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
460 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
461 * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*)
462 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
463 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
464 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
465 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
466 * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
467 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
468 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
469 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
470 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
471 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
472 *
473 * (*) value not defined in all devices.
474 * @retval State of Periphs (1 or 0).
475 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)476 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
477 {
478 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
479 }
480
481 /**
482 * @brief Disable AHB1 bus clock.
483 * @note except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1.
484 * @rmtoll CFGR2 AHB1DIS LL_AHB1_GRP1_DisableBusClock
485 * @retval None
486 */
LL_AHB1_GRP1_DisableBusClock(void)487 __STATIC_INLINE void LL_AHB1_GRP1_DisableBusClock(void)
488 {
489 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS);
490 }
491
492 /**
493 * @brief Disable AHB1 peripherals clock.
494 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n
495 * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
496 * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
497 * AHB1ENR MDF1EN LL_AHB1_GRP1_DisableClock\n
498 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
499 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
500 * AHB1ENR JPEGEN LL_AHB1_GRP1_DisableClock\n
501 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
502 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n
503 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
504 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock\n
505 * AHB1ENR GPU2DEN LL_AHB1_GRP1_DisableClock\n
506 * AHB1ENR DCACHE2EN LL_AHB1_GRP1_DisableClock\n
507 * AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n
508 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
509 * AHB1ENR DCACHEEN LL_AHB1_GRP1_DisableClock\n
510 * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock\n
511 * @param Periphs This parameter can be a combination of the following values:
512 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
513 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
514 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
515 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
516 * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
517 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
518 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
519 * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*)
520 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
521 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
522 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
523 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
524 * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
525 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
526 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
527 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
528 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
529 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
530 *
531 * (*) value not defined in all devices.
532 * @retval None
533 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)534 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
535 {
536 CLEAR_BIT(RCC->AHB1ENR, Periphs);
537 }
538
539 /**
540 * @brief Force AHB1 peripherals reset.
541 * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n
542 * AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ForceReset\n
543 * AHB1RSTR FMACRSTR LL_AHB1_GRP1_ForceReset\n
544 * AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ForceReset\n
545 * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n
546 * AHB1RSTR JPEGRSTR LL_AHB1_GRP1_ForceReset\n
547 * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n
548 * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset\n
549 * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ForceReset\n
550 * AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ForceReset\n
551 * AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ForceReset\n
552 * AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ForceReset\n
553 * @param Periphs This parameter can be a combination of the following values:
554 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
555 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
556 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
557 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
558 * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
559 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
560 * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*)
561 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
562 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
563 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
564 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
565 * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
566 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
567 * (*) value not defined in all devices.
568 * @retval None
569 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)570 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
571 {
572 SET_BIT(RCC->AHB1RSTR, Periphs);
573 }
574
575 /**
576 * @brief Release AHB1 peripherals reset.
577 * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n
578 * AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ReleaseReset\n
579 * AHB1RSTR FMACRSTR LL_AHB1_GRP1_ReleaseReset\n
580 * AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ReleaseReset\n
581 * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n
582 * AHB1RSTR JPEGRSTR LL_AHB1_GRP1_ReleaseReset\n
583 * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n
584 * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n
585 * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ReleaseReset\n
586 * AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ReleaseReset\n
587 * AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ReleaseReset\n
588 * AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ReleaseReset\n
589 * @param Periphs This parameter can be a combination of the following values:
590 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
591 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
592 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
593 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
594 * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
595 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
596 * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*)
597 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
598 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
599 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
600 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
601 * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
602 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
603 *
604 * (*) value not defined in all devices.
605 * @retval None
606 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)607 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
608 {
609 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
610 }
611
612 /**
613 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
614 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
615 * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
616 * AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
617 * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
618 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
619 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
620 * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
621 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
622 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
623 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
624 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
625 * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
626 * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
627 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
628 * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
629 * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n
630 * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n
631 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
632 * @param Periphs This parameter can be a combination of the following values:
633 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
634 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
635 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
636 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
637 * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
638 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
639 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
640 * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*)
641 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
642 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
643 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
644 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
645 * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
646 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
647 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
648 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
649 * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1
650 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
651 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
652 *
653 * (*) value not defined in all devices.
654 * @retval None
655 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)656 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
657 {
658 __IO uint32_t tmpreg;
659 SET_BIT(RCC->AHB1SMENR, Periphs);
660 /* Delay after an RCC peripheral clock enabling */
661 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
662 (void)tmpreg;
663 }
664
665 /**
666 * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not
667 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
668 * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
669 * AHB1SMENR FMACSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
670 * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
671 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
672 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
673 * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
674 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
675 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
676 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
677 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
678 * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
679 * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
680 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
681 * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
682 * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
683 * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
684 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
685 * @param Periphs This parameter can be a combination of the following values:
686 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
687 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
688 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
689 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
690 * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
691 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
692 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
693 * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*)
694 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
695 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
696 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
697 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
698 * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
699 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
700 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
701 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
702 * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1
703 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
704 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
705 *
706 * (*) value not defined in all devices.
707 * @retval State of Periphs (1 or 0).
708 */
LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)709 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
710 {
711 return ((READ_BIT(RCC->AHB1SMENR, Periphs) == Periphs) ? 1UL : 0UL);
712 }
713
714 /**
715 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
716 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
717 * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
718 * AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
719 * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
720 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
721 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
722 * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
723 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
724 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
725 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
726 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
727 * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
728 * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
729 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
730 * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
731 * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n
732 * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n
733 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
734 * @param Periphs This parameter can be a combination of the following values:
735 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
736 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
737 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
738 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
739 * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
740 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
741 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
742 * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*)
743 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
744 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
745 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
746 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
747 * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
748 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
749 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
750 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
751 * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1
752 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
753 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
754 *
755 * (*) value not defined in all devices.
756 * @retval None
757 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)758 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
759 {
760 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
761 }
762
763 /**
764 * @}
765 */
766
767 /** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
768 * @{
769 */
770
771 /**
772 * @brief Enable AHB2_1 bus clock.
773 * @rmtoll CFGR2 AHB2DIS1 LL_AHB2_GRP1_EnableBusClock
774 * @retval None
775 */
LL_AHB2_GRP1_EnableBusClock(void)776 __STATIC_INLINE void LL_AHB2_GRP1_EnableBusClock(void)
777 {
778 __IO uint32_t tmpreg;
779 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1);
780 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1);
781 (void)(tmpreg);
782 }
783
784 /**
785 * @brief Enable AHB2 peripherals clock.
786 * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_EnableClock\n
787 * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_EnableClock\n
788 * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_EnableClock\n
789 * AHB2ENR1 GPIODEN LL_AHB2_GRP1_EnableClock\n
790 * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_EnableClock\n
791 * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_EnableClock\n
792 * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_EnableClock\n
793 * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_EnableClock\n
794 * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_EnableClock\n
795 * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_EnableClock\n
796 * AHB2ENR1 ADC12EN LL_AHB2_GRP1_EnableClock\n
797 * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n
798 * AHB2ENR1 OTGEN LL_AHB2_GRP1_EnableClock\n
799 * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClock\n
800 * AHB2ENR1 AESEN LL_AHB2_GRP1_EnableClock\n
801 * AHB2ENR1 HASHEN LL_AHB2_GRP1_EnableClock\n
802 * AHB2ENR1 RNGEN LL_AHB2_GRP1_EnableClock\n
803 * AHB2ENR1 PKAEN LL_AHB2_GRP1_EnableClock\n
804 * AHB2ENR1 SAESEN LL_AHB2_GRP1_EnableClock\n
805 * AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_EnableClock\n
806 * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_EnableClock\n
807 * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_EnableClock\n
808 * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_EnableClock\n
809 * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_EnableClock\n
810 * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_EnableClock\n
811 * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_EnableClock\n
812 * @param Periphs This parameter can be a combination of the following values:
813 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
814 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
815 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
816 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
817 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
818 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
819 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
820 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
821 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
822 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
823 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
824 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
825 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
826 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*)
827 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*)
828 * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
829 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
830 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
831 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
832 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
833 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
834 * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*)
835 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
836 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*)
837 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
838 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*)
839 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
840 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
841 *
842 * (*) value not defined in all devices.
843 * @retval None
844 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)845 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
846 {
847 __IO uint32_t tmpreg;
848 SET_BIT(RCC->AHB2ENR1, Periphs);
849 /* Delay after an RCC peripheral clock enabling */
850 tmpreg = READ_BIT(RCC->AHB2ENR1, Periphs);
851 (void)tmpreg;
852 }
853
854 /**
855 * @brief Check if AHB2 peripheral clock is enabled or not
856 * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
857 * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
858 * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
859 * AHB2ENR1 GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
860 * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
861 * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
862 * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
863 * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
864 * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
865 * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_IsEnabledClock\n
866 * AHB2ENR1 ADC12EN LL_AHB2_GRP1_IsEnabledClock\n
867 * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n
868 * AHB2ENR1 OTGEN LL_AHB2_GRP1_IsEnabledClock\n
869 * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_IsEnabledClock\n
870 * AHB2ENR1 AESEN LL_AHB2_GRP1_IsEnabledClock\n
871 * AHB2ENR1 HASHEN LL_AHB2_GRP1_IsEnabledClock\n
872 * AHB2ENR1 RNGEN LL_AHB2_GRP1_IsEnabledClock\n
873 * AHB2ENR1 PKAEN LL_AHB2_GRP1_IsEnabledClock\n
874 * AHB2ENR1 SAESEN LL_AHB2_GRP1_IsEnabledClock\n
875 * AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
876 * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_IsEnabledClock\n
877 * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_IsEnabledClock\n
878 * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_IsEnabledClock\n
879 * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
880 * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
881 * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_IsEnabledClock\n
882 * @param Periphs This parameter can be a combination of the following values:
883 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
884 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
885 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
886 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
887 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
888 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
889 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
890 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
891 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
892 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
893 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
894 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
895 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
896 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*)
897 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*)
898 * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
899 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
900 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
901 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
902 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
903 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
904 * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*)
905 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
906 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*)
907 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
908 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*)
909 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
910 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
911 *
912 * (*) value not defined in all devices.
913 * @retval State of Periphs (1 or 0).
914 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)915 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
916 {
917 return ((READ_BIT(RCC->AHB2ENR1, Periphs) == Periphs) ? 1UL : 0UL);
918 }
919
920 /**
921 * @brief Disable AHB2_1 bus clock.
922 * @note except for SRAM2 and SRAM3.
923 * @rmtoll CFGR2 AHB2DIS1 LL_AHB2_GRP1_DisableBusClock
924 * @retval None
925 */
LL_AHB2_GRP1_DisableBusClock(void)926 __STATIC_INLINE void LL_AHB2_GRP1_DisableBusClock(void)
927 {
928 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1);
929 }
930
931 /**
932 * @brief Disable AHB2 peripherals clock.
933 * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_DisableClock\n
934 * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_DisableClock\n
935 * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_DisableClock\n
936 * AHB2ENR1 GPIODEN LL_AHB2_GRP1_DisableClock\n
937 * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_DisableClock\n
938 * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_DisableClock\n
939 * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_DisableClock\n
940 * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_DisableClock\n
941 * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_DisableClock\n
942 * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_DisableClock\n
943 * AHB2ENR1 ADC12EN LL_AHB2_GRP1_DisableClock\n
944 * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n
945 * AHB2ENR1 OTGEN LL_AHB2_GRP1_DisableClock\n
946 * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_DisableClock\n
947 * AHB2ENR1 AESEN LL_AHB2_GRP1_DisableClock\n
948 * AHB2ENR1 HASHEN LL_AHB2_GRP1_DisableClock\n
949 * AHB2ENR1 RNGEN LL_AHB2_GRP1_DisableClock\n
950 * AHB2ENR1 PKAEN LL_AHB2_GRP1_DisableClock\n
951 * AHB2ENR1 SAESEN LL_AHB2_GRP1_DisableClock\n
952 * AHB2ENR1 OSPIMEN LL_AHB2_GRP1_DisableClock\n
953 * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_DisableClock\n
954 * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_DisableClock\n
955 * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_DisableClock\n
956 * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_DisableClock\n
957 * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_DisableClock\n
958 * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_DisableClock\n
959 * @param Periphs This parameter can be a combination of the following values:
960 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
961 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
962 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
963 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
964 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
965 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
966 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
967 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
968 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
969 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
970 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
971 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
972 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
973 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*)
974 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*)
975 * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
976 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
977 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
978 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
979 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
980 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
981 * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*)
982 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
983 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*)
984 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
985 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*)
986 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
987 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
988 *
989 * (*) value not defined in all devices.
990 * @retval None
991 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)992 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
993 {
994 CLEAR_BIT(RCC->AHB2ENR1, Periphs);
995 }
996
997 /**
998 * @brief Force AHB2 peripherals reset.
999 * @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ForceReset\n
1000 * AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ForceReset\n
1001 * AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ForceReset\n
1002 * AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ForceReset\n
1003 * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ForceReset\n
1004 * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ForceReset\n
1005 * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ForceReset\n
1006 * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ForceReset\n
1007 * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ForceReset\n
1008 * AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ForceReset\n
1009 * AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ForceReset\n
1010 * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n
1011 * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ForceReset\n
1012 * AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ForceReset\n
1013 * AHB2RSTR1 AESRST LL_AHB2_GRP1_ForceReset\n
1014 * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ForceReset\n
1015 * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ForceReset\n
1016 * AHB2RSTR1 PKARST LL_AHB2_GRP1_ForceReset\n
1017 * AHB2RSTR1 SAESRST LL_AHB2_GRP1_ForceReset\n
1018 * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ForceReset\n
1019 * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ForceReset\n
1020 * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ForceReset\n
1021 * AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ForceReset\n
1022 * AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ForceReset\n
1023 * @param Periphs This parameter can be a combination of the following values:
1024 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1025 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1026 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1027 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1028 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1029 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
1030 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1031 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
1032 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1033 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1034 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
1035 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
1036 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
1037 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*)
1038 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*)
1039 * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
1040 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
1041 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
1042 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1043 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
1044 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1045 * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*)
1046 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
1047 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*)
1048 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
1049 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*)
1050 *
1051 * (*) value not defined in all devices.
1052 * @retval None
1053 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)1054 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
1055 {
1056 SET_BIT(RCC->AHB2RSTR1, Periphs);
1057 }
1058
1059 /**
1060 * @brief Release AHB2 peripherals reset.
1061 * @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ReleaseReset\n
1062 * AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
1063 * AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
1064 * AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ReleaseReset\n
1065 * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ReleaseReset\n
1066 * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
1067 * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
1068 * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
1069 * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
1070 * AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ReleaseReset\n
1071 * AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ReleaseReset\n
1072 * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n
1073 * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ReleaseReset\n
1074 * AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ReleaseReset\n
1075 * AHB2RSTR1 AESRST LL_AHB2_GRP1_ReleaseReset\n
1076 * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ReleaseReset\n
1077 * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ReleaseReset\n
1078 * AHB2RSTR1 PKARST LL_AHB2_GRP1_ReleaseReset\n
1079 * AHB2RSTR1 SAESRST LL_AHB2_GRP1_ReleaseReset\n
1080 * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ReleaseReset\n
1081 * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ReleaseReset\n
1082 * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ReleaseReset\n
1083 * AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ReleaseReset\n
1084 * AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n
1085 * @param Periphs This parameter can be a combination of the following values:
1086 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1087 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1088 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1089 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1090 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1091 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
1092 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1093 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
1094 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1095 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1096 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
1097 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
1098 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
1099 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*)
1100 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*)
1101 * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
1102 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
1103 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
1104 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1105 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
1106 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1107 * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*)
1108 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
1109 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*)
1110 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
1111 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*)
1112 *
1113 * (*) value not defined in all devices.
1114 * @retval None
1115 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)1116 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
1117 {
1118 CLEAR_BIT(RCC->AHB2RSTR1, Periphs);
1119 }
1120
1121 /**
1122 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
1123 * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1124 * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1125 * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1126 * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1127 * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1128 * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1129 * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1130 * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1131 * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1132 * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1133 * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1134 * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1135 * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1136 * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClockStopSleep\n
1137 * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1138 * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1139 * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1140 * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1141 * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1142 * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1143 * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1144 * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1145 * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1146 * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1147 * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1148 * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
1149 * @param Periphs This parameter can be a combination of the following values:
1150 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1151 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1152 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1153 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1154 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1155 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
1156 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1157 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
1158 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1159 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1160 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
1161 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
1162 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
1163 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*)
1164 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*)
1165 * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
1166 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
1167 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
1168 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1169 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
1170 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1171 * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*)
1172 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
1173 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*)
1174 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
1175 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*)
1176 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
1177 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1178 *
1179 * (*) value not defined in all devices.
1180 * @retval None
1181 */
LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1182 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1183 {
1184 __IO uint32_t tmpreg;
1185 SET_BIT(RCC->AHB2SMENR1, Periphs);
1186 /* Delay after an RCC peripheral clock enabling */
1187 tmpreg = READ_BIT(RCC->AHB2SMENR1, Periphs);
1188 (void)tmpreg;
1189 }
1190
1191 /**
1192 * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not
1193 * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1194 * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1195 * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1196 * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1197 * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1198 * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1199 * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1200 * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1201 * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1202 * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1203 * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1204 * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1205 * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1206 * AHB2SMENR1 USBPHYCMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1207 * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1208 * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1209 * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1210 * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1211 * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1212 * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1213 * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1214 * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1215 * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1216 * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1217 * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1218 * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
1219 * @param Periphs This parameter can be a combination of the following values:
1220 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1221 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1222 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1223 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1224 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1225 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
1226 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1227 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
1228 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1229 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1230 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
1231 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
1232 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
1233 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*)
1234 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*)
1235 * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
1236 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
1237 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
1238 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1239 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
1240 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1241 * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*)
1242 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
1243 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*)
1244 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
1245 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*)
1246 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
1247 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1248 *
1249 * (*) value not defined in all devices.
1250 * @retval State of Periphs (1 or 0).
1251 */
LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)1252 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
1253 {
1254 return ((READ_BIT(RCC->AHB2SMENR1, Periphs) == Periphs) ? 1UL : 0UL);
1255 }
1256
1257 /**
1258 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
1259 * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1260 * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1261 * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1262 * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1263 * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1264 * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1265 * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1266 * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1267 * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1268 * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1269 * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1270 * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1271 * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1272 * AHB2SMENR1 USBPHYCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1273 * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1274 * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1275 * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1276 * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1277 * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1278 * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1279 * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1280 * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1281 * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1282 * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1283 * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1284 * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
1285 * @param Periphs This parameter can be a combination of the following values:
1286 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1287 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1288 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1289 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1290 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1291 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
1292 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1293 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
1294 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1295 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1296 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
1297 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
1298 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
1299 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*)
1300 * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*)
1301 * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
1302 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
1303 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
1304 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1305 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
1306 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1307 * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*)
1308 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
1309 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*)
1310 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
1311 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*)
1312 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
1313 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1314 *
1315 * (*) value not defined in all devices.
1316 * @retval None
1317 */
LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1318 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1319 {
1320 CLEAR_BIT(RCC->AHB2SMENR1, Periphs);
1321 }
1322
1323 /**
1324 * @}
1325 */
1326
1327 /** @defgroup BUS_LL_EF_AHB3 AHB3
1328 * @{
1329 */
1330
1331 /**
1332 * @brief Enable AHB3 bus clock.
1333 * @rmtoll CFGR2 AHB3DIS LL_AHB3_GRP1_EnableBusClock
1334 * @retval None
1335 */
LL_AHB3_GRP1_EnableBusClock(void)1336 __STATIC_INLINE void LL_AHB3_GRP1_EnableBusClock(void)
1337 {
1338 __IO uint32_t tmpreg;
1339 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS);
1340 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS);
1341 (void)(tmpreg);
1342 }
1343
1344 /**
1345 * @brief Enable AHB3 peripherals clock.
1346 * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_EnableClock\n
1347 * AHB3ENR PWREN LL_AHB3_GRP1_EnableClock\n
1348 * AHB3ENR ADC4EN LL_AHB3_GRP1_EnableClock\n
1349 * AHB3ENR DAC1EN LL_AHB3_GRP1_EnableClock\n
1350 * AHB3ENR LPDMA1EN LL_AHB3_GRP1_EnableClock\n
1351 * AHB3ENR ADF1EN LL_AHB3_GRP1_EnableClock\n
1352 * AHB3ENR GTZC2EN LL_AHB3_GRP1_EnableClock\n
1353 * AHB3ENR SRAM4EN LL_AHB3_GRP1_EnableClock\n
1354 * @param Periphs This parameter can be a combination of the following values:
1355 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1356 * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
1357 * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
1358 * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
1359 * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
1360 * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
1361 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
1362 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
1363 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
1364 * @retval None
1365 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)1366 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
1367 {
1368 __IO uint32_t tmpreg;
1369 SET_BIT(RCC->AHB3ENR, Periphs);
1370 /* Delay after an RCC peripheral clock enabling */
1371 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
1372 (void)tmpreg;
1373 }
1374
1375 /**
1376 * @brief Check if AHB3 peripheral clock is enabled or not
1377 * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_IsEnabledClock\n
1378 * AHB3ENR PWREN LL_AHB3_GRP1_IsEnabledClock\n
1379 * AHB3ENR ADC4EN LL_AHB3_GRP1_IsEnabledClock\n
1380 * AHB3ENR DAC1EN LL_AHB3_GRP1_IsEnabledClock\n
1381 * AHB3ENR LPDMA1EN LL_AHB3_GRP1_IsEnabledClock\n
1382 * AHB3ENR ADF1EN LL_AHB3_GRP1_IsEnabledClock\n
1383 * AHB3ENR GTZC2EN LL_AHB3_GRP1_IsEnabledClock\n
1384 * AHB3ENR SRAM4EN LL_AHB3_GRP1_IsEnabledClock\n
1385 * @param Periphs This parameter can be a combination of the following values:
1386 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1387 * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
1388 * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
1389 * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
1390 * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
1391 * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
1392 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
1393 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
1394 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
1395 * @retval State of Periphs (1 or 0).
1396 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)1397 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1398 {
1399 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
1400 }
1401
1402 /**
1403 * @brief Disable AHB3 bus clock.
1404 * @rmtoll CFGR2 AHB3DIS LL_AHB3_GRP1_DisableBusClock
1405 * @retval None
1406 */
LL_AHB3_GRP1_DisableBusClock(void)1407 __STATIC_INLINE void LL_AHB3_GRP1_DisableBusClock(void)
1408 {
1409 SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS);
1410 }
1411
1412 /**
1413 * @brief Disable AHB3 peripherals clock.
1414 * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_DisableClock\n
1415 * AHB3ENR PWREN LL_AHB3_GRP1_DisableClock\n
1416 * AHB3ENR ADC4EN LL_AHB3_GRP1_DisableClock\n
1417 * AHB3ENR DAC1EN LL_AHB3_GRP1_DisableClock\n
1418 * AHB3ENR LPDMA1EN LL_AHB3_GRP1_DisableClock\n
1419 * AHB3ENR ADF1EN LL_AHB3_GRP1_DisableClock\n
1420 * AHB3ENR GTZC2EN LL_AHB3_GRP1_DisableClock\n
1421 * AHB3ENR SRAM4EN LL_AHB3_GRP1_DisableClock\n
1422 * @param Periphs This parameter can be a combination of the following values:
1423 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1424 * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
1425 * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
1426 * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
1427 * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
1428 * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
1429 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
1430 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
1431 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
1432 * @retval None
1433 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)1434 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
1435 {
1436 CLEAR_BIT(RCC->AHB3ENR, Periphs);
1437 }
1438
1439 /**
1440 * @brief Force AHB3 peripherals reset.
1441 * @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ForceReset\n
1442 * AHB3RSTR PWRRST LL_AHB3_GRP1_ForceReset\n
1443 * AHB3RSTR ADC4RST LL_AHB3_GRP1_ForceReset\n
1444 * AHB3RSTR DAC1RST LL_AHB3_GRP1_ForceReset\n
1445 * AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ForceReset\n
1446 * AHB3RSTR ADF1RST LL_AHB3_GRP1_ForceReset\n
1447 * AHB3RSTR GTZC2RST LL_AHB3_GRP1_ForceReset\n
1448 * @param Periphs This parameter can be a combination of the following values:
1449 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1450 * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
1451 * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
1452 * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
1453 * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
1454 * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
1455 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
1456 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
1457 * @retval None
1458 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)1459 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
1460 {
1461 SET_BIT(RCC->AHB3RSTR, Periphs);
1462 }
1463
1464 /**
1465 * @brief Release AHB3 peripherals reset.
1466 * @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ReleaseReset\n
1467 * AHB3RSTR PWRRST LL_AHB3_GRP1_ReleaseReset\n
1468 * AHB3RSTR ADC4RST LL_AHB3_GRP1_ReleaseReset\n
1469 * AHB3RSTR DAC1RST LL_AHB3_GRP1_ReleaseReset\n
1470 * AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ReleaseReset\n
1471 * AHB3RSTR ADF1RST LL_AHB3_GRP1_ReleaseReset\n
1472 * AHB3RSTR GTZC2RST LL_AHB3_GRP1_ReleaseReset\n
1473 * @param Periphs This parameter can be a combination of the following values:
1474 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1475 * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
1476 * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
1477 * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
1478 * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
1479 * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
1480 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
1481 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
1482 * @retval None
1483 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)1484 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
1485 {
1486 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
1487 }
1488
1489 /**
1490 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
1491 * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
1492 * AHB3SMENR PWRSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
1493 * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
1494 * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
1495 * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
1496 * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
1497 * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
1498 * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
1499 * @param Periphs This parameter can be a combination of the following values:
1500 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1501 * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
1502 * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
1503 * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
1504 * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
1505 * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
1506 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
1507 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
1508 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
1509 * @retval None
1510 */
LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)1511 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
1512 {
1513 __IO uint32_t tmpreg;
1514 SET_BIT(RCC->AHB3SMENR, Periphs);
1515 /* Delay after an RCC peripheral clock enabling */
1516 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
1517 (void)tmpreg;
1518 }
1519
1520 /**
1521 * @brief Check if AHB3 peripheral clocks in Sleep and Stop modes is enabled or not
1522 * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
1523 * AHB3SMENR PWRSMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
1524 * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
1525 * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
1526 * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
1527 * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
1528 * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
1529 * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
1530 * @param Periphs This parameter can be a combination of the following values:
1531 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1532 * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
1533 * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
1534 * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
1535 * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
1536 * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
1537 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
1538 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
1539 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
1540 * @retval State of Periphs (1 or 0).
1541 */
LL_AHB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)1542 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
1543 {
1544 return ((READ_BIT(RCC->AHB3SMENR, Periphs) == Periphs) ? 1UL : 0UL);
1545 }
1546
1547 /**
1548 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
1549 * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1550 * AHB3SMENR PWRSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1551 * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1552 * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1553 * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1554 * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1555 * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1556 * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1557 * @param Periphs This parameter can be a combination of the following values:
1558 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1559 * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
1560 * @arg @ref LL_AHB3_GRP1_PERIPH_PWR
1561 * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
1562 * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
1563 * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
1564 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
1565 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
1566 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
1567 * @retval None
1568 */
LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)1569 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
1570 {
1571 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
1572 }
1573
1574 /**
1575 * @}
1576 */
1577
1578 /** @defgroup BUS_LL_EF_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH
1579 * @{
1580 */
1581
1582 /**
1583 * @brief Enable AHB2_2 bus clock.
1584 * @rmtoll CFGR2 AHB2DIS2 LL_AHB2_GRP2_EnableBusClock
1585 * @retval None
1586 */
LL_AHB2_GRP2_EnableBusClock(void)1587 __STATIC_INLINE void LL_AHB2_GRP2_EnableBusClock(void)
1588 {
1589 __IO uint32_t tmpreg;
1590 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2);
1591 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2);
1592 (void)(tmpreg);
1593 }
1594
1595 /**
1596 * @brief Enable AHB2 peripherals clock.
1597 * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_EnableClock\n
1598 * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_EnableClock\n
1599 * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_EnableClock\n
1600 * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_EnableClock\n
1601 * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_EnableClock\n
1602 * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_EnableClock\n
1603 * @param Periphs This parameter can be a combination of the following values:
1604 * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
1605 * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*)
1606 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
1607 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*)
1608 * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
1609 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*)
1610 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
1611 *
1612 *
1613 * (*) value not defined in all devices.
1614 * @retval None
1615 */
LL_AHB2_GRP2_EnableClock(uint32_t Periphs)1616 __STATIC_INLINE void LL_AHB2_GRP2_EnableClock(uint32_t Periphs)
1617 {
1618 __IO uint32_t tmpreg;
1619 SET_BIT(RCC->AHB2ENR2, Periphs);
1620 /* Delay after an RCC peripheral clock enabling */
1621 tmpreg = READ_BIT(RCC->AHB2ENR2, Periphs);
1622 (void)tmpreg;
1623 }
1624
1625 /**
1626 * @brief Check if AHB2 peripheral clock is enabled or not
1627 * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_IsEnabledClock\n
1628 * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_IsEnabledClock\n
1629 * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_IsEnabledClock\n
1630 * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_IsEnabledClock\n
1631 * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_DisableClock\n
1632 * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_IsEnabledClock\n
1633 * @param Periphs This parameter can be a combination of the following values:
1634 * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
1635 * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*)
1636 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
1637 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*)
1638 * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
1639 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*)
1640 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
1641 *
1642 * (*) value not defined in all devices.
1643 * @retval None
1644 * @retval State of Periphs (1 or 0).
1645 */
LL_AHB2_GRP2_IsEnabledClock(uint32_t Periphs)1646 __STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClock(uint32_t Periphs)
1647 {
1648 return ((READ_BIT(RCC->AHB2ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1649 }
1650
1651 /**
1652 * @brief Disable AHB2_2 bus clock.
1653 * @rmtoll CFGR2 AHB2DIS2 LL_AHB2_GRP2_DisableBusClock
1654 * @retval None
1655 */
LL_AHB2_GRP2_DisableBusClock(void)1656 __STATIC_INLINE void LL_AHB2_GRP2_DisableBusClock(void)
1657 {
1658 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2);
1659 }
1660
1661 /**
1662 * @brief Disable AHB2 peripherals clock.
1663 * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_DisableClock\n
1664 * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_DisableClock\n
1665 * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_DisableClock\n
1666 * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_DisableClock\n
1667 * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_DisableClock\n
1668 * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_DisableClock\n
1669 * @param Periphs This parameter can be a combination of the following values:
1670 * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
1671 * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*)
1672 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
1673 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*)
1674 * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
1675 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*)
1676 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
1677 *
1678 * (*) value not defined in all devices.
1679 * @retval None
1680 */
LL_AHB2_GRP2_DisableClock(uint32_t Periphs)1681 __STATIC_INLINE void LL_AHB2_GRP2_DisableClock(uint32_t Periphs)
1682 {
1683 CLEAR_BIT(RCC->AHB2ENR2, Periphs);
1684 }
1685
1686 /**
1687 * @brief Force AHB2 peripherals reset.
1688 * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ForceReset\n
1689 * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ForceReset\n
1690 * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ForceReset\n
1691 * AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ForceReset\n
1692 * @param Periphs This parameter can be a combination of the following values:
1693 * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
1694 * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*)
1695 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
1696 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*)
1697 * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
1698 *
1699 * (*) value not defined in all devices.
1700 * @retval None
1701 */
LL_AHB2_GRP2_ForceReset(uint32_t Periphs)1702 __STATIC_INLINE void LL_AHB2_GRP2_ForceReset(uint32_t Periphs)
1703 {
1704 SET_BIT(RCC->AHB2RSTR2, Periphs);
1705 }
1706
1707 /**
1708 * @brief Release AHB2 peripherals reset.
1709 * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ReleaseReset\n
1710 * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ReleaseReset\n
1711 * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ReleaseReset\n
1712 * AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ReleaseReset\n
1713 * @param Periphs This parameter can be a combination of the following values:
1714 * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
1715 * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*)
1716 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
1717 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*)
1718 * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
1719 *
1720 * (*) value not defined in all devices.
1721 * @retval None
1722 */
LL_AHB2_GRP2_ReleaseReset(uint32_t Periphs)1723 __STATIC_INLINE void LL_AHB2_GRP2_ReleaseReset(uint32_t Periphs)
1724 {
1725 CLEAR_BIT(RCC->AHB2RSTR2, Periphs);
1726 }
1727
1728 /**
1729 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
1730 * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_EnableClockStopSleep\n
1731 * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
1732 * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
1733 * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
1734 * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
1735 * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
1736 * @param Periphs This parameter can be a combination of the following values:
1737 * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
1738 * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*)
1739 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
1740 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*)
1741 * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
1742 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*)
1743 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
1744 *
1745 * (*) value not defined in all devices.
1746 * @retval None
1747 */
LL_AHB2_GRP2_EnableClockStopSleep(uint32_t Periphs)1748 __STATIC_INLINE void LL_AHB2_GRP2_EnableClockStopSleep(uint32_t Periphs)
1749 {
1750 __IO uint32_t tmpreg;
1751 SET_BIT(RCC->AHB2SMENR2, Periphs);
1752 /* Delay after an RCC peripheral clock enabling */
1753 tmpreg = READ_BIT(RCC->AHB2SMENR2, Periphs);
1754 (void)tmpreg;
1755 }
1756
1757 /**
1758 * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not
1759 * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
1760 * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
1761 * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
1762 * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
1763 * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
1764 * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
1765 * @param Periphs This parameter can be a combination of the following values:
1766 * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
1767 * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*)
1768 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
1769 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*)
1770 * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
1771 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*)
1772 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
1773 *
1774 * (*) value not defined in all devices.
1775 * @retval State of Periphs (1 or 0).
1776 */
LL_AHB2_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)1777 __STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)
1778 {
1779 return ((READ_BIT(RCC->AHB2SMENR2, Periphs) == Periphs) ? 1UL : 0UL);
1780 }
1781
1782 /**
1783 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
1784 * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_DisableClockStopSleep\n
1785 * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
1786 * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
1787 * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
1788 * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
1789 * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
1790 * @param Periphs This parameter can be a combination of the following values:
1791 * @arg @ref LL_AHB2_GRP2_PERIPH_ALL
1792 * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*)
1793 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
1794 * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*)
1795 * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
1796 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*)
1797 * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
1798 *
1799 * (*) value not defined in all devices.
1800 * @retval None
1801 */
LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs)1802 __STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs)
1803 {
1804 CLEAR_BIT(RCC->AHB2SMENR2, Periphs);
1805 }
1806
1807 /**
1808 * @}
1809 */
1810
1811 /** @defgroup BUS_LL_EF_APB1 APB1
1812 * @{
1813 */
1814
1815 /**
1816 * @brief Enable APB1 bus clock.
1817 * @rmtoll CFGR2 APB1DIS LL_APB1_GRP1_EnableBusClock
1818 * @retval None
1819 */
LL_APB1_GRP1_EnableBusClock(void)1820 __STATIC_INLINE void LL_APB1_GRP1_EnableBusClock(void)
1821 {
1822 __IO uint32_t tmpreg;
1823 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS);
1824 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS);
1825 (void)(tmpreg);
1826 }
1827
1828 /**
1829 * @brief Enable APB1 peripherals clock.
1830 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
1831 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
1832 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
1833 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
1834 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
1835 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
1836 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
1837 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
1838 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
1839 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
1840 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
1841 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
1842 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
1843 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
1844 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
1845 * APB1ENR1 USART6N LL_APB1_GRP1_EnableClock\n
1846 * @param Periphs This parameter can be a combination of the following values:
1847 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1848 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1849 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1850 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1851 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1852 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1853 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1854 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1855 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1856 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
1857 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1858 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1859 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1860 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1861 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1862 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1863 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1864 *
1865 * (*) value not defined in all devices.
1866 * @retval None
1867 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1868 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1869 {
1870 __IO uint32_t tmpreg;
1871 SET_BIT(RCC->APB1ENR1, Periphs);
1872 /* Delay after an RCC peripheral clock enabling */
1873 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
1874 (void)tmpreg;
1875 }
1876
1877 /**
1878 * @brief Enable APB1 peripherals clock.
1879 * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
1880 * APB1ENR2 I2C5EN LL_APB1_GRP2_EnableClock\n
1881 * APB1ENR2 I2C6EN LL_APB1_GRP2_EnableClock\n
1882 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock\n
1883 * APB1ENR2 FDCAN1EN LL_APB1_GRP2_EnableClock\n
1884 * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
1885 * @param Periphs This parameter can be a combination of the following values:
1886 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1887 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
1888 * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
1889 * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
1890 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1891 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
1892 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
1893 * @retval None
1894 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)1895 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
1896 {
1897 __IO uint32_t tmpreg;
1898 SET_BIT(RCC->APB1ENR2, Periphs);
1899 /* Delay after an RCC peripheral clock enabling */
1900 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
1901 (void)tmpreg;
1902 }
1903
1904 /**
1905 * @brief Check if APB1 peripheral clock is enabled or not
1906 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1907 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1908 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1909 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1910 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1911 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1912 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1913 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1914 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
1915 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
1916 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
1917 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
1918 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1919 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1920 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
1921 * APB1ENR1 USART6EN LL_APB1_GRP1_IsEnabledClock\n
1922 * @param Periphs This parameter can be a combination of the following values:
1923 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1924 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1925 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1926 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1927 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1928 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1929 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1930 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1931 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1932 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
1933 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1934 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1935 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1936 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1937 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1938 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1939 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1940 *
1941 * (*) value not defined in all devices.
1942 * @retval State of Periphs (1 or 0).
1943 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1944 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1945 {
1946 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
1947 }
1948
1949 /**
1950 * @brief Check if APB1 peripheral clock is enabled or not
1951 * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
1952 * APB1ENR2 I2C5EN LL_APB1_GRP2_IsEnabledClock\n
1953 * APB1ENR2 I2C6EN LL_APB1_GRP2_IsEnabledClock\n
1954 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n
1955 * APB1ENR2 FDCAN1EN LL_APB1_GRP2_IsEnabledClock\n
1956 * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
1957 * @param Periphs This parameter can be a combination of the following values:
1958 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1959 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
1960 * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
1961 * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
1962 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1963 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
1964 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
1965 * @retval State of Periphs (1 or 0).
1966 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1967 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1968 {
1969 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1970 }
1971
1972 /**
1973 * @brief Disable APB1 bus clock.
1974 * @note except for IWDG.
1975 * @rmtoll CFGR2 APB1DIS LL_APB1_GRP1_DisableBusClock
1976 * @retval None
1977 */
LL_APB1_GRP1_DisableBusClock(void)1978 __STATIC_INLINE void LL_APB1_GRP1_DisableBusClock(void)
1979 {
1980 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS);
1981 }
1982
1983 /**
1984 * @brief Disable APB1 peripherals clock.
1985 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1986 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1987 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
1988 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
1989 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
1990 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
1991 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
1992 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1993 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1994 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
1995 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
1996 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
1997 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1998 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1999 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
2000 * APB1ENR1 USART6EN LL_APB1_GRP1_DisableClock\n
2001 * @param Periphs This parameter can be a combination of the following values:
2002 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
2003 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2004 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2005 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2006 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2007 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2008 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2009 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2010 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2011 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
2012 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2013 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2014 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2015 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2016 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2017 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2018 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2019 *
2020 * (*) value not defined in all devices.
2021 * @retval None
2022 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)2023 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
2024 {
2025 CLEAR_BIT(RCC->APB1ENR1, Periphs);
2026 }
2027
2028 /**
2029 * @brief Disable APB1 peripherals clock.
2030 * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
2031 * APB1ENR2 I2C5EN LL_APB1_GRP2_DisableClock\n
2032 * APB1ENR2 I2C6EN LL_APB1_GRP2_DisableClock\n
2033 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock\n
2034 * APB1ENR2 FDCAN1EN LL_APB1_GRP2_DisableClock\n
2035 * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock\n
2036 * @param Periphs This parameter can be a combination of the following values:
2037 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2038 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
2039 * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
2040 * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
2041 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2042 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
2043 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
2044 * @retval None
2045 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)2046 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
2047 {
2048 CLEAR_BIT(RCC->APB1ENR2, Periphs);
2049 }
2050
2051 /**
2052 * @brief Force APB1 peripherals reset.
2053 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
2054 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
2055 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
2056 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
2057 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
2058 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
2059 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
2060 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
2061 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
2062 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
2063 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
2064 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
2065 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
2066 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
2067 * APB1RSTR1 USART6RST LL_APB1_GRP1_ForceReset\n
2068 * @param Periphs This parameter can be a combination of the following values:
2069 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
2070 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2071 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2072 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2073 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2074 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2075 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2076 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2077 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
2078 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2079 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2080 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2081 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2082 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2083 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2084 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2085 *
2086 * (*) value not defined in all devices.
2087 * @retval None
2088 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)2089 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
2090 {
2091 SET_BIT(RCC->APB1RSTR1, Periphs);
2092 }
2093
2094 /**
2095 * @brief Force APB1 peripherals reset.
2096 * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_DisableClock\n
2097 * APB1RSTR2 I2C5RST LL_APB1_GRP2_DisableClock\n
2098 * APB1RSTR2 I2C6RST LL_APB1_GRP2_DisableClock\n
2099 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_DisableClock\n
2100 * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_DisableClock\n
2101 * APB1RSTR2 UCPDRST LL_APB1_GRP2_DisableClock\n
2102 * @param Periphs This parameter can be a combination of the following values:
2103 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2104 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
2105 * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
2106 * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
2107 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2108 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
2109 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
2110 *
2111 * (*) value not defined in all devices.
2112 * @retval None
2113 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)2114 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
2115 {
2116 SET_BIT(RCC->APB1RSTR2, Periphs);
2117 }
2118
2119 /**
2120 * @brief Release APB1 peripherals reset.
2121 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
2122 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
2123 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
2124 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
2125 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
2126 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
2127 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
2128 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
2129 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
2130 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
2131 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
2132 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
2133 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
2134 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
2135 * APB1RSTR1 USART6RST LL_APB1_GRP1_ReleaseReset\n
2136 * @param Periphs This parameter can be a combination of the following values:
2137 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
2138 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2139 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2140 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2141 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2142 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2143 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2144 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2145 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
2146 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2147 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2148 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2149 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2150 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2151 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2152 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2153 *
2154 * (*) value not defined in all devices.
2155 * @retval None
2156 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)2157 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
2158 {
2159 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
2160 }
2161
2162 /**
2163 * @brief Release APB1 peripherals reset.
2164 * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
2165 * APB1RSTR2 I2C5RST LL_APB1_GRP2_ReleaseReset\n
2166 * APB1RSTR2 I2C6RST LL_APB1_GRP2_ReleaseReset\n
2167 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset\n
2168 * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_ReleaseReset\n
2169 * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset\n
2170 * @param Periphs This parameter can be a combination of the following values:
2171 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2172 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
2173 * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
2174 * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
2175 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2176 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
2177 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
2178 *
2179 * (*) value not defined in all devices.
2180 * @retval None
2181 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)2182 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
2183 {
2184 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
2185 }
2186
2187 /**
2188 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
2189 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2190 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2191 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2192 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2193 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2194 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2195 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2196 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2197 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2198 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2199 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2200 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2201 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2202 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
2203 * APB1SMENR1 USART6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
2204 * @param Periphs This parameter can be a combination of the following values:
2205 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
2206 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2207 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2208 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2209 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2210 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2211 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2212 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2213 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
2214 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2215 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2216 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2217 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2218 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2219 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2220 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2221 *
2222 * (*) value not defined in all devices.
2223 * @retval None
2224 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)2225 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
2226 {
2227 __IO uint32_t tmpreg;
2228 SET_BIT(RCC->APB1SMENR1, Periphs);
2229 /* Delay after an RCC peripheral clock enabling */
2230 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
2231 (void)tmpreg;
2232 }
2233
2234 /**
2235 * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
2236 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2237 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2238 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2239 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2240 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2241 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2242 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2243 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2244 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2245 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2246 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2247 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2248 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2249 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2250 * APB1SMENR1 USART6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
2251 * @param Periphs This parameter can be a combination of the following values:
2252 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
2253 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2254 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2255 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2256 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2257 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2258 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2259 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2260 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
2261 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2262 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2263 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2264 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2265 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2266 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2267 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2268 *
2269 * (*) value not defined in all devices.
2270 * @retval State of Periphs (1 or 0).
2271 */
LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)2272 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
2273 {
2274 return ((READ_BIT(RCC->APB1SMENR1, Periphs) == Periphs) ? 1UL : 0UL);
2275 }
2276
2277 /**
2278 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
2279 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2280 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2281 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2282 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2283 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2284 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2285 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2286 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2287 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2288 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2289 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2290 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2291 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2292 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
2293 * APB1SMENR1 USART6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
2294 * @param Periphs This parameter can be a combination of the following values:
2295 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
2296 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2297 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2298 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2299 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2300 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2301 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2302 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2303 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
2304 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2305 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2306 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2307 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2308 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2309 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2310 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2311 *
2312 * (*) value not defined in all devices.
2313 * @retval None
2314 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)2315 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
2316 {
2317 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
2318 }
2319
2320 /**
2321 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
2322 * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
2323 * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_EnableClockStopSleep\n
2324 * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_EnableClockStopSleep\n
2325 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep\n
2326 * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
2327 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
2328 * @param Periphs This parameter can be a combination of the following values:
2329 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2330 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
2331 * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
2332 * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
2333 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2334 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
2335 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
2336 *
2337 * (*) value not defined in all devices.
2338 * @retval None
2339 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)2340 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
2341 {
2342 __IO uint32_t tmpreg;
2343 SET_BIT(RCC->APB1SMENR2, Periphs);
2344 /* Delay after an RCC peripheral clock enabling */
2345 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
2346 (void)tmpreg;
2347 }
2348
2349 /**
2350 * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
2351 * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
2352 * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
2353 * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
2354 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
2355 * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
2356 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep
2357 * @param Periphs This parameter can be a combination of the following values:
2358 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2359 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
2360 * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
2361 * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
2362 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2363 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
2364 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
2365 *
2366 * (*) value not defined in all devices.
2367 * @retval State of Periphs (1 or 0).
2368 */
LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)2369 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)
2370 {
2371 return ((READ_BIT(RCC->APB1SMENR2, Periphs) == Periphs) ? 1UL : 0UL);
2372 }
2373
2374 /**
2375 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
2376 * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
2377 * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_DisableClockStopSleep\n
2378 * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_DisableClockStopSleep\n
2379 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep\n
2380 * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
2381 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
2382 * @param Periphs This parameter can be a combination of the following values:
2383 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2384 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
2385 * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
2386 * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
2387 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2388 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
2389 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
2390 *
2391 * (*) value not defined in all devices.
2392 * @retval None
2393 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)2394 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
2395 {
2396 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
2397 }
2398
2399 /**
2400 * @}
2401 */
2402
2403 /** @defgroup BUS_LL_EF_APB2 APB2
2404 * @{
2405 */
2406
2407 /**
2408 * @brief Enable APB2 bus clock.
2409 * @rmtoll CFGR2 APB2DIS LL_APB2_GRP1_EnableBusClock
2410 * @retval None
2411 */
LL_APB2_GRP1_EnableBusClock(void)2412 __STATIC_INLINE void LL_APB2_GRP1_EnableBusClock(void)
2413 {
2414 __IO uint32_t tmpreg;
2415 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS);
2416 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS);
2417 (void)(tmpreg);
2418 }
2419
2420 /**
2421 * @brief Enable APB2 peripherals clock.
2422 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
2423 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
2424 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
2425 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
2426 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
2427 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
2428 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
2429 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
2430 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
2431 * APB2ENR USBEN LL_APB2_GRP1_EnableClock\n
2432 * APB2ENR GFXTIMEN LL_APB2_GRP1_EnableClock\n
2433 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
2434 * APB2ENR DSIHOSTEN LL_APB2_GRP1_EnableClock\n
2435 * @param Periphs This parameter can be a combination of the following values:
2436 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2437 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2438 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2439 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2440 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2441 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2442 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2443 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2444 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2445 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2446 * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*)
2447 * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*)
2448 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2449 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2450 *
2451 * (*) value not defined in all devices.
2452 * @retval None
2453 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)2454 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
2455 {
2456 __IO uint32_t tmpreg;
2457 SET_BIT(RCC->APB2ENR, Periphs);
2458 /* Delay after an RCC peripheral clock enabling */
2459 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
2460 (void)tmpreg;
2461 }
2462
2463 /**
2464 * @brief Check if APB2 peripheral clock is enabled or not
2465 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
2466 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
2467 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
2468 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
2469 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
2470 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
2471 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
2472 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
2473 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
2474 * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock\n
2475 * APB2ENR GFXTIMEN LL_APB2_GRP1_IsEnabledClock\n
2476 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
2477 * APB2ENR DSIHOSTEN LL_APB2_GRP1_IsEnabledClock\n
2478 * @param Periphs This parameter can be a combination of the following values:
2479 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2480 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2481 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2482 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2483 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2484 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2485 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2486 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2487 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2488 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2489 * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*)
2490 * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*)
2491 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2492 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2493 *
2494 * (*) value not defined in all devices.
2495 * @retval State of Periphs (1 or 0).
2496 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2497 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2498 {
2499 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
2500 }
2501
2502 /**
2503 * @brief Disable APB2 bus clock.
2504 * @rmtoll CFGR2 APB2DIS LL_APB2_GRP1_DisableBusClock
2505 * @retval None
2506 */
LL_APB2_GRP1_DisableBusClock(void)2507 __STATIC_INLINE void LL_APB2_GRP1_DisableBusClock(void)
2508 {
2509 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS);
2510 }
2511
2512 /**
2513 * @brief Disable APB2 peripherals clock.
2514 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
2515 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
2516 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
2517 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
2518 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
2519 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
2520 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
2521 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
2522 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
2523 * APB2ENR USBEN LL_APB2_GRP1_DisableClock\n
2524 * APB2ENR GFXTIMEN LL_APB2_GRP1_DisableClock\n
2525 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
2526 * APB2ENR DSIHOSTEN LL_APB2_GRP1_DisableClock\n
2527 * @param Periphs This parameter can be a combination of the following values:
2528 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2529 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2530 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2531 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2532 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2533 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2534 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2535 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2536 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2537 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2538 * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*)
2539 * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*)
2540 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2541 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2542 *
2543 * (*) value not defined in all devices.
2544 * @retval None
2545 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)2546 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2547 {
2548 CLEAR_BIT(RCC->APB2ENR, Periphs);
2549 }
2550
2551 /**
2552 * @brief Force APB2 peripherals reset.
2553 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
2554 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
2555 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
2556 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
2557 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
2558 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
2559 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
2560 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
2561 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
2562 * APB2RSTR USBRST LL_APB2_GRP1_ForceReset\n
2563 * APB2RSTR GFXTIMRST LL_APB2_GRP1_ForceReset\n
2564 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
2565 * APB2RSTR DSIHOSTRST LL_APB2_GRP1_ForceReset\n
2566 * @param Periphs This parameter can be a combination of the following values:
2567 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2568 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2569 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2570 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2571 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2572 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2573 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2574 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2575 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2576 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2577 * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*)
2578 * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*)
2579 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2580 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2581 *
2582 *
2583 * (*) value not defined in all devices.
2584 * @retval None
2585 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)2586 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
2587 {
2588 SET_BIT(RCC->APB2RSTR, Periphs);
2589 }
2590
2591 /**
2592 * @brief Release APB2 peripherals reset.
2593 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
2594 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
2595 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
2596 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
2597 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
2598 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
2599 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
2600 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
2601 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
2602 * APB2RSTR USBRST LL_APB2_GRP1_ReleaseReset\n
2603 * APB2RSTR GFXTIMRST LL_APB2_GRP1_ReleaseReset\n
2604 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
2605 * APB2RSTR DSIHOSTRST LL_APB2_GRP1_ReleaseReset\n
2606 * @param Periphs This parameter can be a combination of the following values:
2607 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2608 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2609 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2610 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2611 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2612 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2613 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2614 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2615 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2616 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2617 * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*)
2618 * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*)
2619 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2620 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2621 *
2622 *
2623 * (*) value not defined in all devices.
2624 * @retval None
2625 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)2626 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
2627 {
2628 CLEAR_BIT(RCC->APB2RSTR, Periphs);
2629 }
2630
2631 /**
2632 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
2633 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2634 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2635 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2636 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2637 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2638 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2639 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2640 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2641 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2642 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2643 * APB2SMENR USBSMEN LL_APB2_GRP1_EnableClockStopSleep\n
2644 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
2645 * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_EnableClockStopSleep\n
2646 * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n
2647 * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_EnableClockStopSleep\n
2648 * @param Periphs This parameter can be a combination of the following values:
2649 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2650 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2651 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2652 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2653 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2654 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2655 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2656 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2657 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2658 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2659 * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*)
2660 * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM(*)
2661 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2662 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2663 *
2664 * (*) value not defined in all devices.
2665 * @retval None
2666 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)2667 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
2668 {
2669 __IO uint32_t tmpreg;
2670 SET_BIT(RCC->APB2SMENR, Periphs);
2671 /* Delay after an RCC peripheral clock enabling */
2672 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
2673 (void)tmpreg;
2674 }
2675
2676
2677 /**
2678 * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not
2679 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2680 * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2681 * APB2SMENR TIM8SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2682 * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2683 * APB2SMENR TIM15SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2684 * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2685 * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2686 * APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2687 * APB2SMENR SAI2SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2688 * APB2SMENR USBSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2689 * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2690 * APB2SMENR LTDCSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2691 * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
2692 * @param Periphs This parameter can be a combination of the following values:
2693 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2694 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2695 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2696 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2697 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2698 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2699 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2700 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2701 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2702 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2703 * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*)
2704 * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*)
2705 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2706 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2707 *
2708 * (*) value not defined in all devices.
2709 * @retval State of Periphs (1 or 0).
2710 */
LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)2711 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
2712 {
2713 return ((READ_BIT(RCC->APB2SMENR, Periphs) == Periphs) ? 1UL : 0UL);
2714 }
2715
2716 /**
2717 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
2718 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2719 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2720 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2721 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2722 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2723 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2724 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2725 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2726 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
2727 * APB2SMENR USBSMEN LL_APB2_GRP1_DisableClockStopSleep\n
2728 * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_DisableClockStopSleep\n
2729 * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n
2730 * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_DisableClockStopSleep\n
2731 * @param Periphs This parameter can be a combination of the following values:
2732 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2733 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2734 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2735 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2736 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2737 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2738 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2739 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2740 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2741 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2742 * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*)
2743 * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*)
2744 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2745 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2746 *
2747 * (*) value not defined in all devices.
2748 * @retval None
2749 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)2750 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
2751 {
2752 CLEAR_BIT(RCC->APB2SMENR, Periphs);
2753 }
2754
2755 /**
2756 * @}
2757 */
2758
2759
2760 /** @defgroup BUS_LL_EF_APB3 APB3
2761 * @{
2762 */
2763
2764 /**
2765 * @brief Enable APB3 bus clock.
2766 * @rmtoll CFGR2 APB3DIS LL_APB3_GRP1_EnableBusClock
2767 * @retval None
2768 */
LL_APB3_GRP1_EnableBusClock(void)2769 __STATIC_INLINE void LL_APB3_GRP1_EnableBusClock(void)
2770 {
2771 __IO uint32_t tmpreg;
2772 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS);
2773 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS);
2774 (void)(tmpreg);
2775 }
2776
2777 /**
2778 * @brief Enable APB3 peripherals clock.
2779 * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_EnableClock\n
2780 * APB3ENR SPI3EN LL_APB3_GRP1_EnableClock\n
2781 * APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock\n
2782 * APB3ENR I2C3EN LL_APB3_GRP1_EnableClock\n
2783 * APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock\n
2784 * APB3ENR LPTIM3EN LL_APB3_GRP1_EnableClock\n
2785 * APB3ENR LPTIM4EN LL_APB3_GRP1_EnableClock\n
2786 * APB3ENR OPAMPEN LL_APB3_GRP1_EnableClock\n
2787 * APB3ENR COMPEN LL_APB3_GRP1_EnableClock\n
2788 * APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n
2789 * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock\n
2790 * @param Periphs This parameter can be a combination of the following values:
2791 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2792 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2793 * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
2794 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2795 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
2796 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2797 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2798 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2799 * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
2800 * @arg @ref LL_APB3_GRP1_PERIPH_COMP
2801 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2802 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2803 * @retval None
2804 */
LL_APB3_GRP1_EnableClock(uint32_t Periphs)2805 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
2806 {
2807 __IO uint32_t tmpreg;
2808 SET_BIT(RCC->APB3ENR, Periphs);
2809 /* Delay after an RCC peripheral clock enabling */
2810 tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
2811 (void)tmpreg;
2812 }
2813
2814 /**
2815 * @brief Check if APB3 peripheral clock is enabled or not
2816 * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_IsEnabledClock\n
2817 * APB3ENR SPI3EN LL_APB3_GRP1_IsEnabledClock\n
2818 * APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock\n
2819 * APB3ENR I2C3EN LL_APB3_GRP1_IsEnabledClock\n
2820 * APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock\n
2821 * APB3ENR LPTIM3EN LL_APB3_GRP1_IsEnabledClock\n
2822 * APB3ENR LPTIM4EN LL_APB3_GRP1_IsEnabledClock\n
2823 * APB3ENR OPAMPEN LL_APB3_GRP1_IsEnabledClock\n
2824 * APB3ENR COMPEN LL_APB3_GRP1_IsEnabledClock\n
2825 * APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n
2826 * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock\n
2827 * @param Periphs This parameter can be a combination of the following values:
2828 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2829 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2830 * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
2831 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2832 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
2833 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2834 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2835 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2836 * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
2837 * @arg @ref LL_APB3_GRP1_PERIPH_COMP
2838 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2839 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2840 * @retval State of Periphs (1 or 0).
2841 */
LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)2842 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
2843 {
2844 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
2845 }
2846
2847 /**
2848 * @brief Disable APB3 bus clock.
2849 * @rmtoll CFGR2 APB3DIS LL_APB3_GRP1_DisableBusClock
2850 * @retval None
2851 */
LL_APB3_GRP1_DisableBusClock(void)2852 __STATIC_INLINE void LL_APB3_GRP1_DisableBusClock(void)
2853 {
2854 SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS);
2855 }
2856
2857 /**
2858 * @brief Disable APB2 peripherals clock.
2859 * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_DisableClock\n
2860 * APB3ENR SPI3EN LL_APB3_GRP1_DisableClock\n
2861 * APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock\n
2862 * APB3ENR I2C3EN LL_APB3_GRP1_DisableClock\n
2863 * APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock\n
2864 * APB3ENR LPTIM3EN LL_APB3_GRP1_DisableClock\n
2865 * APB3ENR LPTIM4EN LL_APB3_GRP1_DisableClock\n
2866 * APB3ENR OPAMPEN LL_APB3_GRP1_DisableClock\n
2867 * APB3ENR COMPEN LL_APB3_GRP1_DisableClock\n
2868 * APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n
2869 * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock\n
2870 * @param Periphs This parameter can be a combination of the following values:
2871 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2872 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2873 * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
2874 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2875 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
2876 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2877 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2878 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2879 * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
2880 * @arg @ref LL_APB3_GRP1_PERIPH_COMP
2881 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2882 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2883 * @retval None
2884 */
LL_APB3_GRP1_DisableClock(uint32_t Periphs)2885 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
2886 {
2887 CLEAR_BIT(RCC->APB3ENR, Periphs);
2888 }
2889
2890 /**
2891 * @brief Force APB3 peripherals reset.
2892 * @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ForceReset\n
2893 * APB3RSTR SPI3RST LL_APB3_GRP1_ForceReset\n
2894 * APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset\n
2895 * APB3RSTR I2C3RST LL_APB3_GRP1_ForceReset\n
2896 * APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset\n
2897 * APB3RSTR LPTIM3RST LL_APB3_GRP1_ForceReset\n
2898 * APB3RSTR LPTIM4RST LL_APB3_GRP1_ForceReset\n
2899 * APB3RSTR OPAMPRST LL_APB3_GRP1_ForceReset\n
2900 * APB3RSTR COMPRST LL_APB3_GRP1_ForceReset\n
2901 * APB3RSTR VREFRST LL_APB3_GRP1_ForceReset\n
2902 * APB3RSTR RTCAPBRST LL_APB3_GRP1_ForceReset\n
2903 * @param Periphs This parameter can be a combination of the following values:
2904 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2905 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2906 * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
2907 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2908 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
2909 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2910 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2911 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2912 * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
2913 * @arg @ref LL_APB3_GRP1_PERIPH_COMP
2914 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2915 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2916 * @retval None
2917 */
LL_APB3_GRP1_ForceReset(uint32_t Periphs)2918 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
2919 {
2920 SET_BIT(RCC->APB3RSTR, Periphs);
2921 }
2922
2923 /**
2924 * @brief Release APB3 peripherals reset.
2925 * @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ReleaseReset\n
2926 * APB3RSTR SPI3RST LL_APB3_GRP1_ReleaseReset\n
2927 * APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset\n
2928 * APB3RSTR I2C3RST LL_APB3_GRP1_ReleaseReset\n
2929 * APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset\n
2930 * APB3RSTR LPTIM3RST LL_APB3_GRP1_ReleaseReset\n
2931 * APB3RSTR LPTIM4RST LL_APB3_GRP1_ReleaseReset\n
2932 * APB3RSTR OPAMPRST LL_APB3_GRP1_ReleaseReset\n
2933 * APB3RSTR COMPRST LL_APB3_GRP1_ReleaseReset\n
2934 * APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset\n
2935 * APB3RSTR RTCAPBRST LL_APB3_GRP1_ReleaseReset\n
2936 * @param Periphs This parameter can be a combination of the following values:
2937 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2938 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2939 * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
2940 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2941 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
2942 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2943 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2944 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2945 * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
2946 * @arg @ref LL_APB3_GRP1_PERIPH_COMP
2947 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2948 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2949 * @retval None
2950 */
LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)2951 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
2952 {
2953 CLEAR_BIT(RCC->APB3RSTR, Periphs);
2954 }
2955
2956 /**
2957 * @brief Enable APB3 peripheral clocks in Sleep and Stop modes
2958 * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_EnableClockStopSleep\n
2959 * APB3SMENR SPI3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
2960 * APB3SMENR LPUART1SMEN LL_APB3_GRP1_EnableClockStopSleep\n
2961 * APB3SMENR I2C3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
2962 * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_EnableClockStopSleep\n
2963 * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
2964 * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_EnableClockStopSleep\n
2965 * APB3SMENR OPAMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n
2966 * APB3SMENR COMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n
2967 * APB3SMENR VREFSMEN LL_APB3_GRP1_EnableClockStopSleep\n
2968 * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_EnableClockStopSleep\n
2969 * @param Periphs This parameter can be a combination of the following values:
2970 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2971 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2972 * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
2973 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2974 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
2975 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2976 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2977 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2978 * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
2979 * @arg @ref LL_APB3_GRP1_PERIPH_COMP
2980 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2981 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2982 * @retval None
2983 */
LL_APB3_GRP1_EnableClockStopSleep(uint32_t Periphs)2984 __STATIC_INLINE void LL_APB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
2985 {
2986 __IO uint32_t tmpreg;
2987 SET_BIT(RCC->APB3SMENR, Periphs);
2988 /* Delay after an RCC peripheral clock enabling */
2989 tmpreg = READ_BIT(RCC->APB3SMENR, Periphs);
2990 (void)tmpreg;
2991 }
2992
2993
2994 /**
2995 * @brief Check if APB3 peripheral clocks in Sleep and Stop modes is enabled or not
2996 * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
2997 * APB3SMENR SPI3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
2998 * APB3SMENR LPUART1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
2999 * APB3SMENR I2C3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
3000 * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
3001 * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
3002 * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
3003 * APB3SMENR OPAMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
3004 * APB3SMENR COMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
3005 * APB3SMENR VREFSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
3006 * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
3007 * @param Periphs This parameter can be a combination of the following values:
3008 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
3009 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
3010 * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
3011 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
3012 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
3013 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
3014 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
3015 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
3016 * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
3017 * @arg @ref LL_APB3_GRP1_PERIPH_COMP
3018 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
3019 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
3020 * @retval State of Periphs (1 or 0).
3021 */
LL_APB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)3022 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
3023 {
3024 return ((READ_BIT(RCC->APB3SMENR, Periphs) == Periphs) ? 1UL : 0UL);
3025 }
3026
3027 /**
3028 * @brief Disable APB3 peripheral clocks in Sleep and Stop modes
3029 * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_DisableClockStopSleep\n
3030 * APB3SMENR SPI3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
3031 * APB3SMENR LPUART1SMEN LL_APB3_GRP1_DisableClockStopSleep\n
3032 * APB3SMENR I2C3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
3033 * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_DisableClockStopSleep\n
3034 * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
3035 * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_DisableClockStopSleep\n
3036 * APB3SMENR OPAMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n
3037 * APB3SMENR COMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n
3038 * APB3SMENR VREFSMEN LL_APB3_GRP1_DisableClockStopSleep\n
3039 * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_DisableClockStopSleep\n
3040 * @param Periphs This parameter can be a combination of the following values:
3041 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
3042 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
3043 * @arg @ref LL_APB3_GRP1_PERIPH_SPI3
3044 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
3045 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3
3046 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
3047 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
3048 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
3049 * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
3050 * @arg @ref LL_APB3_GRP1_PERIPH_COMP
3051 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
3052 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
3053 * @retval None
3054 */
LL_APB3_GRP1_DisableClockStopSleep(uint32_t Periphs)3055 __STATIC_INLINE void LL_APB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
3056 {
3057 CLEAR_BIT(RCC->APB3SMENR, Periphs);
3058 }
3059
3060 /**
3061 * @}
3062 */
3063
3064 /** @defgroup BUS_LL_EF_SRDAMR SRDAMR
3065 * @{
3066 */
3067
3068 /**
3069 * @brief Enable SRDAMR peripheral clocks in autonomous mode
3070 * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3071 * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3072 * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3073 * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3074 * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3075 * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3076 * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3077 * SRDAMR COMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3078 * SRDAMR VREFAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3079 * SRDAMR VREFRST LL_SRDAMR_GRP1_EnableAutonomousClock\n
3080 * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3081 * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3082 * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3083 * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3084 * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3085 * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3086 * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
3087 * @param Periphs This parameter can be a combination of the following values:
3088 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
3089 * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3
3090 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1
3091 * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3
3092 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1
3093 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3
3094 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4
3095 * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP
3096 * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP
3097 * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF
3098 * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB
3099 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4
3100 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1
3101 * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1
3102 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1
3103 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1
3104 * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4
3105 * @retval None
3106 */
LL_SRDAMR_GRP1_EnableAutonomousClock(uint32_t Periphs)3107 __STATIC_INLINE void LL_SRDAMR_GRP1_EnableAutonomousClock(uint32_t Periphs)
3108 {
3109 __IO uint32_t tmpreg;
3110 SET_BIT(RCC->SRDAMR, Periphs);
3111 /* Delay after an RCC peripheral clock enabling */
3112 tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
3113 (void)tmpreg;
3114 }
3115
3116 /**
3117 * @brief Check if SRDAMR peripheral clock is enabled or not
3118 * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3119 * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3120 * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3121 * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3122 * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3123 * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3124 * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3125 * SRDAMR COMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3126 * SRDAMR VREFAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3127 * SRDAMR VREFRST LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3128 * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3129 * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3130 * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3131 * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3132 * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3133 * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3134 * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
3135 * @param Periphs This parameter can be a combination of the following values:
3136 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
3137 * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3
3138 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1
3139 * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3
3140 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1
3141 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3
3142 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4
3143 * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP
3144 * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP
3145 * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF
3146 * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB
3147 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4
3148 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1
3149 * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1
3150 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1
3151 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1
3152 * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4
3153 * @retval State of Periphs (1 or 0).
3154 */
LL_SRDAMR_GRP1_IsEnabledAutonomousClock(uint32_t Periphs)3155 __STATIC_INLINE uint32_t LL_SRDAMR_GRP1_IsEnabledAutonomousClock(uint32_t Periphs)
3156 {
3157 return ((READ_BIT(RCC->SRDAMR, Periphs) == Periphs) ? 1UL : 0UL);
3158 }
3159
3160 /**
3161 * @brief Disable SRDAMR peripheral clocks in Sleep and Stop modes
3162 * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3163 * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3164 * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3165 * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3166 * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3167 * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3168 * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3169 * SRDAMR COMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3170 * SRDAMR VREFAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3171 * SRDAMR VREFRST LL_SRDAMR_GRP1_DisableAutonomousClock\n
3172 * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3173 * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3174 * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3175 * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3176 * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3177 * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3178 * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
3179 * @param Periphs This parameter can be a combination of the following values:
3180 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
3181 * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3
3182 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1
3183 * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3
3184 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1
3185 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3
3186 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4
3187 * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP
3188 * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP
3189 * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF
3190 * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB
3191 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4
3192 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1
3193 * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1
3194 * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1
3195 * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1
3196 * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4
3197 * @retval None
3198 */
LL_SRDAMR_GRP1_DisableAutonomousClock(uint32_t Periphs)3199 __STATIC_INLINE void LL_SRDAMR_GRP1_DisableAutonomousClock(uint32_t Periphs)
3200 {
3201 CLEAR_BIT(RCC->SRDAMR, Periphs);
3202 }
3203 /**
3204 * @}
3205 */
3206
3207 /**
3208 * @}
3209 */
3210 #endif /* defined(RCC) */
3211
3212 /**
3213 * @}
3214 */
3215 /**
3216 * @}
3217 */
3218
3219 #ifdef __cplusplus
3220 }
3221 #endif
3222
3223 #endif /* STM32U5xx_LL_BUS_H */
3224
