1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2023 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file
30 * in the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32U0xx_LL_BUS_H
38 #define __STM32U0xx_LL_BUS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32u0xx.h"
46
47 /** @addtogroup STM32U0xx_LL_Driver
48 * @{
49 */
50
51 #if defined(RCC)
52
53 /** @defgroup BUS_LL BUS
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup RCC_Peripheral_Memory_Mapping Peripheral Memory Mapping
62 * @{
63 */
64 #define RCC_MAP RCC /* Alias Legacy/Non-Secure periphal memory access */
65 /**
66 * @}
67 */
68
69 /* Private macros ------------------------------------------------------------*/
70
71 /* Exported types ------------------------------------------------------------*/
72 /* Exported constants --------------------------------------------------------*/
73 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
74 * @{
75 */
76
77 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB GRP1 PERIPH
78 * @{
79 */
80 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
81 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
82 #if defined (DMA2)
83 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
84 #endif /* DMA2 */
85 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
86 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
87 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
88 #if defined (AES)
89 #define LL_AHB1_GRP1_PERIPH_AES RCC_AHBENR_AESEN
90 #endif /* AES */
91 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN
92 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHBSMENR_SRAM1SMEN
93 /**
94 * @}
95 */
96
97 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
98 * @{
99 */
100 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
101 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
102 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
103 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APBENR1_TIM6EN
104 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APBENR1_TIM7EN
105 #define LL_APB1_GRP1_PERIPH_LPUART2 RCC_APBENR1_LPUART2EN
106 #if defined (LCD)
107 #define LL_APB1_GRP1_PERIPH_LCD RCC_APBENR1_LCDEN
108 #endif /* LCD */
109 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APBENR1_RTCAPBEN
110 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
111 #if defined (LPUART3)
112 #define LL_APB1_GRP1_PERIPH_LPUART3 RCC_APBENR1_LPUART3EN
113 #endif /* LPUART3 */
114 #if defined (USB_DRD_FS)
115 #define LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN
116 #endif /* USB_DRD_FS */
117 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN
118 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APBENR1_SPI3EN
119 #define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
120 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
121 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN
122 #define LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN
123 #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APBENR1_LPUART1EN
124 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN
125 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN
126 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APBENR1_I2C3EN
127 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APBENR1_OPAMPEN
128 #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APBENR1_I2C4EN
129 #if defined (LPTIM3)
130 #define LL_APB1_GRP1_PERIPH_LPTIM3 RCC_APBENR1_LPTIM3EN
131 #endif /* LPTIM3 */
132 #define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
133 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APBENR1_DAC1EN
134 #define LL_APB1_GRP1_PERIPH_LPTIM2 RCC_APBENR1_LPTIM2EN
135 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIM1EN
136 /**
137 * @}
138 */
139
140 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
141 * @{
142 */
143 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
144 #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
145 #define LL_APB1_GRP2_PERIPH_COMP RCC_APBENR2_SYSCFGEN
146 #define LL_APB1_GRP2_PERIPH_VREFBUF RCC_APBENR2_SYSCFGEN
147 #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APBENR2_TIM1EN
148 #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APBENR2_SPI1EN
149 #define LL_APB1_GRP2_PERIPH_USART1 RCC_APBENR2_USART1EN
150 #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APBENR2_TIM15EN
151 #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APBENR2_TIM16EN
152 #define LL_APB1_GRP2_PERIPH_ADC RCC_APBENR2_ADCEN
153
154 /**
155 * @}
156 */
157
158 /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
159 * @{
160 */
161 #define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
162 #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
163 #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
164 #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN
165 #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN
166 #if defined (GPIOE)
167 #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN
168 #endif /* GPIOE */
169 #define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN
170
171 /**
172 * @}
173 */
174
175 /**
176 * @}
177 */
178
179 /* Exported macro ------------------------------------------------------------*/
180 /* Exported functions --------------------------------------------------------*/
181 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
182 * @{
183 */
184
185 /** @defgroup BUS_LL_EF_AHB AHB
186 * @{
187 */
188
189 /**
190 * @brief Enable AHB1 peripherals clock.
191 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
192 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
193 * AHBENR FLASHEN LL_AHB1_GRP1_EnableClock\n
194 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
195 * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n
196 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
197 * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n
198 * AHBENR SRAM1EN LL_AHB1_GRP1_EnableClock
199 * @param Periphs This parameter can be a combination of the following values:
200 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
201 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
202 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
203 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
204 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
205 * @arg @ref LL_AHB1_GRP1_PERIPH_AES
206 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG
207 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
208 *
209 * @retval None
210 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)211 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
212 {
213 __IO uint32_t tmpreg;
214 SET_BIT(RCC->AHBENR, Periphs);
215 /* Delay after an RCC peripheral clock enabling */
216 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
217 (void)tmpreg;
218 }
219
220 /**
221 * @brief Check if AHB1 peripheral clock is enabled or not
222 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
223 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
224 * AHBENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
225 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
226 * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
227 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
228 * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
229 * AHBENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock
230 * @param Periphs This parameter can be a combination of the following values:
231 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
232 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
233 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
234 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
235 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
236 * @arg @ref LL_AHB1_GRP1_PERIPH_AES
237 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG
238 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
239 *
240 * @retval State of Periphs (1 or 0).
241 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)242 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
243 {
244 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
245 }
246
247 /**
248 * @brief Disable AHB1 peripherals clock.
249 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
250 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
251 * AHBENR FLASHEN LL_AHB1_GRP1_DisableClock\n
252 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
253 * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n
254 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
255 * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n
256 * AHBENR SRAM1EN LL_AHB1_GRP1_DisableClock
257 * @param Periphs This parameter can be a combination of the following values:
258 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
259 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
260 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
261 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
262 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
263 * @arg @ref LL_AHB1_GRP1_PERIPH_AES
264 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG
265 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
266 *
267 * @retval None
268 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)269 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
270 {
271 CLEAR_BIT(RCC->AHBENR, Periphs);
272 }
273
274 /**
275 * @brief Force AHB1 peripherals reset.
276 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
277 * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
278 * AHBRSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
279 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
280 * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n
281 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
282 * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n
283 * AHBRSTR SRAM1RST LL_AHB1_GRP1_ForceReset
284 * @param Periphs This parameter can be a combination of the following values:
285 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
286 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
287 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
288 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
289 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
290 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
291 * @arg @ref LL_AHB1_GRP1_PERIPH_AES
292 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG
293 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
294 *
295 * @retval None
296 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)297 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
298 {
299 SET_BIT(RCC->AHBRSTR, Periphs);
300 }
301
302 /**
303 * @brief Release AHB1 peripherals reset.
304 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
305 * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
306 * AHBRSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
307 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
308 * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
309 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
310 * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
311 * AHBRSTR SRAM1RST LL_AHB1_GRP1_ReleaseReset
312 * @param Periphs This parameter can be a combination of the following values:
313 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
314 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
315 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
316 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
317 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
318 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
319 * @arg @ref LL_AHB1_GRP1_PERIPH_AES
320 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG
321 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
322 *
323 * (*) value not defined in all devices.
324 * @retval None
325 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)326 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
327 {
328 CLEAR_BIT(RCC->AHBRSTR, Periphs);
329 }
330
331 /**
332 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
333 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
334 * AHBSMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
335 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
336 * AHBSMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
337 * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
338 * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
339 * AHBSMENR AESSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
340 * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
341 * AHBSMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep
342 * @param Periphs This parameter can be a combination of the following values:
343 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
344 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
345 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
346 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
347 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
348 * @arg @ref LL_AHB1_GRP1_PERIPH_AES
349 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG
350 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
351 *
352 * (*) value not defined in all devices.
353 * @retval None
354 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)355 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
356 {
357 __IO uint32_t tmpreg;
358 SET_BIT(RCC->AHBSMENR, Periphs);
359 /* Delay after an RCC peripheral clock enabling */
360 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
361 (void)tmpreg;
362 }
363
364 /**
365 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
366 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
367 * AHBSMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
368 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
369 * AHBSMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
370 * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
371 * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
372 * AHBSMENR AESSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
373 * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
374 * AHBSMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep
375 * @param Periphs This parameter can be a combination of the following values:
376 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
377 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
378 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
379 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
380 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
381 * @arg @ref LL_AHB1_GRP1_PERIPH_AES
382 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG
383 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
384 *
385 * (*) value not defined in all devices.
386 * @retval None
387 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)388 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
389 {
390 CLEAR_BIT(RCC->AHBSMENR, Periphs);
391 }
392
393 /**
394 * @}
395 */
396
397 /** @defgroup BUS_LL_EF_APB1_GRP1 GRP1
398 * @{
399 */
400
401 /**
402 * @brief Enable APB1 GRP1 peripherals clock.
403 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
404 * APBENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
405 * APBENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
406 * APBENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
407 * APBENR1 LPUART2EN LL_APB1_GRP1_EnableClock\n
408 * APBENR1 LCDEN LL_APB1_GRP1_EnableClock\n
409 * APBENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
410 * APBENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
411 * APBENR1 LPUART3EN LL_APB1_GRP1_EnableClock\n
412 * APBENR1 USBFSEN LL_APB1_GRP1_EnableClock\n
413 * APBENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
414 * APBENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
415 * APBENR1 CRSEN LL_APB1_GRP1_EnableClock\n
416 * APBENR1 USART2EN LL_APB1_GRP1_EnableClock\n
417 * APBENR1 USART3EN LL_APB1_GRP1_EnableClock\n
418 * APBENR1 USART4EN LL_APB1_GRP1_EnableClock\n
419 * APBENR1 LPUART1EN LL_APB1_GRP1_EnableClock\n
420 * APBENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
421 * APBENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
422 * APBENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
423 * APBENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
424 * APBENR1 I2C4EN LL_APB1_GRP1_EnableClock\n
425 * APBENR1 LPTIM3EN LL_APB1_GRP1_EnableClock\n
426 * APBENR1 PWREN LL_APB1_GRP1_EnableClock\n
427 * APBENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
428 * APBENR1 LPTIM2EN LL_APB1_GRP1_EnableClock
429 * APBENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
430 * @param Periphs This parameter can be a combination of the following values:
431 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
432 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
433 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
434 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
435 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2
436 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
437 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
438 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
439 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART3
440 * @arg @ref LL_APB1_GRP1_PERIPH_USB
441 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
442 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
443 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
444 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
445 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
446 * @arg @ref LL_APB1_GRP1_PERIPH_USART4
447 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
448 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
449 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
450 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
451 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
452 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4
453 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM3
454 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
455 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
456 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2
457 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
458 *
459 * @retval None
460 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)461 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
462 {
463 __IO uint32_t tmpreg;
464 SET_BIT(RCC->APBENR1, Periphs);
465 /* Delay after an RCC peripheral clock enabling */
466 tmpreg = READ_BIT(RCC->APBENR1, Periphs);
467 (void)tmpreg;
468 }
469
470 /**
471 * @brief Check if APB1 GRP1 peripheral clock is enabled or not
472 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
473 * APBENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
474 * APBENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
475 * APBENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
476 * APBENR1 LPUART2EN LL_APB1_GRP1_IsEnabledClock\n
477 * APBENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
478 * APBENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
479 * APBENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
480 * APBENR1 LPUART3EN LL_APB1_GRP1_IsEnabledClock\n
481 * APBENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n
482 * APBENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
483 * APBENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
484 * APBENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
485 * APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
486 * APBENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
487 * APBENR1 USART4EN LL_APB1_GRP1_IsEnabledClock\n
488 * APBENR1 USART4EN LL_APB1_GRP1_IsEnabledClock\n
489 * APBENR1 LPUART1EN LL_APB1_GRP1_IsEnabledClock\n
490 * APBENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
491 * APBENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
492 * APBENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
493 * APBENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
494 * APBENR1 I2C4EN LL_APB1_GRP1_IsEnabledClock\n
495 * APBENR1 LPTIM3EN LL_APB1_GRP1_IsEnabledClock\n
496 * APBENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
497 * APBENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
498 * APBENR1 LPTIM2EN LL_APB1_GRP1_IsEnabledClock\n
499 * APBENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
500 * @param Periphs This parameter can be a combination of the following values:
501 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
502 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
503 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
504 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
505 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2
506 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
507 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
508 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
509 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART3
510 * @arg @ref LL_APB1_GRP1_PERIPH_USB
511 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
512 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
513 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
514 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
515 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
516 * @arg @ref LL_APB1_GRP1_PERIPH_USART4
517 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
518 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
519 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
520 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
521 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
522 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4
523 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM3
524 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
525 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
526 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2
527 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
528 *
529 * @retval State of Periphs (1 or 0).
530 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)531 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
532 {
533 return (READ_BIT(RCC->APBENR1, Periphs) == Periphs);
534 }
535
536 /**
537 * @brief Disable APB1 GRP1 peripherals clock.
538 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
539 * APBENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
540 * APBENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
541 * APBENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
542 * APBENR1 LPUART2EN LL_APB1_GRP1_DisableClock\n
543 * APBENR1 LCDEN LL_APB1_GRP1_DisableClock\n
544 * APBENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
545 * APBENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
546 * APBENR1 LPUART3EN LL_APB1_GRP1_DisableClock\n
547 * APBENR1 USBFSEN LL_APB1_GRP1_DisableClock\n
548 * APBENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
549 * APBENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
550 * APBENR1 CRSEN LL_APB1_GRP1_DisableClock\n
551 * APBENR1 USART2EN LL_APB1_GRP1_DisableClock\n
552 * APBENR1 USART3EN LL_APB1_GRP1_DisableClock\n
553 * APBENR1 USART4EN LL_APB1_GRP1_DisableClock\n
554 * APBENR1 LPUART1EN LL_APB1_GRP1_DisableClock\n
555 * APBENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
556 * APBENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
557 * APBENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
558 * APBENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
559 * APBENR1 I2C4EN LL_APB1_GRP1_DisableClock\n
560 * APBENR1 LPTIM3EN LL_APB1_GRP1_DisableClock\n
561 * APBENR1 PWREN LL_APB1_GRP1_DisableClock\n
562 * APBENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
563 * APBENR1 LPTIM2EN LL_APB1_GRP1_DisableClock\n
564 * APBENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
565 * @param Periphs This parameter can be a combination of the following values:
566 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
567 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
568 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
569 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
570 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2
571 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
572 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
573 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
574 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART3
575 * @arg @ref LL_APB1_GRP1_PERIPH_USB
576 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
577 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
578 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
579 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
580 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
581 * @arg @ref LL_APB1_GRP1_PERIPH_USART4
582 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
583 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
584 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
585 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
586 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
587 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4
588 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM3
589 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
590 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
591 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2
592 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
593 *
594 * @retval None
595 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)596 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
597 {
598 CLEAR_BIT(RCC->APBENR1, Periphs);
599 }
600
601 /**
602 * @brief Force APB1 GRP1 peripherals reset.
603 * @rmtoll APBRSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
604 * APBRSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
605 * APBRSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
606 * APBRSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
607 * APBRSTR1 LPUART2RST LL_APB1_GRP1_ForceReset\n
608 * APBRSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
609 * APBRSTR1 RTCAPBRST LL_APB1_GRP1_ForceReset\n
610 * APBRSTR1 WWDGRST LL_APB1_GRP1_ForceReset\n
611 * APBRSTR1 LPUART3RST LL_APB1_GRP1_ForceReset\n
612 * APBRSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n
613 * APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
614 * APBRSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
615 * APBRSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
616 * APBRSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
617 * APBRSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
618 * APBRSTR1 USART4RST LL_APB1_GRP1_ForceReset\n
619 * APBRSTR1 LPUART1RST LL_APB1_GRP1_ForceReset\n
620 * APBRSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
621 * APBRSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
622 * APBRSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
623 * APBRSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
624 * APBRSTR1 I2C4RST LL_APB1_GRP1_ForceReset\n
625 * APBRSTR1 LPTIM3RST LL_APB1_GRP1_ForceReset\n
626 * APBRSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
627 * APBRSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
628 * APBRSTR1 LPTIM2RST LL_APB1_GRP1_ForceReset\n
629 * APBRSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
630 * @param Periphs This parameter can be a combination of the following values:
631 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
632 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
633 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
634 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
635 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2
636 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
637 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
638 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
639 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART3
640 * @arg @ref LL_APB1_GRP1_PERIPH_USB
641 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
642 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
643 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
644 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
645 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
646 * @arg @ref LL_APB1_GRP1_PERIPH_USART4
647 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
648 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
649 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
650 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
651 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
652 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4
653 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM3
654 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
655 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
656 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2
657 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
658 *
659 * @retval None
660 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)661 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
662 {
663 SET_BIT(RCC->APBRSTR1, Periphs);
664 }
665
666 /**
667 * @brief Release APB1 GRP1 peripherals reset.
668 * @rmtoll APBRSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
669 * APBRSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
670 * APBRSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
671 * APBRSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
672 * APBRSTR1 LPUART2RST LL_APB1_GRP1_ReleaseReset\n
673 * APBRSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
674 * APBRSTR1 RTCAPBRST LL_APB1_GRP1_ReleaseReset\n
675 * APBRSTR1 WWDGRST LL_APB1_GRP1_ReleaseReset\n
676 * APBRSTR1 LPUART3RST LL_APB1_GRP1_ReleaseReset\n
677 * APBRSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n
678 * APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
679 * APBRSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
680 * APBRSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
681 * APBRSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
682 * APBRSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
683 * APBRSTR1 USART4RST LL_APB1_GRP1_ReleaseReset\n
684 * APBRSTR1 LPUART1RST LL_APB1_GRP1_ReleaseReset\n
685 * APBRSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
686 * APBRSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
687 * APBRSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
688 * APBRSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
689 * APBRSTR1 I2C4RST LL_APB1_GRP1_ReleaseReset\n
690 * APBRSTR1 LPTIM3RST LL_APB1_GRP1_ReleaseReset\n
691 * APBRSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
692 * APBRSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
693 * APBRSTR1 LPTIM2RST LL_APB1_GRP1_ReleaseReset\n
694 * APBRSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
695 * @param Periphs This parameter can be a combination of the following values:
696 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
697 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
698 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
699 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
700 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2
701 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
702 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
703 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
704 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART3
705 * @arg @ref LL_APB1_GRP1_PERIPH_USB
706 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
707 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
708 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
709 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
710 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
711 * @arg @ref LL_APB1_GRP1_PERIPH_USART4
712 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
713 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
714 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
715 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
716 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
717 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4
718 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM3
719 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
720 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
721 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2
722 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
723 *
724 * @retval None
725 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)726 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
727 {
728 CLEAR_BIT(RCC->APBRSTR1, Periphs);
729 }
730
731 /**
732 * @brief Enable APB1 GRP1 peripheral clocks in Sleep and Stop modes
733 * @rmtoll APBSMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
734 * APBSMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
735 * APBSMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
736 * APBSMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
737 * APBSMENR1 LPUART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
738 * APBSMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
739 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
740 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
741 * APBSMENR1 LPUART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
742 * APBSMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
743 * APBSMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
744 * APBSMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
745 * APBSMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
746 * APBSMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
747 * APBSMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
748 * APBSMENR1 USART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
749 * APBSMENR1 LPUART1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
750 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
751 * APBSMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
752 * APBSMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
753 * APBSMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
754 * APBSMENR1 I2C4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
755 * APBSMENR1 LPTIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
756 * APBSMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
757 * APBSMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
758 * APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
759 * APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
760 * @param Periphs This parameter can be a combination of the following values:
761 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
762 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
763 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
764 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
765 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2
766 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
767 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
768 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
769 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART3
770 * @arg @ref LL_APB1_GRP1_PERIPH_USB
771 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
772 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
773 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
774 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
775 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
776 * @arg @ref LL_APB1_GRP1_PERIPH_USART4
777 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
778 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
779 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
780 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
781 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
782 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4
783 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM3
784 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
785 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
786 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2
787 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
788 *
789 * (*) value not defined in all devices.
790 * @retval None
791 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)792 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
793 {
794 __IO uint32_t tmpreg;
795 SET_BIT(RCC->APBSMENR1, Periphs);
796 /* Delay after an RCC peripheral clock enabling */
797 tmpreg = READ_BIT(RCC->APBSMENR1, Periphs);
798 (void)tmpreg;
799 }
800
801 /**
802 * @brief Disable APB_1 peripheral clocks in Sleep and Stop modes
803 * @rmtoll APBSMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
804 * APBSMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
805 * APBSMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
806 * APBSMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
807 * APBSMENR1 LPUART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
808 * APBSMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
809 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
810 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
811 * APBSMENR1 LPUART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
812 * APBSMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
813 * APBSMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
814 * APBSMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
815 * APBSMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
816 * APBSMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
817 * APBSMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
818 * APBSMENR1 USART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
819 * APBSMENR1 LPUART1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
820 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
821 * APBSMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
822 * APBSMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
823 * APBSMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
824 * APBSMENR1 I2C4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
825 * APBSMENR1 LPTIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
826 * APBSMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
827 * APBSMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
828 * APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
829 * APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
830 * @param Periphs This parameter can be a combination of the following values:
831 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
832 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
833 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
834 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
835 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2
836 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
837 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
838 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
839 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART3
840 * @arg @ref LL_APB1_GRP1_PERIPH_USB
841 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
842 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
843 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
844 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
845 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
846 * @arg @ref LL_APB1_GRP1_PERIPH_USART4
847 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
848 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
849 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
850 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
851 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
852 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4
853 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM3
854 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
855 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
856 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2
857 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
858 *
859 * @retval None
860 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)861 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
862 {
863 CLEAR_BIT(RCC->APBSMENR1, Periphs);
864 }
865
866 /**
867 * @}
868 */
869
870 /** @defgroup BUS_LL_EF_APB1_GRP2 GRP2
871 * @{
872 */
873
874 /**
875 * @brief Enable APB1 GRP2 peripherals clock.
876 * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_EnableClock\n
877 * APBENR2 TIM1EN LL_APB1_GRP2_EnableClock\n
878 * APBENR2 SPI1EN LL_APB1_GRP2_EnableClock\n
879 * APBENR2 USART1EN LL_APB1_GRP2_EnableClock\n
880 * APBENR2 TIM15EN LL_APB1_GRP2_EnableClock\n
881 * APBENR2 TIM16EN LL_APB1_GRP2_EnableClock\n
882 * APBENR2 ADCEN LL_APB1_GRP2_EnableClock
883 * @param Periphs This parameter can be a combination of the following values:
884 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
885 * @arg @ref LL_APB1_GRP2_PERIPH_COMP
886 * @arg @ref LL_APB1_GRP2_PERIPH_VREFBUF
887 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
888 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
889 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
890 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15
891 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
892 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
893 *
894 * @retval None
895 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)896 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
897 {
898 __IO uint32_t tmpreg;
899 SET_BIT(RCC->APBENR2, Periphs);
900 /* Delay after an RCC peripheral clock enabling */
901 tmpreg = READ_BIT(RCC->APBENR2, Periphs);
902 (void)tmpreg;
903 }
904 /**
905 * @brief Check if APB1 GRP2 peripheral clock is enabled or not
906 * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
907 * APBENR2 TIM1EN LL_APB1_GRP2_IsEnabledClock\n
908 * APBENR2 SPI1EN LL_APB1_GRP2_IsEnabledClock\n
909 * APBENR2 USART1EN LL_APB1_GRP2_IsEnabledClock\n
910 * APBENR2 TIM15EN LL_APB1_GRP2_IsEnabledClock\n
911 * APBENR2 TIM16EN LL_APB1_GRP2_IsEnabledClock\n
912 * APBENR2 ADCEN LL_APB1_GRP2_IsEnabledClock
913 * @param Periphs This parameter can be a combination of the following values:
914 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
915 * @arg @ref LL_APB1_GRP2_PERIPH_COMP
916 * @arg @ref LL_APB1_GRP2_PERIPH_VREFBUF
917 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
918 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
919 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
920 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15
921 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
922 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
923 * @note (*) peripheral not available on all devices
924 * @retval State of Periphs (1 or 0).
925 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)926 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
927 {
928 return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
929 }
930
931 /**
932 * @brief Disable APB1 GRP2 peripherals clock.
933 * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_DisableClock\n
934 * APBENR2 TIM1EN LL_APB1_GRP2_DisableClock\n
935 * APBENR2 SPI1EN LL_APB1_GRP2_DisableClock\n
936 * APBENR2 USART1EN LL_APB1_GRP2_DisableClock\n
937 * APBENR2 TIM15EN LL_APB1_GRP2_DisableClock\n
938 * APBENR2 TIM16EN LL_APB1_GRP2_DisableClock\n
939 * APBENR2 ADCEN LL_APB1_GRP2_DisableClock
940 * @param Periphs This parameter can be a combination of the following values:
941 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
942 * @arg @ref LL_APB1_GRP2_PERIPH_VREFBUF
943 * @arg @ref LL_APB1_GRP2_PERIPH_COMP
944 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
945 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
946 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
947 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15
948 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
949 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
950 * @note (*) peripheral not available on all devices
951 * @retval None
952 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)953 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
954 {
955 CLEAR_BIT(RCC->APBENR2, Periphs);
956 }
957
958 /**
959 * @brief Force APB1_GRP2 peripherals reset.
960 * @rmtoll APBRSTR2 SYSCFGRST LL_APB1_GRP2_ForceReset\n
961 * APBRSTR2 TIM1RST LL_APB1_GRP2_ForceReset\n
962 * APBRSTR2 SPI1RST LL_APB1_GRP2_ForceReset\n
963 * APBRSTR2 USART1RST LL_APB1_GRP2_ForceReset\n
964 * APBRSTR2 TIM15RST LL_APB1_GRP2_ForceReset\n
965 * APBRSTR2 TIM16RST LL_APB1_GRP2_ForceReset\n
966 * APBRSTR2 ADCRST LL_APB1_GRP2_ForceReset
967 * @param Periphs This parameter can be a combination of the following values:
968 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
969 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
970 * @arg @ref LL_APB1_GRP2_PERIPH_VREFBUF
971 * @arg @ref LL_APB1_GRP2_PERIPH_COMP
972 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
973 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
974 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
975 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15
976 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
977 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
978 * @note (*) peripheral not available on all devices
979 * @retval None
980 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)981 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
982 {
983 SET_BIT(RCC->APBRSTR2, Periphs);
984 }
985
986 /**
987 * @brief Release APB1_GRP2 peripherals reset.
988 * @rmtoll APBRSTR2 SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
989 * APBRSTR2 TIM1RST LL_APB1_GRP2_ReleaseReset\n
990 * APBRSTR2 SPI1RST LL_APB1_GRP2_ReleaseReset\n
991 * APBRSTR2 USART1RST LL_APB1_GRP2_ReleaseReset\n
992 * APBRSTR2 TIM15RST LL_APB1_GRP2_ReleaseReset\n
993 * APBRSTR2 TIM16RST LL_APB1_GRP2_ReleaseReset\n
994 * APBRSTR2 ADCRST LL_APB1_GRP2_ReleaseReset
995 * @param Periphs This parameter can be a combination of the following values:
996 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
997 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
998 * @arg @ref LL_APB1_GRP2_PERIPH_VREFBUF
999 * @arg @ref LL_APB1_GRP2_PERIPH_COMP
1000 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
1001 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
1002 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
1003 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15
1004 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
1005 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
1006 * @note (*) peripheral not available on all devices
1007 * @retval None
1008 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1009 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1010 {
1011 CLEAR_BIT(RCC->APBRSTR2, Periphs);
1012 }
1013
1014 /**
1015 * @brief Enable APB1_GRP2 peripheral clocks in Sleep and Stop modes
1016 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB1_GRP2_EnableClockStopSleep\n
1017 * APBSMENR2 TIM1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1018 * APBSMENR2 SPI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1019 * APBSMENR2 USART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1020 * APBSMENR2 TIM15SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1021 * APBSMENR2 TIM16SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1022 * APBSMENR2 ADCSMEN LL_APB1_GRP2_EnableClockStopSleep
1023 * @param Periphs This parameter can be a combination of the following values:
1024 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1025 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
1026 * @arg @ref LL_APB1_GRP2_PERIPH_VREFBUF
1027 * @arg @ref LL_APB1_GRP2_PERIPH_COMP
1028 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
1029 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
1030 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
1031 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15
1032 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
1033 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
1034 * @note (*) peripheral not available on all devices
1035 * @retval None
1036 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)1037 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1038 {
1039 __IO uint32_t tmpreg;
1040 SET_BIT(RCC->APBSMENR2, Periphs);
1041 /* Delay after an RCC peripheral clock enabling */
1042 tmpreg = READ_BIT(RCC->APBSMENR2, Periphs);
1043 (void)tmpreg;
1044 }
1045
1046 /**
1047 * @brief Disable APB1_GRP2 peripheral clocks in Sleep and Stop modes
1048 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB1_GRP2_DisableClockStopSleep\n
1049 * APBSMENR2 TIM1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1050 * APBSMENR2 SPI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1051 * APBSMENR2 USART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1052 * APBSMENR2 TIM15SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1053 * APBSMENR2 TIM16SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1054 * APBSMENR2 ADCSMEN LL_APB1_GRP2_DisableClockStopSleep
1055 * @param Periphs This parameter can be a combination of the following values:
1056 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1057 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
1058 * @arg @ref LL_APB1_GRP2_PERIPH_VREFBUF
1059 * @arg @ref LL_APB1_GRP2_PERIPH_COMP
1060 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
1061 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
1062 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
1063 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15
1064 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
1065 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
1066 * @note (*) peripheral not available on all devices
1067 * @retval None
1068 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)1069 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1070 {
1071 CLEAR_BIT(RCC->APBSMENR2, Periphs);
1072 }
1073
1074 /**
1075 * @}
1076 */
1077
1078 /** @defgroup BUS_LL_EF_APB1_DBG DBG
1079 * @{
1080 */
1081
1082 /**
1083 * @brief Enable APB1 DBG clock.
1084 * @rmtoll DBGCFGR DBGEN LL_APB1_DBG_EnableClock
1085 * @retval None
1086 */
LL_APB1_DBG_EnableClock(void)1087 __STATIC_INLINE void LL_APB1_DBG_EnableClock(void)
1088 {
1089 __IO uint32_t tmpreg;
1090 SET_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN);
1091 /* Delay after an RCC peripheral clock enabling */
1092 tmpreg = READ_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN);
1093 (void)tmpreg;
1094 }
1095 /**
1096 * @brief Check if APB1 DBG clock is enabled or not
1097 * @rmtoll DBGCFGR DBGEN LL_APB1_DBG_IsEnabledClock
1098 * @retval State of Periphs (1 or 0).
1099 */
LL_APB1_DBG_IsEnabledClock(void)1100 __STATIC_INLINE uint32_t LL_APB1_DBG_IsEnabledClock(void)
1101 {
1102 return ((READ_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN) == (RCC_DBGCFGR_DBGEN)) ? 1UL : 0UL);
1103 }
1104
1105 /**
1106 * @brief Disable APB1 DBG peripherals clock.
1107 * @rmtoll DBGCFGR DBGEN LL_APB1_DBG_DisableClock
1108 * @retval None
1109 */
LL_APB1_DBG_DisableClock(void)1110 __STATIC_INLINE void LL_APB1_DBG_DisableClock(void)
1111 {
1112 CLEAR_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN);
1113 }
1114
1115 /**
1116 * @brief Force APB1_DBG peripherals reset.
1117 * @rmtoll DBGCFGR DBGRST LL_APB1_DBG_ForceReset
1118 * @retval None
1119 */
LL_APB1_DBG_ForceReset(void)1120 __STATIC_INLINE void LL_APB1_DBG_ForceReset(void)
1121 {
1122 SET_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGRST);
1123 }
1124
1125 /**
1126 * @brief Release APB1_DBG peripherals reset.
1127 * @rmtoll DBGCFGR DBGRST LL_APB1_DBG_ReleaseReset
1128 * @retval None
1129 */
LL_APB1_DBG_ReleaseReset(void)1130 __STATIC_INLINE void LL_APB1_DBG_ReleaseReset(void)
1131 {
1132 CLEAR_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGRST);
1133 }
1134
1135 /**
1136 * @}
1137 */
1138
1139 /** @defgroup BUS_LL_EF_IOP IOP
1140 * @{
1141 */
1142
1143 /**
1144 * @brief Enable IOP peripherals clock.
1145 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n
1146 * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n
1147 * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n
1148 * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n
1149 * IOPENR GPIOFEN LL_IOP_GRP1_EnableClock
1150 * @param Periphs This parameter can be a combination of the following values:
1151 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1152 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1153 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1154 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1155 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1156 * @retval None
1157 */
LL_IOP_GRP1_EnableClock(uint32_t Periphs)1158 __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
1159 {
1160 __IO uint32_t tmpreg;
1161 SET_BIT(RCC->IOPENR, Periphs);
1162 /* Delay after an RCC peripheral clock enabling */
1163 tmpreg = READ_BIT(RCC->IOPENR, Periphs);
1164 (void)tmpreg;
1165 }
1166
1167 /**
1168 * @brief Check if IOP peripheral clock is enabled or not
1169 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n
1170 * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n
1171 * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n
1172 * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n
1173 * IOPENR GPIOFEN LL_IOP_GRP1_IsEnabledClock
1174 * @param Periphs This parameter can be a combination of the following values:
1175 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1176 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1177 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1178 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1179 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1180 * @retval State of Periphs (1 or 0).
1181 */
LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)1182 __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
1183 {
1184 return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
1185 }
1186
1187 /**
1188 * @brief Disable IOP peripherals clock.
1189 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n
1190 * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n
1191 * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n
1192 * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n
1193 * IOPENR GPIOFEN LL_IOP_GRP1_DisableClock
1194 * @param Periphs This parameter can be a combination of the following values:
1195 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1196 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1197 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1198 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1199 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1200 * @retval None
1201 */
LL_IOP_GRP1_DisableClock(uint32_t Periphs)1202 __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
1203 {
1204 CLEAR_BIT(RCC->IOPENR, Periphs);
1205 }
1206
1207 /**
1208 * @brief Disable IOP peripherals clock.
1209 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ForceReset\n
1210 * IOPRSTR GPIOBRST LL_IOP_GRP1_ForceReset\n
1211 * IOPRSTR GPIOCRST LL_IOP_GRP1_ForceReset\n
1212 * IOPRSTR GPIODRST LL_IOP_GRP1_ForceReset\n
1213 * IOPRSTR GPIOFRST LL_IOP_GRP1_ForceReset
1214 * @param Periphs This parameter can be a combination of the following values:
1215 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
1216 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1217 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1218 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1219 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1220 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1221 * @retval None
1222 */
LL_IOP_GRP1_ForceReset(uint32_t Periphs)1223 __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
1224 {
1225 SET_BIT(RCC->IOPRSTR, Periphs);
1226 }
1227
1228 /**
1229 * @brief Release IOP peripherals reset.
1230 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ReleaseReset\n
1231 * IOPRSTR GPIOBRST LL_IOP_GRP1_ReleaseReset\n
1232 * IOPRSTR GPIOCRST LL_IOP_GRP1_ReleaseReset\n
1233 * IOPRSTR GPIODRST LL_IOP_GRP1_ReleaseReset\n
1234 * IOPRSTR GPIOFRST LL_IOP_GRP1_ReleaseReset
1235 * @param Periphs This parameter can be a combination of the following values:
1236 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
1237 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1238 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1239 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1240 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1241 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1242 * @retval None
1243 */
LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)1244 __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
1245 {
1246 CLEAR_BIT(RCC->IOPRSTR, Periphs);
1247 }
1248
1249 /**
1250 * @brief Enable IOP peripheral clocks in Sleep and Stop modes
1251 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_EnableClockStopSleep\n
1252 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1253 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1254 * IOPSMENR GPIODSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1255 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_EnableClockStopSleep
1256 * @param Periphs This parameter can be a combination of the following values:
1257 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1258 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1259 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1260 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1261 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1262 * @retval None
1263 */
LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)1264 __STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)
1265 {
1266 __IO uint32_t tmpreg;
1267 SET_BIT(RCC->IOPSMENR, Periphs);
1268 /* Delay after an RCC peripheral clock enabling */
1269 tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
1270 (void)tmpreg;
1271 }
1272
1273 /**
1274 * @brief Disable IOP peripheral clocks in Sleep and Stop modes
1275 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_DisableClockStopSleep\n
1276 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1277 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1278 * IOPSMENR GPIODSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1279 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_DisableClockStopSleep
1280 * @param Periphs This parameter can be a combination of the following values:
1281 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1282 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1283 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1284 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1285 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1286 * @retval None
1287 */
LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)1288 __STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)
1289 {
1290 CLEAR_BIT(RCC->IOPSMENR, Periphs);
1291 }
1292
1293 /**
1294 * @}
1295 */
1296
1297 /**
1298 * @}
1299 */
1300
1301 /**
1302 * @}
1303 */
1304
1305 #endif /* defined(RCC) */
1306
1307 /**
1308 * @}
1309 */
1310
1311 #ifdef __cplusplus
1312 }
1313 #endif
1314
1315 #endif /* __STM32U0xx_LL_BUS_H */
1316
