1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_LL_ADC_H
21 #define STM32H7RSxx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx.h"
29
30 /** @addtogroup STM32H7RSxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET (0x00000000UL)
56 #define ADC_SQR2_REGOFFSET (0x00000100UL)
57 #define ADC_SQR3_REGOFFSET (0x00000200UL)
58 #define ADC_SQR4_REGOFFSET (0x00000300UL)
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
61 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
83
84
85
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
99 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
100 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
101 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
102
103 /* Definition of ADC group injected sequencer bits information to be inserted */
104 /* into ADC group injected sequencer ranks literals definition. */
105 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
106 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
107 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
108 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
109
110
111
112 /* Internal mask for ADC group regular trigger: */
113 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
114 /* - regular trigger source */
115 /* - regular trigger edge */
116 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for
117 compatibility with some ADC on other STM32 series
118 having this setting set by HW default value) */
119
120 /* Mask containing trigger source masks for each of possible */
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
124 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
125 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
126 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
127
128 /* Mask containing trigger edge masks for each of possible */
129 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
130 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
131 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
132 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
133 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
134 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
135
136 /* Definition of ADC group regular trigger bits information. */
137 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
138 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
139
140
141
142 /* Internal mask for ADC group injected trigger: */
143 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
144 /* - injected trigger source */
145 /* - injected trigger edge */
146 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
147 compatibility with some ADC on other STM32 series
148 having this setting set by HW default value) */
149
150 /* Mask containing trigger source masks for each of possible */
151 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
152 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
153 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
154 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
155 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
156 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
157
158 /* Mask containing trigger edge masks for each of possible */
159 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
160 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
161 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
162 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
163 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
164 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
165
166 /* Definition of ADC group injected trigger bits information. */
167 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
168 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
169
170
171
172
173
174
175 /* Internal mask for ADC channel: */
176 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
177 /* - channel identifier defined by number */
178 /* - channel identifier defined by bitfield */
179 /* - channel differentiation between external channels (connected to */
180 /* GPIO pins) and internal channels (connected to internal paths) */
181 /* - channel sampling time defined by SMPRx register offset */
182 /* and SMPx bits positions into SMPRx register */
183 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
184 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
185 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
186 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
187 | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
188 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
189 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
190 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
191
192 /* Channel differentiation between external and internal channels */
193 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
194 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case
195 of different ADC internal channels mapped on same channel
196 number on different ADC instances */
197 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
198
199 /* Internal register offset for ADC channel sampling time configuration */
200 /* (offset placed into a spare area of literal definition) */
201 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
202 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
203 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
204 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET
205 in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
206
207 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
208 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
209 position in register */
210
211 /* Definition of channels ID number information to be inserted into */
212 /* channels literals definition. */
213 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
214 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
215 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
216 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
217 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
218 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
219 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
220 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
221 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
222 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
223 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
224 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
225 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
226 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
227 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
228 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
229 ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
230 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
231 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
232 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
233
234 /* Definition of channels ID bitfield information to be inserted into */
235 /* channels literals definition. */
236 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
237 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
238 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
239 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
240 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
241 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
242 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
243 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
244 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
245 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
246 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
247 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
248 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
249 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
250 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
251 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
252 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
253 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
254 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
255
256 /* Definition of channels sampling time information to be inserted into */
257 /* channels literals definition. */
258 /* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */
259 /* in register. */
260 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
261 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
262 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
263 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
264 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
265 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
266 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
267 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
268 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
269 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
270 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
271 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
272 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
273 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
274 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
275 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
276 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
277 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
278 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
279
280
281 /* Internal mask for ADC mode single or differential ended: */
282 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
283 /* the relevant bits for: */
284 /* (concatenation of multiple bits used in different registers) */
285 /* - ADC calibration: calibration start, calibration factor get or set */
286 /* - ADC channels: set each ADC channel ending mode */
287 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
288 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
289 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
290 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
291 to perform of shift when single mode is selected, shift value out of
292 channels bits range. */
293 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
294 mask of bit */
295 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
296 position of bit */
297 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
298 ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
299
300 /* Internal mask for ADC analog watchdog: */
301 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
302 /* (concatenation of multiple bits used in different analog watchdogs, */
303 /* (feature of several watchdogs not available on all STM32 series)). */
304 /* - analog watchdog 1: monitored channel defined by number, */
305 /* selection of ADC group (ADC groups regular and-or injected). */
306 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
307 /* selection on groups. */
308
309 /* Internal register offset for ADC analog watchdog channel configuration */
310 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
311 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
312 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
313
314 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
315 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
316 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
317 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
318
319 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
320
321 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
322 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
323 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
324
325 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
326 in ADC_AWD_CRX_REGOFFSET_MASK */
327
328 /* Internal register offset for ADC analog watchdog threshold configuration */
329 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
330 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
331 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
332 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
333 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
334 in ADC_AWD_TRX_REGOFFSET_MASK */
335 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
336 threshold high: mask of bit */
337 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
338 threshold high: position of bit */
339 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
340 position to perform a shift of 4 ranks */
341
342 /* Internal mask for ADC offset: */
343 /* Internal register offset for ADC offset instance configuration */
344 #define ADC_OFR1_REGOFFSET (0x00000000UL)
345 #define ADC_OFR2_REGOFFSET (0x00000001UL)
346 #define ADC_OFR3_REGOFFSET (0x00000002UL)
347 #define ADC_OFR4_REGOFFSET (0x00000003UL)
348 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
349 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
350
351
352 /* ADC registers bits positions */
353 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
354 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
355 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
356 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
357 #define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
358
359
360 /* ADC registers bits groups */
361 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
362 | ADC_CR_JADSTART | ADC_CR_JADSTP \
363 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
364 HW property "rs": Software can read as well as set this bit.
365 Writing '0' has no effect on the bit value. */
366
367
368 /* ADC internal channels related definitions */
369 /* Internal voltage reference VrefInt */
370 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E810UL)) /* Internal voltage reference, address of
371 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
372 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
373 #define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value
374 with which VrefInt has been calibrated in production
375 (tolerance: +-10 mV) (unit: mV). */
376 /* Temperature sensor */
377 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E814UL)) /* Address of parameter TS_CAL1: On STM32H7RS,
378 temperature sensor ADC raw data acquired at temperature 30 DegC
379 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
380 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E818UL)) /* Address of parameter TS_CAL2: On STM32H7RS,
381 temperature sensor ADC raw data acquired at temperature 130 DegC
382 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
383 #define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor
384 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
385 (tolerance: +-5 DegC) (unit: DegC). */
386 #define TEMPSENSOR_CAL2_TEMP (130L) /* Temperature at which temperature sensor
387 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
388 (tolerance: +-5 DegC) (unit: DegC). */
389 #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) value
390 with which temperature sensor has been calibrated in production
391 (tolerance +-10 mV) (unit: mV). */
392
393 /**
394 * @}
395 */
396
397
398 /* Private macros ------------------------------------------------------------*/
399 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
400 * @{
401 */
402
403 /**
404 * @brief Driver macro reserved for internal use: set a pointer to
405 * a register from a register basis from which an offset
406 * is applied.
407 * @param __REG__ Register basis from which the offset is applied.
408 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
409 * @retval Pointer to register address
410 */
411 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
412 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
413
414 /**
415 * @}
416 */
417
418
419 /* Exported types ------------------------------------------------------------*/
420 #if defined(USE_FULL_LL_DRIVER)
421 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
422 * @{
423 */
424
425 /**
426 * @brief Structure definition of some features of ADC common parameters
427 * and multimode
428 * (all ADC instances belonging to the same ADC common instance).
429 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
430 * is conditioned to ADC instances state (all ADC instances
431 * sharing the same ADC common instance):
432 * All ADC instances sharing the same ADC common instance must be
433 * disabled.
434 */
435 typedef struct
436 {
437 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
438 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
439 @note On this STM32 series, if ADC group injected is used, some clock ratio
440 constraints between ADC clock and AHB clock must be respected.
441 Refer to reference manual.
442 This feature can be modified afterwards using unitary function
443 @ref LL_ADC_SetCommonClock(). */
444
445 #if defined(ADC_MULTIMODE_SUPPORT)
446 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode
447 (for devices with several ADC instances).
448 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
449 This feature can be modified afterwards using unitary function
450 @ref LL_ADC_SetMultimode(). */
451
452 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
453 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
454 This feature can be modified afterwards using unitary function
455 @ref LL_ADC_SetMultiDMATransfer(). */
456
457 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
458 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
459 This feature can be modified afterwards using unitary function
460 @ref LL_ADC_SetMultiTwoSamplingDelay(). */
461 #endif /* ADC_MULTIMODE_SUPPORT */
462
463 } LL_ADC_CommonInitTypeDef;
464
465 /**
466 * @brief Structure definition of some features of ADC instance.
467 * @note These parameters have an impact on ADC scope: ADC instance.
468 * Affects both group regular and group injected (availability
469 * of ADC group injected depends on STM32 series).
470 * Refer to corresponding unitary functions into
471 * @ref ADC_LL_EF_Configuration_ADC_Instance .
472 * @note The setting of these parameters by function @ref LL_ADC_Init()
473 * is conditioned to ADC state:
474 * ADC instance must be disabled.
475 * This condition is applied to all ADC features, for efficiency
476 * and compatibility over all STM32 series. However, the different
477 * features can be set under different ADC state conditions
478 * (setting possible with ADC enabled without conversion on going,
479 * ADC enabled with conversion on going, ...)
480 * Each feature can be updated afterwards with a unitary function
481 * and potentially with ADC in a different state than disabled,
482 * refer to description of each function for setting
483 * conditioned to ADC state.
484 */
485 typedef struct
486 {
487 uint32_t Resolution; /*!< Set ADC resolution.
488 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
489 This feature can be modified afterwards using unitary function
490 @ref LL_ADC_SetResolution(). */
491
492 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
493 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
494 This feature can be modified afterwards using unitary function
495 @ref LL_ADC_SetDataAlignment(). */
496
497 uint32_t LowPowerMode; /*!< Set ADC low power mode.
498 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
499 This feature can be modified afterwards using unitary function
500 @ref LL_ADC_SetLowPowerMode(). */
501
502 } LL_ADC_InitTypeDef;
503
504 /**
505 * @brief Structure definition of some features of ADC group regular.
506 * @note These parameters have an impact on ADC scope: ADC group regular.
507 * Refer to corresponding unitary functions into
508 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
509 * (functions with prefix "REG").
510 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
511 * is conditioned to ADC state:
512 * ADC instance must be disabled.
513 * This condition is applied to all ADC features, for efficiency
514 * and compatibility over all STM32 series. However, the different
515 * features can be set under different ADC state conditions
516 * (setting possible with ADC enabled without conversion on going,
517 * ADC enabled with conversion on going, ...)
518 * Each feature can be updated afterwards with a unitary function
519 * and potentially with ADC in a different state than disabled,
520 * refer to description of each function for setting
521 * conditioned to ADC state.
522 */
523 typedef struct
524 {
525 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
526 from external peripheral (timer event, external interrupt line).
527 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
528 @note On this STM32 series, setting trigger source to external trigger also
529 set trigger polarity to rising edge(default setting for compatibility
530 with some ADC on other STM32 series having this setting set by HW
531 default value).
532 In case of need to modify trigger edge, use function
533 @ref LL_ADC_REG_SetTriggerEdge().
534 This feature can be modified afterwards using unitary function
535 @ref LL_ADC_REG_SetTriggerSource(). */
536
537 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
538 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
539 This feature can be modified afterwards using unitary function
540 @ref LL_ADC_REG_SetSequencerLength(). */
541
542 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
543 and scan conversions interrupted every selected number of ranks.
544 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
545 @note This parameter has an effect only if group regular sequencer is
546 enabled (scan length of 2 ranks or more).
547 This feature can be modified afterwards using unitary function
548 @ref LL_ADC_REG_SetSequencerDiscont(). */
549
550 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
551 conversions are performed in single mode (one conversion per trigger) or in
552 continuous mode (after the first trigger, following conversions launched
553 successively automatically).
554 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
555 Note: It is not possible to enable both ADC group regular continuous mode
556 and discontinuous mode.
557 This feature can be modified afterwards using unitary function
558 @ref LL_ADC_REG_SetContinuousMode(). */
559
560 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
561 by DMA, and DMA requests mode.
562 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
563 This feature can be modified afterwards using unitary function
564 @ref LL_ADC_REG_SetDMATransfer(). */
565
566 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
567 data preserved or overwritten.
568 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
569 This feature can be modified afterwards using unitary function
570 @ref LL_ADC_REG_SetOverrun(). */
571
572 } LL_ADC_REG_InitTypeDef;
573
574 /**
575 * @brief Structure definition of some features of ADC group injected.
576 * @note These parameters have an impact on ADC scope: ADC group injected.
577 * Refer to corresponding unitary functions into
578 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
579 * (functions with prefix "INJ").
580 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
581 * is conditioned to ADC state:
582 * ADC instance must be disabled.
583 * This condition is applied to all ADC features, for efficiency
584 * and compatibility over all STM32 series. However, the different
585 * features can be set under different ADC state conditions
586 * (setting possible with ADC enabled without conversion on going,
587 * ADC enabled with conversion on going, ...)
588 * Each feature can be updated afterwards with a unitary function
589 * and potentially with ADC in a different state than disabled,
590 * refer to description of each function for setting
591 * conditioned to ADC state.
592 */
593 typedef struct
594 {
595 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
596 or from external peripheral (timer event, external interrupt line).
597 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
598 @note On this STM32 series, setting trigger source to external trigger also
599 set trigger polarity to rising edge (default setting for
600 compatibility with some ADC on other STM32 series having this
601 setting set by HW default value).
602 In case of need to modify trigger edge, use function
603 @ref LL_ADC_INJ_SetTriggerEdge().
604 This feature can be modified afterwards using unitary function
605 @ref LL_ADC_INJ_SetTriggerSource(). */
606
607 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
608 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
609 This feature can be modified afterwards using unitary function
610 @ref LL_ADC_INJ_SetSequencerLength(). */
611
612 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
613 and scan conversions interrupted every selected number of ranks.
614 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
615 @note This parameter has an effect only if group injected sequencer is
616 enabled (scan length of 2 ranks or more).
617 This feature can be modified afterwards using unitary function
618 @ref LL_ADC_INJ_SetSequencerDiscont(). */
619
620 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group
621 regular.
622 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
623 Note: This parameter must be set to set to independent trigger if injected
624 trigger source is set to an external trigger.
625 This feature can be modified afterwards using unitary function
626 @ref LL_ADC_INJ_SetTrigAuto(). */
627
628 } LL_ADC_INJ_InitTypeDef;
629
630 /**
631 * @}
632 */
633 #endif /* USE_FULL_LL_DRIVER */
634
635 /* Exported constants --------------------------------------------------------*/
636 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
637 * @{
638 */
639
640 /** @defgroup ADC_LL_EC_FLAG ADC flags
641 * @brief Flags defines which can be used with LL_ADC_ReadReg function
642 * @{
643 */
644 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
645 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
646 conversion */
647 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
648 conversions */
649 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
650 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
651 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary
652 conversion */
653 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence
654 conversions */
655 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue
656 overflow */
657 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
658 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
659 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
660 #if defined(ADC_MULTIMODE_SUPPORT)
661 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
662 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
663 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of
664 unitary conversion */
665 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of
666 unitary conversion */
667 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of
668 sequence conversions */
669 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of
670 sequence conversions */
671 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular
672 overrun */
673 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular
674 overrun */
675 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of
676 sampling phase */
677 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of
678 sampling phase */
679 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of
680 unitary conversion */
681 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of
682 unitary conversion */
683 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of
684 sequence conversions */
685 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of
686 sequence conversions */
687 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected
688 contexts queue overflow */
689 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected
690 contexts queue overflow */
691 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
692 of the ADC master */
693 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
694 of the ADC slave */
695 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
696 of the ADC master */
697 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
698 of the ADC slave */
699 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
700 of the ADC master */
701 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
702 of the ADC slave */
703 #endif /* ADC_MULTIMODE_SUPPORT */
704 /**
705 * @}
706 */
707
708 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
709 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
710 * @{
711 */
712 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
713 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
714 conversion */
715 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
716 conversions */
717 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
718 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
719 phase */
720 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary
721 conversion */
722 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence
723 conversions */
724 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue
725 overflow */
726 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
727 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
728 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
729 /**
730 * @}
731 */
732
733 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
734 * @{
735 */
736 /* List of ADC registers intended to be used (most commonly) with */
737 /* DMA transfer. */
738 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
739 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
740 (corresponding to register DR) to be used with ADC configured in independent
741 mode. Without DMA transfer, register accessed by LL function
742 @ref LL_ADC_REG_ReadConversionData32() and other
743 functions @ref LL_ADC_REG_ReadConversionDatax() */
744 #if defined(ADC_MULTIMODE_SUPPORT)
745 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
746 (corresponding to register CDR) to be used with ADC configured in multimode
747 (available on STM32 devices with several ADC instances).
748 Without DMA transfer, register accessed by LL function
749 @ref LL_ADC_REG_ReadMultiConversionData32() */
750 #endif /* ADC_MULTIMODE_SUPPORT */
751 /**
752 * @}
753 */
754
755 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
756 * @{
757 */
758 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
759 AHB clock without prescaler */
760 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from
761 AHB clock with prescaler division by 2 */
762 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
763 AHB clock with prescaler division by 4 */
764 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
765 prescaler */
766 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
767 prescaler division by 2 */
768 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
769 prescaler division by 4 */
770 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
771 prescaler division by 6 */
772 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
773 prescaler division by 8 */
774 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
775 prescaler division by 10 */
776 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
777 prescaler division by 12 */
778 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
779 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
780 prescaler division by 16 */
781 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
782 prescaler division by 32 */
783 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
784 prescaler division by 64 */
785 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
786 prescaler division by 128 */
787 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
788 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
789 prescaler division by 256 */
790 /**
791 * @}
792 */
793
794 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
795 * @{
796 */
797 /* Note: Other measurement paths to internal channels may be available */
798 /* (connections to other peripherals). */
799 /* If they are not listed below, they do not require any specific */
800 /* path enable. In this case, Access to measurement path is done */
801 /* only by selecting the corresponding ADC internal channel. */
802 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
803 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
804 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
805 temperature sensor */
806 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
807 /**
808 * @}
809 */
810
811 /** @defgroup ADC_LL_EC_PATH_INTERNAL ADC instance - Measurement path to internal channels
812 * @{
813 */
814 /* Note: Other measurement paths to internal channels may be available */
815 /* (connections to other peripherals). */
816 /* If they are not listed below, they do not require any specific */
817 /* path enable. In this case, Access to measurement path is done */
818 /* only by selecting the corresponding ADC internal channel. */
819 #define LL_ADC_PATH_INTERNAL_VDDCORE (ADC_OR_OP0) /*!< ADC measurement path to internal channel VddCore */
820 /**
821 * @}
822 */
823
824 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
825 * @{
826 */
827 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
828 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
829 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
830 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
831 /**
832 * @}
833 */
834
835 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
836 * @{
837 */
838 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
839 (alignment on data register LSB bit 0)*/
840 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned
841 (alignment on data register MSB bit 15)*/
842 /**
843 * @}
844 */
845
846 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
847 * @{
848 */
849 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
850 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power
851 mode, ADC conversions are performed only when necessary
852 (when previous ADC conversion data is read).
853 See description with function @ref LL_ADC_SetLowPowerMode(). */
854 /**
855 * @}
856 */
857
858 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance
859 * @{
860 */
861 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
862 to which the offset programmed will be applied (independently of channel
863 mapped on ADC group regular or injected) */
864 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
865 to which the offset programmed will be applied (independently of channel
866 mapped on ADC group regular or injected) */
867 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
868 to which the offset programmed will be applied (independently of channel
869 mapped on ADC group regular or injected) */
870 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
871 to which the offset programmed will be applied (independently of channel
872 mapped on ADC group regular or injected) */
873 /**
874 * @}
875 */
876
877 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
878 * @{
879 */
880 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled
881 (setting offset instance wise) */
882 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled
883 (setting offset instance wise) */
884 /**
885 * @}
886 */
887
888 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
889 * @{
890 */
891 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative */
892 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */
893 /**
894 * @}
895 */
896
897 /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
898 * @{
899 */
900 #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC
901 selected offset instance 1, 2, 3 or 4) */
902 #define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC
903 selected offset instance 1, 2, 3 or 4) */
904 /**
905 * @}
906 */
907 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
908 * @{
909 */
910 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
911 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32
912 devices)*/
913 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
914 /**
915 * @}
916 */
917
918 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
919 * @{
920 */
921 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP \
922 | ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */
923 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP \
924 | ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */
925 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP \
926 | ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */
927 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP \
928 | ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */
929 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP \
930 | ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */
931 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP \
932 | ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */
933 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP \
934 | ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */
935 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP \
936 | ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */
937 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP \
938 | ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */
939 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP \
940 | ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */
941 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \
942 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
943 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \
944 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
945 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \
946 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
947 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \
948 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
949 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \
950 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
951 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \
952 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
953 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP \
954 | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
955 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP \
956 | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
957 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP \
958 | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
959 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
960 connected to VrefInt: Internal voltage reference, channel specific to ADC1.*/
961 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
962 connected to internal temperature sensor, channel specific to ADC1.*/
963 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
964 connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4
965 to have channel voltage always below Vdda, channel specific to ADC2. */
966 #define LL_ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
967 connected to Vcore, channel specific to ADC2. */
968 /**
969 * @}
970 */
971
972 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
973 * @{
974 */
975 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
976 conversion trigger internal: SW start. */
977 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
978 conversion trigger from external peripheral: TIM1 channel 1 event (capture
979 compare: input capture or output capture). Trigger edge set to rising edge
980 (default setting). */
981 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
982 conversion trigger from external peripheral: TIM1 channel 2 event (capture
983 compare: input capture or output capture). Trigger edge set to rising edge
984 (default setting). */
985 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
986 conversion trigger from external peripheral: TIM1 channel 3 event (capture
987 compare: input capture or output capture). Trigger edge set to rising edge
988 (default setting). */
989 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 \
990 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
991 conversion trigger from external peripheral: TIM2 channel 2 event (capture
992 compare: input capture or output capture). Trigger edge set to rising edge
993 (default setting). */
994 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
995 conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge
996 set to rising edge (default setting). */
997 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 \
998 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
999 conversion trigger from external peripheral: TIM4 channel 4 event (capture
1000 compare: input capture or output capture). Trigger edge set to rising edge
1001 (default setting). */
1002 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 \
1003 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1004 conversion trigger from external peripheral: external interrupt line 11
1005 event. Trigger edge set to rising edge (default setting). */
1006 #define LL_ADC_REG_TRIG_EXT_TIM12_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 \
1007 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1008 conversion trigger from external peripheral: TIM12 TRGO event. Trigger edge
1009 set to rising edge (default setting). */
1010 #define LL_ADC_REG_TRIG_EXT_TIM9_TRGO (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1011 conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge
1012 set to rising edge (default setting). */
1013 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 \
1014 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1015 conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge
1016 set to rising edge (default setting). */
1017 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 \
1018 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1019 conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge
1020 set to rising edge (default setting). */
1021 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 \
1022 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1023 conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge
1024 set to rising edge (default setting). */
1025 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \
1026 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1027 conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge
1028 set to rising edge (default setting). */
1029 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \
1030 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1031 conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge
1032 set to rising edge (default setting). */
1033 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \
1034 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1035 conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge
1036 set to rising edge (default setting). */
1037 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \
1038 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 \
1039 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1040 conversion trigger from external peripheral: TIM3 channel 4 event (capture
1041 compare: input capture or output capture). Trigger edge set to rising edge
1042 (default setting). */
1043 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 \
1044 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1045 conversion trigger from external peripheral: LPTIM1 channel 1 event (capture
1046 compare: input capture or output capture). Trigger edge set to rising edge
1047 (default setting). */
1048 #define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 \
1049 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1050 conversion trigger from external peripheral: LPTIM2 channel 1 event (capture
1051 compare: input capture or output capture). Trigger edge set to rising edge
1052 (default setting). */
1053 #define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 \
1054 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1055 conversion trigger from external peripheral: LPTIM3 channel 1 event (capture
1056 compare: input capture or output capture). Trigger edge set to rising edge
1057 (default setting). */
1058 /**
1059 * @}
1060 */
1061
1062 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1063 * @{
1064 */
1065 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1066 trigger polarity set to rising edge */
1067 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion
1068 trigger polarity set to falling edge */
1069 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1070 trigger polarity set to both rising and falling edges */
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
1076 * @{
1077 */
1078 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration
1079 is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
1080 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts
1081 immediately after end of conversion, and stops upon trigger event.
1082 Note: First conversion is using minimal sampling time
1083 (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
1084 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is
1085 controlled by trigger events: trigger rising edge for start sampling,
1086 trigger falling edge for stop sampling and start conversion */
1087 /**
1088 * @}
1089 */
1090
1091 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1092 * @{
1093 */
1094 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
1095 one conversion per trigger */
1096 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode:
1097 after the first trigger, following conversions launched successively
1098 automatically */
1099 /**
1100 * @}
1101 */
1102
1103 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1104 * @{
1105 */
1106 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
1107 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA
1108 in limited mode (one shot mode): DMA transfer requests are stopped when
1109 number of DMA data transfers (number of ADC conversions) is reached.
1110 This ADC mode is intended to be used with DMA mode non-circular. */
1111 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are
1112 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
1113 whatever number of DMA data transferred (number of ADC conversions).
1114 This ADC mode is intended to be used with DMA mode circular. */
1115 /**
1116 * @}
1117 */
1118
1119 /** @defgroup ADC_LL_EC_REG_MDF_TRANSFER ADC group regular - ADC conversion data transfer to MDF peripheral
1120 * @{
1121 */
1122 #define LL_ADC_REG_MDF_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions data are not transferred to MDF
1123 peripheral */
1124 #define LL_ADC_REG_MDF_TRANSFER_ENABLE (ADC_CFGR_ADFCFG) /*!< ADC conversion data are transferred to MDF
1125 peripheral. This configuration cannot be used if DMA transfer is enabled. */
1126 /**
1127 * @}
1128 */
1129
1130 #if defined(ADC_SMPR1_SMPPLUS)
1131 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
1132 * @{
1133 */
1134 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
1135 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock
1136 cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped
1137 with selection sampling time 2.5 ADC clock cycles, whatever channels mapped
1138 on ADC groups regular or injected). */
1139 /**
1140 * @}
1141 */
1142 #endif /* ADC_SMPR1_SMPPLUS */
1143
1144 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1145 * @{
1146 */
1147 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
1148 data preserved */
1149 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun:
1150 data overwritten */
1151 /**
1152 * @}
1153 */
1154
1155 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1156 * @{
1157 */
1158 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable
1159 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1160 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1161 with 2 ranks in the sequence */
1162 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1163 with 3 ranks in the sequence */
1164 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1165 with 4 ranks in the sequence */
1166 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1167 with 5 ranks in the sequence */
1168 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1169 with 6 ranks in the sequence */
1170 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1171 with 7 ranks in the sequence */
1172 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
1173 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1174 with 8 ranks in the sequence */
1175 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable
1176 with 9 ranks in the sequence */
1177 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1178 with 10 ranks in the sequence */
1179 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1180 with 11 ranks in the sequence */
1181 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
1182 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1183 with 12 ranks in the sequence */
1184 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1185 with 13 ranks in the sequence */
1186 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1187 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1188 with 14 ranks in the sequence */
1189 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1190 | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable
1191 with 15 ranks in the sequence */
1192 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1193 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1194 with 16 ranks in the sequence */
1195 /**
1196 * @}
1197 */
1198
1199 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1200 * @{
1201 */
1202 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
1203 discontinuous mode disable */
1204 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1205 discontinuous mode enable with sequence interruption every rank */
1206 #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1207 discontinuous mode enabled with sequence interruption every 2 ranks */
1208 #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1209 discontinuous mode enable with sequence interruption every 3 ranks */
1210 #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \
1211 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1212 discontinuous mode enable with sequence interruption every 4 ranks */
1213 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1214 discontinuous mode enable with sequence interruption every 5 ranks */
1215 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \
1216 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1217 discontinuous mode enable with sequence interruption every 6 ranks */
1218 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1219 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1220 discontinuous mode enable with sequence interruption every 7 ranks */
1221 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1222 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1223 discontinuous mode enable with sequence interruption every 8 ranks */
1224 /**
1225 * @}
1226 */
1227
1228 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1229 * @{
1230 */
1231 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group
1232 regular sequencer rank 1 */
1233 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group
1234 regular sequencer rank 2 */
1235 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group
1236 regular sequencer rank 3 */
1237 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group
1238 regular sequencer rank 4 */
1239 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group
1240 regular sequencer rank 5 */
1241 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group
1242 regular sequencer rank 6 */
1243 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group
1244 regular sequencer rank 7 */
1245 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group
1246 regular sequencer rank 8 */
1247 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group
1248 regular sequencer rank 9 */
1249 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
1250 regular sequencer rank 10 */
1251 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
1252 regular sequencer rank 11 */
1253 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
1254 regular sequencer rank 12 */
1255 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
1256 regular sequencer rank 13 */
1257 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
1258 regular sequencer rank 14 */
1259 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
1260 regular sequencer rank 15 */
1261 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
1262 regular sequencer rank 16 */
1263 /**
1264 * @}
1265 */
1266
1267 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1268 * @{
1269 */
1270 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected
1271 conversion trigger internal: SW start. */
1272 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1273 conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge
1274 set to rising edge (default setting). */
1275 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1276 conversion trigger from external peripheral: TIM1 channel 4 event (capture
1277 compare: input capture or output capture). Trigger edge set to rising edge
1278 (default setting). */
1279 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1280 conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge
1281 set to rising edge (default setting). */
1282 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1283 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1284 conversion trigger from external peripheral: TIM2 channel 1 event (capture
1285 compare: input capture or output capture). Trigger edge set to rising edge
1286 (default setting). */
1287 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1288 conversion trigger from external peripheral: TIM3 channel 4 event (capture
1289 compare: input capture or output capture). Trigger edge set to rising edge
1290 (default setting). */
1291 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
1292 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1293 conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge
1294 set to rising edge (default setting). */
1295 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1296 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1297 conversion trigger from external peripheral: external interrupt line 15.
1298 Trigger edge set to rising edge (default setting). */
1299 #define LL_ADC_INJ_TRIG_EXT_TIM9_CH1 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1300 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1301 conversion trigger from external peripheral: TIM9 channel 1 event (capture
1302 compare: input capture or output capture). Trigger edge set to rising edge
1303 (default setting). */
1304 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1305 conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge
1306 set to rising edge (default setting). */
1307 #define LL_ADC_INJ_TRIG_EXT_TIM12_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 \
1308 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1309 conversion trigger from external peripheral: TIM12 TRGO event. Trigger edge
1310 set to rising edge (default setting). */
1311 #define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \
1312 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1313 conversion trigger from external peripheral: TIM9 TRGO event. Trigger edge
1314 set to rising edge (default setting). */
1315 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \
1316 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1317 conversion trigger from external peripheral: TIM3 channel 3 event (capture
1318 compare: input capture or output capture). Trigger edge set to rising edge
1319 (default setting). */
1320 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1321 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1322 conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge
1323 set to rising edge (default setting). */
1324 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1325 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1326 conversion trigger from external peripheral: TIM3 channel 1 event (capture
1327 compare: input capture or output capture). Trigger edge set to rising edge
1328 (default setting). */
1329 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1330 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1331 conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge
1332 set to rising edge (default setting). */
1333 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1334 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1335 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1336 conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge
1337 set to rising edge (default setting). */
1338 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \
1339 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1340 conversion trigger from external peripheral: LPTIM1 channel 2 event (capture
1341 compare: input capture or output capture). Trigger edge set to rising edge
1342 (default setting). */
1343 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \
1344 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1345 conversion trigger from external peripheral: LPTIM2 channel 2 event (capture
1346 compare: input capture or output capture). Trigger edge set to rising edge
1347 (default setting). */
1348 #define LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
1349 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1350 conversion trigger from external peripheral: LPTIM3 channel 1 event (capture
1351 compare: input capture or output capture). Trigger edge set to rising edge
1352 (default setting). */
1353 /**
1354 * @}
1355 */
1356
1357 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1358 * @{
1359 */
1360 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1361 trigger polarity set to rising edge */
1362 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion
1363 trigger polarity set to falling edge */
1364 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1365 trigger polarity set to both rising and falling edges */
1366 /**
1367 * @}
1368 */
1369
1370 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1371 * @{
1372 */
1373 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent.
1374 Setting mandatory if ADC group injected injected trigger source is set to
1375 an external trigger. */
1376 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group
1377 regular. Setting compliant only with group injected trigger source set to
1378 SW start, without any further action on ADC group injected conversion start
1379 or stop: in this case, ADC group injected is controlled only from ADC group
1380 regular. */
1381 /**
1382 * @}
1383 */
1384
1385 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1386 * @{
1387 */
1388 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled
1389 and can contain up to 2 contexts. When all contexts have been processed,
1390 the queue maintains the last context active perpetually. */
1391 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled
1392 and can contain up to 2 contexts. When all contexts have been processed,
1393 the queue is empty and injected group triggers are disabled. */
1394 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled:
1395 only 1 sequence can be configured and is active perpetually. */
1396 /**
1397 * @}
1398 */
1399
1400 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1401 * @{
1402 */
1403 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable
1404 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1405 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1406 with 2 ranks in the sequence */
1407 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable
1408 with 3 ranks in the sequence */
1409 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1410 with 4 ranks in the sequence */
1411 /**
1412 * @}
1413 */
1414
1415 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1416 * @{
1417 */
1418 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode
1419 disable */
1420 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
1421 enable with sequence interruption every rank */
1422 /**
1423 * @}
1424 */
1425
1426 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1427 * @{
1428 */
1429 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \
1430 | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */
1431 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \
1432 | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */
1433 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \
1434 | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */
1435 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \
1436 | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */
1437 /**
1438 * @}
1439 */
1440
1441 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1442 * @{
1443 */
1444 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1445 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1446 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
1447 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 (ADC_SMPR2_SMP10_1 \
1448 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1449 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
1450 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \
1451 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1452 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \
1453 | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
1454 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \
1455 | ADC_SMPR2_SMP10_1 \
1456 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1457 /**
1458 * @}
1459 */
1460
1461 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1462 * @{
1463 */
1464 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending
1465 set to single ended (literal also used to set calibration mode) */
1466 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending
1467 set to differential (literal also used to set calibration mode) */
1468 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending
1469 set to both single ended and differential (literal used only to set
1470 calibration factors) */
1471 /**
1472 * @}
1473 */
1474
1475 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1476 * @{
1477 */
1478 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
1479 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1480 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
1481 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1482 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
1483 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1484 /**
1485 * @}
1486 */
1487
1488 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1489 * @{
1490 */
1491 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
1492 disabled */
1493 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
1494 | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1495 of all channels, converted by group regular only */
1496 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1497 | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring
1498 of all channels, converted by group injected only */
1499 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1500 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1501 of all channels, converted by either group regular or injected */
1502 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1503 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1504 of ADC channel ADCx_IN0, converted by group regular only */
1505 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1506 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1507 of ADC channel ADCx_IN0, converted by group injected only */
1508 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1509 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1510 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1511 of ADC channel ADCx_IN0, converted by either group regular or injected */
1512 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1513 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1514 of ADC channel ADCx_IN1, converted by group regular only */
1515 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1516 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1517 of ADC channel ADCx_IN1, converted by group injected only */
1518 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1519 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1520 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1521 of ADC channel ADCx_IN1, converted by either group regular or injected */
1522 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1523 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1524 of ADC channel ADCx_IN2, converted by group regular only */
1525 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1526 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1527 of ADC channel ADCx_IN2, converted by group injected only */
1528 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1529 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1530 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1531 of ADC channel ADCx_IN2, converted by either group regular or injected */
1532 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1533 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1534 of ADC channel ADCx_IN3, converted by group regular only */
1535 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1536 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1537 of ADC channel ADCx_IN3, converted by group injected only */
1538 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1539 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1540 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1541 of ADC channel ADCx_IN3, converted by either group regular or injected */
1542 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1543 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1544 of ADC channel ADCx_IN4, converted by group regular only */
1545 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1546 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1547 of ADC channel ADCx_IN4, converted by group injected only */
1548 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1549 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1550 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1551 of ADC channel ADCx_IN4, converted by either group regular or injected */
1552 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1553 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1554 of ADC channel ADCx_IN5, converted by group regular only */
1555 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1556 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1557 of ADC channel ADCx_IN5, converted by group injected only */
1558 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1559 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1560 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1561 of ADC channel ADCx_IN5, converted by either group regular or injected */
1562 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1563 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1564 of ADC channel ADCx_IN6, converted by group regular only */
1565 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1566 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1567 of ADC channel ADCx_IN6, converted by group injected only */
1568 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1569 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1570 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1571 of ADC channel ADCx_IN6, converted by either group regular or injected */
1572 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1573 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1574 of ADC channel ADCx_IN7, converted by group regular only */
1575 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1576 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1577 of ADC channel ADCx_IN7, converted by group injected only */
1578 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1579 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1580 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1581 of ADC channel ADCx_IN7, converted by either group regular or injected */
1582 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1583 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1584 of ADC channel ADCx_IN8, converted by group regular only */
1585 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1586 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1587 of ADC channel ADCx_IN8, converted by group injected only */
1588 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1589 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1590 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1591 of ADC channel ADCx_IN8, converted by either group regular or injected */
1592 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1593 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1594 of ADC channel ADCx_IN9, converted by group regular only */
1595 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1596 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1597 of ADC channel ADCx_IN9, converted by group injected only */
1598 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1599 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1600 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1601 of ADC channel ADCx_IN9, converted by either group regular or injected */
1602 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1603 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1604 of ADC channel ADCx_IN10, converted by group regular only */
1605 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1606 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1607 of ADC channel ADCx_IN10, converted by group injected only */
1608 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\
1609 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1610 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1611 of ADC channel ADCx_IN10, converted by either group regular or injected */
1612 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1613 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1614 of ADC channel ADCx_IN11, converted by group regular only */
1615 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1616 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1617 of ADC channel ADCx_IN11, converted by group injected only */
1618 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1619 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1620 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1621 of ADC channel ADCx_IN11, converted by either group regular or injected */
1622 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1623 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1624 of ADC channel ADCx_IN12, converted by group regular only */
1625 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1626 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1627 of ADC channel ADCx_IN12, converted by group injected only */
1628 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1629 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1630 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1631 of ADC channel ADCx_IN12, converted by either group regular or injected */
1632 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1633 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1634 of ADC channel ADCx_IN13, converted by group regular only */
1635 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1636 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1637 of ADC channel ADCx_IN13, converted by group injected only */
1638 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1639 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1640 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1641 of ADC channel ADCx_IN13, converted by either group regular or injected */
1642 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1643 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1644 of ADC channel ADCx_IN14, converted by group regular only */
1645 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1646 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1647 of ADC channel ADCx_IN14, converted by group only */
1648 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1649 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1650 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1651 of ADC channel ADCx_IN14, converted by either group regular or injected */
1652 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1653 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1654 monitoring of ADC channel ADCx_IN15, converted by group regular only */
1655 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1656 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1657 of ADC channel ADCx_IN15, converted by group injected only */
1658 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1659 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1660 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1661 of ADC channel ADCx_IN15, converted by either group
1662 regular or injected */
1663 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1664 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1665 of ADC channel ADCx_IN16,
1666 converted by group regular only */
1667 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1668 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1669 of ADC channel ADCx_IN16,
1670 converted by group injected only */
1671 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1672 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1673 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1674 of ADC channel ADCx_IN16,
1675 converted by either group regular or injected */
1676 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1677 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1678 of ADC channel ADCx_IN17,
1679 converted by group regular only */
1680 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1681 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1682 of ADC channel ADCx_IN17,
1683 converted by group injected only */
1684 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1685 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1686 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1687 of ADC channel ADCx_IN17,
1688 by either group regular or injected */
1689 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1690 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1691 of ADC channel ADCx_IN18,
1692 converted by group regular only */
1693 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1694 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1695 of ADC channel ADCx_IN18,
1696 converted by group injected only */
1697 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1698 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1699 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1700 of ADC channel ADCx_IN18,
1701 converted by either group regular or injected */
1702 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1703 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1704 of ADC internal channel connected to VrefInt: Internal
1705 voltage reference, converted by group regular only */
1706 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1707 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1708 of ADC internal channel connected to VrefInt: Internal
1709 voltage reference, converted by group injected only */
1710 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1711 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1712 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1713 of ADC internal channel connected to VrefInt: Internal
1714 voltage reference, converted by either group regular or injected */
1715 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1716 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1717 of ADC internal channel connected to internal temperature sensor,
1718 converted by group regular only */
1719 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1720 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1721 of ADC internal channel connected to internal temperature sensor,
1722 converted by group injected only */
1723 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1724 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1725 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1726 of ADC internal channel connected to internal temperature sensor,
1727 converted by either group regular or injected */
1728 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1729 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1730 of ADC internal channel connected to Vbat/4: Vbat
1731 voltage through a divider ladder of factor 1/4 to have channel voltage
1732 always below Vdda, converted by group regular only */
1733 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1734 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1735 of ADC internal channel connected to Vbat/4: Vbat
1736 voltage through a divider ladder of factor 1/4 to have channel voltage
1737 always below Vdda, converted by group injected only */
1738 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1739 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1740 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1741 of ADC internal channel connected to Vbat/4: Vbat
1742 voltage through a divider ladder of factor 1/4 to have channel voltage
1743 always below Vdda */
1744 #define LL_ADC_AWD_CH_VDDCORE_REG ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \
1745 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1746 of ADC internal channel connected to VddCore,
1747 converted by group regular only */
1748 #define LL_ADC_AWD_CH_VDDCORE_INJ ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \
1749 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1750 monitoring of ADC internal channel connected to VddCore,
1751 converted by group injected only */
1752 #define LL_ADC_AWD_CH_VDDCORE_REG_INJ ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \
1753 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1754 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1755 of ADC internal channel connected to VddCore,
1756 converted by either group regular or injected */
1757 /**
1758 * @}
1759 */
1760
1761 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1762 * @{
1763 */
1764 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */
1765 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1766 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \
1767 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low
1768 concatenated into the same data */
1769 /**
1770 * @}
1771 */
1772
1773 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1774 * @{
1775 */
1776 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering,
1777 one out-of-window sample is needed to raise flag or interrupt */
1778 #define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 2
1779 out-of-window samples are needed to raise flag or interrupt */
1780 #define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 3
1781 consecutives out-of-window samples are needed to raise flag or interrupt */
1782 #define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4
1783 consecutives out-of-window samples are needed to raise flag or interrupt */
1784 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2) /*!< ADC analog watchdog 5
1785 consecutives out-of-window samples are needed to raise flag or interrupt */
1786 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6
1787 consecutives out-of-window samples are needed to raise flag or interrupt */
1788 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7
1789 consecutives out-of-window samples are needed to raise flag or interrupt */
1790 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
1791 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 8
1792 consecutives out-of-window samples are needed to raise flag or interrupt */
1793 /**
1794 * @}
1795 */
1796
1797 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1798 * @{
1799 */
1800 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1801 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1802 ADC group regular. If group injected interrupts group regular:
1803 when ADC group injected is triggered, the oversampling on ADC group regular
1804 is temporary stopped and continued afterwards. */
1805 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1806 ADC group regular. If group injected interrupts group regular:
1807 when ADC group injected is triggered, the oversampling on ADC group regular
1808 is resumed from start (oversampler buffer reset). */
1809 #define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of
1810 ADC group injected. */
1811 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1812 both ADC groups regular and injected. If group injected interrupting group
1813 regular: when ADC group injected is triggered, the oversampling on ADC group
1814 regular is resumed from start (oversampler buffer reset). */
1815 /**
1816 * @}
1817 */
1818
1819 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1820 * @{
1821 */
1822 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1823 (all conversions of oversampling ratio are done from 1 trigger) */
1824 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous
1825 mode (each conversion of oversampling ratio needs a trigger) */
1826 /**
1827 * @}
1828 */
1829
1830 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1831 * @{
1832 */
1833 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1834 (sum of conversions data computed to result as oversampling conversion data
1835 (before potential shift) */
1836 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1837 (sum of conversions data computed to result as oversampling conversion data
1838 (before potential shift) */
1839 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1840 (sum of conversions data computed to result as oversampling conversion data
1841 (before potential shift) */
1842 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1843 (sum of conversions data computed to result as oversampling conversion data
1844 (before potential shift) */
1845 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1846 (sum of conversions data computed to result as oversampling conversion data
1847 (before potential shift) */
1848 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1849 (sum of conversions data computed to result as oversampling conversion data
1850 (before potential shift) */
1851 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1852 (sum of conversions data computed to result as oversampling conversion data
1853 (before potential shift) */
1854 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1855 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1856 (sum of conversions data computed to result as oversampling conversion data
1857 (before potential shift) */
1858 /**
1859 * @}
1860 */
1861
1862 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1863 * @{
1864 */
1865 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1866 (sum of the ADC conversions data is not divided to result as oversampling
1867 conversion data) */
1868 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1869 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1870 to result as oversampling conversion data) */
1871 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1872 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1873 to result as oversampling conversion data) */
1874 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1875 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1876 to result as oversampling conversion data) */
1877 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1878 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1879 to result as oversampling conversion data) */
1880 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1881 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1882 to result as oversampling conversion data) */
1883 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1884 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1885 to result as oversampling conversion data) */
1886 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1887 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1888 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1889 to result as oversampling conversion data) */
1890 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1891 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1892 to result as oversampling conversion data) */
1893 /**
1894 * @}
1895 */
1896
1897 #if defined(ADC_MULTIMODE_SUPPORT)
1898 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1899 * @{
1900 */
1901 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC
1902 independent mode) */
1903 #define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
1904 simultaneous */
1905 #define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
1906 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1907 regular interleaved */
1908 #define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1909 simultaneous */
1910 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1911 alternate trigger. Works only with external triggers (not SW start) */
1912 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1913 regular simultaneous + group injected simultaneous */
1914 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group
1915 regular simultaneous + group injected alternate trigger */
1916 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1917 regular interleaved + group injected simultaneous */
1918 /**
1919 * @}
1920 */
1921
1922 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1923 * @{
1924 */
1925 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular
1926 conversions are transferred by DMA: each ADC uses its own DMA channel,
1927 with its individual DMA transfer settings */
1928 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1) /*!< ADC multimode group regular
1929 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1930 ADC master), in limited mode (one shot mode): DMA transfer requests
1931 are stopped when number of DMA data transfers (number of ADC conversions)
1932 is reached. This ADC mode is intended to be used with DMA mode
1933 non-circular. Setting for ADC resolution of 12 and 10 bits */
1934 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
1935 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1936 ADC master), in limited mode (one shot mode): DMA transfer requests
1937 are stopped when number of DMA data transfers (number of ADC conversions)
1938 is reached. This ADC mode is intended to be used with DMA mode
1939 non-circular. Setting for ADC resolution of 8 and 6 bits */
1940 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular
1941 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1942 ADC master), in unlimited mode: DMA transfer requests are unlimited,
1943 whatever number of DMA data transferred (number of ADC conversions).
1944 This ADC mode is intended to be used with DMA mode circular.
1945 Setting for ADC resolution of 12 and 10 bits */
1946 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \
1947 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
1948 conversions are transferred by DMA, one DMA channel for both ADC (DMA of
1949 ADC master), in unlimited mode: DMA transfer requests are unlimited,
1950 whatever number of DMA data transferred (number of ADC conversions).
1951 This ADC mode is intended to be used with DMA mode circular.
1952 Setting for ADC resolution of 8 and 6 bits */
1953 /**
1954 * @}
1955 */
1956
1957 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1958 * @{
1959 */
1960 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two
1961 sampling phases: 1 ADC clock cycle */
1962 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1963 sampling phases: 2 ADC clock cycles */
1964 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1965 sampling phases: 3 ADC clock cycles */
1966 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1967 sampling phases: 4 ADC clock cycles */
1968 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two
1969 sampling phases: 5 ADC clock cycles */
1970 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1971 sampling phases: 6 ADC clock cycles */
1972 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1973 sampling phases: 7 ADC clock cycles */
1974 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
1975 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1976 sampling phases: 8 ADC clock cycles */
1977 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two
1978 sampling phases: 9 ADC clock cycles */
1979 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1980 sampling phases: 10 ADC clock cycles */
1981 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1982 sampling phases: 11 ADC clock cycles */
1983 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
1984 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1985 sampling phases: 12 ADC clock cycles */
1986 /**
1987 * @}
1988 */
1989
1990 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1991 * @{
1992 */
1993 #define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
1994 instances: ADC master */
1995 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
1996 instances: ADC slave */
1997 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \
1998 | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
1999 instances: both ADC master and ADC slave */
2000 /**
2001 * @}
2002 */
2003
2004 #endif /* ADC_MULTIMODE_SUPPORT */
2005
2006 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
2007 * @{
2008 */
2009 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
2010 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
2011 calibration parameters. This value is coded on 16 bits
2012 (to fit on signed word or double word) and corresponds
2013 to an inconsistent temperature value. */
2014 /**
2015 * @}
2016 */
2017
2018 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
2019 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
2020 * not timeout values.
2021 * For details on delays values, refer to descriptions in source code
2022 * above each literal definition.
2023 * @{
2024 */
2025
2026 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
2027 /* not timeout values. */
2028 /* Timeout values for ADC operations are dependent to device clock */
2029 /* configuration (system clock versus ADC clock), */
2030 /* and therefore must be defined in user application. */
2031 /* Indications for estimation of ADC timeout delays, for this */
2032 /* STM32 series: */
2033 /* - ADC calibration time: maximum delay is 112/fADC. */
2034 /* (refer to device datasheet, parameter "tCAL") */
2035 /* - ADC enable time: maximum delay is 1 conversion cycle. */
2036 /* (refer to device datasheet, parameter "tSTAB") */
2037 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
2038 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
2039 /* cycles */
2040 /* - ADC conversion time: duration depending on ADC clock and ADC */
2041 /* configuration. */
2042 /* (refer to device reference manual, section "Timing") */
2043
2044 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
2045 /* Delay set to maximum value (refer to device datasheet, */
2046 /* parameter "tADCVREG_STUP"). */
2047 /* Unit: us */
2048 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
2049 regulator start-up time) */
2050
2051 /* Delay for internal voltage reference stabilization time. */
2052 /* Delay set to maximum value (refer to device datasheet, */
2053 /* parameter "tstart_vrefint"). */
2054 /* Unit: us */
2055 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
2056 time */
2057
2058 /* Delay for temperature sensor stabilization time. */
2059 /* Literal set to maximum value (refer to device datasheet, */
2060 /* parameter "tSTART"). */
2061 /* Unit: us */
2062 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
2063 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
2064 time (starting from ADC enable, refer to
2065 @ref LL_ADC_Enable()) */
2066
2067 /* Delay required between ADC end of calibration and ADC enable. */
2068 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
2069 /* are required between ADC end of calibration and ADC enable. */
2070 /* Wait time can be computed in user application by waiting for the */
2071 /* equivalent number of CPU cycles, by taking into account */
2072 /* ratio of CPU clock versus ADC clock prescalers. */
2073 /* Unit: ADC clock cycles. */
2074 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration
2075 and ADC enable */
2076
2077 /**
2078 * @}
2079 */
2080
2081 /**
2082 * @}
2083 */
2084
2085
2086 /* Exported macro ------------------------------------------------------------*/
2087 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
2088 * @{
2089 */
2090
2091 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
2092 * @{
2093 */
2094
2095 /**
2096 * @brief Write a value in ADC register
2097 * @param __INSTANCE__ ADC Instance
2098 * @param __REG__ Register to be written
2099 * @param __VALUE__ Value to be written in the register
2100 * @retval None
2101 */
2102 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2103
2104 /**
2105 * @brief Read a value in ADC register
2106 * @param __INSTANCE__ ADC Instance
2107 * @param __REG__ Register to be read
2108 * @retval Register value
2109 */
2110 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2111 /**
2112 * @}
2113 */
2114
2115 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
2116 * @{
2117 */
2118
2119 /**
2120 * @brief Helper macro to get ADC channel number in decimal format
2121 * from literals LL_ADC_CHANNEL_x.
2122 * @note Example:
2123 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
2124 * will return decimal number "4".
2125 * @note The input can be a value from functions where a channel
2126 * number is returned, either defined with number
2127 * or with bitfield (only one bit must be set).
2128 * @param __CHANNEL__ This parameter can be one of the following values:
2129 * @arg @ref LL_ADC_CHANNEL_0 (3)
2130 * @arg @ref LL_ADC_CHANNEL_1 (3)
2131 * @arg @ref LL_ADC_CHANNEL_2 (3)
2132 * @arg @ref LL_ADC_CHANNEL_3 (3)
2133 * @arg @ref LL_ADC_CHANNEL_4 (3)
2134 * @arg @ref LL_ADC_CHANNEL_5 (3)
2135 * @arg @ref LL_ADC_CHANNEL_6
2136 * @arg @ref LL_ADC_CHANNEL_7
2137 * @arg @ref LL_ADC_CHANNEL_8
2138 * @arg @ref LL_ADC_CHANNEL_9
2139 * @arg @ref LL_ADC_CHANNEL_10
2140 * @arg @ref LL_ADC_CHANNEL_11
2141 * @arg @ref LL_ADC_CHANNEL_12
2142 * @arg @ref LL_ADC_CHANNEL_13
2143 * @arg @ref LL_ADC_CHANNEL_14
2144 * @arg @ref LL_ADC_CHANNEL_15
2145 * @arg @ref LL_ADC_CHANNEL_16
2146 * @arg @ref LL_ADC_CHANNEL_17
2147 * @arg @ref LL_ADC_CHANNEL_18
2148 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2149 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2150 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2151 *
2152 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
2153 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2154 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2155 * @retval Value between Min_Data=0 and Max_Data=18
2156 */
2157 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
2158 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
2159 ( \
2160 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
2161 ) \
2162 : \
2163 ( \
2164 (uint32_t)POSITION_VAL((__CHANNEL__)) \
2165 ) \
2166 )
2167
2168 /**
2169 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
2170 * from number in decimal format.
2171 * @note Example:
2172 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
2173 * will return a data equivalent to "LL_ADC_CHANNEL_4".
2174 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
2175 * @retval Returned value can be one of the following values:
2176 * @arg @ref LL_ADC_CHANNEL_0 (2)
2177 * @arg @ref LL_ADC_CHANNEL_1 (2)
2178 * @arg @ref LL_ADC_CHANNEL_2 (2)
2179 * @arg @ref LL_ADC_CHANNEL_3 (2)
2180 * @arg @ref LL_ADC_CHANNEL_4 (2)
2181 * @arg @ref LL_ADC_CHANNEL_5 (2)
2182 * @arg @ref LL_ADC_CHANNEL_6
2183 * @arg @ref LL_ADC_CHANNEL_7
2184 * @arg @ref LL_ADC_CHANNEL_8
2185 * @arg @ref LL_ADC_CHANNEL_9
2186 * @arg @ref LL_ADC_CHANNEL_10
2187 * @arg @ref LL_ADC_CHANNEL_11
2188 * @arg @ref LL_ADC_CHANNEL_12
2189 * @arg @ref LL_ADC_CHANNEL_13
2190 * @arg @ref LL_ADC_CHANNEL_14
2191 * @arg @ref LL_ADC_CHANNEL_15
2192 * @arg @ref LL_ADC_CHANNEL_16
2193 * @arg @ref LL_ADC_CHANNEL_17
2194 * @arg @ref LL_ADC_CHANNEL_18
2195 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
2196 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3)
2197 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3)
2198 *
2199 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
2200 * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2201 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2202 * (3) For ADC channel read back from ADC register,
2203 * comparison with internal channel parameter to be done
2204 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2205 */
2206 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
2207 (((__DECIMAL_NB__) <= 9UL) ? \
2208 ( \
2209 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2210 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2211 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2212 ) \
2213 : \
2214 ( \
2215 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2216 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2217 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2218 ) \
2219 )
2220
2221 /**
2222 * @brief Helper macro to determine whether the selected channel
2223 * corresponds to literal definitions of driver.
2224 * @note The different literal definitions of ADC channels are:
2225 * - ADC internal channel:
2226 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
2227 * - ADC external channel (channel connected to a GPIO pin):
2228 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
2229 * @note The channel parameter must be a value defined from literal
2230 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2231 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2232 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
2233 * must not be a value from functions where a channel number is
2234 * returned from ADC registers,
2235 * because internal and external channels share the same channel
2236 * number in ADC registers. The differentiation is made only with
2237 * parameters definitions of driver.
2238 * @param __CHANNEL__ This parameter can be one of the following values:
2239 * @arg @ref LL_ADC_CHANNEL_0 (3)
2240 * @arg @ref LL_ADC_CHANNEL_1 (3)
2241 * @arg @ref LL_ADC_CHANNEL_2 (3)
2242 * @arg @ref LL_ADC_CHANNEL_3 (3)
2243 * @arg @ref LL_ADC_CHANNEL_4 (3)
2244 * @arg @ref LL_ADC_CHANNEL_5 (3)
2245 * @arg @ref LL_ADC_CHANNEL_6
2246 * @arg @ref LL_ADC_CHANNEL_7
2247 * @arg @ref LL_ADC_CHANNEL_8
2248 * @arg @ref LL_ADC_CHANNEL_9
2249 * @arg @ref LL_ADC_CHANNEL_10
2250 * @arg @ref LL_ADC_CHANNEL_11
2251 * @arg @ref LL_ADC_CHANNEL_12
2252 * @arg @ref LL_ADC_CHANNEL_13
2253 * @arg @ref LL_ADC_CHANNEL_14
2254 * @arg @ref LL_ADC_CHANNEL_15
2255 * @arg @ref LL_ADC_CHANNEL_16
2256 * @arg @ref LL_ADC_CHANNEL_17
2257 * @arg @ref LL_ADC_CHANNEL_18
2258 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2259 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2260 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2261 *
2262 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
2263 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2264 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2265 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
2266 connected to a GPIO pin).
2267 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
2268 */
2269 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
2270 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
2271
2272 /**
2273 * @brief Helper macro to convert a channel defined from parameter
2274 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2275 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2276 * to its equivalent parameter definition of a ADC external channel
2277 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
2278 * @note The channel parameter can be, additionally to a value
2279 * defined from parameter definition of a ADC internal channel
2280 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
2281 * a value defined from parameter definition of
2282 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2283 * or a value from functions where a channel number is returned
2284 * from ADC registers.
2285 * @param __CHANNEL__ This parameter can be one of the following values:
2286 * @arg @ref LL_ADC_CHANNEL_0 (3)
2287 * @arg @ref LL_ADC_CHANNEL_1 (3)
2288 * @arg @ref LL_ADC_CHANNEL_2 (3)
2289 * @arg @ref LL_ADC_CHANNEL_3 (3)
2290 * @arg @ref LL_ADC_CHANNEL_4 (3)
2291 * @arg @ref LL_ADC_CHANNEL_5 (3)
2292 * @arg @ref LL_ADC_CHANNEL_6
2293 * @arg @ref LL_ADC_CHANNEL_7
2294 * @arg @ref LL_ADC_CHANNEL_8
2295 * @arg @ref LL_ADC_CHANNEL_9
2296 * @arg @ref LL_ADC_CHANNEL_10
2297 * @arg @ref LL_ADC_CHANNEL_11
2298 * @arg @ref LL_ADC_CHANNEL_12
2299 * @arg @ref LL_ADC_CHANNEL_13
2300 * @arg @ref LL_ADC_CHANNEL_14
2301 * @arg @ref LL_ADC_CHANNEL_15
2302 * @arg @ref LL_ADC_CHANNEL_16
2303 * @arg @ref LL_ADC_CHANNEL_17
2304 * @arg @ref LL_ADC_CHANNEL_18
2305 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2306 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2307 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2308 *
2309 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
2310 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2311 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2312 * @retval Returned value can be one of the following values:
2313 * @arg @ref LL_ADC_CHANNEL_0
2314 * @arg @ref LL_ADC_CHANNEL_1
2315 * @arg @ref LL_ADC_CHANNEL_2
2316 * @arg @ref LL_ADC_CHANNEL_3
2317 * @arg @ref LL_ADC_CHANNEL_4
2318 * @arg @ref LL_ADC_CHANNEL_5
2319 * @arg @ref LL_ADC_CHANNEL_6
2320 * @arg @ref LL_ADC_CHANNEL_7
2321 * @arg @ref LL_ADC_CHANNEL_8
2322 * @arg @ref LL_ADC_CHANNEL_9
2323 * @arg @ref LL_ADC_CHANNEL_10
2324 * @arg @ref LL_ADC_CHANNEL_11
2325 * @arg @ref LL_ADC_CHANNEL_12
2326 * @arg @ref LL_ADC_CHANNEL_13
2327 * @arg @ref LL_ADC_CHANNEL_14
2328 * @arg @ref LL_ADC_CHANNEL_15
2329 * @arg @ref LL_ADC_CHANNEL_16
2330 * @arg @ref LL_ADC_CHANNEL_17
2331 * @arg @ref LL_ADC_CHANNEL_18
2332 */
2333 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
2334 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
2335
2336 /**
2337 * @brief Helper macro to determine whether the internal channel
2338 * selected is available on the ADC instance selected.
2339 * @note The channel parameter must be a value defined from parameter
2340 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2341 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2342 * must not be a value defined from parameter definition of
2343 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2344 * or a value from functions where a channel number is
2345 * returned from ADC registers,
2346 * because internal and external channels share the same channel
2347 * number in ADC registers. The differentiation is made only with
2348 * parameters definitions of driver.
2349 * @param __ADC_INSTANCE__ ADC instance
2350 * @param __CHANNEL__ This parameter can be one of the following values:
2351 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2352 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2353 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2354 *
2355 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.
2356 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
2357 * Value "1" if the internal channel selected is available on the ADC instance selected.
2358 */
2359 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2360 ((((__ADC_INSTANCE__) == ADC1) \
2361 &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2362 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)) \
2363 ) \
2364 || \
2365 (((__ADC_INSTANCE__) == ADC2) \
2366 &&(((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2367 ((__CHANNEL__) == LL_ADC_CHANNEL_VDDCORE)) \
2368 ) \
2369 )
2370
2371 /**
2372 * @brief Helper macro to define ADC analog watchdog parameter:
2373 * define a single channel to monitor with analog watchdog
2374 * from sequencer channel and groups definition.
2375 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2376 * Example:
2377 * LL_ADC_SetAnalogWDMonitChannels(
2378 * ADC1, LL_ADC_AWD1,
2379 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2380 * @param __CHANNEL__ This parameter can be one of the following values:
2381 * @arg @ref LL_ADC_CHANNEL_0 (2)
2382 * @arg @ref LL_ADC_CHANNEL_1 (2)
2383 * @arg @ref LL_ADC_CHANNEL_2 (2)
2384 * @arg @ref LL_ADC_CHANNEL_3 (2)
2385 * @arg @ref LL_ADC_CHANNEL_4 (2)
2386 * @arg @ref LL_ADC_CHANNEL_5 (2)
2387 * @arg @ref LL_ADC_CHANNEL_6
2388 * @arg @ref LL_ADC_CHANNEL_7
2389 * @arg @ref LL_ADC_CHANNEL_8
2390 * @arg @ref LL_ADC_CHANNEL_9
2391 * @arg @ref LL_ADC_CHANNEL_10
2392 * @arg @ref LL_ADC_CHANNEL_11
2393 * @arg @ref LL_ADC_CHANNEL_12
2394 * @arg @ref LL_ADC_CHANNEL_13
2395 * @arg @ref LL_ADC_CHANNEL_14
2396 * @arg @ref LL_ADC_CHANNEL_15
2397 * @arg @ref LL_ADC_CHANNEL_16
2398 * @arg @ref LL_ADC_CHANNEL_17
2399 * @arg @ref LL_ADC_CHANNEL_18
2400 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
2401 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3)
2402 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3)
2403 *
2404 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
2405 * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2406 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2407 * (3) For ADC channel read back from ADC register,
2408 * comparison with internal channel parameter to be done
2409 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2410 * @param __GROUP__ This parameter can be one of the following values:
2411 * @arg @ref LL_ADC_GROUP_REGULAR
2412 * @arg @ref LL_ADC_GROUP_INJECTED
2413 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2414 * @retval Returned value can be one of the following values:
2415 * @arg @ref LL_ADC_AWD_DISABLE
2416 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2417 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2418 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2419 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2420 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2421 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2422 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2423 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2424 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2425 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2426 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2427 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2428 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2429 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2430 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2431 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2432 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2433 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2434 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2435 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2436 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2437 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2438 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2439 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2440 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2441 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2442 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2443 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2444 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2445 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2446 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2447 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2448 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2449 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2450 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2451 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2452 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2453 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2454 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2455 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2456 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2457 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2458 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2459 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2460 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2461 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2462 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2463 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2464 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2465 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2466 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2467 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2468 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2469 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2470 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2471 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2472 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2473 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2474 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2475 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2476 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
2477 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
2478 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
2479 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
2480 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
2481 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
2482 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
2483 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
2484 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
2485 *
2486 * (0) On STM32H7RS, parameter available only on analog watchdog number: AWD1.\n
2487 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
2488 */
2489 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2490 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2491 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2492 : \
2493 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2494 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2495 : \
2496 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2497 )
2498
2499 /**
2500 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2501 * or low in function of ADC resolution, when ADC resolution is
2502 * different of 12 bits.
2503 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2504 * or @ref LL_ADC_SetAnalogWDThresholds().
2505 * Example, with a ADC resolution of 8 bits, to set the value of
2506 * analog watchdog threshold high (on 8 bits):
2507 * LL_ADC_SetAnalogWDThresholds
2508 * (< ADCx param >,
2509 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2510 * );
2511 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2512 * @arg @ref LL_ADC_RESOLUTION_12B
2513 * @arg @ref LL_ADC_RESOLUTION_10B
2514 * @arg @ref LL_ADC_RESOLUTION_8B
2515 * @arg @ref LL_ADC_RESOLUTION_6B
2516 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
2517 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2518 */
2519 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2520 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2521
2522 /**
2523 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2524 * or low in function of ADC resolution, when ADC resolution is
2525 * different of 12 bits.
2526 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2527 * Example, with a ADC resolution of 8 bits, to get the value of
2528 * analog watchdog threshold high (on 8 bits):
2529 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2530 * (LL_ADC_RESOLUTION_8B,
2531 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2532 * );
2533 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2534 * @arg @ref LL_ADC_RESOLUTION_12B
2535 * @arg @ref LL_ADC_RESOLUTION_10B
2536 * @arg @ref LL_ADC_RESOLUTION_8B
2537 * @arg @ref LL_ADC_RESOLUTION_6B
2538 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2539 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2540 */
2541 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2542 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2543
2544 /**
2545 * @brief Helper macro to get the ADC analog watchdog threshold high
2546 * or low from raw value containing both thresholds concatenated.
2547 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2548 * Example, to get analog watchdog threshold high from the register raw value:
2549 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2550 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2551 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2552 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2553 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2554 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2555 */
2556 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2557 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
2558 & LL_ADC_AWD_THRESHOLD_LOW)
2559
2560 /**
2561 * @brief Helper macro to set the ADC calibration value with both single ended
2562 * and differential modes calibration factors concatenated.
2563 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2564 * Example, to set calibration factors single ended to 0x55
2565 * and differential ended to 0x2A:
2566 * LL_ADC_SetCalibrationFactor(
2567 * ADC1,
2568 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2569 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2570 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2571 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2572 */
2573 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2574 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2575
2576 #if defined(ADC_MULTIMODE_SUPPORT)
2577 /**
2578 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2579 * or ADC slave from raw value with both ADC conversion data concatenated.
2580 * @note This macro is intended to be used when multimode transfer by DMA
2581 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2582 * In this case the transferred data need to processed with this macro
2583 * to separate the conversion data of ADC master and ADC slave.
2584 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2585 * @arg @ref LL_ADC_MULTI_MASTER
2586 * @arg @ref LL_ADC_MULTI_SLAVE
2587 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2588 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2589 */
2590 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2591 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2592 #endif /* ADC_MULTIMODE_SUPPORT */
2593
2594 #if defined(ADC_MULTIMODE_SUPPORT)
2595 /**
2596 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2597 * it has a dependence in multimode (ADC master of the corresponding
2598 * ADC common instance).
2599 * @note In case of device with multimode available and a mix of
2600 * ADC instances compliant and not compliant with multimode feature,
2601 * ADC instances not compliant with multimode feature are
2602 * considered as master instances (do not depend to
2603 * any other ADC instance).
2604 * @param __ADCx__ ADC instance
2605 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2606 */
2607 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2608 ( ( ((__ADCx__) == ADC2) \
2609 )? \
2610 (ADC1) \
2611 : \
2612 (__ADCx__) \
2613 )
2614 #endif /* ADC_MULTIMODE_SUPPORT */
2615
2616 /**
2617 * @brief Helper macro to select the ADC common instance
2618 * to which is belonging the selected ADC instance.
2619 * @note ADC common register instance can be used for:
2620 * - Set parameters common to several ADC instances
2621 * - Multimode (for devices with several ADC instances)
2622 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2623 * @param __ADCx__ ADC instance
2624 * @retval ADC common register instance
2625 */
2626 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2627 /**
2628 * @brief Helper macro to check if all ADC instances sharing the same
2629 * ADC common instance are disabled.
2630 * @note This check is required by functions with setting conditioned to
2631 * ADC state:
2632 * All ADC instances of the ADC common group must be disabled.
2633 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2634 * @note On devices with only 1 ADC common instance, parameter of this macro
2635 * is useless and can be ignored (parameter kept for compatibility
2636 * with devices featuring several ADC common instances).
2637 * @param __ADCXY_COMMON__ ADC common instance
2638 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2639 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2640 * are disabled.
2641 * Value "1" if at least one ADC instance sharing the same ADC common instance
2642 * is enabled.
2643 */
2644 #if defined(ADC2)
2645 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2646 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2647 #else
2648 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1))
2649 #endif /* ADC2 */
2650
2651 /**
2652 * @brief Helper macro to define the ADC conversion data full-scale digital
2653 * value corresponding to the selected ADC resolution.
2654 * @note ADC conversion data full-scale corresponds to voltage range
2655 * determined by analog voltage references Vref+ and Vref-
2656 * (refer to reference manual).
2657 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2658 * @arg @ref LL_ADC_RESOLUTION_12B
2659 * @arg @ref LL_ADC_RESOLUTION_10B
2660 * @arg @ref LL_ADC_RESOLUTION_8B
2661 * @arg @ref LL_ADC_RESOLUTION_6B
2662 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2663 */
2664 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2665 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2666
2667 /**
2668 * @brief Helper macro to convert the ADC conversion data from
2669 * a resolution to another resolution.
2670 * @param __DATA__ ADC conversion data to be converted
2671 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2672 * This parameter can be one of the following values:
2673 * @arg @ref LL_ADC_RESOLUTION_12B
2674 * @arg @ref LL_ADC_RESOLUTION_10B
2675 * @arg @ref LL_ADC_RESOLUTION_8B
2676 * @arg @ref LL_ADC_RESOLUTION_6B
2677 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2678 * This parameter can be one of the following values:
2679 * @arg @ref LL_ADC_RESOLUTION_12B
2680 * @arg @ref LL_ADC_RESOLUTION_10B
2681 * @arg @ref LL_ADC_RESOLUTION_8B
2682 * @arg @ref LL_ADC_RESOLUTION_6B
2683 * @retval ADC conversion data to the requested resolution
2684 */
2685 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2686 __ADC_RESOLUTION_CURRENT__,\
2687 __ADC_RESOLUTION_TARGET__) \
2688 (((__DATA__) \
2689 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2690 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2691 )
2692
2693 /**
2694 * @brief Helper macro to calculate the voltage (unit: mVolt)
2695 * corresponding to a ADC conversion data (unit: digital value).
2696 * @note Analog reference voltage (Vref+) must be either known from
2697 * user board environment or can be calculated using ADC measurement
2698 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2699 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2700 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2701 * (unit: digital value).
2702 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2703 * @arg @ref LL_ADC_RESOLUTION_12B
2704 * @arg @ref LL_ADC_RESOLUTION_10B
2705 * @arg @ref LL_ADC_RESOLUTION_8B
2706 * @arg @ref LL_ADC_RESOLUTION_6B
2707 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2708 */
2709 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2710 __ADC_DATA__,\
2711 __ADC_RESOLUTION__) \
2712 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2713 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2714 )
2715
2716 /**
2717 * @brief Helper macro to calculate the voltage (unit: mVolt)
2718 * corresponding to a ADC conversion data (unit: digital value) in
2719 * differential ended mode.
2720 * @note ADC data from ADC data register is unsigned and centered around
2721 * middle code in. Converted voltage can be positive or negative
2722 * depending on differential input voltages.
2723 * @note Analog reference voltage (Vref+) must be either known from
2724 * user board environment or can be calculated using ADC measurement
2725 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2726 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2727 * @param __ADC_DATA__ ADC conversion data (unit: digital value).
2728 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2729 * @arg @ref LL_ADC_RESOLUTION_12B
2730 * @arg @ref LL_ADC_RESOLUTION_10B
2731 * @arg @ref LL_ADC_RESOLUTION_8B
2732 * @arg @ref LL_ADC_RESOLUTION_6B
2733 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2734 */
2735 #define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2736 __ADC_DATA__,\
2737 __ADC_RESOLUTION__)\
2738 ((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\
2739 / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\
2740 - (int32_t)(__VREFANALOG_VOLTAGE__))
2741
2742 /**
2743 * @brief Helper macro to calculate analog reference voltage (Vref+)
2744 * (unit: mVolt) from ADC conversion data of internal voltage
2745 * reference VrefInt.
2746 * @note Computation is using VrefInt calibration value
2747 * stored in system memory for each device during production.
2748 * @note This voltage depends on user board environment: voltage level
2749 * connected to pin Vref+.
2750 * On devices with small package, the pin Vref+ is not present
2751 * and internally bonded to pin Vdda.
2752 * @note On this STM32 series, calibration data of internal voltage reference
2753 * VrefInt corresponds to a resolution of 12 bits,
2754 * this is the recommended ADC resolution to convert voltage of
2755 * internal voltage reference VrefInt.
2756 * Otherwise, this macro performs the processing to scale
2757 * ADC conversion data to 12 bits.
2758 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2759 * of internal voltage reference VrefInt (unit: digital value).
2760 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2761 * @arg @ref LL_ADC_RESOLUTION_12B
2762 * @arg @ref LL_ADC_RESOLUTION_10B
2763 * @arg @ref LL_ADC_RESOLUTION_8B
2764 * @arg @ref LL_ADC_RESOLUTION_6B
2765 * @retval Analog reference voltage (unit: mV)
2766 */
2767 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2768 __ADC_RESOLUTION__) \
2769 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2770 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2771 (__ADC_RESOLUTION__), \
2772 LL_ADC_RESOLUTION_12B) \
2773 )
2774
2775 /**
2776 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2777 * from ADC conversion data of internal temperature sensor.
2778 * @note Computation is using temperature sensor calibration values
2779 * stored in system memory for each device during production.
2780 * @note Calculation formula:
2781 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2782 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2783 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2784 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2785 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2786 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2787 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2788 * TEMP_DEGC_CAL1 (calibrated in factory)
2789 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2790 * TEMP_DEGC_CAL2 (calibrated in factory)
2791 * Caution: Calculation relevancy under reserve that calibration
2792 * parameters are correct (address and data).
2793 * To calculate temperature using temperature sensor
2794 * datasheet typical values (generic values less, therefore
2795 * less accurate than calibrated values),
2796 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2797 * @note As calculation input, the analog reference voltage (Vref+) must be
2798 * defined as it impacts the ADC LSB equivalent voltage.
2799 * @note Analog reference voltage (Vref+) must be either known from
2800 * user board environment or can be calculated using ADC measurement
2801 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2802 * @note On this STM32 series, calibration data of temperature sensor
2803 * corresponds to a resolution of 12 bits,
2804 * this is the recommended ADC resolution to convert voltage of
2805 * temperature sensor.
2806 * Otherwise, this macro performs the processing to scale
2807 * ADC conversion data to 12 bits.
2808 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2809 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2810 * temperature sensor (unit: digital value).
2811 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2812 * sensor voltage has been measured.
2813 * This parameter can be one of the following values:
2814 * @arg @ref LL_ADC_RESOLUTION_12B
2815 * @arg @ref LL_ADC_RESOLUTION_10B
2816 * @arg @ref LL_ADC_RESOLUTION_8B
2817 * @arg @ref LL_ADC_RESOLUTION_6B
2818 * @retval Temperature (unit: degree Celsius)
2819 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
2820 */
2821 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2822 __TEMPSENSOR_ADC_DATA__,\
2823 __ADC_RESOLUTION__)\
2824 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
2825 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2826 (__ADC_RESOLUTION__), \
2827 LL_ADC_RESOLUTION_12B) \
2828 * (__VREFANALOG_VOLTAGE__)) \
2829 / TEMPSENSOR_CAL_VREFANALOG) \
2830 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2831 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2832 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2833 ) + TEMPSENSOR_CAL1_TEMP \
2834 ) \
2835 : \
2836 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
2837 )
2838
2839 /**
2840 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2841 * from ADC conversion data of internal temperature sensor.
2842 * @note Computation is using temperature sensor typical values
2843 * (refer to device datasheet).
2844 * @note Calculation formula:
2845 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2846 * / Avg_Slope + CALx_TEMP
2847 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2848 * (unit: digital value)
2849 * Avg_Slope = temperature sensor slope
2850 * (unit: uV/Degree Celsius)
2851 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2852 * temperature CALx_TEMP (unit: mV)
2853 * Caution: Calculation relevancy under reserve the temperature sensor
2854 * of the current device has characteristics in line with
2855 * datasheet typical values.
2856 * If temperature sensor calibration values are available on
2857 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2858 * temperature calculation will be more accurate using
2859 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2860 * @note As calculation input, the analog reference voltage (Vref+) must be
2861 * defined as it impacts the ADC LSB equivalent voltage.
2862 * @note Analog reference voltage (Vref+) must be either known from
2863 * user board environment or can be calculated using ADC measurement
2864 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2865 * @note ADC measurement data must correspond to a resolution of 12 bits
2866 * (full scale digital value 4095). If not the case, the data must be
2867 * preliminarily rescaled to an equivalent resolution of 12 bits.
2868 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
2869 * (unit: uV/DegCelsius).
2870 * On STM32H7RS, refer to device datasheet parameter "Avg_Slope".
2871 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
2872 * (at temperature and Vref+ defined in parameters below) (unit: mV).
2873 * On this STM32 series, refer to datasheet parameter "V30" (corresponding
2874 * to TS_CAL1).
2875 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
2876 * (see parameter above) is corresponding (unit: mV)
2877 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
2878 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2879 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2880 * This parameter can be one of the following values:
2881 * @arg @ref LL_ADC_RESOLUTION_12B
2882 * @arg @ref LL_ADC_RESOLUTION_10B
2883 * @arg @ref LL_ADC_RESOLUTION_8B
2884 * @arg @ref LL_ADC_RESOLUTION_6B
2885 * @retval Temperature (unit: degree Celsius)
2886 */
2887 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2888 __TEMPSENSOR_TYP_CALX_V__,\
2889 __TEMPSENSOR_CALX_TEMP__,\
2890 __VREFANALOG_VOLTAGE__,\
2891 __TEMPSENSOR_ADC_DATA__,\
2892 __ADC_RESOLUTION__) \
2893 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2894 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2895 * 1000UL) \
2896 - \
2897 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2898 * 1000UL) \
2899 ) \
2900 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2901 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2902 )
2903
2904 /**
2905 * @}
2906 */
2907
2908 /**
2909 * @}
2910 */
2911
2912
2913 /* Exported functions --------------------------------------------------------*/
2914 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2915 * @{
2916 */
2917
2918 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2919 * @{
2920 */
2921 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2922 /* configuration of ADC instance, groups and multimode (if available): */
2923 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2924
2925 /**
2926 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2927 * ADC register address from ADC instance and a list of ADC registers
2928 * intended to be used (most commonly) with DMA transfer.
2929 * @note These ADC registers are data registers:
2930 * when ADC conversion data is available in ADC data registers,
2931 * ADC generates a DMA transfer request.
2932 * @note This macro is intended to be used with LL DMA driver, refer to
2933 * function "LL_DMA_ConfigAddresses()".
2934 * Example:
2935 * LL_DMA_ConfigAddresses(DMA1,
2936 * LL_DMA_CHANNEL_1,
2937 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2938 * (uint32_t)&< array or variable >,
2939 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2940 * @note For devices with several ADC: in multimode, some devices
2941 * use a different data register outside of ADC instance scope
2942 * (common data register). This macro manages this register difference,
2943 * only ADC instance has to be set as parameter.
2944 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2945 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2946 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2947 * @param ADCx ADC instance
2948 * @param Register This parameter can be one of the following values:
2949 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2950 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2951 *
2952 * (1) Available on devices with several ADC instances.
2953 * @retval ADC register address
2954 */
2955 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)2956 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
2957 {
2958 uint32_t data_reg_addr;
2959
2960 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2961 {
2962 /* Retrieve address of register DR */
2963 data_reg_addr = (uint32_t) &(ADCx->DR);
2964 }
2965 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2966 {
2967 /* Retrieve address of register CDR */
2968 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2969 }
2970
2971 return data_reg_addr;
2972 }
2973 #else
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)2974 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
2975 {
2976 /* Prevent unused argument(s) compilation warning */
2977 (void)(Register);
2978
2979 /* Retrieve address of register DR */
2980 return (uint32_t) &(ADCx->DR);
2981 }
2982 #endif /* ADC_MULTIMODE_SUPPORT */
2983
2984 /**
2985 * @}
2986 */
2987
2988 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
2989 * ADC instances
2990 * @{
2991 */
2992
2993 /**
2994 * @brief Set parameter common to several ADC: Clock source and prescaler.
2995 * @note On this STM32 series, if ADC group injected is used, some
2996 * clock ratio constraints between ADC clock and AHB clock
2997 * must be respected.
2998 * Refer to reference manual.
2999 * @note On this STM32 series, setting of this feature is conditioned to
3000 * ADC state:
3001 * All ADC instances of the ADC common group must be disabled.
3002 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3003 * ADC instance or by using helper macro helper macro
3004 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3005 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
3006 * CCR PRESC LL_ADC_SetCommonClock
3007 * @param ADCxy_COMMON ADC common instance
3008 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3009 * @param CommonClock This parameter can be one of the following values:
3010 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
3011 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
3012 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
3013 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3014 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3015 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3016 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3017 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3018 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3019 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3020 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3021 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3022 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3023 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3024 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3025 * @retval None
3026 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)3027 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
3028 {
3029 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
3030 }
3031
3032 /**
3033 * @brief Get parameter common to several ADC: Clock source and prescaler.
3034 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
3035 * CCR PRESC LL_ADC_GetCommonClock
3036 * @param ADCxy_COMMON ADC common instance
3037 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3038 * @retval Returned value can be one of the following values:
3039 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
3040 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
3041 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
3042 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3043 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3044 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3045 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3046 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3047 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3048 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3049 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3050 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3051 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3052 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3053 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3054 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)3055 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
3056 {
3057 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
3058 }
3059
3060 /**
3061 * @brief Set parameter common to several ADC: measurement path to
3062 * internal channels (VrefInt, temperature sensor, ...).
3063 * Configure all paths (overwrite current configuration).
3064 * @note One or several values can be selected.
3065 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3066 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3067 * The values not selected are removed from configuration.
3068 * @note Stabilization time of measurement path to internal channel:
3069 * After enabling internal paths, before starting ADC conversion,
3070 * a delay is required for internal voltage reference and
3071 * temperature sensor stabilization time.
3072 * Refer to device datasheet.
3073 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3074 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3075 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3076 * @note ADC internal channel sampling time constraint:
3077 * For ADC conversion of internal channels,
3078 * a sampling time minimum value is required.
3079 * Refer to device datasheet.
3080 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
3081 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
3082 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
3083 * @param ADCxy_COMMON ADC common instance
3084 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3085 * @param PathInternal This parameter can be a combination of the following values:
3086 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3087 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3088 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3089 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3090 * @retval None
3091 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3092 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3093 {
3094 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
3095 }
3096
3097 /**
3098 * @brief Set parameter common to several ADC: measurement path to
3099 * internal channels (VrefInt, temperature sensor, ...).
3100 * Add paths to the current configuration.
3101 * @note One or several values can be selected.
3102 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3103 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3104 * @note Stabilization time of measurement path to internal channel:
3105 * After enabling internal paths, before starting ADC conversion,
3106 * a delay is required for internal voltage reference and
3107 * temperature sensor stabilization time.
3108 * Refer to device datasheet.
3109 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3110 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3111 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3112 * @note ADC internal channel sampling time constraint:
3113 * For ADC conversion of internal channels,
3114 * a sampling time minimum value is required.
3115 * Refer to device datasheet.
3116 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
3117 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
3118 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
3119 * @param ADCxy_COMMON ADC common instance
3120 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3121 * @param PathInternal This parameter can be a combination of the following values:
3122 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3123 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3124 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3125 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3126 * @retval None
3127 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3128 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3129 {
3130 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
3131 }
3132
3133 /**
3134 * @brief Set parameter common to several ADC: measurement path to
3135 * internal channels (VrefInt, temperature sensor, ...).
3136 * Remove paths to the current configuration.
3137 * @note One or several values can be selected.
3138 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3139 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3140 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
3141 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
3142 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
3143 * @param ADCxy_COMMON ADC common instance
3144 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3145 * @param PathInternal This parameter can be a combination of the following values:
3146 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3147 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3148 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3149 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3150 * @retval None
3151 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3152 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3153 {
3154 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
3155 }
3156
3157 /**
3158 * @brief Get parameter common to several ADC: measurement path to internal
3159 * channels (VrefInt, temperature sensor, ...).
3160 * @note One or several values can be selected.
3161 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3162 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3163 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
3164 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
3165 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
3166 * @param ADCxy_COMMON ADC common instance
3167 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3168 * @retval Returned value can be a combination of the following values:
3169 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3170 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3171 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3172 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3173 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)3174 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
3175 {
3176 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
3177 }
3178
3179 /**
3180 * @}
3181 */
3182
3183 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
3184 * @{
3185 */
3186
3187 /**
3188 * @brief Set parameter on ADC instance scope: measurement path to
3189 * internal channels (Vcore, Vcpu...).
3190 * Configure all paths (overwrite current configuration).
3191 * @note One or several values can be selected.
3192 * Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
3193 * LL_ADC_PATH_INTERNAL_...)
3194 * The values not selected are removed from configuration.
3195 * @note Stabilization time of measurement path to internal channel:
3196 * After enabling internal paths, before starting ADC conversion,
3197 * a delay may be required required for analog stabilization.
3198 * Refer to device datasheet.
3199 * @note ADC internal channel sampling time constraint:
3200 * For ADC conversion of internal channels,
3201 * a sampling time minimum value is required.
3202 * Refer to device datasheet.
3203 * @rmtoll OR OP0 LL_ADC_SetPathInternalCh
3204 * @param ADCx ADC instance
3205 * @param PathInternal This parameter can be a combination of the following values:
3206 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3207 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
3208 * @retval None
3209 */
LL_ADC_SetPathInternalCh(ADC_TypeDef * ADCx,uint32_t PathInternal)3210 __STATIC_INLINE void LL_ADC_SetPathInternalCh(ADC_TypeDef *ADCx, uint32_t PathInternal)
3211 {
3212 MODIFY_REG(ADCx->OR, ADC_OR_OP0, PathInternal);
3213 }
3214
3215 /**
3216 * @brief Set parameter on ADC instance scope: measurement path to
3217 * internal channels (Vcore, Vcpu...).
3218 * Add paths to the current configuration.
3219 * @note One or several values can be selected.
3220 * Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
3221 * LL_ADC_PATH_INTERNAL_...)
3222 * The values not selected are removed from configuration.
3223 * @note Stabilization time of measurement path to internal channel:
3224 * After enabling internal paths, before starting ADC conversion,
3225 * a delay may be required required for analog stabilization.
3226 * Refer to device datasheet.
3227 * @note ADC internal channel sampling time constraint:
3228 * For ADC conversion of internal channels,
3229 * a sampling time minimum value is required.
3230 * Refer to device datasheet.
3231 * @rmtoll OR OP0 LL_ADC_SetPathInternalChAdd
3232 * @param ADCx ADC instance
3233 * @param PathInternal This parameter can be a combination of the following values:
3234 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3235 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
3236 * @retval None
3237 */
LL_ADC_SetPathInternalChAdd(ADC_TypeDef * ADCx,uint32_t PathInternal)3238 __STATIC_INLINE void LL_ADC_SetPathInternalChAdd(ADC_TypeDef *ADCx, uint32_t PathInternal)
3239 {
3240 SET_BIT(ADCx->OR, PathInternal);
3241 }
3242
3243 /**
3244 * @brief Set parameter on ADC instance scope: measurement path to
3245 * internal channels (Vcore, Vcpu...).
3246 * Remove paths to the current configuration.
3247 * @note One or several values can be selected.
3248 * Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
3249 * LL_ADC_PATH_INTERNAL_...)
3250 * The values not selected are removed from configuration.
3251 * @note Stabilization time of measurement path to internal channel:
3252 * After enabling internal paths, before starting ADC conversion,
3253 * a delay may be required required for analog stabilization.
3254 * Refer to device datasheet.
3255 * @note ADC internal channel sampling time constraint:
3256 * For ADC conversion of internal channels,
3257 * a sampling time minimum value is required.
3258 * Refer to device datasheet.
3259 * @rmtoll OR OP0 LL_ADC_SetPathInternalChRem
3260 * @param ADCx ADC instance
3261 * @param PathInternal This parameter can be a combination of the following values:
3262 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3263 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
3264 * @retval None
3265 */
LL_ADC_SetPathInternalChRem(ADC_TypeDef * ADCx,uint32_t PathInternal)3266 __STATIC_INLINE void LL_ADC_SetPathInternalChRem(ADC_TypeDef *ADCx, uint32_t PathInternal)
3267 {
3268 CLEAR_BIT(ADCx->OR, PathInternal);
3269 }
3270
3271 /**
3272 * @brief Get parameter on ADC instance scope: measurement path to
3273 * internal channels (Vcore, Vcpu...).
3274 * @note One or several values can be selected.
3275 * Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
3276 * LL_ADC_PATH_INTERNAL_...)
3277 * @rmtoll OR OP0 LL_ADC_GetPathInternalCh
3278 * @param ADCx ADC instance
3279 * @retval Returned value can be one of the following values:
3280 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3281 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
3282 */
LL_ADC_GetPathInternalCh(const ADC_TypeDef * ADCx)3283 __STATIC_INLINE uint32_t LL_ADC_GetPathInternalCh(const ADC_TypeDef *ADCx)
3284 {
3285 return (uint32_t)(READ_BIT(ADCx->OR, ADC_OR_OP0));
3286 }
3287
3288 /**
3289 * @brief Set ADC calibration factor in the mode single-ended
3290 * or differential (for devices with differential mode available).
3291 * @note This function is intended to set calibration parameters
3292 * without having to perform a new calibration using
3293 * @ref LL_ADC_StartCalibration().
3294 * @note For devices with differential mode available:
3295 * Calibration of offset is specific to each of
3296 * single-ended and differential modes
3297 * (calibration factor must be specified for each of these
3298 * differential modes, if used afterwards and if the application
3299 * requires their calibration).
3300 * @note In case of setting calibration factors of both modes single ended
3301 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
3302 * both calibration factors must be concatenated.
3303 * To perform this processing, use helper macro
3304 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
3305 * @note On this STM32 series, setting of this feature is conditioned to
3306 * ADC state:
3307 * ADC must be enabled, without calibration on going, without conversion
3308 * on going on group regular.
3309 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
3310 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
3311 * @param ADCx ADC instance
3312 * @param SingleDiff This parameter can be one of the following values:
3313 * @arg @ref LL_ADC_SINGLE_ENDED
3314 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3315 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3316 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
3317 * @retval None
3318 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)3319 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
3320 {
3321 MODIFY_REG(ADCx->CALFACT,
3322 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
3323 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK)
3324 >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)
3325 & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
3326 }
3327
3328 /**
3329 * @brief Get ADC calibration factor in the mode single-ended
3330 * or differential (for devices with differential mode available).
3331 * @note Calibration factors are set by hardware after performing
3332 * a calibration run using function @ref LL_ADC_StartCalibration().
3333 * @note For devices with differential mode available:
3334 * Calibration of offset is specific to each of
3335 * single-ended and differential modes
3336 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
3337 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
3338 * @param ADCx ADC instance
3339 * @param SingleDiff This parameter can be one of the following values:
3340 * @arg @ref LL_ADC_SINGLE_ENDED
3341 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3342 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
3343 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx,uint32_t SingleDiff)3344 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
3345 {
3346 /* Retrieve bits with position in register depending on parameter */
3347 /* "SingleDiff". */
3348 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
3349 /* containing other bits reserved for other purpose. */
3350 return (uint32_t)(READ_BIT(ADCx->CALFACT,
3351 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
3352 >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
3353 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
3354 }
3355
3356 /**
3357 * @brief Set ADC resolution.
3358 * Refer to reference manual for alignments formats
3359 * dependencies to ADC resolutions.
3360 * @note On this STM32 series, setting of this feature is conditioned to
3361 * ADC state:
3362 * ADC must be disabled or enabled without conversion on going
3363 * on either groups regular or injected.
3364 * @rmtoll CFGR RES LL_ADC_SetResolution
3365 * @param ADCx ADC instance
3366 * @param Resolution This parameter can be one of the following values:
3367 * @arg @ref LL_ADC_RESOLUTION_12B
3368 * @arg @ref LL_ADC_RESOLUTION_10B
3369 * @arg @ref LL_ADC_RESOLUTION_8B
3370 * @arg @ref LL_ADC_RESOLUTION_6B
3371 * @retval None
3372 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)3373 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3374 {
3375 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3376 }
3377
3378 /**
3379 * @brief Get ADC resolution.
3380 * Refer to reference manual for alignments formats
3381 * dependencies to ADC resolutions.
3382 * @rmtoll CFGR RES LL_ADC_GetResolution
3383 * @param ADCx ADC instance
3384 * @retval Returned value can be one of the following values:
3385 * @arg @ref LL_ADC_RESOLUTION_12B
3386 * @arg @ref LL_ADC_RESOLUTION_10B
3387 * @arg @ref LL_ADC_RESOLUTION_8B
3388 * @arg @ref LL_ADC_RESOLUTION_6B
3389 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)3390 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3391 {
3392 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3393 }
3394
3395 /**
3396 * @brief Set ADC conversion data alignment.
3397 * @note Refer to reference manual for alignments formats
3398 * dependencies to ADC resolutions.
3399 * @note On this STM32 series, setting of this feature is conditioned to
3400 * ADC state:
3401 * ADC must be disabled or enabled without conversion on going
3402 * on either groups regular or injected.
3403 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
3404 * @param ADCx ADC instance
3405 * @param DataAlignment This parameter can be one of the following values:
3406 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3407 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3408 * @retval None
3409 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)3410 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
3411 {
3412 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
3413 }
3414
3415 /**
3416 * @brief Get ADC conversion data alignment.
3417 * @note Refer to reference manual for alignments formats
3418 * dependencies to ADC resolutions.
3419 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
3420 * @param ADCx ADC instance
3421 * @retval Returned value can be one of the following values:
3422 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3423 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3424 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)3425 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
3426 {
3427 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
3428 }
3429
3430 /**
3431 * @brief Set ADC low power mode.
3432 * @note Description of ADC low power modes:
3433 * - ADC low power mode "auto wait": Dynamic low power mode,
3434 * ADC conversions occurrences are limited to the minimum necessary
3435 * in order to reduce power consumption.
3436 * New ADC conversion starts only when the previous
3437 * unitary conversion data (for ADC group regular)
3438 * or previous sequence conversions data (for ADC group injected)
3439 * has been retrieved by user software.
3440 * In the meantime, ADC remains idle: does not performs any
3441 * other conversion.
3442 * This mode allows to automatically adapt the ADC conversions
3443 * triggers to the speed of the software that reads the data.
3444 * Moreover, this avoids risk of overrun for low frequency
3445 * applications.
3446 * How to use this low power mode:
3447 * - It is not recommended to use with interruption or DMA
3448 * since these modes have to clear immediately the EOC flag
3449 * (by CPU to free the IRQ pending event or by DMA).
3450 * Auto wait will work but fort a very short time, discarding
3451 * its intended benefit (except specific case of high load of CPU
3452 * or DMA transfers which can justify usage of auto wait).
3453 * - Do use with polling: 1. Start conversion,
3454 * 2. Later on, when conversion data is needed: poll for end of
3455 * conversion to ensure that conversion is completed and
3456 * retrieve ADC conversion data. This will trig another
3457 * ADC conversion start.
3458 * @note With ADC low power mode "auto wait", the ADC conversion data read
3459 * is corresponding to previous ADC conversion start, independently
3460 * of delay during which ADC was idle.
3461 * Therefore, the ADC conversion data may be outdated: does not
3462 * correspond to the current voltage level on the selected
3463 * ADC channel.
3464 * @note On this STM32 series, setting of this feature is conditioned to
3465 * ADC state:
3466 * ADC must be disabled or enabled without conversion on going
3467 * on either groups regular or injected.
3468 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3469 * @param ADCx ADC instance
3470 * @param LowPowerMode This parameter can be one of the following values:
3471 * @arg @ref LL_ADC_LP_MODE_NONE
3472 * @arg @ref LL_ADC_LP_AUTOWAIT
3473 * @retval None
3474 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)3475 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3476 {
3477 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3478 }
3479
3480 /**
3481 * @brief Get ADC low power mode:
3482 * @note Description of ADC low power modes:
3483 * - ADC low power mode "auto wait": Dynamic low power mode,
3484 * ADC conversions occurrences are limited to the minimum necessary
3485 * in order to reduce power consumption.
3486 * New ADC conversion starts only when the previous
3487 * unitary conversion data (for ADC group regular)
3488 * or previous sequence conversions data (for ADC group injected)
3489 * has been retrieved by user software.
3490 * In the meantime, ADC remains idle: does not performs any
3491 * other conversion.
3492 * This mode allows to automatically adapt the ADC conversions
3493 * triggers to the speed of the software that reads the data.
3494 * Moreover, this avoids risk of overrun for low frequency
3495 * applications.
3496 * How to use this low power mode:
3497 * - It is not recommended to use with interruption or DMA
3498 * since these modes have to clear immediately the EOC flag
3499 * (by CPU to free the IRQ pending event or by DMA).
3500 * Auto wait will work but fort a very short time, discarding
3501 * its intended benefit (except specific case of high load of CPU
3502 * or DMA transfers which can justify usage of auto wait).
3503 * - Do use with polling: 1. Start conversion,
3504 * 2. Later on, when conversion data is needed: poll for end of
3505 * conversion to ensure that conversion is completed and
3506 * retrieve ADC conversion data. This will trig another
3507 * ADC conversion start.
3508 * @note With ADC low power mode "auto wait", the ADC conversion data read
3509 * is corresponding to previous ADC conversion start, independently
3510 * of delay during which ADC was idle.
3511 * Therefore, the ADC conversion data may be outdated: does not
3512 * correspond to the current voltage level on the selected
3513 * ADC channel.
3514 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3515 * @param ADCx ADC instance
3516 * @retval Returned value can be one of the following values:
3517 * @arg @ref LL_ADC_LP_MODE_NONE
3518 * @arg @ref LL_ADC_LP_AUTOWAIT
3519 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)3520 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
3521 {
3522 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3523 }
3524
3525 /**
3526 * @brief Set ADC selected offset instance 1, 2, 3 or 4.
3527 * @note This function set the 2 items of offset configuration:
3528 * - ADC channel to which the offset programmed will be applied
3529 * (independently of channel mapped on ADC group regular
3530 * or group injected)
3531 * - Offset level (offset to be subtracted from the raw
3532 * converted data).
3533 * @note Caution: Offset format is dependent to ADC resolution:
3534 * offset has to be left-aligned on bit 11, the LSB (right bits)
3535 * are set to 0.
3536 * @note This function enables the offset, by default. It can be forced
3537 * to disable state using function LL_ADC_SetOffsetState().
3538 * @note If a channel is mapped on several offsets numbers, only the offset
3539 * with the lowest value is considered for the subtraction.
3540 * @note On this STM32 series, setting of this feature is conditioned to
3541 * ADC state:
3542 * ADC must be disabled or enabled without conversion on going
3543 * on either groups regular or injected.
3544 * @note On STM32H7RS, some fast channels are available: fast analog inputs
3545 * coming from GPIO pads (ADC_IN0..5).
3546 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3547 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3548 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3549 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3550 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3551 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3552 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3553 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3554 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3555 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3556 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3557 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3558 * @param ADCx ADC instance
3559 * @param Offsety This parameter can be one of the following values:
3560 * @arg @ref LL_ADC_OFFSET_1
3561 * @arg @ref LL_ADC_OFFSET_2
3562 * @arg @ref LL_ADC_OFFSET_3
3563 * @arg @ref LL_ADC_OFFSET_4
3564 * @param Channel This parameter can be one of the following values:
3565 * @arg @ref LL_ADC_CHANNEL_0 (3)
3566 * @arg @ref LL_ADC_CHANNEL_1 (3)
3567 * @arg @ref LL_ADC_CHANNEL_2 (3)
3568 * @arg @ref LL_ADC_CHANNEL_3 (3)
3569 * @arg @ref LL_ADC_CHANNEL_4 (3)
3570 * @arg @ref LL_ADC_CHANNEL_5 (3)
3571 * @arg @ref LL_ADC_CHANNEL_6
3572 * @arg @ref LL_ADC_CHANNEL_7
3573 * @arg @ref LL_ADC_CHANNEL_8
3574 * @arg @ref LL_ADC_CHANNEL_9
3575 * @arg @ref LL_ADC_CHANNEL_10
3576 * @arg @ref LL_ADC_CHANNEL_11
3577 * @arg @ref LL_ADC_CHANNEL_12
3578 * @arg @ref LL_ADC_CHANNEL_13
3579 * @arg @ref LL_ADC_CHANNEL_14
3580 * @arg @ref LL_ADC_CHANNEL_15
3581 * @arg @ref LL_ADC_CHANNEL_16
3582 * @arg @ref LL_ADC_CHANNEL_17
3583 * @arg @ref LL_ADC_CHANNEL_18
3584 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3585 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3586 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3587 *
3588 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
3589 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
3590 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
3591 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3592 * @retval None
3593 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)3594 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3595 {
3596 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3597
3598 MODIFY_REG(*preg,
3599 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3600 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3601 }
3602
3603 /**
3604 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3605 * Channel to which the offset programmed will be applied
3606 * (independently of channel mapped on ADC group regular
3607 * or group injected)
3608 * @note Usage of the returned channel number:
3609 * - To reinject this channel into another function LL_ADC_xxx:
3610 * the returned channel number is only partly formatted on definition
3611 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3612 * with parts of literals LL_ADC_CHANNEL_x or using
3613 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3614 * Then the selected literal LL_ADC_CHANNEL_x can be used
3615 * as parameter for another function.
3616 * - To get the channel number in decimal format:
3617 * process the returned value with the helper macro
3618 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3619 * @note On STM32H7RS, some fast channels are available: fast analog inputs
3620 * coming from GPIO pads (ADC_IN0..5).
3621 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3622 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3623 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3624 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3625 * @param ADCx ADC instance
3626 * @param Offsety This parameter can be one of the following values:
3627 * @arg @ref LL_ADC_OFFSET_1
3628 * @arg @ref LL_ADC_OFFSET_2
3629 * @arg @ref LL_ADC_OFFSET_3
3630 * @arg @ref LL_ADC_OFFSET_4
3631 * @retval Returned value can be one of the following values:
3632 * @arg @ref LL_ADC_CHANNEL_0 (2)
3633 * @arg @ref LL_ADC_CHANNEL_1 (2)
3634 * @arg @ref LL_ADC_CHANNEL_2 (2)
3635 * @arg @ref LL_ADC_CHANNEL_3 (2)
3636 * @arg @ref LL_ADC_CHANNEL_4 (2)
3637 * @arg @ref LL_ADC_CHANNEL_5 (2)
3638 * @arg @ref LL_ADC_CHANNEL_6
3639 * @arg @ref LL_ADC_CHANNEL_7
3640 * @arg @ref LL_ADC_CHANNEL_8
3641 * @arg @ref LL_ADC_CHANNEL_9
3642 * @arg @ref LL_ADC_CHANNEL_10
3643 * @arg @ref LL_ADC_CHANNEL_11
3644 * @arg @ref LL_ADC_CHANNEL_12
3645 * @arg @ref LL_ADC_CHANNEL_13
3646 * @arg @ref LL_ADC_CHANNEL_14
3647 * @arg @ref LL_ADC_CHANNEL_15
3648 * @arg @ref LL_ADC_CHANNEL_16
3649 * @arg @ref LL_ADC_CHANNEL_17
3650 * @arg @ref LL_ADC_CHANNEL_18
3651 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
3652 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3)
3653 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3)
3654 *
3655 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
3656 * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
3657 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
3658 * (3) For ADC channel read back from ADC register,
3659 * comparison with internal channel parameter to be done
3660 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3661 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)3662 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3663 {
3664 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3665
3666 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3667 }
3668
3669 /**
3670 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3671 * Offset level (offset to be subtracted from the raw
3672 * converted data).
3673 * @note Caution: Offset format is dependent to ADC resolution:
3674 * offset has to be left-aligned on bit 11, the LSB (right bits)
3675 * are set to 0.
3676 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3677 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3678 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3679 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3680 * @param ADCx ADC instance
3681 * @param Offsety This parameter can be one of the following values:
3682 * @arg @ref LL_ADC_OFFSET_1
3683 * @arg @ref LL_ADC_OFFSET_2
3684 * @arg @ref LL_ADC_OFFSET_3
3685 * @arg @ref LL_ADC_OFFSET_4
3686 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3687 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)3688 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3689 {
3690 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3691
3692 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3693 }
3694
3695 /**
3696 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3697 * force offset state disable or enable
3698 * without modifying offset channel or offset value.
3699 * @note This function should be needed only in case of offset to be
3700 * enabled-disabled dynamically, and should not be needed in other cases:
3701 * function LL_ADC_SetOffset() automatically enables the offset.
3702 * @note On this STM32 series, setting of this feature is conditioned to
3703 * ADC state:
3704 * ADC must be disabled or enabled without conversion on going
3705 * on either groups regular or injected.
3706 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3707 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3708 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3709 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3710 * @param ADCx ADC instance
3711 * @param Offsety This parameter can be one of the following values:
3712 * @arg @ref LL_ADC_OFFSET_1
3713 * @arg @ref LL_ADC_OFFSET_2
3714 * @arg @ref LL_ADC_OFFSET_3
3715 * @arg @ref LL_ADC_OFFSET_4
3716 * @param OffsetState This parameter can be one of the following values:
3717 * @arg @ref LL_ADC_OFFSET_DISABLE
3718 * @arg @ref LL_ADC_OFFSET_ENABLE
3719 * @retval None
3720 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3721 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3722 {
3723 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3724
3725 MODIFY_REG(*preg,
3726 ADC_OFR1_OFFSET1_EN,
3727 OffsetState);
3728 }
3729
3730 /**
3731 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3732 * offset state disabled or enabled.
3733 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3734 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3735 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3736 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3737 * @param ADCx ADC instance
3738 * @param Offsety This parameter can be one of the following values:
3739 * @arg @ref LL_ADC_OFFSET_1
3740 * @arg @ref LL_ADC_OFFSET_2
3741 * @arg @ref LL_ADC_OFFSET_3
3742 * @arg @ref LL_ADC_OFFSET_4
3743 * @retval Returned value can be one of the following values:
3744 * @arg @ref LL_ADC_OFFSET_DISABLE
3745 * @arg @ref LL_ADC_OFFSET_ENABLE
3746 */
LL_ADC_GetOffsetState(const ADC_TypeDef * ADCx,uint32_t Offsety)3747 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
3748 {
3749 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3750
3751 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3752 }
3753
3754 /**
3755 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3756 * choose offset sign.
3757 * @note On this STM32 series, setting of this feature is conditioned to
3758 * ADC state:
3759 * ADC must be disabled or enabled without conversion on going
3760 * on either groups regular or injected.
3761 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
3762 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
3763 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
3764 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
3765 * @param ADCx ADC instance
3766 * @param Offsety This parameter can be one of the following values:
3767 * @arg @ref LL_ADC_OFFSET_1
3768 * @arg @ref LL_ADC_OFFSET_2
3769 * @arg @ref LL_ADC_OFFSET_3
3770 * @arg @ref LL_ADC_OFFSET_4
3771 * @param OffsetSign This parameter can be one of the following values:
3772 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3773 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3774 * @retval None
3775 */
LL_ADC_SetOffsetSign(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSign)3776 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3777 {
3778 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3779
3780 MODIFY_REG(*preg,
3781 ADC_OFR1_OFFSETPOS,
3782 OffsetSign);
3783 }
3784
3785 /**
3786 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3787 * offset sign if positive or negative.
3788 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
3789 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
3790 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
3791 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
3792 * @param ADCx ADC instance
3793 * @param Offsety This parameter can be one of the following values:
3794 * @arg @ref LL_ADC_OFFSET_1
3795 * @arg @ref LL_ADC_OFFSET_2
3796 * @arg @ref LL_ADC_OFFSET_3
3797 * @arg @ref LL_ADC_OFFSET_4
3798 * @retval Returned value can be one of the following values:
3799 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3800 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3801 */
LL_ADC_GetOffsetSign(const ADC_TypeDef * ADCx,uint32_t Offsety)3802 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
3803 {
3804 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3805
3806 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
3807 }
3808
3809 /**
3810 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3811 * choose offset saturation mode.
3812 * @note On this STM32 series, setting of this feature is conditioned to
3813 * ADC state:
3814 * ADC must be disabled or enabled without conversion on going
3815 * on either groups regular or injected.
3816 * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
3817 * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
3818 * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
3819 * OFR4 SATEN LL_ADC_SetOffsetSaturation
3820 * @param ADCx ADC instance
3821 * @param Offsety This parameter can be one of the following values:
3822 * @arg @ref LL_ADC_OFFSET_1
3823 * @arg @ref LL_ADC_OFFSET_2
3824 * @arg @ref LL_ADC_OFFSET_3
3825 * @arg @ref LL_ADC_OFFSET_4
3826 * @param OffsetSaturation This parameter can be one of the following values:
3827 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3828 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3829 * @retval None
3830 */
LL_ADC_SetOffsetSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSaturation)3831 __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
3832 {
3833 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3834
3835 MODIFY_REG(*preg,
3836 ADC_OFR1_SATEN,
3837 OffsetSaturation);
3838 }
3839
3840 /**
3841 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3842 * offset saturation if enabled or disabled.
3843 * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
3844 * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
3845 * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
3846 * OFR4 SATEN LL_ADC_GetOffsetSaturation
3847 * @param ADCx ADC instance
3848 * @param Offsety This parameter can be one of the following values:
3849 * @arg @ref LL_ADC_OFFSET_1
3850 * @arg @ref LL_ADC_OFFSET_2
3851 * @arg @ref LL_ADC_OFFSET_3
3852 * @arg @ref LL_ADC_OFFSET_4
3853 * @retval Returned value can be one of the following values:
3854 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3855 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3856 */
LL_ADC_GetOffsetSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)3857 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3858 {
3859 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3860
3861 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
3862 }
3863
3864 #if defined(ADC_SMPR1_SMPPLUS)
3865 /**
3866 * @brief Set ADC sampling time common configuration impacting
3867 * settings of sampling time channel wise.
3868 * @note On this STM32 series, setting of this feature is conditioned to
3869 * ADC state:
3870 * ADC must be disabled or enabled without conversion on going
3871 * on either groups regular or injected.
3872 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3873 * @param ADCx ADC instance
3874 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3875 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3876 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3877 * @retval None
3878 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)3879 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3880 {
3881 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3882 }
3883
3884 /**
3885 * @brief Get ADC sampling time common configuration impacting
3886 * settings of sampling time channel wise.
3887 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3888 * @param ADCx ADC instance
3889 * @retval Returned value can be one of the following values:
3890 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3891 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3892 */
LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef * ADCx)3893 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx)
3894 {
3895 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3896 }
3897 #endif /* ADC_SMPR1_SMPPLUS */
3898
3899 /**
3900 * @}
3901 */
3902
3903 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3904 * @{
3905 */
3906
3907 /**
3908 * @brief Set ADC group regular conversion trigger source:
3909 * internal (SW start) or from external peripheral (timer event,
3910 * external interrupt line).
3911 * @note On this STM32 series, setting trigger source to external trigger
3912 * also set trigger polarity to rising edge
3913 * (default setting for compatibility with some ADC on other
3914 * STM32 series having this setting set by HW default value).
3915 * In case of need to modify trigger edge, use
3916 * function @ref LL_ADC_REG_SetTriggerEdge().
3917 * @note Availability of parameters of trigger sources from timer
3918 * depends on timers availability on the selected device.
3919 * @note On this STM32 series, setting of this feature is conditioned to
3920 * ADC state:
3921 * ADC must be disabled or enabled without conversion on going
3922 * on group regular.
3923 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3924 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3925 * @param ADCx ADC instance
3926 * @param TriggerSource This parameter can be one of the following values:
3927 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3928 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3929 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3930 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3931 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3932 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3933 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3934 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3935 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM12_TRGO
3936 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
3937 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3938 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3939 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3940 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3941 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3942 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3943 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3944 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
3945 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
3946 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
3947 * @retval None
3948 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3949 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3950 {
3951 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3952 }
3953
3954 /**
3955 * @brief Get ADC group regular conversion trigger source:
3956 * internal (SW start) or from external peripheral (timer event,
3957 * external interrupt line).
3958 * @note To determine whether group regular trigger source is
3959 * internal (SW start) or external, without detail
3960 * of which peripheral is selected as external trigger,
3961 * (equivalent to
3962 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3963 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3964 * @note Availability of parameters of trigger sources from timer
3965 * depends on timers availability on the selected device.
3966 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3967 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3968 * @param ADCx ADC instance
3969 * @retval Returned value can be one of the following values:
3970 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3971 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3972 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3973 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3974 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3975 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3976 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3977 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3978 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM12_TRGO
3979 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
3980 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3981 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3982 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3983 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3984 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3985 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3986 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3987 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
3988 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
3989 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
3990 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)3991 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
3992 {
3993 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3994
3995 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3996 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3997 uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3998
3999 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
4000 /* to match with triggers literals definition. */
4001 return ((trigger_source
4002 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL)
4003 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN)
4004 );
4005 }
4006
4007 /**
4008 * @brief Get ADC group regular conversion trigger source internal (SW start)
4009 * or external.
4010 * @note In case of group regular trigger source set to external trigger,
4011 * to determine which peripheral is selected as external trigger,
4012 * use function @ref LL_ADC_REG_GetTriggerSource().
4013 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
4014 * @param ADCx ADC instance
4015 * @retval Value "0" if trigger source external trigger
4016 * Value "1" if trigger source SW start.
4017 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4018 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4019 {
4020 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
4021 }
4022
4023 /**
4024 * @brief Set ADC group regular conversion trigger polarity.
4025 * @note Applicable only for trigger source set to external trigger.
4026 * @note On this STM32 series, setting of this feature is conditioned to
4027 * ADC state:
4028 * ADC must be disabled or enabled without conversion on going
4029 * on group regular.
4030 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
4031 * @param ADCx ADC instance
4032 * @param ExternalTriggerEdge This parameter can be one of the following values:
4033 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4034 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4035 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4036 * @retval None
4037 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4038 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4039 {
4040 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
4041 }
4042
4043 /**
4044 * @brief Get ADC group regular conversion trigger polarity.
4045 * @note Applicable only for trigger source set to external trigger.
4046 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
4047 * @param ADCx ADC instance
4048 * @retval Returned value can be one of the following values:
4049 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4050 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4051 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4052 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)4053 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
4054 {
4055 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
4056 }
4057
4058 /**
4059 * @brief Set ADC sampling mode.
4060 * @note This function set the ADC conversion sampling mode
4061 * @note This mode applies to regular group only.
4062 * @note Set sampling mode is applied to all conversion of regular group.
4063 * @note On this STM32 series, setting of this feature is conditioned to
4064 * ADC state:
4065 * ADC must be disabled or enabled without conversion on going
4066 * on group regular.
4067 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
4068 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
4069 * @param ADCx ADC instance
4070 * @param SamplingMode This parameter can be one of the following values:
4071 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4072 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4073 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4074 * @retval None
4075 */
LL_ADC_REG_SetSamplingMode(ADC_TypeDef * ADCx,uint32_t SamplingMode)4076 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
4077 {
4078 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
4079 }
4080
4081 /**
4082 * @brief Get the ADC sampling mode
4083 * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
4084 * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
4085 * @param ADCx ADC instance
4086 * @retval Returned value can be one of the following values:
4087 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4088 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4089 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4090 */
LL_ADC_REG_GetSamplingMode(const ADC_TypeDef * ADCx)4091 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
4092 {
4093 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
4094 }
4095
4096 /**
4097 * @brief Set ADC group regular sequencer length and scan direction.
4098 * @note Description of ADC group regular sequencer features:
4099 * - For devices with sequencer fully configurable
4100 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4101 * sequencer length and each rank affectation to a channel
4102 * are configurable.
4103 * This function performs configuration of:
4104 * - Sequence length: Number of ranks in the scan sequence.
4105 * - Sequence direction: Unless specified in parameters, sequencer
4106 * scan direction is forward (from rank 1 to rank n).
4107 * Sequencer ranks are selected using
4108 * function "LL_ADC_REG_SetSequencerRanks()".
4109 * - For devices with sequencer not fully configurable
4110 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4111 * sequencer length and each rank affectation to a channel
4112 * are defined by channel number.
4113 * This function performs configuration of:
4114 * - Sequence length: Number of ranks in the scan sequence is
4115 * defined by number of channels set in the sequence,
4116 * rank of each channel is fixed by channel HW number.
4117 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4118 * - Sequence direction: Unless specified in parameters, sequencer
4119 * scan direction is forward (from lowest channel number to
4120 * highest channel number).
4121 * Sequencer ranks are selected using
4122 * function "LL_ADC_REG_SetSequencerChannels()".
4123 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4124 * ADC conversion on only 1 channel.
4125 * @note On this STM32 series, setting of this feature is conditioned to
4126 * ADC state:
4127 * ADC must be disabled or enabled without conversion on going
4128 * on group regular.
4129 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
4130 * @param ADCx ADC instance
4131 * @param SequencerNbRanks This parameter can be one of the following values:
4132 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4133 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4134 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4135 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4136 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4137 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4138 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4139 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4140 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4141 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4142 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4143 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4144 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4145 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4146 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4147 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4148 * @retval None
4149 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4150 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4151 {
4152 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4153 }
4154
4155 /**
4156 * @brief Get ADC group regular sequencer length and scan direction.
4157 * @note Description of ADC group regular sequencer features:
4158 * - For devices with sequencer fully configurable
4159 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4160 * sequencer length and each rank affectation to a channel
4161 * are configurable.
4162 * This function retrieves:
4163 * - Sequence length: Number of ranks in the scan sequence.
4164 * - Sequence direction: Unless specified in parameters, sequencer
4165 * scan direction is forward (from rank 1 to rank n).
4166 * Sequencer ranks are selected using
4167 * function "LL_ADC_REG_SetSequencerRanks()".
4168 * - For devices with sequencer not fully configurable
4169 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4170 * sequencer length and each rank affectation to a channel
4171 * are defined by channel number.
4172 * This function retrieves:
4173 * - Sequence length: Number of ranks in the scan sequence is
4174 * defined by number of channels set in the sequence,
4175 * rank of each channel is fixed by channel HW number.
4176 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4177 * - Sequence direction: Unless specified in parameters, sequencer
4178 * scan direction is forward (from lowest channel number to
4179 * highest channel number).
4180 * Sequencer ranks are selected using
4181 * function "LL_ADC_REG_SetSequencerChannels()".
4182 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4183 * ADC conversion on only 1 channel.
4184 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
4185 * @param ADCx ADC instance
4186 * @retval Returned value can be one of the following values:
4187 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4188 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4189 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4190 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4191 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4192 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4193 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4194 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4195 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4196 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4197 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4198 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4199 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4200 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4201 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4202 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4203 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)4204 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
4205 {
4206 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4207 }
4208
4209 /**
4210 * @brief Set ADC group regular sequencer discontinuous mode:
4211 * sequence subdivided and scan conversions interrupted every selected
4212 * number of ranks.
4213 * @note It is not possible to enable both ADC group regular
4214 * continuous mode and sequencer discontinuous mode.
4215 * @note It is not possible to enable both ADC auto-injected mode
4216 * and ADC group regular sequencer discontinuous mode.
4217 * @note On this STM32 series, setting of this feature is conditioned to
4218 * ADC state:
4219 * ADC must be disabled or enabled without conversion on going
4220 * on group regular.
4221 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
4222 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
4223 * @param ADCx ADC instance
4224 * @param SeqDiscont This parameter can be one of the following values:
4225 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4226 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4227 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4228 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4229 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4230 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4231 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4232 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4233 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4234 * @retval None
4235 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4236 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4237 {
4238 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
4239 }
4240
4241 /**
4242 * @brief Get ADC group regular sequencer discontinuous mode:
4243 * sequence subdivided and scan conversions interrupted every selected
4244 * number of ranks.
4245 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
4246 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
4247 * @param ADCx ADC instance
4248 * @retval Returned value can be one of the following values:
4249 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4250 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4251 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4252 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4253 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4254 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4255 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4256 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4257 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4258 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)4259 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4260 {
4261 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
4262 }
4263
4264 /**
4265 * @brief Set ADC group regular sequence: channel on the selected
4266 * scan sequence rank.
4267 * @note This function performs configuration of:
4268 * - Channels ordering into each rank of scan sequence:
4269 * whatever channel can be placed into whatever rank.
4270 * @note On this STM32 series, ADC group regular sequencer is
4271 * fully configurable: sequencer length and each rank
4272 * affectation to a channel are configurable.
4273 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4274 * @note Depending on devices and packages, some channels may not be available.
4275 * Refer to device datasheet for channels availability.
4276 * @note On this STM32 series, to measure internal channels (VrefInt,
4277 * TempSensor, ...), measurement paths to internal channels must be
4278 * enabled separately.
4279 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4280 * @note On this STM32 series, setting of this feature is conditioned to
4281 * ADC state:
4282 * ADC must be disabled or enabled without conversion on going
4283 * on group regular.
4284 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4285 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4286 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4287 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4288 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4289 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4290 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4291 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4292 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4293 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4294 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4295 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4296 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4297 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4298 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4299 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4300 * @param ADCx ADC instance
4301 * @param Rank This parameter can be one of the following values:
4302 * @arg @ref LL_ADC_REG_RANK_1
4303 * @arg @ref LL_ADC_REG_RANK_2
4304 * @arg @ref LL_ADC_REG_RANK_3
4305 * @arg @ref LL_ADC_REG_RANK_4
4306 * @arg @ref LL_ADC_REG_RANK_5
4307 * @arg @ref LL_ADC_REG_RANK_6
4308 * @arg @ref LL_ADC_REG_RANK_7
4309 * @arg @ref LL_ADC_REG_RANK_8
4310 * @arg @ref LL_ADC_REG_RANK_9
4311 * @arg @ref LL_ADC_REG_RANK_10
4312 * @arg @ref LL_ADC_REG_RANK_11
4313 * @arg @ref LL_ADC_REG_RANK_12
4314 * @arg @ref LL_ADC_REG_RANK_13
4315 * @arg @ref LL_ADC_REG_RANK_14
4316 * @arg @ref LL_ADC_REG_RANK_15
4317 * @arg @ref LL_ADC_REG_RANK_16
4318 * @param Channel This parameter can be one of the following values:
4319 * @arg @ref LL_ADC_CHANNEL_0 (3)
4320 * @arg @ref LL_ADC_CHANNEL_1 (3)
4321 * @arg @ref LL_ADC_CHANNEL_2 (3)
4322 * @arg @ref LL_ADC_CHANNEL_3 (3)
4323 * @arg @ref LL_ADC_CHANNEL_4 (3)
4324 * @arg @ref LL_ADC_CHANNEL_5 (3)
4325 * @arg @ref LL_ADC_CHANNEL_6
4326 * @arg @ref LL_ADC_CHANNEL_7
4327 * @arg @ref LL_ADC_CHANNEL_8
4328 * @arg @ref LL_ADC_CHANNEL_9
4329 * @arg @ref LL_ADC_CHANNEL_10
4330 * @arg @ref LL_ADC_CHANNEL_11
4331 * @arg @ref LL_ADC_CHANNEL_12
4332 * @arg @ref LL_ADC_CHANNEL_13
4333 * @arg @ref LL_ADC_CHANNEL_14
4334 * @arg @ref LL_ADC_CHANNEL_15
4335 * @arg @ref LL_ADC_CHANNEL_16
4336 * @arg @ref LL_ADC_CHANNEL_17
4337 * @arg @ref LL_ADC_CHANNEL_18
4338 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4339 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4340 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4341 *
4342 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
4343 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
4344 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
4345 * @retval None
4346 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4347 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4348 {
4349 /* Set bits with content of parameter "Channel" with bits position */
4350 /* in register and register position depending on parameter "Rank". */
4351 /* Parameters "Rank" and "Channel" are used with masks because containing */
4352 /* other bits reserved for other purpose. */
4353 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4354 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4355
4356 MODIFY_REG(*preg,
4357 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4358 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4359 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4360 }
4361
4362 /**
4363 * @brief Get ADC group regular sequence: channel on the selected
4364 * scan sequence rank.
4365 * @note On this STM32 series, ADC group regular sequencer is
4366 * fully configurable: sequencer length and each rank
4367 * affectation to a channel are configurable.
4368 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4369 * @note Depending on devices and packages, some channels may not be available.
4370 * Refer to device datasheet for channels availability.
4371 * @note Usage of the returned channel number:
4372 * - To reinject this channel into another function LL_ADC_xxx:
4373 * the returned channel number is only partly formatted on definition
4374 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4375 * with parts of literals LL_ADC_CHANNEL_x or using
4376 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4377 * Then the selected literal LL_ADC_CHANNEL_x can be used
4378 * as parameter for another function.
4379 * - To get the channel number in decimal format:
4380 * process the returned value with the helper macro
4381 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4382 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4383 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4384 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4385 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4386 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4387 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4388 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4389 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4390 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4391 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4392 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4393 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4394 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4395 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4396 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4397 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4398 * @param ADCx ADC instance
4399 * @param Rank This parameter can be one of the following values:
4400 * @arg @ref LL_ADC_REG_RANK_1
4401 * @arg @ref LL_ADC_REG_RANK_2
4402 * @arg @ref LL_ADC_REG_RANK_3
4403 * @arg @ref LL_ADC_REG_RANK_4
4404 * @arg @ref LL_ADC_REG_RANK_5
4405 * @arg @ref LL_ADC_REG_RANK_6
4406 * @arg @ref LL_ADC_REG_RANK_7
4407 * @arg @ref LL_ADC_REG_RANK_8
4408 * @arg @ref LL_ADC_REG_RANK_9
4409 * @arg @ref LL_ADC_REG_RANK_10
4410 * @arg @ref LL_ADC_REG_RANK_11
4411 * @arg @ref LL_ADC_REG_RANK_12
4412 * @arg @ref LL_ADC_REG_RANK_13
4413 * @arg @ref LL_ADC_REG_RANK_14
4414 * @arg @ref LL_ADC_REG_RANK_15
4415 * @arg @ref LL_ADC_REG_RANK_16
4416 * @retval Returned value can be one of the following values:
4417 * @arg @ref LL_ADC_CHANNEL_0 (2)
4418 * @arg @ref LL_ADC_CHANNEL_1 (2)
4419 * @arg @ref LL_ADC_CHANNEL_2 (2)
4420 * @arg @ref LL_ADC_CHANNEL_3 (2)
4421 * @arg @ref LL_ADC_CHANNEL_4 (2)
4422 * @arg @ref LL_ADC_CHANNEL_5 (2)
4423 * @arg @ref LL_ADC_CHANNEL_6
4424 * @arg @ref LL_ADC_CHANNEL_7
4425 * @arg @ref LL_ADC_CHANNEL_8
4426 * @arg @ref LL_ADC_CHANNEL_9
4427 * @arg @ref LL_ADC_CHANNEL_10
4428 * @arg @ref LL_ADC_CHANNEL_11
4429 * @arg @ref LL_ADC_CHANNEL_12
4430 * @arg @ref LL_ADC_CHANNEL_13
4431 * @arg @ref LL_ADC_CHANNEL_14
4432 * @arg @ref LL_ADC_CHANNEL_15
4433 * @arg @ref LL_ADC_CHANNEL_16
4434 * @arg @ref LL_ADC_CHANNEL_17
4435 * @arg @ref LL_ADC_CHANNEL_18
4436 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
4437 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3)
4438 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3)
4439 *
4440 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
4441 * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
4442 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
4443 * (3) For ADC channel read back from ADC register,
4444 * comparison with internal channel parameter to be done
4445 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4446 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4447 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4448 {
4449 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4450 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4451
4452 return (uint32_t)((READ_BIT(*preg,
4453 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4454 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4455 );
4456 }
4457
4458 /**
4459 * @brief Set ADC continuous conversion mode on ADC group regular.
4460 * @note Description of ADC continuous conversion mode:
4461 * - single mode: one conversion per trigger
4462 * - continuous mode: after the first trigger, following
4463 * conversions launched successively automatically.
4464 * @note It is not possible to enable both ADC group regular
4465 * continuous mode and sequencer discontinuous mode.
4466 * @note On this STM32 series, setting of this feature is conditioned to
4467 * ADC state:
4468 * ADC must be disabled or enabled without conversion on going
4469 * on group regular.
4470 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4471 * @param ADCx ADC instance
4472 * @param Continuous This parameter can be one of the following values:
4473 * @arg @ref LL_ADC_REG_CONV_SINGLE
4474 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4475 * @retval None
4476 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)4477 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4478 {
4479 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4480 }
4481
4482 /**
4483 * @brief Get ADC continuous conversion mode on ADC group regular.
4484 * @note Description of ADC continuous conversion mode:
4485 * - single mode: one conversion per trigger
4486 * - continuous mode: after the first trigger, following
4487 * conversions launched successively automatically.
4488 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4489 * @param ADCx ADC instance
4490 * @retval Returned value can be one of the following values:
4491 * @arg @ref LL_ADC_REG_CONV_SINGLE
4492 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4493 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)4494 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
4495 {
4496 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4497 }
4498
4499 /**
4500 * @brief Set ADC group regular conversion data transfer: no transfer or
4501 * transfer by DMA, and DMA requests mode.
4502 * @note If transfer by DMA selected, specifies the DMA requests
4503 * mode:
4504 * - Limited mode (One shot mode): DMA transfer requests are stopped
4505 * when number of DMA data transfers (number of
4506 * ADC conversions) is reached.
4507 * This ADC mode is intended to be used with DMA mode non-circular.
4508 * - Unlimited mode: DMA transfer requests are unlimited,
4509 * whatever number of DMA data transfers (number of
4510 * ADC conversions).
4511 * This ADC mode is intended to be used with DMA mode circular.
4512 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4513 * mode non-circular:
4514 * when DMA transfers size will be reached, DMA will stop transfers of
4515 * ADC conversions data ADC will raise an overrun error
4516 * (overrun flag and interruption if enabled).
4517 * @note For devices with several ADC instances: ADC multimode DMA
4518 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
4519 * @note To configure DMA source address (peripheral address),
4520 * use function @ref LL_ADC_DMA_GetRegAddr().
4521 * @note On this STM32 series, setting of this feature is conditioned to
4522 * ADC state:
4523 * ADC must be disabled or enabled without conversion on going
4524 * on either groups regular or injected.
4525 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4526 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
4527 * @param ADCx ADC instance
4528 * @param DMATransfer This parameter can be one of the following values:
4529 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4530 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4531 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4532 * @retval None
4533 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)4534 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4535 {
4536 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
4537 }
4538
4539 /**
4540 * @brief Get ADC group regular conversion data transfer: no transfer or
4541 * transfer by DMA, and DMA requests mode.
4542 * @note If transfer by DMA selected, specifies the DMA requests
4543 * mode:
4544 * - Limited mode (One shot mode): DMA transfer requests are stopped
4545 * when number of DMA data transfers (number of
4546 * ADC conversions) is reached.
4547 * This ADC mode is intended to be used with DMA mode non-circular.
4548 * - Unlimited mode: DMA transfer requests are unlimited,
4549 * whatever number of DMA data transfers (number of
4550 * ADC conversions).
4551 * This ADC mode is intended to be used with DMA mode circular.
4552 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4553 * mode non-circular:
4554 * when DMA transfers size will be reached, DMA will stop transfers of
4555 * ADC conversions data ADC will raise an overrun error
4556 * (overrun flag and interruption if enabled).
4557 * @note For devices with several ADC instances: ADC multimode DMA
4558 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
4559 * @note To configure DMA source address (peripheral address),
4560 * use function @ref LL_ADC_DMA_GetRegAddr().
4561 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4562 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4563 * @param ADCx ADC instance
4564 * @retval Returned value can be one of the following values:
4565 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4566 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4567 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4568 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)4569 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
4570 {
4571 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
4572 }
4573
4574 /**
4575 * @brief Set ADC group regular conversion data transfer to MDF (ADF).
4576 * @note MDF transfer cannot be used if DMA transfer is enabled.
4577 * @note To configure MDF source address (peripheral address),
4578 * use the same function as for DMA transfer:
4579 * function @ref LL_ADC_DMA_GetRegAddr().
4580 * @note On this STM32 series, setting of this feature is conditioned to
4581 * ADC state:
4582 * ADC must be disabled or enabled without conversion on going
4583 * on either groups regular or injected.
4584 * @rmtoll CFGR ADFCFG LL_ADC_REG_GetMDFTransfer
4585 * @param ADCx ADC instance
4586 * @param MDFTransfer This parameter can be one of the following values:
4587 * @arg @ref LL_ADC_REG_MDF_TRANSFER_NONE
4588 * @arg @ref LL_ADC_REG_MDF_TRANSFER_ENABLE
4589 * @retval None
4590 */
LL_ADC_REG_SetMDFTransfer(ADC_TypeDef * ADCx,uint32_t MDFTransfer)4591 __STATIC_INLINE void LL_ADC_REG_SetMDFTransfer(ADC_TypeDef *ADCx, uint32_t MDFTransfer)
4592 {
4593 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ADFCFG, MDFTransfer);
4594 }
4595
4596 /**
4597 * @brief Get ADC group regular conversion data transfer to MDF (ADF).
4598 * @rmtoll CFGR ADFCFG LL_ADC_REG_GetMDFTransfer
4599 * @param ADCx ADC instance
4600 * @retval Returned value can be one of the following values:
4601 * @arg @ref LL_ADC_REG_MDF_TRANSFER_NONE
4602 * @arg @ref LL_ADC_REG_MDF_TRANSFER_ENABLE
4603 */
LL_ADC_REG_GetMDFTransfer(const ADC_TypeDef * ADCx)4604 __STATIC_INLINE uint32_t LL_ADC_REG_GetMDFTransfer(const ADC_TypeDef *ADCx)
4605 {
4606 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ADFCFG));
4607 }
4608
4609 /**
4610 * @brief Set ADC group regular behavior in case of overrun:
4611 * data preserved or overwritten.
4612 * @note Compatibility with devices without feature overrun:
4613 * other devices without this feature have a behavior
4614 * equivalent to data overwritten.
4615 * The default setting of overrun is data preserved.
4616 * Therefore, for compatibility with all devices, parameter
4617 * overrun should be set to data overwritten.
4618 * @note On this STM32 series, setting of this feature is conditioned to
4619 * ADC state:
4620 * ADC must be disabled or enabled without conversion on going
4621 * on group regular.
4622 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4623 * @param ADCx ADC instance
4624 * @param Overrun This parameter can be one of the following values:
4625 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4626 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4627 * @retval None
4628 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)4629 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4630 {
4631 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4632 }
4633
4634 /**
4635 * @brief Get ADC group regular behavior in case of overrun:
4636 * data preserved or overwritten.
4637 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4638 * @param ADCx ADC instance
4639 * @retval Returned value can be one of the following values:
4640 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4641 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4642 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)4643 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
4644 {
4645 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4646 }
4647
4648 /**
4649 * @}
4650 */
4651
4652 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4653 * @{
4654 */
4655
4656 /**
4657 * @brief Set ADC group injected conversion trigger source:
4658 * internal (SW start) or from external peripheral (timer event,
4659 * external interrupt line).
4660 * @note On this STM32 series, setting trigger source to external trigger
4661 * also set trigger polarity to rising edge
4662 * (default setting for compatibility with some ADC on other
4663 * STM32 series having this setting set by HW default value).
4664 * In case of need to modify trigger edge, use
4665 * function @ref LL_ADC_INJ_SetTriggerEdge().
4666 * @note Availability of parameters of trigger sources from timer
4667 * depends on timers availability on the selected device.
4668 * @note On this STM32 series, setting of this feature is conditioned to
4669 * ADC state:
4670 * ADC must not be disabled. Can be enabled with or without conversion
4671 * on going on either groups regular or injected.
4672 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4673 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4674 * @param ADCx ADC instance
4675 * @param TriggerSource This parameter can be one of the following values:
4676 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4677 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4678 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4679 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4680 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4681 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4682 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4683 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4684 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
4685 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4686 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO
4687 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
4688 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4689 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4690 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4691 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4692 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4693 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
4694 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
4695 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
4696 * @retval None
4697 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4698 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4699 {
4700 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4701 }
4702
4703 /**
4704 * @brief Get ADC group injected conversion trigger source:
4705 * internal (SW start) or from external peripheral (timer event,
4706 * external interrupt line).
4707 * @note To determine whether group injected trigger source is
4708 * internal (SW start) or external, without detail
4709 * of which peripheral is selected as external trigger,
4710 * (equivalent to
4711 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4712 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4713 * @note Availability of parameters of trigger sources from timer
4714 * depends on timers availability on the selected device.
4715 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4716 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4717 * @param ADCx ADC instance
4718 * @retval Returned value can be one of the following values:
4719 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4720 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4721 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4722 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4723 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4724 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4725 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4726 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4727 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
4728 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4729 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO
4730 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
4731 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4732 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4733 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4734 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4735 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4736 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
4737 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
4738 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
4739 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)4740 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
4741 {
4742 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4743
4744 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4745 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4746 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4747
4748 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4749 /* to match with triggers literals definition. */
4750 return ((trigger_source
4751 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
4752 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
4753 );
4754 }
4755
4756 /**
4757 * @brief Get ADC group injected conversion trigger source internal (SW start)
4758 or external
4759 * @note In case of group injected trigger source set to external trigger,
4760 * to determine which peripheral is selected as external trigger,
4761 * use function @ref LL_ADC_INJ_GetTriggerSource.
4762 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4763 * @param ADCx ADC instance
4764 * @retval Value "0" if trigger source external trigger
4765 * Value "1" if trigger source SW start.
4766 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4767 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4768 {
4769 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4770 }
4771
4772 /**
4773 * @brief Set ADC group injected conversion trigger polarity.
4774 * Applicable only for trigger source set to external trigger.
4775 * @note On this STM32 series, setting of this feature is conditioned to
4776 * ADC state:
4777 * ADC must not be disabled. Can be enabled with or without conversion
4778 * on going on either groups regular or injected.
4779 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4780 * @param ADCx ADC instance
4781 * @param ExternalTriggerEdge This parameter can be one of the following values:
4782 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4783 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4784 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4785 * @retval None
4786 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4787 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4788 {
4789 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4790 }
4791
4792 /**
4793 * @brief Get ADC group injected conversion trigger polarity.
4794 * Applicable only for trigger source set to external trigger.
4795 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4796 * @param ADCx ADC instance
4797 * @retval Returned value can be one of the following values:
4798 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4799 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4800 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4801 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)4802 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
4803 {
4804 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4805 }
4806
4807 /**
4808 * @brief Set ADC group injected sequencer length and scan direction.
4809 * @note This function performs configuration of:
4810 * - Sequence length: Number of ranks in the scan sequence.
4811 * - Sequence direction: Unless specified in parameters, sequencer
4812 * scan direction is forward (from rank 1 to rank n).
4813 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4814 * ADC conversion on only 1 channel.
4815 * @note On this STM32 series, setting of this feature is conditioned to
4816 * ADC state:
4817 * ADC must not be disabled. Can be enabled with or without conversion
4818 * on going on either groups regular or injected.
4819 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4820 * @param ADCx ADC instance
4821 * @param SequencerNbRanks This parameter can be one of the following values:
4822 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4823 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4824 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4825 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4826 * @retval None
4827 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4828 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4829 {
4830 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4831 }
4832
4833 /**
4834 * @brief Get ADC group injected sequencer length and scan direction.
4835 * @note This function retrieves:
4836 * - Sequence length: Number of ranks in the scan sequence.
4837 * - Sequence direction: Unless specified in parameters, sequencer
4838 * scan direction is forward (from rank 1 to rank n).
4839 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4840 * ADC conversion on only 1 channel.
4841 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4842 * @param ADCx ADC instance
4843 * @retval Returned value can be one of the following values:
4844 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4845 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4846 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4847 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4848 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)4849 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
4850 {
4851 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4852 }
4853
4854 /**
4855 * @brief Set ADC group injected sequencer discontinuous mode:
4856 * sequence subdivided and scan conversions interrupted every selected
4857 * number of ranks.
4858 * @note It is not possible to enable both ADC group injected
4859 * auto-injected mode and sequencer discontinuous mode.
4860 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4861 * @param ADCx ADC instance
4862 * @param SeqDiscont This parameter can be one of the following values:
4863 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4864 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4865 * @retval None
4866 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4867 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4868 {
4869 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4870 }
4871
4872 /**
4873 * @brief Get ADC group injected sequencer discontinuous mode:
4874 * sequence subdivided and scan conversions interrupted every selected
4875 * number of ranks.
4876 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4877 * @param ADCx ADC instance
4878 * @retval Returned value can be one of the following values:
4879 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4880 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4881 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)4882 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4883 {
4884 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4885 }
4886
4887 /**
4888 * @brief Set ADC group injected sequence: channel on the selected
4889 * sequence rank.
4890 * @note Depending on devices and packages, some channels may not be available.
4891 * Refer to device datasheet for channels availability.
4892 * @note On this STM32 series, to measure internal channels (VrefInt,
4893 * TempSensor, ...), measurement paths to internal channels must be
4894 * enabled separately.
4895 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4896 * @note On STM32H7RS, some fast channels are available: fast analog inputs
4897 * coming from GPIO pads (ADC_IN0..5).
4898 * @note On this STM32 series, setting of this feature is conditioned to
4899 * ADC state:
4900 * ADC must not be disabled. Can be enabled with or without conversion
4901 * on going on either groups regular or injected.
4902 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4903 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4904 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4905 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4906 * @param ADCx ADC instance
4907 * @param Rank This parameter can be one of the following values:
4908 * @arg @ref LL_ADC_INJ_RANK_1
4909 * @arg @ref LL_ADC_INJ_RANK_2
4910 * @arg @ref LL_ADC_INJ_RANK_3
4911 * @arg @ref LL_ADC_INJ_RANK_4
4912 * @param Channel This parameter can be one of the following values:
4913 * @arg @ref LL_ADC_CHANNEL_0 (3)
4914 * @arg @ref LL_ADC_CHANNEL_1 (3)
4915 * @arg @ref LL_ADC_CHANNEL_2 (3)
4916 * @arg @ref LL_ADC_CHANNEL_3 (3)
4917 * @arg @ref LL_ADC_CHANNEL_4 (3)
4918 * @arg @ref LL_ADC_CHANNEL_5 (3)
4919 * @arg @ref LL_ADC_CHANNEL_6
4920 * @arg @ref LL_ADC_CHANNEL_7
4921 * @arg @ref LL_ADC_CHANNEL_8
4922 * @arg @ref LL_ADC_CHANNEL_9
4923 * @arg @ref LL_ADC_CHANNEL_10
4924 * @arg @ref LL_ADC_CHANNEL_11
4925 * @arg @ref LL_ADC_CHANNEL_12
4926 * @arg @ref LL_ADC_CHANNEL_13
4927 * @arg @ref LL_ADC_CHANNEL_14
4928 * @arg @ref LL_ADC_CHANNEL_15
4929 * @arg @ref LL_ADC_CHANNEL_16
4930 * @arg @ref LL_ADC_CHANNEL_17
4931 * @arg @ref LL_ADC_CHANNEL_18
4932 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4933 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4934 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4935 *
4936 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
4937 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
4938 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
4939 * @retval None
4940 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4941 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4942 {
4943 /* Set bits with content of parameter "Channel" with bits position */
4944 /* in register depending on parameter "Rank". */
4945 /* Parameters "Rank" and "Channel" are used with masks because containing */
4946 /* other bits reserved for other purpose. */
4947 MODIFY_REG(ADCx->JSQR,
4948 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4949 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4950 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4951 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4952 }
4953
4954 /**
4955 * @brief Get ADC group injected sequence: channel on the selected
4956 * sequence rank.
4957 * @note Depending on devices and packages, some channels may not be available.
4958 * Refer to device datasheet for channels availability.
4959 * @note Usage of the returned channel number:
4960 * - To reinject this channel into another function LL_ADC_xxx:
4961 * the returned channel number is only partly formatted on definition
4962 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4963 * with parts of literals LL_ADC_CHANNEL_x or using
4964 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4965 * Then the selected literal LL_ADC_CHANNEL_x can be used
4966 * as parameter for another function.
4967 * - To get the channel number in decimal format:
4968 * process the returned value with the helper macro
4969 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4970 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4971 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4972 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4973 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4974 * @param ADCx ADC instance
4975 * @param Rank This parameter can be one of the following values:
4976 * @arg @ref LL_ADC_INJ_RANK_1
4977 * @arg @ref LL_ADC_INJ_RANK_2
4978 * @arg @ref LL_ADC_INJ_RANK_3
4979 * @arg @ref LL_ADC_INJ_RANK_4
4980 * @retval Returned value can be one of the following values:
4981 * @arg @ref LL_ADC_CHANNEL_0 (2)
4982 * @arg @ref LL_ADC_CHANNEL_1 (2)
4983 * @arg @ref LL_ADC_CHANNEL_2 (2)
4984 * @arg @ref LL_ADC_CHANNEL_3 (2)
4985 * @arg @ref LL_ADC_CHANNEL_4 (2)
4986 * @arg @ref LL_ADC_CHANNEL_5 (2)
4987 * @arg @ref LL_ADC_CHANNEL_6
4988 * @arg @ref LL_ADC_CHANNEL_7
4989 * @arg @ref LL_ADC_CHANNEL_8
4990 * @arg @ref LL_ADC_CHANNEL_9
4991 * @arg @ref LL_ADC_CHANNEL_10
4992 * @arg @ref LL_ADC_CHANNEL_11
4993 * @arg @ref LL_ADC_CHANNEL_12
4994 * @arg @ref LL_ADC_CHANNEL_13
4995 * @arg @ref LL_ADC_CHANNEL_14
4996 * @arg @ref LL_ADC_CHANNEL_15
4997 * @arg @ref LL_ADC_CHANNEL_16
4998 * @arg @ref LL_ADC_CHANNEL_17
4999 * @arg @ref LL_ADC_CHANNEL_18
5000 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
5001 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3)
5002 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3)
5003 *
5004 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
5005 * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5006 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5007 * (3) For ADC channel read back from ADC register,
5008 * comparison with internal channel parameter to be done
5009 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
5010 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)5011 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
5012 {
5013 return (uint32_t)((READ_BIT(ADCx->JSQR,
5014 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5015 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
5016 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
5017 );
5018 }
5019
5020 /**
5021 * @brief Set ADC group injected conversion trigger:
5022 * independent or from ADC group regular.
5023 * @note This mode can be used to extend number of data registers
5024 * updated after one ADC conversion trigger and with data
5025 * permanently kept (not erased by successive conversions of scan of
5026 * ADC sequencer ranks), up to 5 data registers:
5027 * 1 data register on ADC group regular, 4 data registers
5028 * on ADC group injected.
5029 * @note If ADC group injected injected trigger source is set to an
5030 * external trigger, this feature must be must be set to
5031 * independent trigger.
5032 * ADC group injected automatic trigger is compliant only with
5033 * group injected trigger source set to SW start, without any
5034 * further action on ADC group injected conversion start or stop:
5035 * in this case, ADC group injected is controlled only
5036 * from ADC group regular.
5037 * @note It is not possible to enable both ADC group injected
5038 * auto-injected mode and sequencer discontinuous mode.
5039 * @note On this STM32 series, setting of this feature is conditioned to
5040 * ADC state:
5041 * ADC must be disabled or enabled without conversion on going
5042 * on either groups regular or injected.
5043 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
5044 * @param ADCx ADC instance
5045 * @param TrigAuto This parameter can be one of the following values:
5046 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5047 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5048 * @retval None
5049 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)5050 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
5051 {
5052 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
5053 }
5054
5055 /**
5056 * @brief Get ADC group injected conversion trigger:
5057 * independent or from ADC group regular.
5058 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
5059 * @param ADCx ADC instance
5060 * @retval Returned value can be one of the following values:
5061 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5062 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5063 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)5064 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
5065 {
5066 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
5067 }
5068
5069 /**
5070 * @brief Set ADC group injected contexts queue mode.
5071 * @note A context is a setting of group injected sequencer:
5072 * - group injected trigger
5073 * - sequencer length
5074 * - sequencer ranks
5075 * If contexts queue is disabled:
5076 * - only 1 sequence can be configured
5077 * and is active perpetually.
5078 * If contexts queue is enabled:
5079 * - up to 2 contexts can be queued
5080 * and are checked in and out as a FIFO stack (first-in, first-out).
5081 * - If a new context is set when queues is full, error is triggered
5082 * by interruption "Injected Queue Overflow".
5083 * - Two behaviors are possible when all contexts have been processed:
5084 * the contexts queue can maintain the last context active perpetually
5085 * or can be empty and injected group triggers are disabled.
5086 * - Triggers can be only external (not internal SW start)
5087 * - Caution: The sequence must be fully configured in one time
5088 * (one write of register JSQR makes a check-in of a new context
5089 * into the queue).
5090 * Therefore functions to set separately injected trigger and
5091 * sequencer channels cannot be used, register JSQR must be set
5092 * using function @ref LL_ADC_INJ_ConfigQueueContext().
5093 * @note This parameter can be modified only when no conversion is on going
5094 * on either groups regular or injected.
5095 * @note A modification of the context mode (bit JQDIS) causes the contexts
5096 * queue to be flushed and the register JSQR is cleared.
5097 * @note On this STM32 series, setting of this feature is conditioned to
5098 * ADC state:
5099 * ADC must be disabled or enabled without conversion on going
5100 * on either groups regular or injected.
5101 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
5102 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
5103 * @param ADCx ADC instance
5104 * @param QueueMode This parameter can be one of the following values:
5105 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5106 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5107 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5108 * @retval None
5109 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)5110 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
5111 {
5112 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
5113 }
5114
5115 /**
5116 * @brief Get ADC group injected context queue mode.
5117 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
5118 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
5119 * @param ADCx ADC instance
5120 * @retval Returned value can be one of the following values:
5121 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5122 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5123 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5124 */
LL_ADC_INJ_GetQueueMode(const ADC_TypeDef * ADCx)5125 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
5126 {
5127 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
5128 }
5129
5130 /**
5131 * @brief Set one context on ADC group injected that will be checked in
5132 * contexts queue.
5133 * @note A context is a setting of group injected sequencer:
5134 * - group injected trigger
5135 * - sequencer length
5136 * - sequencer ranks
5137 * This function is intended to be used when contexts queue is enabled,
5138 * because the sequence must be fully configured in one time
5139 * (functions to set separately injected trigger and sequencer channels
5140 * cannot be used):
5141 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
5142 * @note In the contexts queue, only the active context can be read.
5143 * The parameters of this function can be read using functions:
5144 * @arg @ref LL_ADC_INJ_GetTriggerSource()
5145 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
5146 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
5147 * @note On this STM32 series, to measure internal channels (VrefInt,
5148 * TempSensor, ...), measurement paths to internal channels must be
5149 * enabled separately.
5150 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5151 * @note On STM32H7RS, some fast channels are available: fast analog inputs
5152 * coming from GPIO pads (ADC_IN0..5).
5153 * @note On this STM32 series, setting of this feature is conditioned to
5154 * ADC state:
5155 * ADC must not be disabled. Can be enabled with or without conversion
5156 * on going on either groups regular or injected.
5157 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
5158 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
5159 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
5160 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
5161 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
5162 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
5163 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
5164 * @param ADCx ADC instance
5165 * @param TriggerSource This parameter can be one of the following values:
5166 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5167 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5168 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5169 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5170 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5171 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
5172 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5173 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5174 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
5175 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5176 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO
5177 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
5178 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
5179 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5180 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5181 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5182 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5183 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
5184 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
5185 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
5186 * @param ExternalTriggerEdge This parameter can be one of the following values:
5187 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5188 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5189 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5190 *
5191 * Note: This parameter is discarded in case of SW start:
5192 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
5193 * @param SequencerNbRanks This parameter can be one of the following values:
5194 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5195 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5196 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5197 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5198 * @param Rank1_Channel This parameter can be one of the following values:
5199 * @arg @ref LL_ADC_CHANNEL_0 (3)
5200 * @arg @ref LL_ADC_CHANNEL_1 (3)
5201 * @arg @ref LL_ADC_CHANNEL_2 (3)
5202 * @arg @ref LL_ADC_CHANNEL_3 (3)
5203 * @arg @ref LL_ADC_CHANNEL_4 (3)
5204 * @arg @ref LL_ADC_CHANNEL_5 (3)
5205 * @arg @ref LL_ADC_CHANNEL_6
5206 * @arg @ref LL_ADC_CHANNEL_7
5207 * @arg @ref LL_ADC_CHANNEL_8
5208 * @arg @ref LL_ADC_CHANNEL_9
5209 * @arg @ref LL_ADC_CHANNEL_10
5210 * @arg @ref LL_ADC_CHANNEL_11
5211 * @arg @ref LL_ADC_CHANNEL_12
5212 * @arg @ref LL_ADC_CHANNEL_13
5213 * @arg @ref LL_ADC_CHANNEL_14
5214 * @arg @ref LL_ADC_CHANNEL_15
5215 * @arg @ref LL_ADC_CHANNEL_16
5216 * @arg @ref LL_ADC_CHANNEL_17
5217 * @arg @ref LL_ADC_CHANNEL_18
5218 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5219 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5220 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5221 *
5222 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
5223 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5224 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5225 * @param Rank2_Channel This parameter can be one of the following values:
5226 * @arg @ref LL_ADC_CHANNEL_0 (3)
5227 * @arg @ref LL_ADC_CHANNEL_1 (3)
5228 * @arg @ref LL_ADC_CHANNEL_2 (3)
5229 * @arg @ref LL_ADC_CHANNEL_3 (3)
5230 * @arg @ref LL_ADC_CHANNEL_4 (3)
5231 * @arg @ref LL_ADC_CHANNEL_5 (3)
5232 * @arg @ref LL_ADC_CHANNEL_6
5233 * @arg @ref LL_ADC_CHANNEL_7
5234 * @arg @ref LL_ADC_CHANNEL_8
5235 * @arg @ref LL_ADC_CHANNEL_9
5236 * @arg @ref LL_ADC_CHANNEL_10
5237 * @arg @ref LL_ADC_CHANNEL_11
5238 * @arg @ref LL_ADC_CHANNEL_12
5239 * @arg @ref LL_ADC_CHANNEL_13
5240 * @arg @ref LL_ADC_CHANNEL_14
5241 * @arg @ref LL_ADC_CHANNEL_15
5242 * @arg @ref LL_ADC_CHANNEL_16
5243 * @arg @ref LL_ADC_CHANNEL_17
5244 * @arg @ref LL_ADC_CHANNEL_18
5245 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5246 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5247 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5248 *
5249 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
5250 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5251 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5252 * @param Rank3_Channel This parameter can be one of the following values:
5253 * @arg @ref LL_ADC_CHANNEL_0 (3)
5254 * @arg @ref LL_ADC_CHANNEL_1 (3)
5255 * @arg @ref LL_ADC_CHANNEL_2 (3)
5256 * @arg @ref LL_ADC_CHANNEL_3 (3)
5257 * @arg @ref LL_ADC_CHANNEL_4 (3)
5258 * @arg @ref LL_ADC_CHANNEL_5 (3)
5259 * @arg @ref LL_ADC_CHANNEL_6
5260 * @arg @ref LL_ADC_CHANNEL_7
5261 * @arg @ref LL_ADC_CHANNEL_8
5262 * @arg @ref LL_ADC_CHANNEL_9
5263 * @arg @ref LL_ADC_CHANNEL_10
5264 * @arg @ref LL_ADC_CHANNEL_11
5265 * @arg @ref LL_ADC_CHANNEL_12
5266 * @arg @ref LL_ADC_CHANNEL_13
5267 * @arg @ref LL_ADC_CHANNEL_14
5268 * @arg @ref LL_ADC_CHANNEL_15
5269 * @arg @ref LL_ADC_CHANNEL_16
5270 * @arg @ref LL_ADC_CHANNEL_17
5271 * @arg @ref LL_ADC_CHANNEL_18
5272 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5273 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5274 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5275 *
5276 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
5277 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5278 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5279 * @param Rank4_Channel This parameter can be one of the following values:
5280 * @arg @ref LL_ADC_CHANNEL_0 (3)
5281 * @arg @ref LL_ADC_CHANNEL_1 (3)
5282 * @arg @ref LL_ADC_CHANNEL_2 (3)
5283 * @arg @ref LL_ADC_CHANNEL_3 (3)
5284 * @arg @ref LL_ADC_CHANNEL_4 (3)
5285 * @arg @ref LL_ADC_CHANNEL_5 (3)
5286 * @arg @ref LL_ADC_CHANNEL_6
5287 * @arg @ref LL_ADC_CHANNEL_7
5288 * @arg @ref LL_ADC_CHANNEL_8
5289 * @arg @ref LL_ADC_CHANNEL_9
5290 * @arg @ref LL_ADC_CHANNEL_10
5291 * @arg @ref LL_ADC_CHANNEL_11
5292 * @arg @ref LL_ADC_CHANNEL_12
5293 * @arg @ref LL_ADC_CHANNEL_13
5294 * @arg @ref LL_ADC_CHANNEL_14
5295 * @arg @ref LL_ADC_CHANNEL_15
5296 * @arg @ref LL_ADC_CHANNEL_16
5297 * @arg @ref LL_ADC_CHANNEL_17
5298 * @arg @ref LL_ADC_CHANNEL_18
5299 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5300 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5301 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5302 *
5303 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
5304 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5305 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5306 * @retval None
5307 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)5308 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5309 uint32_t TriggerSource,
5310 uint32_t ExternalTriggerEdge,
5311 uint32_t SequencerNbRanks,
5312 uint32_t Rank1_Channel,
5313 uint32_t Rank2_Channel,
5314 uint32_t Rank3_Channel,
5315 uint32_t Rank4_Channel)
5316 {
5317 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5318 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5319 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5320 /* because containing other bits reserved for other purpose. */
5321 /* If parameter "TriggerSource" is set to SW start, then parameter */
5322 /* "ExternalTriggerEdge" is discarded. */
5323 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5324 MODIFY_REG(ADCx->JSQR,
5325 ADC_JSQR_JEXTSEL |
5326 ADC_JSQR_JEXTEN |
5327 ADC_JSQR_JSQ4 |
5328 ADC_JSQR_JSQ3 |
5329 ADC_JSQR_JSQ2 |
5330 ADC_JSQR_JSQ1 |
5331 ADC_JSQR_JL,
5332 (TriggerSource & ADC_JSQR_JEXTSEL) |
5333 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5334 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5335 << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5336 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5337 << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5338 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5339 << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5340 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5341 << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5342 SequencerNbRanks
5343 );
5344 }
5345
5346 /**
5347 * @}
5348 */
5349
5350 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5351 * @{
5352 */
5353
5354 /**
5355 * @brief Set sampling time of the selected ADC channel
5356 * Unit: ADC clock cycles.
5357 * @note On this device, sampling time is on channel scope: independently
5358 * of channel mapped on ADC group regular or injected.
5359 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5360 * converted:
5361 * sampling time constraints must be respected (sampling time can be
5362 * adjusted in function of ADC clock frequency and sampling time
5363 * setting).
5364 * Refer to device datasheet for timings values (parameters TS_vrefint,
5365 * TS_temp, ...).
5366 * @note Conversion time is the addition of sampling time and processing time.
5367 * On this STM32 series, ADC processing time is:
5368 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5369 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5370 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5371 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5372 * @note In case of ADC conversion of internal channel (VrefInt,
5373 * temperature sensor, ...), a sampling time minimum value
5374 * is required.
5375 * Refer to device datasheet.
5376 * @note On this STM32 series, setting of this feature is conditioned to
5377 * ADC state:
5378 * ADC must be disabled or enabled without conversion on going
5379 * on either groups regular or injected.
5380 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5381 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5382 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5383 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5384 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5385 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5386 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5387 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5388 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5389 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5390 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5391 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5392 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5393 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5394 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5395 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5396 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5397 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5398 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5399 * @param ADCx ADC instance
5400 * @param Channel This parameter can be one of the following values:
5401 * @arg @ref LL_ADC_CHANNEL_0 (3)
5402 * @arg @ref LL_ADC_CHANNEL_1 (3)
5403 * @arg @ref LL_ADC_CHANNEL_2 (3)
5404 * @arg @ref LL_ADC_CHANNEL_3 (3)
5405 * @arg @ref LL_ADC_CHANNEL_4 (3)
5406 * @arg @ref LL_ADC_CHANNEL_5 (3)
5407 * @arg @ref LL_ADC_CHANNEL_6
5408 * @arg @ref LL_ADC_CHANNEL_7
5409 * @arg @ref LL_ADC_CHANNEL_8
5410 * @arg @ref LL_ADC_CHANNEL_9
5411 * @arg @ref LL_ADC_CHANNEL_10
5412 * @arg @ref LL_ADC_CHANNEL_11
5413 * @arg @ref LL_ADC_CHANNEL_12
5414 * @arg @ref LL_ADC_CHANNEL_13
5415 * @arg @ref LL_ADC_CHANNEL_14
5416 * @arg @ref LL_ADC_CHANNEL_15
5417 * @arg @ref LL_ADC_CHANNEL_16
5418 * @arg @ref LL_ADC_CHANNEL_17
5419 * @arg @ref LL_ADC_CHANNEL_18
5420 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5421 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5422 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5423 *
5424 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
5425 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5426 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5427 * @param SamplingTime This parameter can be one of the following values:
5428 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5429 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5430 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5431 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5432 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5433 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5434 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5435 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5436 *
5437 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5438 * can be replaced by 3.5 ADC clock cycles.
5439 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5440 * @retval None
5441 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)5442 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5443 {
5444 /* Set bits with content of parameter "SamplingTime" with bits position */
5445 /* in register and register position depending on parameter "Channel". */
5446 /* Parameter "Channel" is used with masks because containing */
5447 /* other bits reserved for other purpose. */
5448 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
5449 ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5450
5451 MODIFY_REG(*preg,
5452 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5453 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5454 }
5455
5456 /**
5457 * @brief Get sampling time of the selected ADC channel
5458 * Unit: ADC clock cycles.
5459 * @note On this device, sampling time is on channel scope: independently
5460 * of channel mapped on ADC group regular or injected.
5461 * @note Conversion time is the addition of sampling time and processing time.
5462 * On this STM32 series, ADC processing time is:
5463 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5464 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5465 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5466 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5467 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5468 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5469 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5470 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5471 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5472 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5473 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5474 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5475 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5476 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5477 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5478 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5479 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5480 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5481 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5482 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5483 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5484 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5485 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5486 * @param ADCx ADC instance
5487 * @param Channel This parameter can be one of the following values:
5488 * @arg @ref LL_ADC_CHANNEL_0 (3)
5489 * @arg @ref LL_ADC_CHANNEL_1 (3)
5490 * @arg @ref LL_ADC_CHANNEL_2 (3)
5491 * @arg @ref LL_ADC_CHANNEL_3 (3)
5492 * @arg @ref LL_ADC_CHANNEL_4 (3)
5493 * @arg @ref LL_ADC_CHANNEL_5 (3)
5494 * @arg @ref LL_ADC_CHANNEL_6
5495 * @arg @ref LL_ADC_CHANNEL_7
5496 * @arg @ref LL_ADC_CHANNEL_8
5497 * @arg @ref LL_ADC_CHANNEL_9
5498 * @arg @ref LL_ADC_CHANNEL_10
5499 * @arg @ref LL_ADC_CHANNEL_11
5500 * @arg @ref LL_ADC_CHANNEL_12
5501 * @arg @ref LL_ADC_CHANNEL_13
5502 * @arg @ref LL_ADC_CHANNEL_14
5503 * @arg @ref LL_ADC_CHANNEL_15
5504 * @arg @ref LL_ADC_CHANNEL_16
5505 * @arg @ref LL_ADC_CHANNEL_17
5506 * @arg @ref LL_ADC_CHANNEL_18
5507 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5508 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5509 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5510 *
5511 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
5512 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5513 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5514 * @retval Returned value can be one of the following values:
5515 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5516 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5517 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5518 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5519 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5520 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5521 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5522 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5523 *
5524 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5525 * can be replaced by 3.5 ADC clock cycles.
5526 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5527 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)5528 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
5529 {
5530 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK)
5531 >> ADC_SMPRX_REGOFFSET_POS));
5532
5533 return (uint32_t)(READ_BIT(*preg,
5534 ADC_SMPR1_SMP0
5535 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5536 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5537 );
5538 }
5539
5540 /**
5541 * @brief Set mode single-ended or differential input of the selected
5542 * ADC channel.
5543 * @note Channel ending is on channel scope: independently of channel mapped
5544 * on ADC group regular or injected.
5545 * In differential mode: Differential measurement is carried out
5546 * between the selected channel 'i' (positive input) and
5547 * channel 'i+1' (negative input). Only channel 'i' has to be
5548 * configured, channel 'i+1' is configured automatically.
5549 * @note Refer to Reference Manual to ensure the selected channel is
5550 * available in differential mode.
5551 * For example, internal channels (VrefInt, TempSensor, ...) are
5552 * not available in differential mode.
5553 * @note When configuring a channel 'i' in differential mode,
5554 * the channel 'i+1' is not usable separately.
5555 * @note Channels 0, 5, 6, 7, 9, 13, 14, 15, 16, 17, 18
5556 * are internally fixed to single-ended inputs configuration.
5557 * @note For ADC channels configured in differential mode, both inputs
5558 * should be biased at (Vref+)/2 +/-200mV.
5559 * (Vref+ is the analog voltage reference)
5560 * @note On this STM32 series, setting of this feature is conditioned to
5561 * ADC state:
5562 * ADC must be ADC disabled.
5563 * @note One or several values can be selected.
5564 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5565 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5566 * @param ADCx ADC instance
5567 * @param Channel This parameter can be one of the following values:
5568 * @arg @ref LL_ADC_CHANNEL_1
5569 * @arg @ref LL_ADC_CHANNEL_2
5570 * @arg @ref LL_ADC_CHANNEL_3
5571 * @arg @ref LL_ADC_CHANNEL_4
5572 * @arg @ref LL_ADC_CHANNEL_5
5573 * @arg @ref LL_ADC_CHANNEL_6
5574 * @arg @ref LL_ADC_CHANNEL_7
5575 * @arg @ref LL_ADC_CHANNEL_8
5576 * @arg @ref LL_ADC_CHANNEL_9
5577 * @arg @ref LL_ADC_CHANNEL_10
5578 * @arg @ref LL_ADC_CHANNEL_11
5579 * @arg @ref LL_ADC_CHANNEL_12
5580 * @arg @ref LL_ADC_CHANNEL_13
5581 * @arg @ref LL_ADC_CHANNEL_14
5582 * @arg @ref LL_ADC_CHANNEL_15
5583 * @param SingleDiff This parameter can be a combination of the following values:
5584 * @arg @ref LL_ADC_SINGLE_ENDED
5585 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5586 * @retval None
5587 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)5588 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5589 {
5590 /* Bits of channels in single or differential mode are set only for */
5591 /* differential mode (for single mode, mask of bits allowed to be set is */
5592 /* shifted out of range of bits of channels in single or differential mode. */
5593 MODIFY_REG(ADCx->DIFSEL,
5594 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5595 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
5596 & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5597 }
5598
5599 /**
5600 * @brief Get mode single-ended or differential input of the selected
5601 * ADC channel.
5602 * @note When configuring a channel 'i' in differential mode,
5603 * the channel 'i+1' is not usable separately.
5604 * Therefore, to ensure a channel is configured in single-ended mode,
5605 * the configuration of channel itself and the channel 'i-1' must be
5606 * read back (to ensure that the selected channel channel has not been
5607 * configured in differential mode by the previous channel).
5608 * @note Refer to Reference Manual to ensure the selected channel is
5609 * available in differential mode.
5610 * For example, internal channels (VrefInt, TempSensor, ...) are
5611 * not available in differential mode.
5612 * @note When configuring a channel 'i' in differential mode,
5613 * the channel 'i+1' is not usable separately.
5614 * @note Channels 0, 5, 6, 7, 9, 13, 14, 15, 16, 17, 18
5615 * are internally fixed to single-ended inputs configuration.
5616 * @note One or several values can be selected. In this case, the value
5617 * returned is null if all channels are in single ended-mode.
5618 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5619 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5620 * @param ADCx ADC instance
5621 * @param Channel This parameter can be a combination of the following values:
5622 * @arg @ref LL_ADC_CHANNEL_1
5623 * @arg @ref LL_ADC_CHANNEL_2
5624 * @arg @ref LL_ADC_CHANNEL_3
5625 * @arg @ref LL_ADC_CHANNEL_4
5626 * @arg @ref LL_ADC_CHANNEL_5
5627 * @arg @ref LL_ADC_CHANNEL_6
5628 * @arg @ref LL_ADC_CHANNEL_7
5629 * @arg @ref LL_ADC_CHANNEL_8
5630 * @arg @ref LL_ADC_CHANNEL_9
5631 * @arg @ref LL_ADC_CHANNEL_10
5632 * @arg @ref LL_ADC_CHANNEL_11
5633 * @arg @ref LL_ADC_CHANNEL_12
5634 * @arg @ref LL_ADC_CHANNEL_13
5635 * @arg @ref LL_ADC_CHANNEL_14
5636 * @arg @ref LL_ADC_CHANNEL_15
5637 * @retval 0: channel in single-ended mode, else: channel in differential mode
5638 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)5639 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
5640 {
5641 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5642 }
5643
5644 /**
5645 * @}
5646 */
5647
5648 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5649 * @{
5650 */
5651
5652 /**
5653 * @brief Set ADC analog watchdog monitored channels:
5654 * a single channel, multiple channels or all channels,
5655 * on ADC groups regular and-or injected.
5656 * @note Once monitored channels are selected, analog watchdog
5657 * is enabled.
5658 * @note In case of need to define a single channel to monitor
5659 * with analog watchdog from sequencer channel definition,
5660 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5661 * @note On this STM32 series, there are 2 kinds of analog watchdog
5662 * instance:
5663 * - AWD standard (instance AWD1):
5664 * - channels monitored: can monitor 1 channel or all channels.
5665 * - groups monitored: ADC groups regular and-or injected.
5666 * - resolution: resolution is not limited (corresponds to
5667 * ADC resolution configured).
5668 * - AWD flexible (instances AWD2, AWD3):
5669 * - channels monitored: flexible on channels monitored, selection is
5670 * channel wise, from from 1 to all channels.
5671 * Specificity of this analog watchdog: Multiple channels can
5672 * be selected. For example:
5673 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5674 * - groups monitored: not selection possible (monitoring on both
5675 * groups regular and injected).
5676 * Channels selected are monitored on groups regular and injected:
5677 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5678 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5679 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5680 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5681 * the 2 LSB are ignored.
5682 * @note On this STM32 series, setting of this feature is conditioned to
5683 * ADC state:
5684 * ADC must be disabled or enabled without conversion on going
5685 * on either groups regular or injected.
5686 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5687 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5688 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5689 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5690 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5691 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5692 * @param ADCx ADC instance
5693 * @param AWDy This parameter can be one of the following values:
5694 * @arg @ref LL_ADC_AWD1
5695 * @arg @ref LL_ADC_AWD2
5696 * @arg @ref LL_ADC_AWD3
5697 * @param AWDChannelGroup This parameter can be one of the following values:
5698 * @arg @ref LL_ADC_AWD_DISABLE
5699 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5700 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5701 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5702 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5703 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5704 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5705 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5706 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5707 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5708 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5709 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5710 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5711 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5712 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5713 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5714 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5715 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5716 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5717 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5718 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5719 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5720 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5721 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5722 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5723 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5724 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5725 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5726 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5727 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5728 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5729 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5730 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5731 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5732 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5733 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5734 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5735 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5736 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5737 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5738 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5739 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5740 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5741 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5742 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5743 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5744 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5745 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5746 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5747 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5748 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5749 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5750 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5751 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5752 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5753 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5754 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5755 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5756 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5757 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5758 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5759 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
5760 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
5761 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
5762 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
5763 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
5764 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
5765 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
5766 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
5767 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
5768 *
5769 * (0) On STM32H7RS, parameter available only on analog watchdog number: AWD1.\n
5770 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n
5771 * @retval None
5772 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5773 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5774 {
5775 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5776 /* in register and register position depending on parameter "AWDy". */
5777 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5778 /* containing other bits reserved for other purpose. */
5779 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
5780 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5781 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5782 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5783
5784 MODIFY_REG(*preg,
5785 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5786 AWDChannelGroup & AWDy);
5787 }
5788
5789 /**
5790 * @brief Get ADC analog watchdog monitored channel.
5791 * @note Usage of the returned channel number:
5792 * - To reinject this channel into another function LL_ADC_xxx:
5793 * the returned channel number is only partly formatted on definition
5794 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5795 * with parts of literals LL_ADC_CHANNEL_x or using
5796 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5797 * Then the selected literal LL_ADC_CHANNEL_x can be used
5798 * as parameter for another function.
5799 * - To get the channel number in decimal format:
5800 * process the returned value with the helper macro
5801 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5802 * Applicable only when the analog watchdog is set to monitor
5803 * one channel.
5804 * @note On this STM32 series, there are 2 kinds of analog watchdog
5805 * instance:
5806 * - AWD standard (instance AWD1):
5807 * - channels monitored: can monitor 1 channel or all channels.
5808 * - groups monitored: ADC groups regular and-or injected.
5809 * - resolution: resolution is not limited (corresponds to
5810 * ADC resolution configured).
5811 * - AWD flexible (instances AWD2, AWD3):
5812 * - channels monitored: flexible on channels monitored, selection is
5813 * channel wise, from from 1 to all channels.
5814 * Specificity of this analog watchdog: Multiple channels can
5815 * be selected. For example:
5816 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5817 * - groups monitored: not selection possible (monitoring on both
5818 * groups regular and injected).
5819 * Channels selected are monitored on groups regular and injected:
5820 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5821 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5822 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5823 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5824 * the 2 LSB are ignored.
5825 * @note On this STM32 series, setting of this feature is conditioned to
5826 * ADC state:
5827 * ADC must be disabled or enabled without conversion on going
5828 * on either groups regular or injected.
5829 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5830 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5831 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5832 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5833 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5834 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5835 * @param ADCx ADC instance
5836 * @param AWDy This parameter can be one of the following values:
5837 * @arg @ref LL_ADC_AWD1
5838 * @arg @ref LL_ADC_AWD2 (1)
5839 * @arg @ref LL_ADC_AWD3 (1)
5840 *
5841 * (1) On this AWD number, monitored channel can be retrieved
5842 * if only 1 channel is programmed (or none or all channels).
5843 * This function cannot retrieve monitored channel if
5844 * multiple channels are programmed simultaneously
5845 * by bitfield.
5846 * @retval Returned value can be one of the following values:
5847 * @arg @ref LL_ADC_AWD_DISABLE
5848 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5849 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5850 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5851 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5852 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5853 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5854 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5855 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5856 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5857 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5858 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5859 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5860 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5861 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5862 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5863 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5864 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5865 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5866 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5867 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5868 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5869 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5870 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5871 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5872 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5873 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5874 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5875 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5876 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5877 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5878 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5879 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5880 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5881 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5882 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5883 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5884 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5885 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5886 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5887 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5888 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5889 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5890 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5891 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5892 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5893 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5894 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5895 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5896 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5897 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5898 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5899 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5900 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5901 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5902 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5903 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5904 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5905 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5906 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5907 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5908 *
5909 * (0) On STM32H7RS, parameter available only on analog watchdog number: AWD1.
5910 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)5911 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
5912 {
5913 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
5914 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5915 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5916 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5917
5918 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5919
5920 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
5921 /* (parameter value LL_ADC_AWD_DISABLE). */
5922 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5923 /* or a single channel. */
5924 if (analog_wd_monit_channels != 0UL)
5925 {
5926 if (AWDy == LL_ADC_AWD1)
5927 {
5928 if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL)
5929 {
5930 /* AWD monitoring a group of channels */
5931 analog_wd_monit_channels = ((analog_wd_monit_channels
5932 | (ADC_AWD_CR23_CHANNEL_MASK)
5933 )
5934 & (~(ADC_CFGR_AWD1CH))
5935 );
5936 }
5937 else
5938 {
5939 /* AWD monitoring a single channel */
5940 analog_wd_monit_channels = (analog_wd_monit_channels
5941 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos))
5942 );
5943 }
5944 }
5945 else
5946 {
5947 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5948 {
5949 /* AWD monitoring a group of channels */
5950 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
5951 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5952 );
5953 }
5954 else
5955 {
5956 /* AWD monitoring a single channel */
5957 /* AWD monitoring a group of channels */
5958 analog_wd_monit_channels = (analog_wd_monit_channels
5959 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5960 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos)
5961 );
5962 }
5963 }
5964 }
5965
5966 return analog_wd_monit_channels;
5967 }
5968
5969 /**
5970 * @brief Set ADC analog watchdog thresholds value of both thresholds
5971 * high and low.
5972 * @note If value of only one threshold high or low must be set,
5973 * use function @ref LL_ADC_SetAnalogWDThresholds().
5974 * @note In case of ADC resolution different of 12 bits,
5975 * analog watchdog thresholds data require a specific shift.
5976 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5977 * @note On this STM32 series, there are 2 kinds of analog watchdog
5978 * instance:
5979 * - AWD standard (instance AWD1):
5980 * - channels monitored: can monitor 1 channel or all channels.
5981 * - groups monitored: ADC groups regular and-or injected.
5982 * - resolution: resolution is not limited (corresponds to
5983 * ADC resolution configured).
5984 * - AWD flexible (instances AWD2, AWD3):
5985 * - channels monitored: flexible on channels monitored, selection is
5986 * channel wise, from from 1 to all channels.
5987 * Specificity of this analog watchdog: Multiple channels can
5988 * be selected. For example:
5989 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5990 * - groups monitored: not selection possible (monitoring on both
5991 * groups regular and injected).
5992 * Channels selected are monitored on groups regular and injected:
5993 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5994 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5995 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5996 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5997 * the 2 LSB are ignored.
5998 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5999 * impacted: the comparison of analog watchdog thresholds is done on
6000 * oversampling final computation (after ratio and shift application):
6001 * ADC data register bitfield [15:4] (12 most significant bits).
6002 * Examples:
6003 * - Oversampling ratio and shift selected to have ADC conversion data
6004 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
6005 * ADC analog watchdog thresholds must be divided by 16.
6006 * - Oversampling ratio and shift selected to have ADC conversion data
6007 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
6008 * ADC analog watchdog thresholds must be divided by 4.
6009 * - Oversampling ratio and shift selected to have ADC conversion data
6010 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
6011 * ADC analog watchdog thresholds match directly to ADC data register.
6012 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
6013 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
6014 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
6015 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
6016 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
6017 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
6018 * @param ADCx ADC instance
6019 * @param AWDy This parameter can be one of the following values:
6020 * @arg @ref LL_ADC_AWD1
6021 * @arg @ref LL_ADC_AWD2
6022 * @arg @ref LL_ADC_AWD3
6023 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
6024 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
6025 * @retval None
6026 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)6027 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
6028 uint32_t AWDThresholdLowValue)
6029 {
6030 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6031 /* position in register and register position depending on parameter */
6032 /* "AWDy". */
6033 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6034 /* containing other bits reserved for other purpose. */
6035 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6036 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6037
6038 MODIFY_REG(*preg,
6039 ADC_TR1_HT1 | ADC_TR1_LT1,
6040 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
6041 }
6042
6043 /**
6044 * @brief Set ADC analog watchdog threshold value of threshold
6045 * high or low.
6046 * @note If values of both thresholds high or low must be set,
6047 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
6048 * @note In case of ADC resolution different of 12 bits,
6049 * analog watchdog thresholds data require a specific shift.
6050 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6051 * @note On this STM32 series, there are 2 kinds of analog watchdog
6052 * instance:
6053 * - AWD standard (instance AWD1):
6054 * - channels monitored: can monitor 1 channel or all channels.
6055 * - groups monitored: ADC groups regular and-or injected.
6056 * - resolution: resolution is not limited (corresponds to
6057 * ADC resolution configured).
6058 * - AWD flexible (instances AWD2, AWD3):
6059 * - channels monitored: flexible on channels monitored, selection is
6060 * channel wise, from from 1 to all channels.
6061 * Specificity of this analog watchdog: Multiple channels can
6062 * be selected. For example:
6063 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6064 * - groups monitored: not selection possible (monitoring on both
6065 * groups regular and injected).
6066 * Channels selected are monitored on groups regular and injected:
6067 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6068 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6069 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6070 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6071 * the 2 LSB are ignored.
6072 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6073 * impacted: the comparison of analog watchdog thresholds is done on
6074 * oversampling final computation (after ratio and shift application):
6075 * ADC data register bitfield [15:4] (12 most significant bits).
6076 * Examples:
6077 * - Oversampling ratio and shift selected to have ADC conversion data
6078 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
6079 * ADC analog watchdog thresholds must be divided by 16.
6080 * - Oversampling ratio and shift selected to have ADC conversion data
6081 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
6082 * ADC analog watchdog thresholds must be divided by 4.
6083 * - Oversampling ratio and shift selected to have ADC conversion data
6084 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
6085 * ADC analog watchdog thresholds match directly to ADC data register.
6086 * @note On this STM32 series, setting of this feature is not conditioned to
6087 * ADC state:
6088 * ADC can be disabled, enabled with or without conversion on going
6089 * on either ADC groups regular or injected.
6090 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
6091 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
6092 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
6093 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
6094 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
6095 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
6096 * @param ADCx ADC instance
6097 * @param AWDy This parameter can be one of the following values:
6098 * @arg @ref LL_ADC_AWD1
6099 * @arg @ref LL_ADC_AWD2
6100 * @arg @ref LL_ADC_AWD3
6101 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6102 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6103 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6104 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
6105 * @retval None
6106 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)6107 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
6108 uint32_t AWDThresholdValue)
6109 {
6110 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6111 /* position in register and register position depending on parameters */
6112 /* "AWDThresholdsHighLow" and "AWDy". */
6113 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6114 /* containing other bits reserved for other purpose. */
6115 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6116 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6117
6118 MODIFY_REG(*preg,
6119 AWDThresholdsHighLow,
6120 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6121 }
6122
6123 /**
6124 * @brief Get ADC analog watchdog threshold value of threshold high,
6125 * threshold low or raw data with ADC thresholds high and low
6126 * concatenated.
6127 * @note If raw data with ADC thresholds high and low is retrieved,
6128 * the data of each threshold high or low can be isolated
6129 * using helper macro:
6130 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
6131 * @note In case of ADC resolution different of 12 bits,
6132 * analog watchdog thresholds data require a specific shift.
6133 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
6134 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
6135 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
6136 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
6137 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
6138 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
6139 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
6140 * @param ADCx ADC instance
6141 * @param AWDy This parameter can be one of the following values:
6142 * @arg @ref LL_ADC_AWD1
6143 * @arg @ref LL_ADC_AWD2
6144 * @arg @ref LL_ADC_AWD3
6145 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6146 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6147 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6148 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
6149 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6150 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)6151 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
6152 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
6153 {
6154 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6155 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6156
6157 return (uint32_t)(READ_BIT(*preg,
6158 (AWDThresholdsHighLow | ADC_TR1_LT1))
6159 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
6160 & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
6161 }
6162
6163 /**
6164 * @brief Set ADC analog watchdog filtering configuration
6165 * @note On this STM32 series, setting of this feature is conditioned to
6166 * ADC state:
6167 * ADC must be disabled or enabled without conversion on going
6168 * on either groups regular or injected.
6169 * @note On this STM32 series, this feature is only available on first
6170 * analog watchdog (AWD1)
6171 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
6172 * @param ADCx ADC instance
6173 * @param AWDy This parameter can be one of the following values:
6174 * @arg @ref LL_ADC_AWD1
6175 * @param FilteringConfig This parameter can be one of the following values:
6176 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6177 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6178 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6179 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6180 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6181 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6182 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6183 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6184 * @retval None
6185 */
LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t FilteringConfig)6186 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
6187 {
6188 /* Prevent unused argument(s) compilation warning */
6189 (void)(AWDy);
6190 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
6191 }
6192
6193 /**
6194 * @brief Get ADC analog watchdog filtering configuration
6195 * @note On this STM32 series, this feature is only available on first
6196 * analog watchdog (AWD1)
6197 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
6198 * @param ADCx ADC instance
6199 * @param AWDy This parameter can be one of the following values:
6200 * @arg @ref LL_ADC_AWD1
6201 * @retval Returned value can be:
6202 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6203 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6204 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6205 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6206 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6207 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6208 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6209 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6210 */
LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef * ADCx,uint32_t AWDy)6211 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
6212 {
6213 /* Prevent unused argument(s) compilation warning */
6214 (void)(AWDy);
6215 return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
6216 }
6217
6218 /**
6219 * @}
6220 */
6221
6222 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
6223 * @{
6224 */
6225
6226 /**
6227 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
6228 * (availability of ADC group injected depends on STM32 series).
6229 * @note If both groups regular and injected are selected,
6230 * specify behavior of ADC group injected interrupting
6231 * group regular: when ADC group injected is triggered,
6232 * the oversampling on ADC group regular is either
6233 * temporary stopped and continued, or resumed from start
6234 * (oversampler buffer reset).
6235 * @note On this STM32 series, setting of this feature is conditioned to
6236 * ADC state:
6237 * ADC must be disabled or enabled without conversion on going
6238 * on either groups regular or injected.
6239 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
6240 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
6241 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
6242 * @param ADCx ADC instance
6243 * @param OvsScope This parameter can be one of the following values:
6244 * @arg @ref LL_ADC_OVS_DISABLE
6245 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6246 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6247 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6248 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6249 * @retval None
6250 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)6251 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6252 {
6253 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6254 }
6255
6256 /**
6257 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
6258 * (availability of ADC group injected depends on STM32 series).
6259 * @note If both groups regular and injected are selected,
6260 * specify behavior of ADC group injected interrupting
6261 * group regular: when ADC group injected is triggered,
6262 * the oversampling on ADC group regular is either
6263 * temporary stopped and continued, or resumed from start
6264 * (oversampler buffer reset).
6265 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
6266 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
6267 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
6268 * @param ADCx ADC instance
6269 * @retval Returned value can be one of the following values:
6270 * @arg @ref LL_ADC_OVS_DISABLE
6271 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6272 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6273 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6274 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6275 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)6276 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
6277 {
6278 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6279 }
6280
6281 /**
6282 * @brief Set ADC oversampling discontinuous mode (triggered mode)
6283 * on the selected ADC group.
6284 * @note Number of oversampled conversions are done either in:
6285 * - continuous mode (all conversions of oversampling ratio
6286 * are done from 1 trigger)
6287 * - discontinuous mode (each conversion of oversampling ratio
6288 * needs a trigger)
6289 * @note On this STM32 series, setting of this feature is conditioned to
6290 * ADC state:
6291 * ADC must be disabled or enabled without conversion on going
6292 * on group regular.
6293 * @note On this STM32 series, oversampling discontinuous mode
6294 * (triggered mode) can be used only when oversampling is
6295 * set on group regular only and in resumed mode.
6296 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
6297 * @param ADCx ADC instance
6298 * @param OverSamplingDiscont This parameter can be one of the following values:
6299 * @arg @ref LL_ADC_OVS_REG_CONT
6300 * @arg @ref LL_ADC_OVS_REG_DISCONT
6301 * @retval None
6302 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)6303 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6304 {
6305 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6306 }
6307
6308 /**
6309 * @brief Get ADC oversampling discontinuous mode (triggered mode)
6310 * on the selected ADC group.
6311 * @note Number of oversampled conversions are done either in:
6312 * - continuous mode (all conversions of oversampling ratio
6313 * are done from 1 trigger)
6314 * - discontinuous mode (each conversion of oversampling ratio
6315 * needs a trigger)
6316 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
6317 * @param ADCx ADC instance
6318 * @retval Returned value can be one of the following values:
6319 * @arg @ref LL_ADC_OVS_REG_CONT
6320 * @arg @ref LL_ADC_OVS_REG_DISCONT
6321 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)6322 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
6323 {
6324 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6325 }
6326
6327 /**
6328 * @brief Set ADC oversampling
6329 * (impacting both ADC groups regular and injected)
6330 * @note This function set the 2 items of oversampling configuration:
6331 * - ratio
6332 * - shift
6333 * @note On this STM32 series, setting of this feature is conditioned to
6334 * ADC state:
6335 * ADC must be disabled or enabled without conversion on going
6336 * on either groups regular or injected.
6337 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6338 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6339 * @param ADCx ADC instance
6340 * @param Ratio This parameter can be one of the following values:
6341 * @arg @ref LL_ADC_OVS_RATIO_2
6342 * @arg @ref LL_ADC_OVS_RATIO_4
6343 * @arg @ref LL_ADC_OVS_RATIO_8
6344 * @arg @ref LL_ADC_OVS_RATIO_16
6345 * @arg @ref LL_ADC_OVS_RATIO_32
6346 * @arg @ref LL_ADC_OVS_RATIO_64
6347 * @arg @ref LL_ADC_OVS_RATIO_128
6348 * @arg @ref LL_ADC_OVS_RATIO_256
6349 * @param Shift This parameter can be one of the following values:
6350 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6351 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6352 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6353 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6354 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6355 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6356 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6357 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6358 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6359 * @retval None
6360 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)6361 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6362 {
6363 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
6364 }
6365
6366 /**
6367 * @brief Get ADC oversampling ratio
6368 * (impacting both ADC groups regular and injected)
6369 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6370 * @param ADCx ADC instance
6371 * @retval Ratio This parameter can be one of the following values:
6372 * @arg @ref LL_ADC_OVS_RATIO_2
6373 * @arg @ref LL_ADC_OVS_RATIO_4
6374 * @arg @ref LL_ADC_OVS_RATIO_8
6375 * @arg @ref LL_ADC_OVS_RATIO_16
6376 * @arg @ref LL_ADC_OVS_RATIO_32
6377 * @arg @ref LL_ADC_OVS_RATIO_64
6378 * @arg @ref LL_ADC_OVS_RATIO_128
6379 * @arg @ref LL_ADC_OVS_RATIO_256
6380 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)6381 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
6382 {
6383 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
6384 }
6385
6386 /**
6387 * @brief Get ADC oversampling shift
6388 * (impacting both ADC groups regular and injected)
6389 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6390 * @param ADCx ADC instance
6391 * @retval Shift This parameter can be one of the following values:
6392 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6393 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6394 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6395 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6396 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6397 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6398 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6399 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6400 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6401 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)6402 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
6403 {
6404 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6405 }
6406
6407 /**
6408 * @}
6409 */
6410
6411 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
6412 * @{
6413 */
6414
6415 #if defined(ADC_MULTIMODE_SUPPORT)
6416 /**
6417 * @brief Set ADC multimode configuration to operate in independent mode
6418 * or multimode (for devices with several ADC instances).
6419 * @note If multimode configuration: the selected ADC instance is
6420 * either master or slave depending on hardware.
6421 * Refer to reference manual.
6422 * @note On this STM32 series, setting of this feature is conditioned to
6423 * ADC state:
6424 * All ADC instances of the ADC common group must be disabled.
6425 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6426 * ADC instance or by using helper macro
6427 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6428 * @rmtoll CCR DUAL LL_ADC_SetMultimode
6429 * @param ADCxy_COMMON ADC common instance
6430 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6431 * @param Multimode This parameter can be one of the following values:
6432 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6433 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6434 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6435 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6436 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6437 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6438 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6439 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6440 * @retval None
6441 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)6442 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6443 {
6444 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6445 }
6446
6447 /**
6448 * @brief Get ADC multimode configuration to operate in independent mode
6449 * or multimode (for devices with several ADC instances).
6450 * @note If multimode configuration: the selected ADC instance is
6451 * either master or slave depending on hardware.
6452 * Refer to reference manual.
6453 * @rmtoll CCR DUAL LL_ADC_GetMultimode
6454 * @param ADCxy_COMMON ADC common instance
6455 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6456 * @retval Returned value can be one of the following values:
6457 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6458 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6459 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6460 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6461 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6462 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6463 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6464 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6465 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)6466 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
6467 {
6468 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6469 }
6470
6471 /**
6472 * @brief Set ADC multimode conversion data transfer: no transfer
6473 * or transfer by DMA.
6474 * @note If ADC multimode transfer by DMA is not selected:
6475 * each ADC uses its own DMA channel, with its individual
6476 * DMA transfer settings.
6477 * If ADC multimode transfer by DMA is selected:
6478 * One DMA channel is used for both ADC (DMA of ADC master)
6479 * Specifies the DMA requests mode:
6480 * - Limited mode (One shot mode): DMA transfer requests are stopped
6481 * when number of DMA data transfers (number of
6482 * ADC conversions) is reached.
6483 * This ADC mode is intended to be used with DMA mode non-circular.
6484 * - Unlimited mode: DMA transfer requests are unlimited,
6485 * whatever number of DMA data transfers (number of
6486 * ADC conversions).
6487 * This ADC mode is intended to be used with DMA mode circular.
6488 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6489 * mode non-circular:
6490 * when DMA transfers size will be reached, DMA will stop transfers of
6491 * ADC conversions data ADC will raise an overrun error
6492 * (overrun flag and interruption if enabled).
6493 * @note How to retrieve multimode conversion data:
6494 * Whatever multimode transfer by DMA setting: using function
6495 * @ref LL_ADC_REG_ReadMultiConversionData32().
6496 * If ADC multimode transfer by DMA is selected: conversion data
6497 * is a raw data with ADC master and slave concatenated.
6498 * A macro is available to get the conversion data of
6499 * ADC master or ADC slave: see helper macro
6500 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6501 * @note On this STM32 series, setting of this feature is conditioned to
6502 * ADC state:
6503 * All ADC instances of the ADC common group must be disabled
6504 * or enabled without conversion on going on group regular.
6505 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
6506 * CCR DMACFG LL_ADC_SetMultiDMATransfer
6507 * @param ADCxy_COMMON ADC common instance
6508 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6509 * @param MultiDMATransfer This parameter can be one of the following values:
6510 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6511 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6512 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6513 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6514 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6515 * @retval None
6516 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)6517 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6518 {
6519 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
6520 }
6521
6522 /**
6523 * @brief Get ADC multimode conversion data transfer: no transfer
6524 * or transfer by DMA.
6525 * @note If ADC multimode transfer by DMA is not selected:
6526 * each ADC uses its own DMA channel, with its individual
6527 * DMA transfer settings.
6528 * If ADC multimode transfer by DMA is selected:
6529 * One DMA channel is used for both ADC (DMA of ADC master)
6530 * Specifies the DMA requests mode:
6531 * - Limited mode (One shot mode): DMA transfer requests are stopped
6532 * when number of DMA data transfers (number of
6533 * ADC conversions) is reached.
6534 * This ADC mode is intended to be used with DMA mode non-circular.
6535 * - Unlimited mode: DMA transfer requests are unlimited,
6536 * whatever number of DMA data transfers (number of
6537 * ADC conversions).
6538 * This ADC mode is intended to be used with DMA mode circular.
6539 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6540 * mode non-circular:
6541 * when DMA transfers size will be reached, DMA will stop transfers of
6542 * ADC conversions data ADC will raise an overrun error
6543 * (overrun flag and interruption if enabled).
6544 * @note How to retrieve multimode conversion data:
6545 * Whatever multimode transfer by DMA setting: using function
6546 * @ref LL_ADC_REG_ReadMultiConversionData32().
6547 * If ADC multimode transfer by DMA is selected: conversion data
6548 * is a raw data with ADC master and slave concatenated.
6549 * A macro is available to get the conversion data of
6550 * ADC master or ADC slave: see helper macro
6551 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6552 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
6553 * CCR DMACFG LL_ADC_GetMultiDMATransfer
6554 * @param ADCxy_COMMON ADC common instance
6555 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6556 * @retval Returned value can be one of the following values:
6557 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6558 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6559 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6560 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6561 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6562 */
LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef * ADCxy_COMMON)6563 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
6564 {
6565 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
6566 }
6567
6568 /**
6569 * @brief Set ADC multimode delay between 2 sampling phases.
6570 * @note The sampling delay range depends on ADC resolution:
6571 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6572 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6573 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6574 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6575 * @note On this STM32 series, setting of this feature is conditioned to
6576 * ADC state:
6577 * All ADC instances of the ADC common group must be disabled.
6578 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6579 * ADC instance or by using helper macro helper macro
6580 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6581 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6582 * @param ADCxy_COMMON ADC common instance
6583 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6584 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6585 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6586 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6587 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6588 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6589 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6590 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6591 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6592 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6593 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6594 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6595 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6596 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6597 *
6598 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6599 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6600 * (3) Parameter available only if ADC resolution is 12 bits.
6601 * @retval None
6602 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)6603 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6604 {
6605 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6606 }
6607
6608 /**
6609 * @brief Get ADC multimode delay between 2 sampling phases.
6610 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6611 * @param ADCxy_COMMON ADC common instance
6612 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6613 * @retval Returned value can be one of the following values:
6614 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6615 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6616 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6617 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6618 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6619 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6620 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6621 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6622 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6623 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6624 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6625 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6626 *
6627 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6628 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6629 * (3) Parameter available only if ADC resolution is 12 bits.
6630 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)6631 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
6632 {
6633 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6634 }
6635 #endif /* ADC_MULTIMODE_SUPPORT */
6636
6637 /**
6638 * @}
6639 */
6640 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6641 * @{
6642 */
6643
6644 /**
6645 * @brief Put ADC instance in deep power down state.
6646 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6647 * state, the internal analog calibration is lost. After exiting from
6648 * deep power down, calibration must be relaunched or calibration factor
6649 * (preliminarily saved) must be set back into calibration register.
6650 * @note On this STM32 series, setting of this feature is conditioned to
6651 * ADC state:
6652 * ADC must be ADC disabled.
6653 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6654 * @param ADCx ADC instance
6655 * @retval None
6656 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)6657 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6658 {
6659 /* Note: Write register with some additional bits forced to state reset */
6660 /* instead of modifying only the selected bit for this function, */
6661 /* to not interfere with bits with HW property "rs". */
6662 MODIFY_REG(ADCx->CR,
6663 ADC_CR_BITS_PROPERTY_RS,
6664 ADC_CR_DEEPPWD);
6665 }
6666
6667 /**
6668 * @brief Disable ADC deep power down mode.
6669 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6670 * state, the internal analog calibration is lost. After exiting from
6671 * deep power down, calibration must be relaunched or calibration factor
6672 * (preliminarily saved) must be set back into calibration register.
6673 * @note On this STM32 series, setting of this feature is conditioned to
6674 * ADC state:
6675 * ADC must be ADC disabled.
6676 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6677 * @param ADCx ADC instance
6678 * @retval None
6679 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)6680 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6681 {
6682 /* Note: Write register with some additional bits forced to state reset */
6683 /* instead of modifying only the selected bit for this function, */
6684 /* to not interfere with bits with HW property "rs". */
6685 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6686 }
6687
6688 /**
6689 * @brief Get the selected ADC instance deep power down state.
6690 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6691 * @param ADCx ADC instance
6692 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6693 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)6694 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
6695 {
6696 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6697 }
6698
6699 /**
6700 * @brief Enable ADC instance internal voltage regulator.
6701 * @note On this STM32 series, after ADC internal voltage regulator enable,
6702 * a delay for ADC internal voltage regulator stabilization
6703 * is required before performing a ADC calibration or ADC enable.
6704 * Refer to device datasheet, parameter tADCVREG_STUP.
6705 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6706 * @note On this STM32 series, setting of this feature is conditioned to
6707 * ADC state:
6708 * ADC must be ADC disabled.
6709 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6710 * @param ADCx ADC instance
6711 * @retval None
6712 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)6713 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6714 {
6715 /* Note: Write register with some additional bits forced to state reset */
6716 /* instead of modifying only the selected bit for this function, */
6717 /* to not interfere with bits with HW property "rs". */
6718 MODIFY_REG(ADCx->CR,
6719 ADC_CR_BITS_PROPERTY_RS,
6720 ADC_CR_ADVREGEN);
6721 }
6722
6723 /**
6724 * @brief Disable ADC internal voltage regulator.
6725 * @note On this STM32 series, setting of this feature is conditioned to
6726 * ADC state:
6727 * ADC must be ADC disabled.
6728 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6729 * @param ADCx ADC instance
6730 * @retval None
6731 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)6732 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6733 {
6734 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6735 }
6736
6737 /**
6738 * @brief Get the selected ADC instance internal voltage regulator state.
6739 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6740 * @param ADCx ADC instance
6741 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6742 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)6743 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
6744 {
6745 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6746 }
6747
6748 /**
6749 * @brief Enable the selected ADC instance.
6750 * @note On this STM32 series, after ADC enable, a delay for
6751 * ADC internal analog stabilization is required before performing a
6752 * ADC conversion start.
6753 * Refer to device datasheet, parameter tSTAB.
6754 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6755 * is enabled and when conversion clock is active.
6756 * (not only core clock: this ADC has a dual clock domain)
6757 * @note On this STM32 series, setting of this feature is conditioned to
6758 * ADC state:
6759 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6760 * @rmtoll CR ADEN LL_ADC_Enable
6761 * @param ADCx ADC instance
6762 * @retval None
6763 */
LL_ADC_Enable(ADC_TypeDef * ADCx)6764 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6765 {
6766 /* Note: Write register with some additional bits forced to state reset */
6767 /* instead of modifying only the selected bit for this function, */
6768 /* to not interfere with bits with HW property "rs". */
6769 MODIFY_REG(ADCx->CR,
6770 ADC_CR_BITS_PROPERTY_RS,
6771 ADC_CR_ADEN);
6772 }
6773
6774 /**
6775 * @brief Disable the selected ADC instance.
6776 * @note On this STM32 series, setting of this feature is conditioned to
6777 * ADC state:
6778 * ADC must be not disabled. Must be enabled without conversion on going
6779 * on either groups regular or injected.
6780 * @rmtoll CR ADDIS LL_ADC_Disable
6781 * @param ADCx ADC instance
6782 * @retval None
6783 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6784 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6785 {
6786 /* Note: Write register with some additional bits forced to state reset */
6787 /* instead of modifying only the selected bit for this function, */
6788 /* to not interfere with bits with HW property "rs". */
6789 MODIFY_REG(ADCx->CR,
6790 ADC_CR_BITS_PROPERTY_RS,
6791 ADC_CR_ADDIS);
6792 }
6793
6794 /**
6795 * @brief Get the selected ADC instance enable state.
6796 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6797 * is enabled and when conversion clock is active.
6798 * (not only core clock: this ADC has a dual clock domain)
6799 * @rmtoll CR ADEN LL_ADC_IsEnabled
6800 * @param ADCx ADC instance
6801 * @retval 0: ADC is disabled, 1: ADC is enabled.
6802 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)6803 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
6804 {
6805 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6806 }
6807
6808 /**
6809 * @brief Get the selected ADC instance disable state.
6810 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6811 * @param ADCx ADC instance
6812 * @retval 0: no ADC disable command on going.
6813 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)6814 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
6815 {
6816 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6817 }
6818
6819 /**
6820 * @brief Start ADC calibration in the mode single-ended
6821 * or differential (for devices with differential mode available).
6822 * @note On this STM32 series, a minimum number of ADC clock cycles
6823 * are required between ADC end of calibration and ADC enable.
6824 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6825 * @note For devices with differential mode available:
6826 * Calibration of offset is specific to each of
6827 * single-ended and differential modes
6828 * (calibration run must be performed for each of these
6829 * differential modes, if used afterwards and if the application
6830 * requires their calibration).
6831 * @note On this STM32 series, setting of this feature is conditioned to
6832 * ADC state:
6833 * ADC must be ADC disabled.
6834 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6835 * CR ADCALDIF LL_ADC_StartCalibration
6836 * @param ADCx ADC instance
6837 * @param SingleDiff This parameter can be one of the following values:
6838 * @arg @ref LL_ADC_SINGLE_ENDED
6839 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6840 * @retval None
6841 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6842 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6843 {
6844 /* Note: Write register with some additional bits forced to state reset */
6845 /* instead of modifying only the selected bit for this function, */
6846 /* to not interfere with bits with HW property "rs". */
6847 MODIFY_REG(ADCx->CR,
6848 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6849 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6850 }
6851
6852 /**
6853 * @brief Get ADC calibration state.
6854 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6855 * @param ADCx ADC instance
6856 * @retval 0: calibration complete, 1: calibration in progress.
6857 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)6858 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
6859 {
6860 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6861 }
6862
6863 /**
6864 * @}
6865 */
6866
6867 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6868 * @{
6869 */
6870
6871 /**
6872 * @brief Start ADC group regular conversion.
6873 * @note On this STM32 series, this function is relevant for both
6874 * internal trigger (SW start) and external trigger:
6875 * - If ADC trigger has been set to software start, ADC conversion
6876 * starts immediately.
6877 * - If ADC trigger has been set to external trigger, ADC conversion
6878 * will start at next trigger event (on the selected trigger edge)
6879 * following the ADC start conversion command.
6880 * @note On this STM32 series, setting of this feature is conditioned to
6881 * ADC state:
6882 * ADC must be enabled without conversion on going on group regular,
6883 * without conversion stop command on going on group regular,
6884 * without ADC disable command on going.
6885 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6886 * @param ADCx ADC instance
6887 * @retval None
6888 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6889 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6890 {
6891 /* Note: Write register with some additional bits forced to state reset */
6892 /* instead of modifying only the selected bit for this function, */
6893 /* to not interfere with bits with HW property "rs". */
6894 MODIFY_REG(ADCx->CR,
6895 ADC_CR_BITS_PROPERTY_RS,
6896 ADC_CR_ADSTART);
6897 }
6898
6899 /**
6900 * @brief Stop ADC group regular conversion.
6901 * @note On this STM32 series, setting of this feature is conditioned to
6902 * ADC state:
6903 * ADC must be enabled with conversion on going on group regular,
6904 * without ADC disable command on going.
6905 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6906 * @param ADCx ADC instance
6907 * @retval None
6908 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6909 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6910 {
6911 /* Note: Write register with some additional bits forced to state reset */
6912 /* instead of modifying only the selected bit for this function, */
6913 /* to not interfere with bits with HW property "rs". */
6914 MODIFY_REG(ADCx->CR,
6915 ADC_CR_BITS_PROPERTY_RS,
6916 ADC_CR_ADSTP);
6917 }
6918
6919 /**
6920 * @brief Get ADC group regular conversion state.
6921 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6922 * @param ADCx ADC instance
6923 * @retval 0: no conversion is on going on ADC group regular.
6924 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)6925 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
6926 {
6927 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6928 }
6929
6930 /**
6931 * @brief Get ADC group regular command of conversion stop state
6932 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6933 * @param ADCx ADC instance
6934 * @retval 0: no command of conversion stop is on going on ADC group regular.
6935 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)6936 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
6937 {
6938 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6939 }
6940
6941 /**
6942 * @brief Start ADC sampling phase for sampling time trigger mode
6943 * @note This function is relevant only when
6944 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
6945 * using @ref LL_ADC_REG_SetSamplingMode
6946 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
6947 * @note On this STM32 series, setting of this feature is conditioned to
6948 * ADC state:
6949 * ADC must be enabled without conversion on going on group regular,
6950 * without conversion stop command on going on group regular,
6951 * without ADC disable command on going.
6952 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
6953 * @param ADCx ADC instance
6954 * @retval None
6955 */
LL_ADC_REG_StartSamplingPhase(ADC_TypeDef * ADCx)6956 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
6957 {
6958 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
6959 }
6960
6961 /**
6962 * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
6963 * @note This function is relevant only when
6964 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
6965 * using @ref LL_ADC_REG_SetSamplingMode
6966 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
6967 * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
6968 * the sampling phase
6969 * @note On this STM32 series, setting of this feature is conditioned to
6970 * ADC state:
6971 * ADC must be enabled without conversion on going on group regular,
6972 * without conversion stop command on going on group regular,
6973 * without ADC disable command on going.
6974 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
6975 * @param ADCx ADC instance
6976 * @retval None
6977 */
LL_ADC_REG_StopSamplingPhase(ADC_TypeDef * ADCx)6978 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
6979 {
6980 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
6981 }
6982
6983 /**
6984 * @brief Get ADC group regular conversion data, range fit for
6985 * all ADC configurations: all ADC resolutions and
6986 * all oversampling increased data width (for devices
6987 * with feature oversampling).
6988 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6989 * @param ADCx ADC instance
6990 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6991 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)6992 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
6993 {
6994 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6995 }
6996
6997 /**
6998 * @brief Get ADC group regular conversion data, range fit for
6999 * ADC resolution 12 bits.
7000 * @note For devices with feature oversampling: Oversampling
7001 * can increase data width, function for extended range
7002 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7003 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
7004 * @param ADCx ADC instance
7005 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7006 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)7007 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
7008 {
7009 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7010 }
7011
7012 /**
7013 * @brief Get ADC group regular conversion data, range fit for
7014 * ADC resolution 10 bits.
7015 * @note For devices with feature oversampling: Oversampling
7016 * can increase data width, function for extended range
7017 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7018 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
7019 * @param ADCx ADC instance
7020 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7021 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)7022 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
7023 {
7024 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7025 }
7026
7027 /**
7028 * @brief Get ADC group regular conversion data, range fit for
7029 * ADC resolution 8 bits.
7030 * @note For devices with feature oversampling: Oversampling
7031 * can increase data width, function for extended range
7032 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7033 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
7034 * @param ADCx ADC instance
7035 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7036 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)7037 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
7038 {
7039 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7040 }
7041
7042 /**
7043 * @brief Get ADC group regular conversion data, range fit for
7044 * ADC resolution 6 bits.
7045 * @note For devices with feature oversampling: Oversampling
7046 * can increase data width, function for extended range
7047 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7048 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
7049 * @param ADCx ADC instance
7050 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7051 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)7052 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
7053 {
7054 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7055 }
7056
7057 #if defined(ADC_MULTIMODE_SUPPORT)
7058 /**
7059 * @brief Get ADC multimode conversion data of ADC master, ADC slave
7060 * or raw data with ADC master and slave concatenated.
7061 * @note If raw data with ADC master and slave concatenated is retrieved,
7062 * a macro is available to get the conversion data of
7063 * ADC master or ADC slave: see helper macro
7064 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7065 * (however this macro is mainly intended for multimode
7066 * transfer by DMA, because this function can do the same
7067 * by getting multimode conversion data of ADC master or ADC slave
7068 * separately).
7069 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
7070 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
7071 * @param ADCxy_COMMON ADC common instance
7072 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7073 * @param ConversionData This parameter can be one of the following values:
7074 * @arg @ref LL_ADC_MULTI_MASTER
7075 * @arg @ref LL_ADC_MULTI_SLAVE
7076 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
7077 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7078 */
LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)7079 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
7080 uint32_t ConversionData)
7081 {
7082 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
7083 ConversionData)
7084 >> (POSITION_VAL(ConversionData) & 0x1FUL)
7085 );
7086 }
7087 #endif /* ADC_MULTIMODE_SUPPORT */
7088
7089 /**
7090 * @}
7091 */
7092
7093 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
7094 * @{
7095 */
7096
7097 /**
7098 * @brief Start ADC group injected conversion.
7099 * @note On this STM32 series, this function is relevant for both
7100 * internal trigger (SW start) and external trigger:
7101 * - If ADC trigger has been set to software start, ADC conversion
7102 * starts immediately.
7103 * - If ADC trigger has been set to external trigger, ADC conversion
7104 * will start at next trigger event (on the selected trigger edge)
7105 * following the ADC start conversion command.
7106 * @note On this STM32 series, setting of this feature is conditioned to
7107 * ADC state:
7108 * ADC must be enabled without conversion on going on group injected,
7109 * without conversion stop command on going on group injected,
7110 * without ADC disable command on going.
7111 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
7112 * @param ADCx ADC instance
7113 * @retval None
7114 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)7115 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
7116 {
7117 /* Note: Write register with some additional bits forced to state reset */
7118 /* instead of modifying only the selected bit for this function, */
7119 /* to not interfere with bits with HW property "rs". */
7120 MODIFY_REG(ADCx->CR,
7121 ADC_CR_BITS_PROPERTY_RS,
7122 ADC_CR_JADSTART);
7123 }
7124
7125 /**
7126 * @brief Stop ADC group injected conversion.
7127 * @note On this STM32 series, setting of this feature is conditioned to
7128 * ADC state:
7129 * ADC must be enabled with conversion on going on group injected,
7130 * without ADC disable command on going.
7131 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
7132 * @param ADCx ADC instance
7133 * @retval None
7134 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)7135 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7136 {
7137 /* Note: Write register with some additional bits forced to state reset */
7138 /* instead of modifying only the selected bit for this function, */
7139 /* to not interfere with bits with HW property "rs". */
7140 MODIFY_REG(ADCx->CR,
7141 ADC_CR_BITS_PROPERTY_RS,
7142 ADC_CR_JADSTP);
7143 }
7144
7145 /**
7146 * @brief Get ADC group injected conversion state.
7147 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
7148 * @param ADCx ADC instance
7149 * @retval 0: no conversion is on going on ADC group injected.
7150 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)7151 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
7152 {
7153 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7154 }
7155
7156 /**
7157 * @brief Get ADC group injected command of conversion stop state
7158 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
7159 * @param ADCx ADC instance
7160 * @retval 0: no command of conversion stop is on going on ADC group injected.
7161 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)7162 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
7163 {
7164 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7165 }
7166
7167 /**
7168 * @brief Get ADC group injected conversion data, range fit for
7169 * all ADC configurations: all ADC resolutions and
7170 * all oversampling increased data width (for devices
7171 * with feature oversampling).
7172 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
7173 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
7174 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
7175 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
7176 * @param ADCx ADC instance
7177 * @param Rank This parameter can be one of the following values:
7178 * @arg @ref LL_ADC_INJ_RANK_1
7179 * @arg @ref LL_ADC_INJ_RANK_2
7180 * @arg @ref LL_ADC_INJ_RANK_3
7181 * @arg @ref LL_ADC_INJ_RANK_4
7182 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7183 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)7184 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
7185 {
7186 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7187 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7188
7189 return (uint32_t)(READ_BIT(*preg,
7190 ADC_JDR1_JDATA)
7191 );
7192 }
7193
7194 /**
7195 * @brief Get ADC group injected conversion data, range fit for
7196 * ADC resolution 12 bits.
7197 * @note For devices with feature oversampling: Oversampling
7198 * can increase data width, function for extended range
7199 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7200 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
7201 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
7202 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
7203 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
7204 * @param ADCx ADC instance
7205 * @param Rank This parameter can be one of the following values:
7206 * @arg @ref LL_ADC_INJ_RANK_1
7207 * @arg @ref LL_ADC_INJ_RANK_2
7208 * @arg @ref LL_ADC_INJ_RANK_3
7209 * @arg @ref LL_ADC_INJ_RANK_4
7210 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7211 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)7212 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
7213 {
7214 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7215 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7216
7217 return (uint16_t)(READ_BIT(*preg,
7218 ADC_JDR1_JDATA)
7219 );
7220 }
7221
7222 /**
7223 * @brief Get ADC group injected conversion data, range fit for
7224 * ADC resolution 10 bits.
7225 * @note For devices with feature oversampling: Oversampling
7226 * can increase data width, function for extended range
7227 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7228 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
7229 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
7230 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
7231 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
7232 * @param ADCx ADC instance
7233 * @param Rank This parameter can be one of the following values:
7234 * @arg @ref LL_ADC_INJ_RANK_1
7235 * @arg @ref LL_ADC_INJ_RANK_2
7236 * @arg @ref LL_ADC_INJ_RANK_3
7237 * @arg @ref LL_ADC_INJ_RANK_4
7238 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7239 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)7240 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
7241 {
7242 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7243 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7244
7245 return (uint16_t)(READ_BIT(*preg,
7246 ADC_JDR1_JDATA)
7247 );
7248 }
7249
7250 /**
7251 * @brief Get ADC group injected conversion data, range fit for
7252 * ADC resolution 8 bits.
7253 * @note For devices with feature oversampling: Oversampling
7254 * can increase data width, function for extended range
7255 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7256 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
7257 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
7258 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
7259 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
7260 * @param ADCx ADC instance
7261 * @param Rank This parameter can be one of the following values:
7262 * @arg @ref LL_ADC_INJ_RANK_1
7263 * @arg @ref LL_ADC_INJ_RANK_2
7264 * @arg @ref LL_ADC_INJ_RANK_3
7265 * @arg @ref LL_ADC_INJ_RANK_4
7266 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7267 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)7268 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
7269 {
7270 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7271 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7272
7273 return (uint8_t)(READ_BIT(*preg,
7274 ADC_JDR1_JDATA)
7275 );
7276 }
7277
7278 /**
7279 * @brief Get ADC group injected conversion data, range fit for
7280 * ADC resolution 6 bits.
7281 * @note For devices with feature oversampling: Oversampling
7282 * can increase data width, function for extended range
7283 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7284 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
7285 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
7286 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
7287 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
7288 * @param ADCx ADC instance
7289 * @param Rank This parameter can be one of the following values:
7290 * @arg @ref LL_ADC_INJ_RANK_1
7291 * @arg @ref LL_ADC_INJ_RANK_2
7292 * @arg @ref LL_ADC_INJ_RANK_3
7293 * @arg @ref LL_ADC_INJ_RANK_4
7294 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7295 */
LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef * ADCx,uint32_t Rank)7296 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
7297 {
7298 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7299 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7300
7301 return (uint8_t)(READ_BIT(*preg,
7302 ADC_JDR1_JDATA)
7303 );
7304 }
7305
7306 /**
7307 * @}
7308 */
7309
7310 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
7311 * @{
7312 */
7313
7314 /**
7315 * @brief Get flag ADC ready.
7316 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7317 * is enabled and when conversion clock is active.
7318 * (not only core clock: this ADC has a dual clock domain)
7319 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
7320 * @param ADCx ADC instance
7321 * @retval State of bit (1 or 0).
7322 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)7323 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
7324 {
7325 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7326 }
7327
7328 /**
7329 * @brief Get flag ADC group regular end of unitary conversion.
7330 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
7331 * @param ADCx ADC instance
7332 * @retval State of bit (1 or 0).
7333 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)7334 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
7335 {
7336 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7337 }
7338
7339 /**
7340 * @brief Get flag ADC group regular end of sequence conversions.
7341 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
7342 * @param ADCx ADC instance
7343 * @retval State of bit (1 or 0).
7344 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)7345 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
7346 {
7347 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7348 }
7349
7350 /**
7351 * @brief Get flag ADC group regular overrun.
7352 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
7353 * @param ADCx ADC instance
7354 * @retval State of bit (1 or 0).
7355 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)7356 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
7357 {
7358 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7359 }
7360
7361 /**
7362 * @brief Get flag ADC group regular end of sampling phase.
7363 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7364 * @param ADCx ADC instance
7365 * @retval State of bit (1 or 0).
7366 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)7367 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
7368 {
7369 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7370 }
7371
7372 /**
7373 * @brief Get flag ADC group injected end of unitary conversion.
7374 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7375 * @param ADCx ADC instance
7376 * @retval State of bit (1 or 0).
7377 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)7378 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
7379 {
7380 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7381 }
7382
7383 /**
7384 * @brief Get flag ADC group injected end of sequence conversions.
7385 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7386 * @param ADCx ADC instance
7387 * @retval State of bit (1 or 0).
7388 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)7389 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
7390 {
7391 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7392 }
7393
7394 /**
7395 * @brief Get flag ADC group injected contexts queue overflow.
7396 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7397 * @param ADCx ADC instance
7398 * @retval State of bit (1 or 0).
7399 */
LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef * ADCx)7400 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
7401 {
7402 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7403 }
7404
7405 /**
7406 * @brief Get flag ADC analog watchdog 1 flag
7407 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7408 * @param ADCx ADC instance
7409 * @retval State of bit (1 or 0).
7410 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)7411 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
7412 {
7413 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7414 }
7415
7416 /**
7417 * @brief Get flag ADC analog watchdog 2.
7418 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7419 * @param ADCx ADC instance
7420 * @retval State of bit (1 or 0).
7421 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)7422 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
7423 {
7424 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7425 }
7426
7427 /**
7428 * @brief Get flag ADC analog watchdog 3.
7429 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7430 * @param ADCx ADC instance
7431 * @retval State of bit (1 or 0).
7432 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)7433 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
7434 {
7435 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7436 }
7437
7438 /**
7439 * @brief Clear flag ADC ready.
7440 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7441 * is enabled and when conversion clock is active.
7442 * (not only core clock: this ADC has a dual clock domain)
7443 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7444 * @param ADCx ADC instance
7445 * @retval None
7446 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)7447 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7448 {
7449 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7450 }
7451
7452 /**
7453 * @brief Clear flag ADC group regular end of unitary conversion.
7454 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7455 * @param ADCx ADC instance
7456 * @retval None
7457 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)7458 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7459 {
7460 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7461 }
7462
7463 /**
7464 * @brief Clear flag ADC group regular end of sequence conversions.
7465 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7466 * @param ADCx ADC instance
7467 * @retval None
7468 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)7469 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7470 {
7471 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7472 }
7473
7474 /**
7475 * @brief Clear flag ADC group regular overrun.
7476 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7477 * @param ADCx ADC instance
7478 * @retval None
7479 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)7480 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7481 {
7482 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7483 }
7484
7485 /**
7486 * @brief Clear flag ADC group regular end of sampling phase.
7487 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7488 * @param ADCx ADC instance
7489 * @retval None
7490 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)7491 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7492 {
7493 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7494 }
7495
7496 /**
7497 * @brief Clear flag ADC group injected end of unitary conversion.
7498 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7499 * @param ADCx ADC instance
7500 * @retval None
7501 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)7502 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7503 {
7504 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7505 }
7506
7507 /**
7508 * @brief Clear flag ADC group injected end of sequence conversions.
7509 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7510 * @param ADCx ADC instance
7511 * @retval None
7512 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)7513 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7514 {
7515 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7516 }
7517
7518 /**
7519 * @brief Clear flag ADC group injected contexts queue overflow.
7520 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7521 * @param ADCx ADC instance
7522 * @retval None
7523 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)7524 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7525 {
7526 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7527 }
7528
7529 /**
7530 * @brief Clear flag ADC analog watchdog 1.
7531 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7532 * @param ADCx ADC instance
7533 * @retval None
7534 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)7535 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7536 {
7537 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7538 }
7539
7540 /**
7541 * @brief Clear flag ADC analog watchdog 2.
7542 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7543 * @param ADCx ADC instance
7544 * @retval None
7545 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)7546 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7547 {
7548 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7549 }
7550
7551 /**
7552 * @brief Clear flag ADC analog watchdog 3.
7553 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7554 * @param ADCx ADC instance
7555 * @retval None
7556 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)7557 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7558 {
7559 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7560 }
7561
7562 #if defined(ADC_MULTIMODE_SUPPORT)
7563 /**
7564 * @brief Get flag multimode ADC ready of the ADC master.
7565 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
7566 * @param ADCxy_COMMON ADC common instance
7567 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7568 * @retval State of bit (1 or 0).
7569 */
LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)7570 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7571 {
7572 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7573 }
7574
7575 /**
7576 * @brief Get flag multimode ADC ready of the ADC slave.
7577 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
7578 * @param ADCxy_COMMON ADC common instance
7579 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7580 * @retval State of bit (1 or 0).
7581 */
LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)7582 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7583 {
7584 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7585 }
7586
7587 /**
7588 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
7589 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
7590 * @param ADCxy_COMMON ADC common instance
7591 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7592 * @retval State of bit (1 or 0).
7593 */
LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)7594 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7595 {
7596 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7597 }
7598
7599 /**
7600 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
7601 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
7602 * @param ADCxy_COMMON ADC common instance
7603 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7604 * @retval State of bit (1 or 0).
7605 */
LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)7606 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7607 {
7608 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7609 }
7610
7611 /**
7612 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
7613 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
7614 * @param ADCxy_COMMON ADC common instance
7615 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7616 * @retval State of bit (1 or 0).
7617 */
LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7618 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7619 {
7620 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7621 }
7622
7623 /**
7624 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7625 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7626 * @param ADCxy_COMMON ADC common instance
7627 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7628 * @retval State of bit (1 or 0).
7629 */
LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7630 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7631 {
7632 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7633 }
7634
7635 /**
7636 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7637 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7638 * @param ADCxy_COMMON ADC common instance
7639 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7640 * @retval State of bit (1 or 0).
7641 */
LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7642 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7643 {
7644 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7645 }
7646
7647 /**
7648 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7649 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7650 * @param ADCxy_COMMON ADC common instance
7651 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7652 * @retval State of bit (1 or 0).
7653 */
LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7654 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7655 {
7656 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7657 }
7658
7659 /**
7660 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7661 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7662 * @param ADCxy_COMMON ADC common instance
7663 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7664 * @retval State of bit (1 or 0).
7665 */
LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7666 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7667 {
7668 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7669 }
7670
7671 /**
7672 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7673 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7674 * @param ADCxy_COMMON ADC common instance
7675 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7676 * @retval State of bit (1 or 0).
7677 */
LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7678 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7679 {
7680 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7681 }
7682
7683 /**
7684 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7685 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7686 * @param ADCxy_COMMON ADC common instance
7687 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7688 * @retval State of bit (1 or 0).
7689 */
LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7690 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7691 {
7692 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7693 }
7694
7695 /**
7696 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7697 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7698 * @param ADCxy_COMMON ADC common instance
7699 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7700 * @retval State of bit (1 or 0).
7701 */
LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7702 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7703 {
7704 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7705 }
7706
7707 /**
7708 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7709 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7710 * @param ADCxy_COMMON ADC common instance
7711 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7712 * @retval State of bit (1 or 0).
7713 */
LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7714 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7715 {
7716 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7717 }
7718
7719 /**
7720 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7721 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7722 * @param ADCxy_COMMON ADC common instance
7723 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7724 * @retval State of bit (1 or 0).
7725 */
LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7726 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7727 {
7728 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7729 }
7730
7731 /**
7732 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
7733 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
7734 * @param ADCxy_COMMON ADC common instance
7735 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7736 * @retval State of bit (1 or 0).
7737 */
LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)7738 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7739 {
7740 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7741 }
7742
7743 /**
7744 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
7745 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
7746 * @param ADCxy_COMMON ADC common instance
7747 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7748 * @retval State of bit (1 or 0).
7749 */
LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)7750 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7751 {
7752 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7753 }
7754
7755 /**
7756 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7757 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7758 * @param ADCxy_COMMON ADC common instance
7759 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7760 * @retval State of bit (1 or 0).
7761 */
LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7762 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7763 {
7764 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7765 }
7766
7767 /**
7768 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7769 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7770 * @param ADCxy_COMMON ADC common instance
7771 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7772 * @retval State of bit (1 or 0).
7773 */
LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7774 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7775 {
7776 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7777 }
7778
7779 /**
7780 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7781 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7782 * @param ADCxy_COMMON ADC common instance
7783 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7784 * @retval State of bit (1 or 0).
7785 */
LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7786 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7787 {
7788 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7789 }
7790
7791 /**
7792 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7793 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7794 * @param ADCxy_COMMON ADC common instance
7795 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7796 * @retval State of bit (1 or 0).
7797 */
LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7798 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7799 {
7800 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7801 }
7802
7803 /**
7804 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7805 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7806 * @param ADCxy_COMMON ADC common instance
7807 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7808 * @retval State of bit (1 or 0).
7809 */
LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7810 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7811 {
7812 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7813 }
7814
7815 /**
7816 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7817 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7818 * @param ADCxy_COMMON ADC common instance
7819 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7820 * @retval State of bit (1 or 0).
7821 */
LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7822 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7823 {
7824 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7825 }
7826 #endif /* ADC_MULTIMODE_SUPPORT */
7827
7828 /**
7829 * @}
7830 */
7831
7832 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7833 * @{
7834 */
7835
7836 /**
7837 * @brief Enable ADC ready.
7838 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7839 * @param ADCx ADC instance
7840 * @retval None
7841 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7842 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7843 {
7844 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7845 }
7846
7847 /**
7848 * @brief Enable interruption ADC group regular end of unitary conversion.
7849 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7850 * @param ADCx ADC instance
7851 * @retval None
7852 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7853 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7854 {
7855 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7856 }
7857
7858 /**
7859 * @brief Enable interruption ADC group regular end of sequence conversions.
7860 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7861 * @param ADCx ADC instance
7862 * @retval None
7863 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7864 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7865 {
7866 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7867 }
7868
7869 /**
7870 * @brief Enable ADC group regular interruption overrun.
7871 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7872 * @param ADCx ADC instance
7873 * @retval None
7874 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7875 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7876 {
7877 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7878 }
7879
7880 /**
7881 * @brief Enable interruption ADC group regular end of sampling.
7882 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7883 * @param ADCx ADC instance
7884 * @retval None
7885 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7886 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7887 {
7888 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7889 }
7890
7891 /**
7892 * @brief Enable interruption ADC group injected end of unitary conversion.
7893 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7894 * @param ADCx ADC instance
7895 * @retval None
7896 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7897 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7898 {
7899 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7900 }
7901
7902 /**
7903 * @brief Enable interruption ADC group injected end of sequence conversions.
7904 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7905 * @param ADCx ADC instance
7906 * @retval None
7907 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7908 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7909 {
7910 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7911 }
7912
7913 /**
7914 * @brief Enable interruption ADC group injected context queue overflow.
7915 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7916 * @param ADCx ADC instance
7917 * @retval None
7918 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7919 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7920 {
7921 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7922 }
7923
7924 /**
7925 * @brief Enable interruption ADC analog watchdog 1.
7926 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7927 * @param ADCx ADC instance
7928 * @retval None
7929 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7930 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7931 {
7932 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7933 }
7934
7935 /**
7936 * @brief Enable interruption ADC analog watchdog 2.
7937 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7938 * @param ADCx ADC instance
7939 * @retval None
7940 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7941 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7942 {
7943 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7944 }
7945
7946 /**
7947 * @brief Enable interruption ADC analog watchdog 3.
7948 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7949 * @param ADCx ADC instance
7950 * @retval None
7951 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7952 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7953 {
7954 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7955 }
7956
7957 /**
7958 * @brief Disable interruption ADC ready.
7959 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7960 * @param ADCx ADC instance
7961 * @retval None
7962 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7963 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7964 {
7965 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7966 }
7967
7968 /**
7969 * @brief Disable interruption ADC group regular end of unitary conversion.
7970 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7971 * @param ADCx ADC instance
7972 * @retval None
7973 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7974 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7975 {
7976 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7977 }
7978
7979 /**
7980 * @brief Disable interruption ADC group regular end of sequence conversions.
7981 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7982 * @param ADCx ADC instance
7983 * @retval None
7984 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7985 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7986 {
7987 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7988 }
7989
7990 /**
7991 * @brief Disable interruption ADC group regular overrun.
7992 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7993 * @param ADCx ADC instance
7994 * @retval None
7995 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7996 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7997 {
7998 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7999 }
8000
8001 /**
8002 * @brief Disable interruption ADC group regular end of sampling.
8003 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
8004 * @param ADCx ADC instance
8005 * @retval None
8006 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)8007 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
8008 {
8009 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8010 }
8011
8012 /**
8013 * @brief Disable interruption ADC group regular end of unitary conversion.
8014 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
8015 * @param ADCx ADC instance
8016 * @retval None
8017 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)8018 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8019 {
8020 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8021 }
8022
8023 /**
8024 * @brief Disable interruption ADC group injected end of sequence conversions.
8025 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
8026 * @param ADCx ADC instance
8027 * @retval None
8028 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)8029 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8030 {
8031 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8032 }
8033
8034 /**
8035 * @brief Disable interruption ADC group injected context queue overflow.
8036 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
8037 * @param ADCx ADC instance
8038 * @retval None
8039 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)8040 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
8041 {
8042 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8043 }
8044
8045 /**
8046 * @brief Disable interruption ADC analog watchdog 1.
8047 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
8048 * @param ADCx ADC instance
8049 * @retval None
8050 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)8051 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8052 {
8053 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8054 }
8055
8056 /**
8057 * @brief Disable interruption ADC analog watchdog 2.
8058 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
8059 * @param ADCx ADC instance
8060 * @retval None
8061 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)8062 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8063 {
8064 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8065 }
8066
8067 /**
8068 * @brief Disable interruption ADC analog watchdog 3.
8069 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
8070 * @param ADCx ADC instance
8071 * @retval None
8072 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)8073 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8074 {
8075 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8076 }
8077
8078 /**
8079 * @brief Get state of interruption ADC ready
8080 * (0: interrupt disabled, 1: interrupt enabled).
8081 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
8082 * @param ADCx ADC instance
8083 * @retval State of bit (1 or 0).
8084 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)8085 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
8086 {
8087 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8088 }
8089
8090 /**
8091 * @brief Get state of interruption ADC group regular end of unitary conversion
8092 * (0: interrupt disabled, 1: interrupt enabled).
8093 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
8094 * @param ADCx ADC instance
8095 * @retval State of bit (1 or 0).
8096 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)8097 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
8098 {
8099 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8100 }
8101
8102 /**
8103 * @brief Get state of interruption ADC group regular end of sequence conversions
8104 * (0: interrupt disabled, 1: interrupt enabled).
8105 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
8106 * @param ADCx ADC instance
8107 * @retval State of bit (1 or 0).
8108 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)8109 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
8110 {
8111 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8112 }
8113
8114 /**
8115 * @brief Get state of interruption ADC group regular overrun
8116 * (0: interrupt disabled, 1: interrupt enabled).
8117 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
8118 * @param ADCx ADC instance
8119 * @retval State of bit (1 or 0).
8120 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)8121 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
8122 {
8123 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8124 }
8125
8126 /**
8127 * @brief Get state of interruption ADC group regular end of sampling
8128 * (0: interrupt disabled, 1: interrupt enabled).
8129 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
8130 * @param ADCx ADC instance
8131 * @retval State of bit (1 or 0).
8132 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)8133 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
8134 {
8135 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8136 }
8137
8138 /**
8139 * @brief Get state of interruption ADC group injected end of unitary conversion
8140 * (0: interrupt disabled, 1: interrupt enabled).
8141 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
8142 * @param ADCx ADC instance
8143 * @retval State of bit (1 or 0).
8144 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)8145 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
8146 {
8147 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8148 }
8149
8150 /**
8151 * @brief Get state of interruption ADC group injected end of sequence conversions
8152 * (0: interrupt disabled, 1: interrupt enabled).
8153 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
8154 * @param ADCx ADC instance
8155 * @retval State of bit (1 or 0).
8156 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)8157 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
8158 {
8159 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8160 }
8161
8162 /**
8163 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
8164 * (0: interrupt disabled, 1: interrupt enabled).
8165 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
8166 * @param ADCx ADC instance
8167 * @retval State of bit (1 or 0).
8168 */
LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef * ADCx)8169 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
8170 {
8171 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
8172 }
8173
8174 /**
8175 * @brief Get state of interruption ADC analog watchdog 1
8176 * (0: interrupt disabled, 1: interrupt enabled).
8177 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
8178 * @param ADCx ADC instance
8179 * @retval State of bit (1 or 0).
8180 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)8181 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
8182 {
8183 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8184 }
8185
8186 /**
8187 * @brief Get state of interruption Get ADC analog watchdog 2
8188 * (0: interrupt disabled, 1: interrupt enabled).
8189 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
8190 * @param ADCx ADC instance
8191 * @retval State of bit (1 or 0).
8192 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)8193 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
8194 {
8195 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
8196 }
8197
8198 /**
8199 * @brief Get state of interruption Get ADC analog watchdog 3
8200 * (0: interrupt disabled, 1: interrupt enabled).
8201 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
8202 * @param ADCx ADC instance
8203 * @retval State of bit (1 or 0).
8204 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)8205 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
8206 {
8207 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
8208 }
8209
8210 /**
8211 * @}
8212 */
8213
8214 #if defined(USE_FULL_LL_DRIVER)
8215 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
8216 * @{
8217 */
8218
8219 /* Initialization of some features of ADC common parameters and multimode */
8220 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
8221 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
8222 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
8223
8224 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
8225 /* (availability of ADC group injected depends on STM32 series) */
8226 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8227
8228 /* Initialization of some features of ADC instance */
8229 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
8230 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
8231
8232 /* Initialization of some features of ADC instance and ADC group regular */
8233 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
8234 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
8235
8236 /* Initialization of some features of ADC instance and ADC group injected */
8237 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
8238 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
8239
8240 /**
8241 * @}
8242 */
8243 #endif /* USE_FULL_LL_DRIVER */
8244
8245 /**
8246 * @}
8247 */
8248
8249 /**
8250 * @}
8251 */
8252
8253 #endif /* ADC1 || ADC2 */
8254
8255 /**
8256 * @}
8257 */
8258
8259 #ifdef __cplusplus
8260 }
8261 #endif
8262
8263 #endif /* STM32H7RSxx_LL_ADC_H */
8264
