1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_ADC_H
21 #define STM32WBAxx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC4)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer rank bits position into the selected register */
51
52 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
53
54 /* Definition of ADC group regular sequencer bits information to be inserted */
55 /* into ADC group regular sequencer ranks literals definition. */
56 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
57 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
58 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
59 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
60 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
61 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
62 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
63 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
64
65
66 /* Internal mask for ADC group regular trigger: */
67 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
68 /* - regular trigger source */
69 /* - regular trigger edge */
70 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
71 compatibility with some ADC on other STM32 series
72 having this setting set by HW default value) */
73
74 /* Mask containing trigger source masks for each of possible */
75 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
76 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
77 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
78 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
79 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
80 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
81
82 /* Mask containing trigger edge masks for each of possible */
83 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
84 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
85 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
86 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
87 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
88 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
89
90 /* Definition of ADC group regular trigger bits information. */
91 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
92 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
93
94
95 /* Internal mask for ADC channel: */
96 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
97 /* - channel identifier defined by number */
98 /* - channel identifier defined by bitfield */
99 /* - channel differentiation between external channels (connected to */
100 /* GPIO pins) and internal channels (connected to internal paths) */
101 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
102 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
103 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
104 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
105 if set to mode "fully configurable", can contain channels with a restricted channel number.
106 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
107 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
108 position in register */
109 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
110 ADC_CHANNEL_ID_INTERNAL_CH_MASK)
111 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
112 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
113 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
114
115 /* Channel differentiation between external and internal channels */
116 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
117 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
118
119 /* Definition of channels ID number information to be inserted into */
120 /* channels literals definition. */
121 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
122 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
123 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
124 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
125 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
126 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
127 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
128 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
129 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
130 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
131 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
132 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
133 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
134 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
135 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
136 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
137 ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
138 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
139 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
140 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
141
142 /* Definition of channels ID bitfield information to be inserted into */
143 /* channels literals definition. */
144 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
145 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
146 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
147 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
148 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
149 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
150 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
151 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
152 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
153 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
154 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
155 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
156 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
157 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
158 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
159 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
160 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
161 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
162
163 /* Internal mask for ADC channel sampling time: */
164 /* To select into literals LL_ADC_SAMPLINGTIME_x */
165 /* the relevant bits for: */
166 /* (concatenation of multiple bits used in register SMPR) */
167 /* - ADC channels sampling time: setting channel wise, to map each channel */
168 /* on one of the common sampling time available. */
169 /* - ADC channels common sampling time: set a sampling time into one of the */
170 /* common sampling time available. */
171 #define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
172 #define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
173 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
174
175 /* Internal mask for ADC analog watchdog: */
176 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
177 /* (concatenation of multiple bits used in different analog watchdogs, */
178 /* (feature of several watchdogs not available on all STM32 series)). */
179 /* - analog watchdog 1: monitored channel defined by number, */
180 /* selection of ADC group (ADC group regular). */
181 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
182 /* selection on groups. */
183
184 /* Internal register offset for ADC analog watchdog channel configuration */
185 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
186 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
187 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
188
189 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
190 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
191 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
192 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
193
194 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
195 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
196
197 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
198 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
199 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
200
201 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
202 in ADC_AWD_CRX_REGOFFSET_MASK */
203
204 /* Internal register offset for ADC analog watchdog threshold configuration */
205 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
206 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
207 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
208 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
209 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
210 in ADC_AWD_TRX_REGOFFSET_MASK */
211 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
212 threshold high: mask of bit */
213 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
214 threshold high: position of bit */
215 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
216 position to perform a shift of 4 ranks */
217 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
218
219
220 /* ADC registers bits positions */
221 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
222 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
223 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
224 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
225 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
226 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
227 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
228 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
229 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
230 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
231 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
232 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
233 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
234 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
235 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
236 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
237 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
238 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
239 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
240 #define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
241 #define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
242 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
243
244
245 /* ADC registers bits groups */
246 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
247 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
248 HW property "rs": Software can read as well as set this bit.
249 Writing '0' has no effect on the bit value. */
250
251
252 /* ADC internal channels related definitions */
253 /* Internal voltage reference VrefInt */
254 #define VREFINT_CAL_ADDR ((uint16_t*) (0x0BF907A5UL)) /* Internal voltage reference, address of
255 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
256 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
257 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value
258 with which VrefInt has been calibrated in production
259 (tolerance: +-10 mV) (unit: mV). */
260 /* Temperature sensor */
261 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BF90710UL)) /* Address of parameter TS_CAL1: On this series,
262 temperature sensor ADC raw data acquired at temperature 30 DegC
263 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
264 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BF90742UL)) /* Address of parameter TS_CAL2: On this series,
265 temperature sensor ADC raw data acquired at temperature 130 DegC
266 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
267 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor
268 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
269 (tolerance: +-5 DegC) (unit: DegC). */
270 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor
271 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
272 (tolerance: +-5 DegC) (unit: DegC). */
273 #define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) value
274 with which temperature sensor has been calibrated in production
275 (tolerance: +-10 mV) (unit: mV). */
276
277 /**
278 * @}
279 */
280
281
282 /* Private macros ------------------------------------------------------------*/
283 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
284 * @{
285 */
286
287 /**
288 * @brief Driver macro reserved for internal use: isolate bits with the
289 * selected mask and shift them to the register LSB
290 * (shift mask on register position bit 0).
291 * @param __BITS__ Bits in register 32 bits
292 * @param __MASK__ Mask in register 32 bits
293 * @retval Bits in register 32 bits
294 */
295 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
296 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
297
298 /**
299 * @brief Driver macro reserved for internal use: set a pointer to
300 * a register from a register basis from which an offset
301 * is applied.
302 * @param __REG__ Register basis from which the offset is applied.
303 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
304 * @retval Pointer to register address
305 */
306 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
307 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
308
309 /**
310 * @}
311 */
312
313
314 /* Exported types ------------------------------------------------------------*/
315 #if defined(USE_FULL_LL_DRIVER)
316 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
317 * @{
318 */
319
320 /**
321 * @brief Structure definition of some features of ADC common parameters
322 * and multimode
323 * (all ADC instances belonging to the same ADC common instance).
324 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
325 * is conditioned to ADC instances state (all ADC instances
326 * sharing the same ADC common instance):
327 * All ADC instances sharing the same ADC common instance must be
328 * disabled.
329 */
330 typedef struct
331 {
332 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
333 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
334 This feature can be modified afterwards using unitary function
335 @ref LL_ADC_SetCommonClock(). */
336
337 } LL_ADC_CommonInitTypeDef;
338
339 /**
340 * @brief Structure definition of some features of ADC instance.
341 * @note These parameters have an impact on ADC scope: ADC instance.
342 * Refer to corresponding unitary functions into
343 * @ref ADC_LL_EF_Configuration_ADC_Instance .
344 * @note The setting of these parameters by function @ref LL_ADC_Init()
345 * is conditioned to ADC state:
346 * ADC instance must be disabled.
347 * This condition is applied to all ADC features, for efficiency
348 * and compatibility over all STM32 series. However, the different
349 * features can be set under different ADC state conditions
350 * (setting possible with ADC enabled without conversion on going,
351 * ADC enabled with conversion on going, ...)
352 * Each feature can be updated afterwards with a unitary function
353 * and potentially with ADC in a different state than disabled,
354 * refer to description of each function for setting
355 * conditioned to ADC state.
356 */
357 typedef struct
358 {
359 uint32_t Resolution; /*!< Set ADC resolution.
360 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
361 This feature can be modified afterwards using unitary function
362 @ref LL_ADC_SetResolution(). */
363
364 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
365 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
366 This feature can be modified afterwards using unitary function
367 @ref LL_ADC_SetDataAlignment(). */
368
369
370 } LL_ADC_InitTypeDef;
371
372 /**
373 * @brief Structure definition of some features of ADC group regular.
374 * @note These parameters have an impact on ADC scope: ADC group regular.
375 * Refer to corresponding unitary functions into
376 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
377 * (functions with prefix "REG").
378 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
379 * is conditioned to ADC state:
380 * ADC instance must be disabled.
381 * This condition is applied to all ADC features, for efficiency
382 * and compatibility over all STM32 series. However, the different
383 * features can be set under different ADC state conditions
384 * (setting possible with ADC enabled without conversion on going,
385 * ADC enabled with conversion on going, ...)
386 * Each feature can be updated afterwards with a unitary function
387 * and potentially with ADC in a different state than disabled,
388 * refer to description of each function for setting
389 * conditioned to ADC state.
390 */
391 typedef struct
392 {
393 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
394 from external peripheral (timer event, external interrupt line).
395 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
396 @note On this STM32 series, setting trigger source to external trigger also
397 set trigger polarity to rising edge(default setting for compatibility
398 with some ADC on other STM32 series having this setting set by HW
399 default value).
400 In case of need to modify trigger edge, use function
401 @ref LL_ADC_REG_SetTriggerEdge().
402 This feature can be modified afterwards using unitary function
403 @ref LL_ADC_REG_SetTriggerSource(). */
404
405 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
406 @note This parameter has an effect only if group regular sequencer is set
407 to mode "fully configurable". Refer to function
408 @ref LL_ADC_REG_SetSequencerConfigurable().
409 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
410 This feature can be modified afterwards using unitary function
411 @ref LL_ADC_REG_SetSequencerLength(). */
412
413 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
414 and scan conversions interrupted every selected number of ranks.
415 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
416 @note This parameter has an effect only if group regular sequencer is
417 enabled (depending on the sequencer mode: scan length of 2 ranks or
418 more, or several ADC channels enabled in group regular sequencer.
419 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
420 This feature can be modified afterwards using unitary function
421 @ref LL_ADC_REG_SetSequencerDiscont(). */
422
423 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
424 conversions are performed in single mode (one conversion per trigger) or in
425 continuous mode (after the first trigger, following conversions launched
426 successively automatically).
427 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
428 Note: It is not possible to enable both ADC group regular continuous mode
429 and discontinuous mode.
430 This feature can be modified afterwards using unitary function
431 @ref LL_ADC_REG_SetContinuousMode(). */
432
433 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
434 by DMA, and DMA requests mode.
435 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
436 This feature can be modified afterwards using unitary function
437 @ref LL_ADC_REG_SetDMATransfer(). */
438
439 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
440 data preserved or overwritten.
441 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
442 This feature can be modified afterwards using unitary function
443 @ref LL_ADC_REG_SetOverrun(). */
444
445 } LL_ADC_REG_InitTypeDef;
446
447 /**
448 * @}
449 */
450 #endif /* USE_FULL_LL_DRIVER */
451
452 /* Exported constants --------------------------------------------------------*/
453 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
454 * @{
455 */
456
457 /** @defgroup ADC_LL_EC_FLAG ADC flags
458 * @brief Flags defines which can be used with LL_ADC_ReadReg function
459 * @{
460 */
461 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
462 #define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag ADC internal voltage regulator ready */
463 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
464 conversion */
465 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
466 conversions */
467 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
468 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
469 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
470 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
471 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
472 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
473 /**
474 * @}
475 */
476
477 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
478 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
479 * @{
480 */
481 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
482 #define LL_ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC interruption internal voltage regulator ready */
483 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
484 conversion */
485 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
486 conversions */
487 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
488 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
489 phase */
490 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
491 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
492 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
493 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
494 /**
495 * @}
496 */
497
498 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
499 * @{
500 */
501 /* List of ADC registers intended to be used (most commonly) with */
502 /* DMA transfer. */
503 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
504 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
505 (corresponding to register DR) to be used with ADC configured in independent
506 mode. Without DMA transfer, register accessed by LL function
507 @ref LL_ADC_REG_ReadConversionData32() and other
508 functions @ref LL_ADC_REG_ReadConversionDatax() */
509 /**
510 * @}
511 */
512
513 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
514 * @{
515 */
516 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
517 prescaler */
518 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
519 prescaler division by 2. Setting common to ADC instances of ADC common
520 group */
521 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
522 prescaler division by 4. Setting common to ADC instances of ADC common
523 group */
524 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
525 prescaler division by 6. Setting common to ADC instances of ADC common
526 group */
527 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
528 prescaler division by 8. Setting common to ADC instances of ADC common
529 group */
530 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
531 prescaler division by 10. Setting common to ADC instances of ADC common
532 group */
533 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
534 prescaler division by 12. Setting common to ADC instances of ADC common
535 group */
536 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
537 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
538 prescaler division by 16. Setting common to ADC instances of ADC common
539 group */
540 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
541 prescaler division by 32. Setting common to ADC instances of ADC common
542 group */
543 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
544 prescaler division by 64. Setting common to ADC instances of ADC common
545 group */
546 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
547 prescaler division by 128. Setting common to ADC instances of ADC common
548 group */
549 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
550 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
551 prescaler division by 256. Setting common to ADC instances of ADC common
552 group */
553 /**
554 * @}
555 */
556
557 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
558 * @{
559 */
560 /* Note: Other measurement paths to internal channels may be available */
561 /* (connections to other peripherals). */
562 /* If they are not listed below, they do not require any specific */
563 /* path enable. In this case, Access to measurement path is done */
564 /* only by selecting the corresponding ADC internal channel. */
565 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
566 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
567 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
568 temperature sensor */
569 /**
570 * @}
571 */
572
573 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
574 * @{
575 */
576 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
577 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
578 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
579 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
580 /**
581 * @}
582 */
583
584 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
585 * @{
586 */
587 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
588 (alignment on data register LSB bit 0)*/
589 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
590 (alignment on data register MSB bit 15)*/
591 /**
592 * @}
593 */
594
595 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
596 * @{
597 */
598 #define LL_ADC_LP_AUTOWAIT_DISABLE (0x00000000UL) /*!< ADC low power mode auto delay disabled. */
599 #define LL_ADC_LP_AUTOWAIT_ENABLE (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay enabled: dynamic
600 low power mode, ADC conversions are performed only when necessary
601 (when previous ADC conversion data is read).
602 See description with function @ref LL_ADC_SetLPModeAutoWait(). */
603 /**
604 * @}
605 */
606 /* Definitions for backward compatibility with legacy STM32 series */
607 #define LL_ADC_LP_MODE_NONE LL_ADC_LP_AUTOWAIT_DISABLE
608 #define LL_ADC_LP_AUTOWAIT LL_ADC_LP_AUTOWAIT_ENABLE
609
610
611 /** @defgroup ADC_LL_EC_AUTOPOWEROFF_MODE ADC instance - Low power mode auto power-off
612 * @{
613 */
614 #define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */
615 #define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC_PWRR_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC
616 automatically powers-off after a ADC conversion and automatically wakes up
617 when a new ADC conversion is triggered (with startup time between trigger
618 and start of sampling). See description with function
619 @ref LL_ADC_SetLPModeAutoPowerOff().
620 It can be combined with mode low power mode auto wait. */
621 /**
622 * @}
623 */
624
625
626 /** @defgroup ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC instance - Autonomous deep power down mode
627 * @{
628 */
629 #define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */
630 #define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC_PWRR_DPD) /*!< ADC deep power down in autonomous mode enabled */
631 /**
632 * @}
633 */
634
635 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
636 * @{
637 */
638 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency.
639 Note: ADC trigger frequency mode must be set to low frequency when a duration
640 is exceeded before ADC conversion start trigger event (between ADC enable
641 and ADC conversion start trigger event or between two ADC conversion start
642 trigger event).
643 Duration value: Refer to device datasheet, parameter "tIdle". */
644 #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency.
645 Note: ADC trigger frequency mode must be set to low frequency when a duration
646 is exceeded before ADC conversion start trigger event (between ADC enable
647 and ADC conversion start trigger event or between two ADC conversion start
648 trigger event).
649 Duration value: Refer to device datasheet, parameter "tIdle". */
650 /**
651 * @}
652 */
653
654 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
655 * @{
656 */
657 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group
658 of channels: sampling time nb 1 */
659 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \
660 | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group
661 of channels: sampling time nb 2 */
662 /**
663 * @}
664 */
665
666 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
667 * @{
668 */
669 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
670 /**
671 * @}
672 */
673
674 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
675 * @{
676 */
677 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \
678 | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */
679 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \
680 | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */
681 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \
682 | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */
683 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \
684 | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */
685 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \
686 | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */
687 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \
688 | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */
689 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \
690 | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */
691 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \
692 | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */
693 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \
694 | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */
695 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \
696 | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */
697 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \
698 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
699 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \
700 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
701 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \
702 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
703 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \
704 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
705 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
706 connected to VrefInt: Internal voltage reference. */
707 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
708 connected to internal temperature sensor. */
709 #define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
710 connected to Vcore: internal power supply of MCU digital logic */
711 /**
712 * @}
713 */
714
715 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
716 * @{
717 */
718 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
719 conversion trigger internal: SW start. */
720 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
721 conversion trigger from external peripheral: TIM1 TRGO.
722 Trigger edge set to rising edge (default setting). */
723 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
724 conversion trigger from external peripheral: TIM1 channel 4 event
725 (capture compare: input capture or output capture).
726 Trigger edge set to rising edge (default setting). */
727 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
728 conversion trigger from external peripheral: TIM2 TRGO.
729 Trigger edge set to rising edge (default setting). */
730 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
731 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
732 conversion trigger from external peripheral: LPTIM1 channel 1 event
733 (capture compare: input capture or output capture).
734 Trigger edge set to rising edge (default setting). */
735 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
736 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
737 conversion trigger from external peripheral: external interrupt line 15.
738 Trigger edge set to rising edge (default setting). */
739 /**
740 * @}
741 */
742
743 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
744 * @{
745 */
746 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
747 trigger polarity set to rising edge */
748 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion
749 trigger polarity set to falling edge */
750 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
751 trigger polarity set to both rising and falling edges */
752 /**
753 * @}
754 */
755
756 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
757 * @{
758 */
759 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
760 one conversion per trigger */
761 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode:
762 after the first trigger, following conversions launched successively
763 automatically */
764 /**
765 * @}
766 */
767
768 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
769 * @{
770 */
771 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
772 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA,
773 in limited mode (one shot mode): DMA transfer requests are stopped when
774 number of DMA data transfers (number of ADC conversions) is reached.
775 This ADC mode is intended to be used with DMA mode non-circular. */
776 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are
777 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
778 whatever number of DMA data transferred (number of ADC conversions).
779 This ADC mode is intended to be used with DMA mode circular. */
780 /**
781 * @}
782 */
783
784 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
785 * @{
786 */
787 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
788 data preserved */
789 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
790 data overwritten */
791 /**
792 * @}
793 */
794
795 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
796 * @{
797 */
798 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable:
799 sequencer length and each rank affectation to a channel are fixed
800 by channel HW number. Refer to description of function
801 @ref LL_ADC_REG_SetSequencerChannels(). */
802 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable:
803 sequencer length and each rank affectation to a channel are configurable.
804 Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
805 /**
806 * @}
807 */
808
809 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
810 * @{
811 */
812 #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable
813 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
814 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable
815 with 2 ranks in the sequence */
816 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable
817 with 3 ranks in the sequence */
818 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable
819 with 4 ranks in the sequence */
820 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable
821 with 5 ranks in the sequence */
822 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable
823 with 6 ranks in the sequence */
824 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable
825 with 7 ranks in the sequence */
826 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable
827 with 8 ranks in the sequence */
828 /**
829 * @}
830 */
831
832 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
833 * @{
834 */
835 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if
836 sequencer set to mode not fully configurable, refer to function
837 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
838 direction forward: from lowest channel number to highest channel number
839 (scan of all ranks, ADC conversion of ranks with channels enabled in
840 sequencer). On some other STM32 series, this setting is not available
841 and the default scan direction is forward. */
842 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if
843 sequencer set to mode not fully configurable, refer to function
844 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
845 direction backward: from highest channel number to lowest channel number
846 (scan of all ranks, ADC conversion of ranks with channels enabled in
847 sequencer) */
848 /**
849 * @}
850 */
851
852 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
853 * @{
854 */
855 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
856 discontinuous mode disable */
857 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
858 discontinuous mode enable with sequence interruption every rank */
859 /**
860 * @}
861 */
862
863 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
864 * @{
865 */
866 #define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */
867 #define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */
868 #define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */
869 #define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */
870 #define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */
871 #define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */
872 #define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */
873 #define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */
874 /**
875 * @}
876 */
877
878 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
879 * @{
880 */
881 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
882 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
883 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
884 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \
885 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
886 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
887 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \
888 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
889 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \
890 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
891 #define LL_ADC_SAMPLINGTIME_814CYCLES_5 (ADC_SMPR_SMP1_2 \
892 | ADC_SMPR_SMP1_1 \
893 | ADC_SMPR_SMP1_0) /*!< Sampling time 814.5 ADC clock cycles */
894 /**
895 * @}
896 */
897
898 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
899 * @{
900 */
901 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
902 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
903 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
904 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
905 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
906 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
907 /**
908 * @}
909 */
910
911 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
912 * @{
913 */
914 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
915 disabled */
916 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
917 | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring
918 of all channels, converted by group regular only */
919 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
920 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
921 of ADC channel ADCx_IN0, converted by group regular only */
922 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
923 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
924 of ADC channel ADCx_IN1, converted by group regular only */
925 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
926 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
927 of ADC channel ADCx_IN2, converted by group regular only */
928 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
929 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
930 of ADC channel ADCx_IN3, converted by group regular only */
931 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
932 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
933 of ADC channel ADCx_IN4, converted by group regular only */
934 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
935 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
936 of ADC channel ADCx_IN5, converted by group regular only */
937 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
938 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
939 of ADC channel ADCx_IN6, converted by group regular only */
940 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
941 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
942 of ADC channel ADCx_IN7, converted by group regular only */
943 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
944 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
945 of ADC channel ADCx_IN8, converted by group regular only */
946 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
947 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
948 of ADC channel ADCx_IN9, converted by group regular only */
949 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
950 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
951 of ADC channel ADCx_IN10, converted by group regular only */
952 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
953 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
954 of ADC channel ADCx_IN11, converted by group regular only */
955 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
956 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
957 of ADC channel ADCx_IN12, converted by group regular only */
958 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
959 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
960 of ADC channel ADCx_IN13, converted by group regular only */
961 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
962 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
963 of ADC internal channel connected to VrefInt: Internal
964 voltage reference, converted by group regular only */
965 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
966 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
967 of ADC internal channel connected to internal temperature sensor,
968 converted by group regular only */
969 #define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) \
970 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
971 of ADC internal channel connected to Vcore,
972 converted by group regular only */
973 /**
974 * @}
975 */
976
977 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
978 * @{
979 */
980 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */
981 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
982 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \
983 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low
984 concatenated into the same data */
985 /**
986 * @}
987 */
988
989 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
990 * @{
991 */
992 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
993 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of
994 ADC group regular. Literal suffix "continued" is kept for compatibility
995 with other STM32 devices featuring ADC group injected, in this case other
996 oversampling scope parameters are available. */
997 /**
998 * @}
999 */
1000
1001 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1002 * @{
1003 */
1004 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1005 (all conversions of oversampling ratio are done from 1 trigger) */
1006 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous
1007 mode (each conversion of oversampling ratio needs a trigger) */
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1013 * @{
1014 */
1015 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1016 (sum of conversions data computed to result as oversampling conversion data
1017 (before potential shift) */
1018 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1019 (sum of conversions data computed to result as oversampling conversion data
1020 (before potential shift) */
1021 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1022 (sum of conversions data computed to result as oversampling conversion data
1023 (before potential shift) */
1024 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1025 (sum of conversions data computed to result as oversampling conversion data
1026 (before potential shift) */
1027 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1028 (sum of conversions data computed to result as oversampling conversion data
1029 (before potential shift) */
1030 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1031 (sum of conversions data computed to result as oversampling conversion data
1032 (before potential shift) */
1033 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1034 (sum of conversions data computed to result as oversampling conversion data
1035 (before potential shift) */
1036 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1037 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1038 (sum of conversions data computed to result as oversampling conversion data
1039 (before potential shift) */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1045 * @{
1046 */
1047 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1048 (sum of the ADC conversions data is not divided to result as oversampling
1049 conversion data) */
1050 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1051 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1052 to result as oversampling conversion data) */
1053 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1054 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1055 to result as oversampling conversion data) */
1056 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1057 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1058 to result as oversampling conversion data) */
1059 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1060 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1061 to result as oversampling conversion data) */
1062 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1063 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1064 to result as oversampling conversion data) */
1065 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1066 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1067 to result as oversampling conversion data) */
1068 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1069 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1070 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1071 to result as oversampling conversion data) */
1072 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1073 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1074 to result as oversampling conversion data) */
1075 /**
1076 * @}
1077 */
1078
1079 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
1080 * @{
1081 */
1082 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
1083 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
1084 calibration parameters. This value is coded on 16 bits
1085 (to fit on signed word or double word) and corresponds
1086 to an inconsistent temperature value. */
1087 /**
1088 * @}
1089 */
1090
1091 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1092 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1093 * not timeout values.
1094 * For details on delays values, refer to descriptions in source code
1095 * above each literal definition.
1096 * @{
1097 */
1098
1099 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1100 /* not timeout values. */
1101 /* Timeout values for ADC operations are dependent to device clock */
1102 /* configuration (system clock versus ADC clock), */
1103 /* and therefore must be defined in user application. */
1104 /* Indications for estimation of ADC timeout delays, for this */
1105 /* STM32 series: */
1106 /* - ADC calibration time: maximum delay is 82/fADC. */
1107 /* (refer to device datasheet, parameter "tCAL") */
1108 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1109 /* (refer to device datasheet, parameter "tSTAB") */
1110 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1111 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1112 /* cycles */
1113 /* - ADC conversion time: duration depending on ADC clock and ADC */
1114 /* configuration. */
1115 /* (refer to device reference manual, section "Timing") */
1116
1117 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1118 /* Delay set to maximum value (refer to device datasheet, */
1119 /* parameter "tADCVREG_STUP"). */
1120 /* Unit: us */
1121 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
1122 regulator start-up time) */
1123
1124 /* Delay for internal voltage reference stabilization time. */
1125 /* Delay set to maximum value (refer to device datasheet, */
1126 /* parameter "tstart_vrefint"). */
1127 /* Unit: us */
1128 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
1129 time */
1130
1131 /* Delay for temperature sensor stabilization time. */
1132 /* Literal set to maximum value (refer to device datasheet, */
1133 /* parameter "tSTART"). */
1134 /* Unit: us */
1135 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time
1136 (starting from temperature sensor enable, refer to
1137 @ref LL_ADC_SetCommonPathInternalCh()) */
1138 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
1139 time (starting from ADC enable, refer to
1140 @ref LL_ADC_Enable()) */
1141
1142 /* Delay required between ADC end of calibration and ADC enable. */
1143 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1144 /* are required between ADC end of calibration and ADC enable. */
1145 /* Wait time can be computed in user application by waiting for the */
1146 /* equivalent number of CPU cycles, by taking into account */
1147 /* ratio of CPU clock versus ADC clock prescalers. */
1148 /* Unit: ADC clock cycles. */
1149 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration
1150 and ADC enable */
1151
1152 /**
1153 * @}
1154 */
1155
1156 /**
1157 * @}
1158 */
1159
1160
1161 /* Exported macro ------------------------------------------------------------*/
1162 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1163 * @{
1164 */
1165
1166 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1167 * @{
1168 */
1169
1170 /**
1171 * @brief Write a value in ADC register
1172 * @param __INSTANCE__ ADC Instance
1173 * @param __REG__ Register to be written
1174 * @param __VALUE__ Value to be written in the register
1175 * @retval None
1176 */
1177 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1178
1179 /**
1180 * @brief Read a value in ADC register
1181 * @param __INSTANCE__ ADC Instance
1182 * @param __REG__ Register to be read
1183 * @retval Register value
1184 */
1185 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1191 * @{
1192 */
1193
1194 /**
1195 * @brief Helper macro to get ADC channel number in decimal format
1196 * from literals LL_ADC_CHANNEL_x.
1197 * @note Example:
1198 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1199 * will return decimal number "4".
1200 * @note The input can be a value from functions where a channel
1201 * number is returned, either defined with number
1202 * or with bitfield (only one bit must be set).
1203 * @param __CHANNEL__ This parameter can be one of the following values:
1204 * @arg @ref LL_ADC_CHANNEL_0
1205 * @arg @ref LL_ADC_CHANNEL_1
1206 * @arg @ref LL_ADC_CHANNEL_2
1207 * @arg @ref LL_ADC_CHANNEL_3
1208 * @arg @ref LL_ADC_CHANNEL_4
1209 * @arg @ref LL_ADC_CHANNEL_5
1210 * @arg @ref LL_ADC_CHANNEL_6
1211 * @arg @ref LL_ADC_CHANNEL_7
1212 * @arg @ref LL_ADC_CHANNEL_8
1213 * @arg @ref LL_ADC_CHANNEL_9
1214 * @arg @ref LL_ADC_CHANNEL_10
1215 * @arg @ref LL_ADC_CHANNEL_11
1216 * @arg @ref LL_ADC_CHANNEL_12
1217 * @arg @ref LL_ADC_CHANNEL_13
1218 * @arg @ref LL_ADC_CHANNEL_VREFINT
1219 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1220 * @arg @ref LL_ADC_CHANNEL_VCORE
1221 * @retval Value between Min_Data=0 and Max_Data=18
1222 */
1223 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1224 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1225 ( \
1226 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1227 ) \
1228 : \
1229 ( \
1230 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1231 ) \
1232 )
1233
1234 /**
1235 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1236 * from number in decimal format.
1237 * @note Example:
1238 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1239 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1240 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1241 * @retval Returned value can be one of the following values:
1242 * @arg @ref LL_ADC_CHANNEL_0
1243 * @arg @ref LL_ADC_CHANNEL_1
1244 * @arg @ref LL_ADC_CHANNEL_2
1245 * @arg @ref LL_ADC_CHANNEL_3
1246 * @arg @ref LL_ADC_CHANNEL_4
1247 * @arg @ref LL_ADC_CHANNEL_5
1248 * @arg @ref LL_ADC_CHANNEL_6
1249 * @arg @ref LL_ADC_CHANNEL_7
1250 * @arg @ref LL_ADC_CHANNEL_8
1251 * @arg @ref LL_ADC_CHANNEL_9
1252 * @arg @ref LL_ADC_CHANNEL_10
1253 * @arg @ref LL_ADC_CHANNEL_11
1254 * @arg @ref LL_ADC_CHANNEL_12
1255 * @arg @ref LL_ADC_CHANNEL_13
1256 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1257 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1258 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1259 *
1260 * (1) For ADC channel read back from ADC register,
1261 * comparison with internal channel parameter to be done
1262 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1263 */
1264 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1265 (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1266 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
1267
1268 /**
1269 * @brief Helper macro to determine whether the selected channel
1270 * corresponds to literal definitions of driver.
1271 * @note The different literal definitions of ADC channels are:
1272 * - ADC internal channel:
1273 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1274 * - ADC external channel (channel connected to a GPIO pin):
1275 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1276 * @note The channel parameter must be a value defined from literal
1277 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1278 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1279 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1280 * must not be a value from functions where a channel number is
1281 * returned from ADC registers,
1282 * because internal and external channels share the same channel
1283 * number in ADC registers. The differentiation is made only with
1284 * parameters definitions of driver.
1285 * @param __CHANNEL__ This parameter can be one of the following values:
1286 * @arg @ref LL_ADC_CHANNEL_0
1287 * @arg @ref LL_ADC_CHANNEL_1
1288 * @arg @ref LL_ADC_CHANNEL_2
1289 * @arg @ref LL_ADC_CHANNEL_3
1290 * @arg @ref LL_ADC_CHANNEL_4
1291 * @arg @ref LL_ADC_CHANNEL_5
1292 * @arg @ref LL_ADC_CHANNEL_6
1293 * @arg @ref LL_ADC_CHANNEL_7
1294 * @arg @ref LL_ADC_CHANNEL_8
1295 * @arg @ref LL_ADC_CHANNEL_9
1296 * @arg @ref LL_ADC_CHANNEL_10
1297 * @arg @ref LL_ADC_CHANNEL_11
1298 * @arg @ref LL_ADC_CHANNEL_12
1299 * @arg @ref LL_ADC_CHANNEL_13
1300 * @arg @ref LL_ADC_CHANNEL_VREFINT
1301 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1302 * @arg @ref LL_ADC_CHANNEL_VCORE
1303 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
1304 connected to a GPIO pin).
1305 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1306 */
1307 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1308 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1309
1310 /**
1311 * @brief Helper macro to convert a channel defined from parameter
1312 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1313 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1314 * to its equivalent parameter definition of a ADC external channel
1315 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1316 * @note The channel parameter can be, additionally to a value
1317 * defined from parameter definition of a ADC internal channel
1318 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1319 * a value defined from parameter definition of
1320 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1321 * or a value from functions where a channel number is returned
1322 * from ADC registers.
1323 * @param __CHANNEL__ This parameter can be one of the following values:
1324 * @arg @ref LL_ADC_CHANNEL_0
1325 * @arg @ref LL_ADC_CHANNEL_1
1326 * @arg @ref LL_ADC_CHANNEL_2
1327 * @arg @ref LL_ADC_CHANNEL_3
1328 * @arg @ref LL_ADC_CHANNEL_4
1329 * @arg @ref LL_ADC_CHANNEL_5
1330 * @arg @ref LL_ADC_CHANNEL_6
1331 * @arg @ref LL_ADC_CHANNEL_7
1332 * @arg @ref LL_ADC_CHANNEL_8
1333 * @arg @ref LL_ADC_CHANNEL_9
1334 * @arg @ref LL_ADC_CHANNEL_10
1335 * @arg @ref LL_ADC_CHANNEL_11
1336 * @arg @ref LL_ADC_CHANNEL_12
1337 * @arg @ref LL_ADC_CHANNEL_13
1338 * @arg @ref LL_ADC_CHANNEL_VREFINT
1339 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1340 * @arg @ref LL_ADC_CHANNEL_VCORE
1341 * @retval Returned value can be one of the following values:
1342 * @arg @ref LL_ADC_CHANNEL_0
1343 * @arg @ref LL_ADC_CHANNEL_1
1344 * @arg @ref LL_ADC_CHANNEL_2
1345 * @arg @ref LL_ADC_CHANNEL_3
1346 * @arg @ref LL_ADC_CHANNEL_4
1347 * @arg @ref LL_ADC_CHANNEL_5
1348 * @arg @ref LL_ADC_CHANNEL_6
1349 * @arg @ref LL_ADC_CHANNEL_7
1350 * @arg @ref LL_ADC_CHANNEL_8
1351 * @arg @ref LL_ADC_CHANNEL_9
1352 * @arg @ref LL_ADC_CHANNEL_10
1353 * @arg @ref LL_ADC_CHANNEL_11
1354 * @arg @ref LL_ADC_CHANNEL_12
1355 * @arg @ref LL_ADC_CHANNEL_13
1356 */
1357 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1358 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1359
1360 /**
1361 * @brief Helper macro to determine whether the internal channel
1362 * selected is available on the ADC instance selected.
1363 * @note The channel parameter must be a value defined from parameter
1364 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1365 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1366 * must not be a value defined from parameter definition of
1367 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1368 * or a value from functions where a channel number is
1369 * returned from ADC registers,
1370 * because internal and external channels share the same channel
1371 * number in ADC registers. The differentiation is made only with
1372 * parameters definitions of driver.
1373 * @param __ADC_INSTANCE__ ADC instance
1374 * @param __CHANNEL__ This parameter can be one of the following values:
1375 * @arg @ref LL_ADC_CHANNEL_VREFINT
1376 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1377 * @arg @ref LL_ADC_CHANNEL_VCORE
1378 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1379 * Value "1" if the internal channel selected is available on the ADC instance selected.
1380 */
1381 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1382 (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1383 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1384 ((__CHANNEL__) == LL_ADC_CHANNEL_VCORE))
1385
1386 /**
1387 * @brief Helper macro to define ADC analog watchdog parameter:
1388 * define a single channel to monitor with analog watchdog
1389 * from sequencer channel and groups definition.
1390 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1391 * Example:
1392 * LL_ADC_SetAnalogWDMonitChannels(
1393 * ADC1, LL_ADC_AWD1,
1394 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1395 * @param __CHANNEL__ This parameter can be one of the following values:
1396 * @arg @ref LL_ADC_CHANNEL_0
1397 * @arg @ref LL_ADC_CHANNEL_1
1398 * @arg @ref LL_ADC_CHANNEL_2
1399 * @arg @ref LL_ADC_CHANNEL_3
1400 * @arg @ref LL_ADC_CHANNEL_4
1401 * @arg @ref LL_ADC_CHANNEL_5
1402 * @arg @ref LL_ADC_CHANNEL_6
1403 * @arg @ref LL_ADC_CHANNEL_7
1404 * @arg @ref LL_ADC_CHANNEL_8
1405 * @arg @ref LL_ADC_CHANNEL_9
1406 * @arg @ref LL_ADC_CHANNEL_10
1407 * @arg @ref LL_ADC_CHANNEL_11
1408 * @arg @ref LL_ADC_CHANNEL_12
1409 * @arg @ref LL_ADC_CHANNEL_13
1410 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1411 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1412 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1413 *
1414 * (1) For ADC channel read back from ADC register,
1415 * comparison with internal channel parameter to be done
1416 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1417 * @param __GROUP__ This parameter can be one of the following values:
1418 * @arg @ref LL_ADC_GROUP_REGULAR
1419 * @retval Returned value can be one of the following values:
1420 * @arg @ref LL_ADC_AWD_DISABLE
1421 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1422 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1423 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1424 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1425 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1426 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1427 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1428 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1429 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1430 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1431 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1432 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1433 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1434 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1435 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1436 * @arg @ref LL_ADC_AWD_CH_VCORE_REG
1437 */
1438 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1439 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
1440
1441 /**
1442 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1443 * or low in function of ADC resolution, when ADC resolution is
1444 * different of 12 bits.
1445 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1446 * or @ref LL_ADC_SetAnalogWDThresholds().
1447 * Example, with a ADC resolution of 8 bits, to set the value of
1448 * analog watchdog threshold high (on 8 bits):
1449 * LL_ADC_SetAnalogWDThresholds
1450 * (< ADCx param >,
1451 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1452 * );
1453 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1454 * @arg @ref LL_ADC_RESOLUTION_12B
1455 * @arg @ref LL_ADC_RESOLUTION_10B
1456 * @arg @ref LL_ADC_RESOLUTION_8B
1457 * @arg @ref LL_ADC_RESOLUTION_6B
1458 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1459 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1460 */
1461 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1462 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U )))
1463
1464 /**
1465 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1466 * or low in function of ADC resolution, when ADC resolution is
1467 * different of 12 bits.
1468 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1469 * Example, with a ADC resolution of 8 bits, to get the value of
1470 * analog watchdog threshold high (on 8 bits):
1471 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1472 * (LL_ADC_RESOLUTION_8B,
1473 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1474 * );
1475 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1476 * @arg @ref LL_ADC_RESOLUTION_12B
1477 * @arg @ref LL_ADC_RESOLUTION_10B
1478 * @arg @ref LL_ADC_RESOLUTION_8B
1479 * @arg @ref LL_ADC_RESOLUTION_6B
1480 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1481 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1482 */
1483 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1484 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U )))
1485
1486 /**
1487 * @brief Helper macro to get the ADC analog watchdog threshold high
1488 * or low from raw value containing both thresholds concatenated.
1489 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1490 * Example, to get analog watchdog threshold high from the register raw value:
1491 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1492 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1493 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1494 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1495 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1496 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1497 */
1498 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1499 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
1500 & LL_ADC_AWD_THRESHOLD_LOW)
1501
1502 /**
1503 * @brief Helper macro to select the ADC common instance
1504 * to which is belonging the selected ADC instance.
1505 * @note ADC common register instance can be used for:
1506 * - Set parameters common to several ADC instances
1507 * - Multimode (for devices with several ADC instances)
1508 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1509 * @param __ADCx__ ADC instance
1510 * @retval ADC common register instance
1511 */
1512 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1513 (ADC4_COMMON)
1514
1515 /**
1516 * @brief Helper macro to check if all ADC instances sharing the same
1517 * ADC common instance are disabled.
1518 * @note This check is required by functions with setting conditioned to
1519 * ADC state:
1520 * All ADC instances of the ADC common group must be disabled.
1521 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1522 * @note On devices with only 1 ADC common instance, parameter of this macro
1523 * is useless and can be ignored (parameter kept for compatibility
1524 * with devices featuring several ADC common instances).
1525 * @param __ADCXY_COMMON__ ADC common instance
1526 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1527 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1528 * are disabled.
1529 * Value "1" if at least one ADC instance sharing the same ADC common instance
1530 * is enabled.
1531 */
1532 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1533 LL_ADC_IsEnabled(ADC4)
1534
1535 /**
1536 * @brief Helper macro to define the ADC conversion data full-scale digital
1537 * value corresponding to the selected ADC resolution.
1538 * @note ADC conversion data full-scale corresponds to voltage range
1539 * determined by analog voltage references Vref+ and Vref-
1540 * (refer to reference manual).
1541 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1542 * @arg @ref LL_ADC_RESOLUTION_12B
1543 * @arg @ref LL_ADC_RESOLUTION_10B
1544 * @arg @ref LL_ADC_RESOLUTION_8B
1545 * @arg @ref LL_ADC_RESOLUTION_6B
1546 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
1547 */
1548 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1549 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1UL)))
1550
1551 /**
1552 * @brief Helper macro to convert the ADC conversion data from
1553 * a resolution to another resolution.
1554 * @param __DATA__ ADC conversion data to be converted
1555 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
1556 * This parameter can be one of the following values:
1557 * @arg @ref LL_ADC_RESOLUTION_12B
1558 * @arg @ref LL_ADC_RESOLUTION_10B
1559 * @arg @ref LL_ADC_RESOLUTION_8B
1560 * @arg @ref LL_ADC_RESOLUTION_6B
1561 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1562 * This parameter can be one of the following values:
1563 * @arg @ref LL_ADC_RESOLUTION_12B
1564 * @arg @ref LL_ADC_RESOLUTION_10B
1565 * @arg @ref LL_ADC_RESOLUTION_8B
1566 * @arg @ref LL_ADC_RESOLUTION_6B
1567 * @retval ADC conversion data to the requested resolution
1568 */
1569 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1570 __ADC_RESOLUTION_CURRENT__,\
1571 __ADC_RESOLUTION_TARGET__) \
1572 (((__DATA__) \
1573 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_Pos - 1UL))) \
1574 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_Pos - 1UL)) \
1575 )
1576
1577 /**
1578 * @brief Helper macro to calculate the voltage (unit: mVolt)
1579 * corresponding to a ADC conversion data (unit: digital value).
1580 * @note Analog reference voltage (Vref+) must be either known from
1581 * user board environment or can be calculated using ADC measurement
1582 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1583 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1584 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1585 * (unit: digital value).
1586 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1587 * @arg @ref LL_ADC_RESOLUTION_12B
1588 * @arg @ref LL_ADC_RESOLUTION_10B
1589 * @arg @ref LL_ADC_RESOLUTION_8B
1590 * @arg @ref LL_ADC_RESOLUTION_6B
1591 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1592 */
1593 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1594 __ADC_DATA__,\
1595 __ADC_RESOLUTION__) \
1596 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1597 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1598 )
1599
1600 /**
1601 * @brief Helper macro to calculate analog reference voltage (Vref+)
1602 * (unit: mVolt) from ADC conversion data of internal voltage
1603 * reference VrefInt.
1604 * @note Computation is using VrefInt calibration value
1605 * stored in system memory for each device during production.
1606 * @note This voltage depends on user board environment: voltage level
1607 * connected to pin Vref+.
1608 * On devices with small package, the pin Vref+ is not present
1609 * and internally bonded to pin Vdda.
1610 * @note On this STM32 series, calibration data of internal voltage reference
1611 * VrefInt corresponds to a resolution of 12 bits,
1612 * this is the recommended ADC resolution to convert voltage of
1613 * internal voltage reference VrefInt.
1614 * Otherwise, this macro performs the processing to scale
1615 * ADC conversion data to 12 bits.
1616 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1617 * of internal voltage reference VrefInt (unit: digital value).
1618 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1619 * @arg @ref LL_ADC_RESOLUTION_12B
1620 * @arg @ref LL_ADC_RESOLUTION_10B
1621 * @arg @ref LL_ADC_RESOLUTION_8B
1622 * @arg @ref LL_ADC_RESOLUTION_6B
1623 * @retval Analog reference voltage (unit: mV)
1624 */
1625 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1626 __ADC_RESOLUTION__) \
1627 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1628 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1629 (__ADC_RESOLUTION__), \
1630 LL_ADC_RESOLUTION_12B) \
1631 )
1632
1633 /**
1634 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1635 * from ADC conversion data of internal temperature sensor.
1636 * @note Computation is using temperature sensor calibration values
1637 * stored in system memory for each device during production.
1638 * @note Calculation formula:
1639 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1640 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1641 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1642 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1643 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1644 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1645 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1646 * TEMP_DEGC_CAL1 (calibrated in factory)
1647 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1648 * TEMP_DEGC_CAL2 (calibrated in factory)
1649 * Caution: Calculation relevancy under reserve that calibration
1650 * parameters are correct (address and data).
1651 * To calculate temperature using temperature sensor
1652 * datasheet typical values (generic values less, therefore
1653 * less accurate than calibrated values),
1654 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1655 * @note As calculation input, the analog reference voltage (Vref+) must be
1656 * defined as it impacts the ADC LSB equivalent voltage.
1657 * @note Analog reference voltage (Vref+) must be either known from
1658 * user board environment or can be calculated using ADC measurement
1659 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1660 * @note On this STM32 series, calibration data of temperature sensor
1661 * corresponds to a resolution of 12 bits,
1662 * this is the recommended ADC resolution to convert voltage of
1663 * temperature sensor.
1664 * Otherwise, this macro performs the processing to scale
1665 * ADC conversion data to 12 bits.
1666 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1667 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1668 * temperature sensor (unit: digital value).
1669 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1670 * sensor voltage has been measured.
1671 * This parameter can be one of the following values:
1672 * @arg @ref LL_ADC_RESOLUTION_12B
1673 * @arg @ref LL_ADC_RESOLUTION_10B
1674 * @arg @ref LL_ADC_RESOLUTION_8B
1675 * @arg @ref LL_ADC_RESOLUTION_6B
1676 * @retval Temperature (unit: degree Celsius)
1677 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
1678 */
1679 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1680 __TEMPSENSOR_ADC_DATA__,\
1681 __ADC_RESOLUTION__)\
1682 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
1683 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1684 (__ADC_RESOLUTION__), \
1685 LL_ADC_RESOLUTION_12B) \
1686 * (__VREFANALOG_VOLTAGE__)) \
1687 / TEMPSENSOR_CAL_VREFANALOG) \
1688 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1689 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1690 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1691 ) + TEMPSENSOR_CAL1_TEMP \
1692 ) \
1693 : \
1694 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
1695 )
1696
1697 /**
1698 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1699 * from ADC conversion data of internal temperature sensor.
1700 * @note Computation is using temperature sensor typical values
1701 * (refer to device datasheet).
1702 * @note Calculation formula:
1703 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1704 * / Avg_Slope + CALx_TEMP
1705 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1706 * (unit: digital value)
1707 * Avg_Slope = temperature sensor slope
1708 * (unit: uV/Degree Celsius)
1709 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1710 * temperature CALx_TEMP (unit: mV)
1711 * Caution: Calculation relevancy under reserve the temperature sensor
1712 * of the current device has characteristics in line with
1713 * datasheet typical values.
1714 * If temperature sensor calibration values are available on
1715 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1716 * temperature calculation will be more accurate using
1717 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1718 * @note As calculation input, the analog reference voltage (Vref+) must be
1719 * defined as it impacts the ADC LSB equivalent voltage.
1720 * @note Analog reference voltage (Vref+) must be either known from
1721 * user board environment or can be calculated using ADC measurement
1722 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1723 * @note ADC measurement data must correspond to a resolution of 12 bits
1724 * (full scale digital value 4095). If not the case, the data must be
1725 * preliminarily rescaled to an equivalent resolution of 12 bits.
1726 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
1727 (unit: uV/DegCelsius).
1728 * On this STM32 series, refer to device datasheet parameter "Avg_Slope".
1729 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
1730 (at temperature and Vref+ defined in parameters below) (unit: mV).
1731 * On this STM32 series, refer to datasheet parameter "V30" (corresponding
1732 * to TS_CAL1).
1733 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
1734 (see parameter above) is corresponding (unit: degree Celsius)
1735 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
1736 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1737 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1738 * This parameter can be one of the following values:
1739 * @arg @ref LL_ADC_RESOLUTION_12B
1740 * @arg @ref LL_ADC_RESOLUTION_10B
1741 * @arg @ref LL_ADC_RESOLUTION_8B
1742 * @arg @ref LL_ADC_RESOLUTION_6B
1743 * @retval Temperature (unit: degree Celsius)
1744 */
1745 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1746 __TEMPSENSOR_TYP_CALX_V__,\
1747 __TEMPSENSOR_CALX_TEMP__,\
1748 __VREFANALOG_VOLTAGE__,\
1749 __TEMPSENSOR_ADC_DATA__,\
1750 __ADC_RESOLUTION__) \
1751 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1752 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1753 * 1000UL) \
1754 - \
1755 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1756 * 1000UL) \
1757 ) \
1758 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
1759 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
1760 )
1761
1762 /**
1763 * @}
1764 */
1765
1766 /**
1767 * @}
1768 */
1769
1770
1771 /* Exported functions --------------------------------------------------------*/
1772 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1773 * @{
1774 */
1775
1776 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1777 * @{
1778 */
1779 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1780 /* configuration of ADC instance, groups and multimode (if available): */
1781 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1782
1783 /**
1784 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1785 * ADC register address from ADC instance and a list of ADC registers
1786 * intended to be used (most commonly) with DMA transfer.
1787 * @note These ADC registers are data registers:
1788 * when ADC conversion data is available in ADC data registers,
1789 * ADC generates a DMA transfer request.
1790 * @note This macro is intended to be used with LL DMA driver, refer to
1791 * function "LL_DMA_ConfigAddresses()".
1792 * Example:
1793 * LL_DMA_ConfigAddresses(DMA1,
1794 * LL_DMA_CHANNEL_1,
1795 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1796 * (uint32_t)&< array or variable >,
1797 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1798 * @note For devices with several ADC: in multimode, some devices
1799 * use a different data register outside of ADC instance scope
1800 * (common data register). This macro manages this register difference,
1801 * only ADC instance has to be set as parameter.
1802 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1803 * @param ADCx ADC instance
1804 * @param Register This parameter can be one of the following values:
1805 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1806 * @retval ADC register address
1807 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)1808 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
1809 {
1810 /* Prevent unused argument(s) compilation warning */
1811 (void)(Register);
1812
1813 /* Retrieve address of register DR */
1814 return (uint32_t) &(ADCx->DR);
1815 }
1816
1817 /**
1818 * @}
1819 */
1820
1821 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
1822 * ADC instances
1823 * @{
1824 */
1825
1826 /**
1827 * @brief Set parameter common to several ADC: Clock source and prescaler.
1828 * @note On this STM32 series, setting of this feature is conditioned to
1829 * ADC state:
1830 * All ADC instances of the ADC common group must be disabled.
1831 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1832 * ADC instance or by using helper macro helper macro
1833 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1834 * @rmtoll CCR PRESC LL_ADC_SetCommonClock
1835 * @param ADCxy_COMMON ADC common instance
1836 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1837 * @param CommonClock This parameter can be one of the following values:
1838 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1839 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1840 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1841 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1842 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1843 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1844 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1845 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1846 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1847 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1848 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1849 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1850 * @retval None
1851 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1852 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1853 {
1854 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
1855 }
1856
1857 /**
1858 * @brief Get parameter common to several ADC: Clock source and prescaler.
1859 * @rmtoll CCR PRESC LL_ADC_GetCommonClock
1860 * @param ADCxy_COMMON ADC common instance
1861 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1862 * @retval Returned value can be one of the following values:
1863 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1864 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1865 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1866 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1867 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1868 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1869 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1870 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1871 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1872 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1873 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1874 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1875 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)1876 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
1877 {
1878 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
1879 }
1880
1881 /**
1882 * @brief Set parameter common to several ADC: measurement path to
1883 * internal channels (VrefInt, temperature sensor, ...).
1884 * Configure all paths (overwrite current configuration).
1885 * @note One or several values can be selected.
1886 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1887 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1888 * The values not selected are removed from configuration.
1889 * @note Stabilization time of measurement path to internal channel:
1890 * After enabling internal paths, before starting ADC conversion,
1891 * a delay is required for internal voltage reference and
1892 * temperature sensor stabilization time.
1893 * Refer to device datasheet.
1894 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1895 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
1896 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
1897 * @note ADC internal channel sampling time constraint:
1898 * For ADC conversion of internal channels,
1899 * a sampling time minimum value is required.
1900 * Refer to device datasheet.
1901 * @note On this STM32 series, setting of this feature is conditioned to
1902 * ADC state:
1903 * All ADC instances of the ADC common group must be disabled.
1904 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1905 * ADC instance or by using helper macro helper macro
1906 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1907 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
1908 * CCR TSEN LL_ADC_SetCommonPathInternalCh
1909 * @param ADCxy_COMMON ADC common instance
1910 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1911 * @param PathInternal This parameter can be a combination of the following values:
1912 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1913 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1914 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1915 * @retval None
1916 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1917 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1918 {
1919 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
1920 }
1921
1922 /**
1923 * @brief Set parameter common to several ADC: measurement path to
1924 * internal channels (VrefInt, temperature sensor, ...).
1925 * Add paths to the current configuration.
1926 * @note One or several values can be selected.
1927 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1928 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1929 * @note Stabilization time of measurement path to internal channel:
1930 * After enabling internal paths, before starting ADC conversion,
1931 * a delay is required for internal voltage reference and
1932 * temperature sensor stabilization time.
1933 * Refer to device datasheet.
1934 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1935 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
1936 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
1937 * @note ADC internal channel sampling time constraint:
1938 * For ADC conversion of internal channels,
1939 * a sampling time minimum value is required.
1940 * Refer to device datasheet.
1941 * @note On this STM32 series, setting of this feature is conditioned to
1942 * ADC state:
1943 * All ADC instances of the ADC common group must be disabled.
1944 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1945 * ADC instance or by using helper macro helper macro
1946 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1947 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
1948 * CCR TSEN LL_ADC_SetCommonPathInternalCh
1949 * @param ADCxy_COMMON ADC common instance
1950 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1951 * @param PathInternal This parameter can be a combination of the following values:
1952 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1953 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1954 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1955 * @retval None
1956 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1957 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1958 {
1959 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
1960 }
1961
1962 /**
1963 * @brief Set parameter common to several ADC: measurement path to
1964 * internal channels (VrefInt, temperature sensor, ...).
1965 * Remove paths to the current configuration.
1966 * @note One or several values can be selected.
1967 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1968 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1969 * @note On this STM32 series, setting of this feature is conditioned to
1970 * ADC state:
1971 * All ADC instances of the ADC common group must be disabled.
1972 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1973 * ADC instance or by using helper macro helper macro
1974 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1975 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
1976 * CCR TSEN LL_ADC_SetCommonPathInternalChRem
1977 * @param ADCxy_COMMON ADC common instance
1978 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1979 * @param PathInternal This parameter can be a combination of the following values:
1980 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1981 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1982 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1983 * @retval None
1984 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1985 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1986 {
1987 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
1988 }
1989
1990 /**
1991 * @brief Get parameter common to several ADC: measurement path to internal
1992 * channels (VrefInt, temperature sensor, ...).
1993 * @note One or several values can be selected.
1994 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1995 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1996 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
1997 * CCR TSEN LL_ADC_GetCommonPathInternalCh
1998 * @param ADCxy_COMMON ADC common instance
1999 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2000 * @retval Returned value can be a combination of the following values:
2001 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2002 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2003 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2004 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)2005 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
2006 {
2007 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
2008 }
2009
2010 /**
2011 * @}
2012 */
2013
2014 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2015 * @{
2016 */
2017
2018 /**
2019 * @brief Set ADC calibration factor in the mode single-ended
2020 * or differential (for devices with differential mode available).
2021 * @note This function is intended to set calibration parameters
2022 * without having to perform a new calibration using
2023 * @ref LL_ADC_StartCalibration().
2024 * @note On this STM32 series, setting of this feature is conditioned to
2025 * ADC state:
2026 * ADC must be enabled, without calibration on going, without conversion
2027 * on going on group regular.
2028 * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor
2029 * @param ADCx ADC instance
2030 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2031 * @retval None
2032 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)2033 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
2034 {
2035 MODIFY_REG(ADCx->CALFACT,
2036 ADC_CALFACT_CALFACT,
2037 CalibrationFactor);
2038 }
2039
2040 /**
2041 * @brief Get ADC calibration factor in the mode single-ended
2042 * or differential (for devices with differential mode available).
2043 * @note Calibration factors are set by hardware after performing
2044 * a calibration run using function @ref LL_ADC_StartCalibration().
2045 * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor
2046 * @param ADCx ADC instance
2047 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2048 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx)2049 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx)
2050 {
2051 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
2052 }
2053
2054 /**
2055 * @brief Set ADC resolution.
2056 * Refer to reference manual for alignments formats
2057 * dependencies to ADC resolutions.
2058 * @note On this STM32 series, setting of this feature is conditioned to
2059 * ADC state:
2060 * ADC must be disabled or enabled without conversion on going
2061 * on group regular.
2062 * @rmtoll CFGR1 RES LL_ADC_SetResolution
2063 * @param ADCx ADC instance
2064 * @param Resolution This parameter can be one of the following values:
2065 * @arg @ref LL_ADC_RESOLUTION_12B
2066 * @arg @ref LL_ADC_RESOLUTION_10B
2067 * @arg @ref LL_ADC_RESOLUTION_8B
2068 * @arg @ref LL_ADC_RESOLUTION_6B
2069 * @retval None
2070 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2071 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2072 {
2073 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
2074 }
2075
2076 /**
2077 * @brief Get ADC resolution.
2078 * Refer to reference manual for alignments formats
2079 * dependencies to ADC resolutions.
2080 * @rmtoll CFGR1 RES LL_ADC_GetResolution
2081 * @param ADCx ADC instance
2082 * @retval Returned value can be one of the following values:
2083 * @arg @ref LL_ADC_RESOLUTION_12B
2084 * @arg @ref LL_ADC_RESOLUTION_10B
2085 * @arg @ref LL_ADC_RESOLUTION_8B
2086 * @arg @ref LL_ADC_RESOLUTION_6B
2087 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)2088 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
2089 {
2090 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
2091 }
2092
2093 /**
2094 * @brief Set ADC conversion data alignment.
2095 * @note Refer to reference manual for alignments formats
2096 * dependencies to ADC resolutions.
2097 * @note On this STM32 series, setting of this feature is conditioned to
2098 * ADC state:
2099 * ADC must be disabled or enabled without conversion on going
2100 * on group regular.
2101 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
2102 * @param ADCx ADC instance
2103 * @param DataAlignment This parameter can be one of the following values:
2104 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2105 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2106 * @retval None
2107 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2108 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2109 {
2110 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
2111 }
2112
2113 /**
2114 * @brief Get ADC conversion data alignment.
2115 * @note Refer to reference manual for alignments formats
2116 * dependencies to ADC resolutions.
2117 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
2118 * @param ADCx ADC instance
2119 * @retval Returned value can be one of the following values:
2120 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2121 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2122 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)2123 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
2124 {
2125 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2126 }
2127
2128 /**
2129 * @brief Set ADC low power mode.
2130 * @note Description of ADC low power modes:
2131 * - ADC low power mode "auto wait": Dynamic low power mode,
2132 * ADC conversions occurrences are limited to the minimum necessary
2133 * in order to reduce power consumption.
2134 * New ADC conversion starts only when the previous
2135 * unitary conversion data (for ADC group regular)
2136 * has been retrieved by user software.
2137 * In the meantime, ADC remains idle: does not performs any
2138 * other conversion.
2139 * This mode allows to automatically adapt the ADC conversions
2140 * triggers to the speed of the software that reads the data.
2141 * Moreover, this avoids risk of overrun for low frequency
2142 * applications.
2143 * How to use this low power mode:
2144 * - It is not recommended to use with interruption or DMA
2145 * since these modes have to clear immediately the EOC flag
2146 * (by CPU to free the IRQ pending event or by DMA).
2147 * Auto wait will work but fort a very short time, discarding
2148 * its intended benefit (except specific case of high load of CPU
2149 * or DMA transfers which can justify usage of auto wait).
2150 * - Do use with polling: 1. Start conversion,
2151 * 2. Later on, when conversion data is needed: poll for end of
2152 * conversion to ensure that conversion is completed and
2153 * retrieve ADC conversion data. This will trig another
2154 * ADC conversion start.
2155 * @note With ADC low power mode "auto wait", the ADC conversion data read
2156 * is corresponding to previous ADC conversion start, independently
2157 * of delay during which ADC was idle.
2158 * Therefore, the ADC conversion data may be outdated: does not
2159 * correspond to the current voltage level on the selected
2160 * ADC channel.
2161 * @note On this STM32 series, setting of this feature is conditioned to
2162 * ADC state:
2163 * ADC must be disabled or enabled without conversion on going
2164 * on group regular.
2165 * @rmtoll CFGR WAIT LL_ADC_SetLPModeAutoWait
2166 * @param ADCx ADC instance
2167 * @param LowPowerMode This parameter can be one of the following values:
2168 * @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE
2169 * @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE
2170 * @retval None
2171 */
LL_ADC_SetLPModeAutoWait(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2172 __STATIC_INLINE void LL_ADC_SetLPModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2173 {
2174 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT), LowPowerMode);
2175 }
2176
2177 /**
2178 * @brief Get ADC low power mode:
2179 * @note Description of ADC low power modes:
2180 * - ADC low power mode "auto wait": Dynamic low power mode,
2181 * ADC conversions occurrences are limited to the minimum necessary
2182 * in order to reduce power consumption.
2183 * New ADC conversion starts only when the previous
2184 * unitary conversion data (for ADC group regular)
2185 * has been retrieved by user software.
2186 * In the meantime, ADC remains idle: does not performs any
2187 * other conversion.
2188 * This mode allows to automatically adapt the ADC conversions
2189 * triggers to the speed of the software that reads the data.
2190 * Moreover, this avoids risk of overrun for low frequency
2191 * applications.
2192 * How to use this low power mode:
2193 * - It is not recommended to use with interruption or DMA
2194 * since these modes have to clear immediately the EOC flag
2195 * (by CPU to free the IRQ pending event or by DMA).
2196 * Auto wait will work but fort a very short time, discarding
2197 * its intended benefit (except specific case of high load of CPU
2198 * or DMA transfers which can justify usage of auto wait).
2199 * - Do use with polling: 1. Start conversion,
2200 * 2. Later on, when conversion data is needed: poll for end of
2201 * conversion to ensure that conversion is completed and
2202 * retrieve ADC conversion data. This will trig another
2203 * ADC conversion start.
2204 * @note With ADC low power mode "auto wait", the ADC conversion data read
2205 * is corresponding to previous ADC conversion start, independently
2206 * of delay during which ADC was idle.
2207 * Therefore, the ADC conversion data may be outdated: does not
2208 * correspond to the current voltage level on the selected
2209 * ADC channel.
2210 * @rmtoll CFGR WAIT LL_ADC_GetLPModeAutoWait
2211 * @param ADCx ADC instance
2212 * @retval Returned value can be one of the following values:
2213 * @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE
2214 * @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE
2215 */
LL_ADC_GetLPModeAutoWait(const ADC_TypeDef * ADCx)2216 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoWait(const ADC_TypeDef *ADCx)
2217 {
2218 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_WAIT));
2219 }
2220
2221 /* Definitions for backward compatibility with legacy STM32 series */
2222 #define LL_ADC_SetLowPowerMode LL_ADC_SetLPModeAutoWait /* Redefinition for legacy purpose */
2223 #define LL_ADC_GetLowPowerMode LL_ADC_GetLPModeAutoWait /* Redefinition for legacy purpose */
2224
2225 /**
2226 * @brief Set ADC low power mode: auto power off.
2227 * @note Description of ADC low power mode:
2228 * - ADC low power mode "auto power-off":
2229 * the ADC automatically powers-off after a conversion and
2230 * automatically wakes up when a new conversion is triggered
2231 * (with startup time between trigger and start of sampling).
2232 * This feature can be combined with low power mode "auto wait".
2233 * @note On this STM32 series, setting of this feature is conditioned to
2234 * ADC state:
2235 * ADC must be disabled.
2236 * @rmtoll PWRR AUTOFF LL_ADC_SetLPModeAutoPowerOff
2237 * @param ADCx ADC instance
2238 * @param LowPowerMode This parameter can be one of the following values:
2239 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
2240 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
2241 * @retval None
2242 */
LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2243 __STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2244 {
2245 MODIFY_REG(ADCx->PWRR, ADC_PWRR_AUTOFF, LowPowerMode);
2246 }
2247
2248 /**
2249 * @brief Get ADC low power mode: auto power off.
2250 * @note Description of ADC low power mode:
2251 * - ADC low power mode "auto power-off":
2252 * the ADC automatically powers-off after a conversion and
2253 * automatically wakes up when a new conversion is triggered
2254 * (with startup time between trigger and start of sampling).
2255 * This feature can be combined with low power mode "auto wait".
2256 * @rmtoll PWRR AUTOFF LL_ADC_GetLPModeAutoPowerOff
2257 * @param ADCx ADC instance
2258 * @retval Returned value can be one of the following values:
2259 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
2260 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
2261 */
LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef * ADCx)2262 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef *ADCx)
2263 {
2264 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC_PWRR_AUTOFF));
2265 }
2266
2267 /**
2268 * @brief Set ADC low power mode: deep power down in autonomous mode
2269 * @note On this STM32 series, setting of this feature is conditioned to
2270 * ADC state:
2271 * ADC must be disabled.
2272 * @rmtoll PWRR DPD LL_ADC_SetLPModeAutonomousDPD
2273 * @param ADCx ADC instance
2274 * @param LowPowerMode This parameter can be one of the following values:
2275 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
2276 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
2277 * @retval None
2278 */
LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2279 __STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2280 {
2281 MODIFY_REG(ADCx->PWRR, ADC_PWRR_DPD, LowPowerMode);
2282 }
2283
2284 /**
2285 * @brief Get ADC low power mode: deep power down in autonomous mode
2286 * @rmtoll PWRR DPD LL_ADC_GetLPModeAutonomousDPD
2287 * @param ADCx ADC instance
2288 * @retval Returned value can be one of the following values:
2289 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
2290 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
2291 */
LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef * ADCx)2292 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx)
2293 {
2294 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC_PWRR_DPD));
2295 }
2296
2297
2298 /**
2299 * @brief Set ADC trigger frequency mode.
2300 * @note ADC trigger frequency mode must be set to low frequency when
2301 * a duration is exceeded before ADC conversion start trigger event
2302 * (between ADC enable and ADC conversion start trigger event
2303 * or between two ADC conversion start trigger event).
2304 * Duration value: Refer to device datasheet, parameter "tIdle".
2305 * @note When ADC trigger frequency mode is set to low frequency,
2306 * some rearm cycles are inserted before performing ADC conversion
2307 * start, inducing a delay of 2 ADC clock cycles.
2308 * @note Usage of ADC trigger frequency mode with ADC low power mode:
2309 * - Low power mode auto wait: Only the first ADC conversion
2310 * start trigger inserts the rearm delay.
2311 * @note On this STM32 series, setting of this feature is conditioned to
2312 * ADC state:
2313 * ADC must be disabled.
2314 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
2315 * @param ADCx ADC instance
2316 * @param TriggerFrequencyMode This parameter can be one of the following values:
2317 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2318 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2319 * @retval None
2320 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)2321 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
2322 {
2323 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
2324 }
2325
2326 /**
2327 * @brief Get ADC trigger frequency mode.
2328 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
2329 * @param ADCx ADC instance
2330 * @retval Returned value can be one of the following values:
2331 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2332 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2333 */
LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef * ADCx)2334 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx)
2335 {
2336 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
2337 }
2338
2339 /**
2340 * @brief Set sampling time common to a group of channels.
2341 * @note Unit: ADC clock cycles.
2342 * @note On this STM32 series, sampling time scope is on ADC instance:
2343 * Sampling time common to all channels.
2344 * (on some other STM32 series, sampling time is channel wise)
2345 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2346 * converted:
2347 * sampling time constraints must be respected (sampling time can be
2348 * adjusted in function of ADC clock frequency and sampling time
2349 * setting).
2350 * Refer to device datasheet for timings values (parameters TS_vrefint,
2351 * TS_temp, ...).
2352 * @note Conversion time is the addition of sampling time and processing time.
2353 * On this STM32 series, ADC processing time is:
2354 * - 12.5 ADC clock cycles at ADC resolution 12 bits
2355 * - 10.5 ADC clock cycles at ADC resolution 10 bits
2356 * - 8.5 ADC clock cycles at ADC resolution 8 bits
2357 * - 6.5 ADC clock cycles at ADC resolution 6 bits
2358 * @note In case of ADC conversion of internal channel (VrefInt,
2359 * temperature sensor, ...), a sampling time minimum value
2360 * is required.
2361 * Refer to device datasheet.
2362 * @note On this STM32 series, setting of this feature is conditioned to
2363 * ADC state:
2364 * ADC must be disabled or enabled without conversion on going
2365 * on group regular.
2366 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
2367 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
2368 * @param ADCx ADC instance
2369 * @param SamplingTimeY This parameter can be one of the following values:
2370 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2371 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2372 * @param SamplingTime This parameter can be one of the following values:
2373 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2374 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2375 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2376 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2377 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2378 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2379 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2380 * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES_5
2381 * @retval None
2382 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)2383 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
2384 uint32_t SamplingTime)
2385 {
2386 MODIFY_REG(ADCx->SMPR,
2387 ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
2388 SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2389 }
2390
2391 /**
2392 * @brief Get sampling time common to a group of channels.
2393 * @note Unit: ADC clock cycles.
2394 * @note On this STM32 series, sampling time scope is on ADC instance:
2395 * Sampling time common to all channels.
2396 * (on some other STM32 series, sampling time is channel wise)
2397 * @note Conversion time is the addition of sampling time and processing time.
2398 * Refer to reference manual for ADC processing time of
2399 * this STM32 series.
2400 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
2401 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
2402 * @param ADCx ADC instance
2403 * @param SamplingTimeY This parameter can be one of the following values:
2404 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2405 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2406 * @retval Returned value can be one of the following values:
2407 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2408 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2409 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2410 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2411 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2412 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2413 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2414 * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES_5
2415 */
LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef * ADCx,uint32_t SamplingTimeY)2416 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
2417 {
2418 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
2419 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2420 }
2421
2422 /**
2423 * @}
2424 */
2425
2426 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2427 * @{
2428 */
2429
2430 /**
2431 * @brief Set ADC group regular conversion trigger source:
2432 * internal (SW start) or from external peripheral (timer event,
2433 * external interrupt line).
2434 * @note On this STM32 series, setting trigger source to external trigger
2435 * also set trigger polarity to rising edge
2436 * (default setting for compatibility with some ADC on other
2437 * STM32 series having this setting set by HW default value).
2438 * In case of need to modify trigger edge, use
2439 * function @ref LL_ADC_REG_SetTriggerEdge().
2440 * @note On this STM32 series, ADC trigger frequency mode must be set
2441 * in function of frequency of ADC group regular conversion trigger.
2442 * Refer to description of function
2443 * @ref LL_ADC_SetTriggerFrequencyMode().
2444 * @note Availability of parameters of trigger sources from timer
2445 * depends on timers availability on the selected device.
2446 * @note On this STM32 series, setting of this feature is conditioned to
2447 * ADC state:
2448 * ADC must be disabled or enabled without conversion on going
2449 * on group regular.
2450 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
2451 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
2452 * @param ADCx ADC instance
2453 * @param TriggerSource This parameter can be one of the following values:
2454 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2455 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2456 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2457 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2458 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
2459 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE15
2460 * @retval None
2461 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2462 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2463 {
2464 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
2465 }
2466
2467 /**
2468 * @brief Get ADC group regular conversion trigger source:
2469 * internal (SW start) or from external peripheral (timer event,
2470 * external interrupt line).
2471 * @note To determine whether group regular trigger source is
2472 * internal (SW start) or external, without detail
2473 * of which peripheral is selected as external trigger,
2474 * (equivalent to
2475 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2476 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2477 * @note Availability of parameters of trigger sources from timer
2478 * depends on timers availability on the selected device.
2479 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
2480 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
2481 * @param ADCx ADC instance
2482 * @retval Returned value can be one of the following values:
2483 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2484 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2485 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2486 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2487 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
2488 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE15
2489 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)2490 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
2491 {
2492 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
2493
2494 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2495 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
2496 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2497
2498 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
2499 /* to match with triggers literals definition. */
2500 return ((trigger_source
2501 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
2502 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
2503 );
2504 }
2505
2506 /**
2507 * @brief Get ADC group regular conversion trigger source internal (SW start)
2508 * or external.
2509 * @note In case of group regular trigger source set to external trigger,
2510 * to determine which peripheral is selected as external trigger,
2511 * use function @ref LL_ADC_REG_GetTriggerSource().
2512 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2513 * @param ADCx ADC instance
2514 * @retval Value "0" if trigger source external trigger
2515 * Value "1" if trigger source SW start.
2516 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)2517 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
2518 {
2519 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
2520 }
2521
2522 /**
2523 * @brief Set ADC group regular conversion trigger polarity.
2524 * @note Applicable only for trigger source set to external trigger.
2525 * @note On this STM32 series, setting of this feature is conditioned to
2526 * ADC state:
2527 * ADC must be disabled or enabled without conversion on going
2528 * on group regular.
2529 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
2530 * @param ADCx ADC instance
2531 * @param ExternalTriggerEdge This parameter can be one of the following values:
2532 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2533 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2534 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2535 * @retval None
2536 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)2537 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
2538 {
2539 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
2540 }
2541
2542 /**
2543 * @brief Get ADC group regular conversion trigger polarity.
2544 * @note Applicable only for trigger source set to external trigger.
2545 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
2546 * @param ADCx ADC instance
2547 * @retval Returned value can be one of the following values:
2548 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2549 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2550 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2551 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)2552 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
2553 {
2554 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
2555 }
2556
2557 /**
2558 * @brief Set ADC group regular sequencer configuration flexibility.
2559 * @note On this STM32 series, ADC group regular sequencer both modes
2560 * "fully configurable" or "not fully configurable" are
2561 * available:
2562 * - sequencer configured to fully configurable:
2563 * sequencer length and each rank
2564 * affectation to a channel are configurable.
2565 * Refer to description of function
2566 * @ref LL_ADC_REG_SetSequencerLength().
2567 * - sequencer configured to not fully configurable:
2568 * sequencer length and each rank affectation to a channel
2569 * are fixed by channel HW number.
2570 * Refer to description of function
2571 * @ref LL_ADC_REG_SetSequencerChannels().
2572 * @note On this STM32 series, setting of this feature is conditioned to
2573 * ADC state:
2574 * ADC must be disabled or enabled without conversion on going
2575 * on group regular.
2576 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2577 * @param ADCx ADC instance
2578 * @param Configurability This parameter can be one of the following values:
2579 * @arg @ref LL_ADC_REG_SEQ_FIXED
2580 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2581 * @retval None
2582 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)2583 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
2584 {
2585 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
2586 }
2587
2588 /**
2589 * @brief Get ADC group regular sequencer configuration flexibility.
2590 * @note On this STM32 series, ADC group regular sequencer both modes
2591 * "fully configurable" or "not fully configurable" are
2592 * available:
2593 * - sequencer configured to fully configurable:
2594 * sequencer length and each rank
2595 * affectation to a channel are configurable.
2596 * Refer to description of function
2597 * @ref LL_ADC_REG_SetSequencerLength().
2598 * - sequencer configured to not fully configurable:
2599 * sequencer length and each rank affectation to a channel
2600 * are fixed by channel HW number.
2601 * Refer to description of function
2602 * @ref LL_ADC_REG_SetSequencerChannels().
2603 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2604 * @param ADCx ADC instance
2605 * @retval Returned value can be one of the following values:
2606 * @arg @ref LL_ADC_REG_SEQ_FIXED
2607 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2608 */
LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef * ADCx)2609 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx)
2610 {
2611 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
2612 }
2613
2614 /**
2615 * @brief Set ADC group regular sequencer length and scan direction.
2616 * @note Description of ADC group regular sequencer features:
2617 * - For devices with sequencer fully configurable
2618 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2619 * sequencer length and each rank affectation to a channel
2620 * are configurable.
2621 * This function performs configuration of:
2622 * - Sequence length: Number of ranks in the scan sequence.
2623 * - Sequence direction: Unless specified in parameters, sequencer
2624 * scan direction is forward (from rank 1 to rank n).
2625 * Sequencer ranks are selected using
2626 * function "LL_ADC_REG_SetSequencerRanks()".
2627 * - For devices with sequencer not fully configurable
2628 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2629 * sequencer length and each rank affectation to a channel
2630 * are defined by channel number.
2631 * This function performs configuration of:
2632 * - Sequence length: Number of ranks in the scan sequence is
2633 * defined by number of channels set in the sequence,
2634 * rank of each channel is fixed by channel HW number.
2635 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2636 * - Sequence direction: Unless specified in parameters, sequencer
2637 * scan direction is forward (from lowest channel number to
2638 * highest channel number).
2639 * Sequencer ranks are selected using
2640 * function "LL_ADC_REG_SetSequencerChannels()".
2641 * To set scan direction differently, refer to function
2642 * @ref LL_ADC_REG_SetSequencerScanDirection().
2643 * @note On this STM32 series, ADC group regular sequencer both modes
2644 * "fully configurable" or "not fully configurable"
2645 * are available, they can be chosen using
2646 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2647 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2648 * ADC conversion on only 1 channel.
2649 * @note On this STM32 series, setting of this feature is conditioned to
2650 * ADC state:
2651 * ADC must be disabled or enabled without conversion on going
2652 * on group regular.
2653 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
2654 * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
2655 * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
2656 * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
2657 * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
2658 * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
2659 * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
2660 * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
2661 * @param ADCx ADC instance
2662 * @param SequencerNbRanks This parameter can be one of the following values:
2663 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2664 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2665 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2666 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2667 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2668 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2669 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2670 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2671 * @retval None
2672 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2673 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2674 {
2675 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
2676 }
2677
2678 /**
2679 * @brief Get ADC group regular sequencer length and scan direction.
2680 * @note Description of ADC group regular sequencer features:
2681 * - For devices with sequencer fully configurable
2682 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2683 * sequencer length and each rank affectation to a channel
2684 * are configurable.
2685 * This function retrieves:
2686 * - Sequence length: Number of ranks in the scan sequence.
2687 * - Sequence direction: Unless specified in parameters, sequencer
2688 * scan direction is forward (from rank 1 to rank n).
2689 * Sequencer ranks are selected using
2690 * function "LL_ADC_REG_SetSequencerRanks()".
2691 * - For devices with sequencer not fully configurable
2692 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2693 * sequencer length and each rank affectation to a channel
2694 * are defined by channel number.
2695 * This function retrieves:
2696 * - Sequence length: Number of ranks in the scan sequence is
2697 * defined by number of channels set in the sequence,
2698 * rank of each channel is fixed by channel HW number.
2699 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2700 * - Sequence direction: Unless specified in parameters, sequencer
2701 * scan direction is forward (from lowest channel number to
2702 * highest channel number).
2703 * Sequencer ranks are selected using
2704 * function "LL_ADC_REG_SetSequencerChannels()".
2705 * To set scan direction differently, refer to function
2706 * @ref LL_ADC_REG_SetSequencerScanDirection().
2707 * @note On this STM32 series, ADC group regular sequencer both modes
2708 * "fully configurable" or "not fully configurable"
2709 * are available, they can be chosen using
2710 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2711 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2712 * ADC conversion on only 1 channel.
2713 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
2714 * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
2715 * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
2716 * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
2717 * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
2718 * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
2719 * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
2720 * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
2721 * @param ADCx ADC instance
2722 * @retval Returned value can be one of the following values:
2723 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2724 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2725 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2726 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2727 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2728 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2729 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2730 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2731 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)2732 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
2733 {
2734 __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
2735 uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
2736 uint32_t rank_index;
2737 uint32_t rank_shifted;
2738
2739 /* Parse register for end of sequence identifier */
2740 /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
2741 (ADC_CHSELR_SQ2), value "4" to length of end of sequence
2742 identifier (0xF) */
2743 for (rank_index = 0U; rank_index <= (28U - 4U); rank_index += 4U)
2744 {
2745 rank_shifted = (uint32_t)(0xF0UL << rank_index);
2746 if ((channels_ranks & rank_shifted) == rank_shifted)
2747 {
2748 sequencer_length = rank_shifted;
2749 break;
2750 }
2751 }
2752
2753 return sequencer_length;
2754 }
2755
2756 /**
2757 * @brief Set ADC group regular sequencer scan direction.
2758 * @note On this STM32 series, parameter relevant only is sequencer is set
2759 * to mode not fully configurable,
2760 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2761 * @note On some other STM32 series, this setting is not available and
2762 * the default scan direction is forward.
2763 * @note On this STM32 series, setting of this feature is conditioned to
2764 * ADC state:
2765 * ADC must be disabled or enabled without conversion on going
2766 * on group regular.
2767 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
2768 * @param ADCx ADC instance
2769 * @param ScanDirection This parameter can be one of the following values:
2770 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2771 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2772 * @retval None
2773 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)2774 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
2775 {
2776 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
2777 }
2778
2779 /**
2780 * @brief Get ADC group regular sequencer scan direction.
2781 * @note On this STM32 series, parameter relevant only is sequencer is set
2782 * to mode not fully configurable,
2783 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2784 * @note On some other STM32 series, this setting is not available and
2785 * the default scan direction is forward.
2786 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
2787 * @param ADCx ADC instance
2788 * @retval Returned value can be one of the following values:
2789 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2790 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2791 */
LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef * ADCx)2792 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx)
2793 {
2794 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
2795 }
2796
2797 /**
2798 * @brief Set ADC group regular sequencer discontinuous mode:
2799 * sequence subdivided and scan conversions interrupted every selected
2800 * number of ranks.
2801 * @note It is not possible to enable both ADC group regular
2802 * continuous mode and sequencer discontinuous mode.
2803 * @note On this STM32 series, setting of this feature is conditioned to
2804 * ADC state:
2805 * ADC must be disabled or enabled without conversion on going
2806 * on group regular.
2807 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2808 * @param ADCx ADC instance
2809 * @param SeqDiscont This parameter can be one of the following values:
2810 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2811 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2812 * @retval None
2813 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2814 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2815 {
2816 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
2817 }
2818
2819 /**
2820 * @brief Get ADC group regular sequencer discontinuous mode:
2821 * sequence subdivided and scan conversions interrupted every selected
2822 * number of ranks.
2823 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2824 * @param ADCx ADC instance
2825 * @retval Returned value can be one of the following values:
2826 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2827 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2828 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)2829 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
2830 {
2831 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
2832 }
2833
2834 /**
2835 * @brief Set ADC group regular sequence: channel on the selected
2836 * scan sequence rank.
2837 * @note This function performs configuration of:
2838 * - Channels ordering into each rank of scan sequence:
2839 * whatever channel can be placed into whatever rank.
2840 * @note On this STM32 series, ADC group regular sequencer is
2841 * fully configurable: sequencer length and each rank
2842 * affectation to a channel are configurable.
2843 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2844 * @note Depending on devices and packages, some channels may not be available.
2845 * Refer to device datasheet for channels availability.
2846 * @note On this STM32 series, to measure internal channels (VrefInt,
2847 * TempSensor, ...), measurement paths to internal channels must be
2848 * enabled separately.
2849 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2850 * @note On this STM32 series, setting of this feature is conditioned to
2851 * ADC state:
2852 * ADC must be disabled or enabled without conversion on going
2853 * on group regular.
2854 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n
2855 * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n
2856 * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n
2857 * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n
2858 * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n
2859 * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n
2860 * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n
2861 * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks
2862 * @param ADCx ADC instance
2863 * @param Rank This parameter can be one of the following values:
2864 * @arg @ref LL_ADC_REG_RANK_1
2865 * @arg @ref LL_ADC_REG_RANK_2
2866 * @arg @ref LL_ADC_REG_RANK_3
2867 * @arg @ref LL_ADC_REG_RANK_4
2868 * @arg @ref LL_ADC_REG_RANK_5
2869 * @arg @ref LL_ADC_REG_RANK_6
2870 * @arg @ref LL_ADC_REG_RANK_7
2871 * @arg @ref LL_ADC_REG_RANK_8
2872 * @param Channel This parameter can be one of the following values:
2873 * @arg @ref LL_ADC_CHANNEL_0
2874 * @arg @ref LL_ADC_CHANNEL_1
2875 * @arg @ref LL_ADC_CHANNEL_2
2876 * @arg @ref LL_ADC_CHANNEL_3
2877 * @arg @ref LL_ADC_CHANNEL_4
2878 * @arg @ref LL_ADC_CHANNEL_5
2879 * @arg @ref LL_ADC_CHANNEL_6
2880 * @arg @ref LL_ADC_CHANNEL_7
2881 * @arg @ref LL_ADC_CHANNEL_8
2882 * @arg @ref LL_ADC_CHANNEL_9
2883 * @arg @ref LL_ADC_CHANNEL_10
2884 * @arg @ref LL_ADC_CHANNEL_11
2885 * @arg @ref LL_ADC_CHANNEL_12
2886 * @arg @ref LL_ADC_CHANNEL_13
2887 * @arg @ref LL_ADC_CHANNEL_VREFINT
2888 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2889 * @arg @ref LL_ADC_CHANNEL_VCORE
2890 * @retval None
2891 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2892 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2893 {
2894 /* Set bits with content of parameter "Channel" with bits position */
2895 /* in register depending on parameter "Rank". */
2896 /* Parameters "Rank" and "Channel" are used with masks because containing */
2897 /* other bits reserved for other purpose. */
2898 MODIFY_REG(ADCx->CHSELR,
2899 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2900 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
2901 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2902 }
2903
2904 /**
2905 * @brief Get ADC group regular sequence: channel on the selected
2906 * scan sequence rank.
2907 * @note On this STM32 series, ADC group regular sequencer is
2908 * fully configurable: sequencer length and each rank
2909 * affectation to a channel are configurable.
2910 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2911 * @note Depending on devices and packages, some channels may not be available.
2912 * Refer to device datasheet for channels availability.
2913 * @note Usage of the returned channel number:
2914 * - To reinject this channel into another function LL_ADC_xxx:
2915 * the returned channel number is only partly formatted on definition
2916 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2917 * with parts of literals LL_ADC_CHANNEL_x or using
2918 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2919 * Then the selected literal LL_ADC_CHANNEL_x can be used
2920 * as parameter for another function.
2921 * - To get the channel number in decimal format:
2922 * process the returned value with the helper macro
2923 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2924 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n
2925 * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n
2926 * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n
2927 * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n
2928 * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n
2929 * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n
2930 * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n
2931 * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks
2932 * @param ADCx ADC instance
2933 * @param Rank This parameter can be one of the following values:
2934 * @arg @ref LL_ADC_REG_RANK_1
2935 * @arg @ref LL_ADC_REG_RANK_2
2936 * @arg @ref LL_ADC_REG_RANK_3
2937 * @arg @ref LL_ADC_REG_RANK_4
2938 * @arg @ref LL_ADC_REG_RANK_5
2939 * @arg @ref LL_ADC_REG_RANK_6
2940 * @arg @ref LL_ADC_REG_RANK_7
2941 * @arg @ref LL_ADC_REG_RANK_8
2942 * @retval Returned value can be one of the following values:
2943 * @arg @ref LL_ADC_CHANNEL_0
2944 * @arg @ref LL_ADC_CHANNEL_1
2945 * @arg @ref LL_ADC_CHANNEL_2
2946 * @arg @ref LL_ADC_CHANNEL_3
2947 * @arg @ref LL_ADC_CHANNEL_4
2948 * @arg @ref LL_ADC_CHANNEL_5
2949 * @arg @ref LL_ADC_CHANNEL_6
2950 * @arg @ref LL_ADC_CHANNEL_7
2951 * @arg @ref LL_ADC_CHANNEL_8
2952 * @arg @ref LL_ADC_CHANNEL_9
2953 * @arg @ref LL_ADC_CHANNEL_10
2954 * @arg @ref LL_ADC_CHANNEL_11
2955 * @arg @ref LL_ADC_CHANNEL_12
2956 * @arg @ref LL_ADC_CHANNEL_13
2957 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2958 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2959 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
2960 *
2961 * (1) For ADC channel read back from ADC register,
2962 * comparison with internal channel parameter to be done
2963 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2964 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)2965 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
2966 {
2967 return (uint32_t)((READ_BIT(ADCx->CHSELR,
2968 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2969 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2970 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
2971 );
2972 }
2973
2974 /**
2975 * @brief Set ADC group regular sequence: channel on rank corresponding to
2976 * channel number.
2977 * @note This function performs:
2978 * - Channels ordering into each rank of scan sequence:
2979 * rank of each channel is fixed by channel HW number
2980 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2981 * - Set channels selected by overwriting the current sequencer
2982 * configuration.
2983 * @note On this STM32 series, ADC group regular sequencer both modes
2984 * "fully configurable" or "not fully configurable"
2985 * are available, they can be chosen using
2986 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2987 * This function can be used with setting "not fully configurable".
2988 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
2989 * and @ref LL_ADC_REG_SetSequencerLength().
2990 * @note Depending on devices and packages, some channels may not be available.
2991 * Refer to device datasheet for channels availability.
2992 * @note On this STM32 series, to measure internal channels (VrefInt,
2993 * TempSensor, ...), measurement paths to internal channels must be
2994 * enabled separately.
2995 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2996 * @note On this STM32 series, setting of this feature is conditioned to
2997 * ADC state:
2998 * ADC must be disabled or enabled without conversion on going
2999 * on group regular.
3000 * @note One or several values can be selected.
3001 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3002 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
3003 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
3004 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
3005 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
3006 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
3007 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
3008 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
3009 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
3010 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
3011 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
3012 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
3013 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
3014 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
3015 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
3016 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
3017 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
3018 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
3019 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
3020 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
3021 * @param ADCx ADC instance
3022 * @param Channel This parameter can be a combination of the following values:
3023 * @arg @ref LL_ADC_CHANNEL_0
3024 * @arg @ref LL_ADC_CHANNEL_1
3025 * @arg @ref LL_ADC_CHANNEL_2
3026 * @arg @ref LL_ADC_CHANNEL_3
3027 * @arg @ref LL_ADC_CHANNEL_4
3028 * @arg @ref LL_ADC_CHANNEL_5
3029 * @arg @ref LL_ADC_CHANNEL_6
3030 * @arg @ref LL_ADC_CHANNEL_7
3031 * @arg @ref LL_ADC_CHANNEL_8
3032 * @arg @ref LL_ADC_CHANNEL_9
3033 * @arg @ref LL_ADC_CHANNEL_10
3034 * @arg @ref LL_ADC_CHANNEL_11
3035 * @arg @ref LL_ADC_CHANNEL_12
3036 * @arg @ref LL_ADC_CHANNEL_13
3037 * @arg @ref LL_ADC_CHANNEL_VREFINT
3038 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3039 * @arg @ref LL_ADC_CHANNEL_VCORE
3040 * @retval None
3041 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)3042 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
3043 {
3044 /* Parameter "Channel" is used with masks because containing */
3045 /* other bits reserved for other purpose. */
3046 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3047 }
3048
3049 /**
3050 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
3051 * channel number.
3052 * @note This function performs:
3053 * - Channels ordering into each rank of scan sequence:
3054 * rank of each channel is fixed by channel HW number
3055 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3056 * - Set channels selected by adding them to the current sequencer
3057 * configuration.
3058 * @note On this STM32 series, ADC group regular sequencer both modes
3059 * "fully configurable" or "not fully configurable"
3060 * are available, they can be chosen using
3061 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3062 * This function can be used with setting "not fully configurable".
3063 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3064 * and @ref LL_ADC_REG_SetSequencerLength().
3065 * @note Depending on devices and packages, some channels may not be available.
3066 * Refer to device datasheet for channels availability.
3067 * @note On this STM32 series, to measure internal channels (VrefInt,
3068 * TempSensor, ...), measurement paths to internal channels must be
3069 * enabled separately.
3070 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3071 * @note On this STM32 series, setting of this feature is conditioned to
3072 * ADC state:
3073 * ADC must be disabled or enabled without conversion on going
3074 * on group regular.
3075 * @note One or several values can be selected.
3076 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3077 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
3078 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
3079 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
3080 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
3081 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
3082 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
3083 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
3084 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
3085 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
3086 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
3087 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
3088 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
3089 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
3090 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
3091 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
3092 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
3093 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
3094 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
3095 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
3096 * @param ADCx ADC instance
3097 * @param Channel This parameter can be a combination of the following values:
3098 * @arg @ref LL_ADC_CHANNEL_0
3099 * @arg @ref LL_ADC_CHANNEL_1
3100 * @arg @ref LL_ADC_CHANNEL_2
3101 * @arg @ref LL_ADC_CHANNEL_3
3102 * @arg @ref LL_ADC_CHANNEL_4
3103 * @arg @ref LL_ADC_CHANNEL_5
3104 * @arg @ref LL_ADC_CHANNEL_6
3105 * @arg @ref LL_ADC_CHANNEL_7
3106 * @arg @ref LL_ADC_CHANNEL_8
3107 * @arg @ref LL_ADC_CHANNEL_9
3108 * @arg @ref LL_ADC_CHANNEL_10
3109 * @arg @ref LL_ADC_CHANNEL_11
3110 * @arg @ref LL_ADC_CHANNEL_12
3111 * @arg @ref LL_ADC_CHANNEL_13
3112 * @arg @ref LL_ADC_CHANNEL_VREFINT
3113 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3114 * @arg @ref LL_ADC_CHANNEL_VCORE
3115 * @retval None
3116 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)3117 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
3118 {
3119 /* Parameter "Channel" is used with masks because containing */
3120 /* other bits reserved for other purpose. */
3121 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3122 }
3123
3124 /**
3125 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
3126 * channel number.
3127 * @note This function performs:
3128 * - Channels ordering into each rank of scan sequence:
3129 * rank of each channel is fixed by channel HW number
3130 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3131 * - Set channels selected by removing them to the current sequencer
3132 * configuration.
3133 * @note On this STM32 series, ADC group regular sequencer both modes
3134 * "fully configurable" or "not fully configurable"
3135 * are available, they can be chosen using
3136 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3137 * This function can be used with setting "not fully configurable".
3138 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3139 * and @ref LL_ADC_REG_SetSequencerLength().
3140 * @note Depending on devices and packages, some channels may not be available.
3141 * Refer to device datasheet for channels availability.
3142 * @note On this STM32 series, to measure internal channels (VrefInt,
3143 * TempSensor, ...), measurement paths to internal channels must be
3144 * enabled separately.
3145 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3146 * @note On this STM32 series, setting of this feature is conditioned to
3147 * ADC state:
3148 * ADC must be disabled or enabled without conversion on going
3149 * on group regular.
3150 * @note One or several values can be selected.
3151 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3152 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
3153 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
3154 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
3155 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
3156 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
3157 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
3158 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
3159 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
3160 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
3161 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
3162 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
3163 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
3164 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
3165 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
3166 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
3167 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
3168 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
3169 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
3170 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
3171 * @param ADCx ADC instance
3172 * @param Channel This parameter can be a combination of the following values:
3173 * @arg @ref LL_ADC_CHANNEL_0
3174 * @arg @ref LL_ADC_CHANNEL_1
3175 * @arg @ref LL_ADC_CHANNEL_2
3176 * @arg @ref LL_ADC_CHANNEL_3
3177 * @arg @ref LL_ADC_CHANNEL_4
3178 * @arg @ref LL_ADC_CHANNEL_5
3179 * @arg @ref LL_ADC_CHANNEL_6
3180 * @arg @ref LL_ADC_CHANNEL_7
3181 * @arg @ref LL_ADC_CHANNEL_8
3182 * @arg @ref LL_ADC_CHANNEL_9
3183 * @arg @ref LL_ADC_CHANNEL_10
3184 * @arg @ref LL_ADC_CHANNEL_11
3185 * @arg @ref LL_ADC_CHANNEL_12
3186 * @arg @ref LL_ADC_CHANNEL_13
3187 * @arg @ref LL_ADC_CHANNEL_VREFINT
3188 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3189 * @arg @ref LL_ADC_CHANNEL_VCORE
3190 * @retval None
3191 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)3192 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
3193 {
3194 /* Parameter "Channel" is used with masks because containing */
3195 /* other bits reserved for other purpose. */
3196 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3197 }
3198
3199 /**
3200 * @brief Get ADC group regular sequence: channel on rank corresponding to
3201 * channel number.
3202 * @note This function performs:
3203 * - Channels order reading into each rank of scan sequence:
3204 * rank of each channel is fixed by channel HW number
3205 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3206 * @note On this STM32 series, ADC group regular sequencer both modes
3207 * "fully configurable" or "not fully configurable"
3208 * are available, they can be chosen using
3209 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3210 * This function can be used with setting "not fully configurable".
3211 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3212 * and @ref LL_ADC_REG_SetSequencerLength().
3213 * @note Depending on devices and packages, some channels may not be available.
3214 * Refer to device datasheet for channels availability.
3215 * @note On this STM32 series, to measure internal channels (VrefInt,
3216 * TempSensor, ...), measurement paths to internal channels must be
3217 * enabled separately.
3218 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3219 * @note On this STM32 series, setting of this feature is conditioned to
3220 * ADC state:
3221 * ADC must be disabled or enabled without conversion on going
3222 * on group regular.
3223 * @note One or several values can be retrieved.
3224 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3225 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
3226 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
3227 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
3228 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
3229 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
3230 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
3231 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
3232 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
3233 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
3234 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
3235 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
3236 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
3237 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
3238 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
3239 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
3240 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
3241 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
3242 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
3243 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
3244 * @param ADCx ADC instance
3245 * @retval Returned value can be a combination of the following values:
3246 * @arg @ref LL_ADC_CHANNEL_0
3247 * @arg @ref LL_ADC_CHANNEL_1
3248 * @arg @ref LL_ADC_CHANNEL_2
3249 * @arg @ref LL_ADC_CHANNEL_3
3250 * @arg @ref LL_ADC_CHANNEL_4
3251 * @arg @ref LL_ADC_CHANNEL_5
3252 * @arg @ref LL_ADC_CHANNEL_6
3253 * @arg @ref LL_ADC_CHANNEL_7
3254 * @arg @ref LL_ADC_CHANNEL_8
3255 * @arg @ref LL_ADC_CHANNEL_9
3256 * @arg @ref LL_ADC_CHANNEL_10
3257 * @arg @ref LL_ADC_CHANNEL_11
3258 * @arg @ref LL_ADC_CHANNEL_12
3259 * @arg @ref LL_ADC_CHANNEL_13
3260 * @arg @ref LL_ADC_CHANNEL_VREFINT
3261 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3262 * @arg @ref LL_ADC_CHANNEL_VCORE
3263 */
LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef * ADCx)3264 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx)
3265 {
3266 uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
3267
3268 return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
3269 | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
3270 | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
3271 | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
3272 | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
3273 | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
3274 | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
3275 | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
3276 | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
3277 | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
3278 | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
3279 | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
3280 );
3281 }
3282
3283 /**
3284 * @brief Set ADC continuous conversion mode on ADC group regular.
3285 * @note Description of ADC continuous conversion mode:
3286 * - single mode: one conversion per trigger
3287 * - continuous mode: after the first trigger, following
3288 * conversions launched successively automatically.
3289 * @note It is not possible to enable both ADC group regular
3290 * continuous mode and sequencer discontinuous mode.
3291 * @note On this STM32 series, setting of this feature is conditioned to
3292 * ADC state:
3293 * ADC must be disabled or enabled without conversion on going
3294 * on group regular.
3295 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
3296 * @param ADCx ADC instance
3297 * @param Continuous This parameter can be one of the following values:
3298 * @arg @ref LL_ADC_REG_CONV_SINGLE
3299 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3300 * @retval None
3301 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3302 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3303 {
3304 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
3305 }
3306
3307 /**
3308 * @brief Get ADC continuous conversion mode on ADC group regular.
3309 * @note Description of ADC continuous conversion mode:
3310 * - single mode: one conversion per trigger
3311 * - continuous mode: after the first trigger, following
3312 * conversions launched successively automatically.
3313 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
3314 * @param ADCx ADC instance
3315 * @retval Returned value can be one of the following values:
3316 * @arg @ref LL_ADC_REG_CONV_SINGLE
3317 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3318 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)3319 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
3320 {
3321 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
3322 }
3323
3324 /**
3325 * @brief Set ADC group regular conversion data transfer: no transfer or
3326 * transfer by DMA, and DMA requests mode.
3327 * @note If transfer by DMA selected, specifies the DMA requests
3328 * mode:
3329 * - Limited mode (One shot mode): DMA transfer requests are stopped
3330 * when number of DMA data transfers (number of
3331 * ADC conversions) is reached.
3332 * This ADC mode is intended to be used with DMA mode non-circular.
3333 * - Unlimited mode: DMA transfer requests are unlimited,
3334 * whatever number of DMA data transfers (number of
3335 * ADC conversions).
3336 * This ADC mode is intended to be used with DMA mode circular.
3337 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3338 * mode non-circular:
3339 * when DMA transfers size will be reached, DMA will stop transfers of
3340 * ADC conversions data ADC will raise an overrun error
3341 * (overrun flag and interruption if enabled).
3342 * @note To configure DMA source address (peripheral address),
3343 * use function @ref LL_ADC_DMA_GetRegAddr().
3344 * @note On this STM32 series, setting of this feature is conditioned to
3345 * ADC state:
3346 * ADC must be disabled or enabled without conversion on going
3347 * on group regular.
3348 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
3349 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
3350 * @param ADCx ADC instance
3351 * @param DMATransfer This parameter can be one of the following values:
3352 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3353 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3354 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3355 * @retval None
3356 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3357 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3358 {
3359 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
3360 }
3361
3362 /**
3363 * @brief Get ADC group regular conversion data transfer: no transfer or
3364 * transfer by DMA, and DMA requests mode.
3365 * @note If transfer by DMA selected, specifies the DMA requests
3366 * mode:
3367 * - Limited mode (One shot mode): DMA transfer requests are stopped
3368 * when number of DMA data transfers (number of
3369 * ADC conversions) is reached.
3370 * This ADC mode is intended to be used with DMA mode non-circular.
3371 * - Unlimited mode: DMA transfer requests are unlimited,
3372 * whatever number of DMA data transfers (number of
3373 * ADC conversions).
3374 * This ADC mode is intended to be used with DMA mode circular.
3375 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3376 * mode non-circular:
3377 * when DMA transfers size will be reached, DMA will stop transfers of
3378 * ADC conversions data ADC will raise an overrun error
3379 * (overrun flag and interruption if enabled).
3380 * @note To configure DMA source address (peripheral address),
3381 * use function @ref LL_ADC_DMA_GetRegAddr().
3382 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
3383 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
3384 * @param ADCx ADC instance
3385 * @retval Returned value can be one of the following values:
3386 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3387 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3388 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3389 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)3390 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
3391 {
3392 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
3393 }
3394
3395 /**
3396 * @brief Set ADC group regular behavior in case of overrun:
3397 * data preserved or overwritten.
3398 * @note Compatibility with devices without feature overrun:
3399 * other devices without this feature have a behavior
3400 * equivalent to data overwritten.
3401 * The default setting of overrun is data preserved.
3402 * Therefore, for compatibility with all devices, parameter
3403 * overrun should be set to data overwritten.
3404 * @note On this STM32 series, setting of this feature is conditioned to
3405 * ADC state:
3406 * ADC must be disabled or enabled without conversion on going
3407 * on group regular.
3408 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
3409 * @param ADCx ADC instance
3410 * @param Overrun This parameter can be one of the following values:
3411 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3412 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3413 * @retval None
3414 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3415 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3416 {
3417 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
3418 }
3419
3420 /**
3421 * @brief Get ADC group regular behavior in case of overrun:
3422 * data preserved or overwritten.
3423 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
3424 * @param ADCx ADC instance
3425 * @retval Returned value can be one of the following values:
3426 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3427 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3428 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)3429 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
3430 {
3431 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
3432 }
3433
3434 /**
3435 * @}
3436 */
3437
3438 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3439 * @{
3440 */
3441
3442 /**
3443 * @brief Set sampling time of the selected ADC channel
3444 * Unit: ADC clock cycles.
3445 * @note On this device, sampling time is on channel scope: independently
3446 * of channel mapped on ADC group regular or injected.
3447 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3448 * converted:
3449 * sampling time constraints must be respected (sampling time can be
3450 * adjusted in function of ADC clock frequency and sampling time
3451 * setting).
3452 * Refer to device datasheet for timings values (parameters TS_vrefint,
3453 * TS_temp, ...).
3454 * @note Conversion time is the addition of sampling time and processing time.
3455 * Refer to reference manual for ADC processing time of
3456 * this STM32 series.
3457 * @note In case of ADC conversion of internal channel (VrefInt,
3458 * temperature sensor, ...), a sampling time minimum value
3459 * is required.
3460 * Refer to device datasheet.
3461 * @note On this STM32 series, setting of this feature is conditioned to
3462 * ADC state:
3463 * ADC must be disabled or enabled without conversion on going
3464 * on group regular.
3465 * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n
3466 * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n
3467 * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n
3468 * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n
3469 * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n
3470 * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n
3471 * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n
3472 * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n
3473 * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n
3474 * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n
3475 * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n
3476 * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n
3477 * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n
3478 * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n
3479 * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n
3480 * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n
3481 * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n
3482 * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n
3483 * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime
3484 * @param ADCx ADC instance
3485 * @param Channel This parameter can be a combination of the following values:
3486 * @arg @ref LL_ADC_CHANNEL_0
3487 * @arg @ref LL_ADC_CHANNEL_1
3488 * @arg @ref LL_ADC_CHANNEL_2
3489 * @arg @ref LL_ADC_CHANNEL_3
3490 * @arg @ref LL_ADC_CHANNEL_4
3491 * @arg @ref LL_ADC_CHANNEL_5
3492 * @arg @ref LL_ADC_CHANNEL_6
3493 * @arg @ref LL_ADC_CHANNEL_7
3494 * @arg @ref LL_ADC_CHANNEL_8
3495 * @arg @ref LL_ADC_CHANNEL_9
3496 * @arg @ref LL_ADC_CHANNEL_10
3497 * @arg @ref LL_ADC_CHANNEL_11
3498 * @arg @ref LL_ADC_CHANNEL_12
3499 * @arg @ref LL_ADC_CHANNEL_13
3500 * @arg @ref LL_ADC_CHANNEL_VREFINT
3501 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3502 * @arg @ref LL_ADC_CHANNEL_VCORE
3503 * @param SamplingTimeY This parameter can be one of the following values:
3504 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3505 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3506 * @retval None
3507 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTimeY)3508 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
3509 {
3510 /* Parameter "Channel" is used with masks because containing */
3511 /* other bits reserved for other purpose. */
3512 MODIFY_REG(ADCx->SMPR,
3513 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
3514 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
3515 );
3516 }
3517
3518 /**
3519 * @brief Get sampling time of the selected ADC channel
3520 * Unit: ADC clock cycles.
3521 * @note On this device, sampling time is on channel scope: independently
3522 * of channel mapped on ADC group regular or injected.
3523 * @note Conversion time is the addition of sampling time and processing time.
3524 * Refer to reference manual for ADC processing time of
3525 * this STM32 series.
3526 * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n
3527 * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n
3528 * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n
3529 * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n
3530 * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n
3531 * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n
3532 * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n
3533 * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n
3534 * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n
3535 * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n
3536 * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n
3537 * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n
3538 * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n
3539 * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n
3540 * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n
3541 * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n
3542 * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n
3543 * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n
3544 * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime
3545 * @param ADCx ADC instance
3546 * @param Channel This parameter can be one of the following values:
3547 * @arg @ref LL_ADC_CHANNEL_0
3548 * @arg @ref LL_ADC_CHANNEL_1
3549 * @arg @ref LL_ADC_CHANNEL_2
3550 * @arg @ref LL_ADC_CHANNEL_3
3551 * @arg @ref LL_ADC_CHANNEL_4
3552 * @arg @ref LL_ADC_CHANNEL_5
3553 * @arg @ref LL_ADC_CHANNEL_6
3554 * @arg @ref LL_ADC_CHANNEL_7
3555 * @arg @ref LL_ADC_CHANNEL_8
3556 * @arg @ref LL_ADC_CHANNEL_9
3557 * @arg @ref LL_ADC_CHANNEL_10
3558 * @arg @ref LL_ADC_CHANNEL_11
3559 * @arg @ref LL_ADC_CHANNEL_12
3560 * @arg @ref LL_ADC_CHANNEL_13
3561 * @arg @ref LL_ADC_CHANNEL_VREFINT
3562 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3563 * @arg @ref LL_ADC_CHANNEL_VCORE
3564 * @retval Returned value can be one of the following values:
3565 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3566 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3567 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)3568 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
3569 {
3570 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
3571
3572 /* Retrieve sampling time bit corresponding to the selected channel */
3573 /* and shift it to position 0. */
3574 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
3575 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3576 + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
3577 & 0x1FUL));
3578
3579 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
3580 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
3581 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
3582 }
3583
3584 /**
3585 * @}
3586 */
3587
3588 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3589 * @{
3590 */
3591
3592 /**
3593 * @brief Set ADC analog watchdog monitored channels:
3594 * a single channel, multiple channels or all channels,
3595 * on ADC group regular.
3596 * @note Once monitored channels are selected, analog watchdog
3597 * is enabled.
3598 * @note In case of need to define a single channel to monitor
3599 * with analog watchdog from sequencer channel definition,
3600 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3601 * @note On this STM32 series, setting of this feature is conditioned to
3602 * ADC state:
3603 * ADC must be disabled or enabled without conversion on going
3604 * on group regular.
3605 * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3606 * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3607 * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
3608 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
3609 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
3610 * @param ADCx ADC instance
3611 * @param AWDy This parameter can be one of the following values:
3612 * @arg @ref LL_ADC_AWD1
3613 * @arg @ref LL_ADC_AWD2
3614 * @arg @ref LL_ADC_AWD3
3615 * @param AWDChannelGroup This parameter can be one of the following values:
3616 * @arg @ref LL_ADC_AWD_DISABLE
3617 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3618 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3619 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3620 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3621 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3622 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3623 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3624 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3625 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3626 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3627 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3628 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3629 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3630 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
3631 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
3632 * @arg @ref LL_ADC_AWD_CH_VCORE_REG
3633 * @retval None
3634 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)3635 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
3636 {
3637 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
3638 /* in register and register position depending on parameter "AWDy". */
3639 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
3640 /* containing other bits reserved for other purpose. */
3641 __IO uint32_t *preg;
3642
3643 if (AWDy == LL_ADC_AWD1)
3644 {
3645 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
3646 }
3647 else
3648 {
3649 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
3650 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
3651 }
3652
3653 MODIFY_REG(*preg,
3654 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
3655 AWDChannelGroup & AWDy);
3656 }
3657
3658 /**
3659 * @brief Get ADC analog watchdog monitored channel.
3660 * @note Usage of the returned channel number:
3661 * - To reinject this channel into another function LL_ADC_xxx:
3662 * the returned channel number is only partly formatted on definition
3663 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3664 * with parts of literals LL_ADC_CHANNEL_x or using
3665 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3666 * Then the selected literal LL_ADC_CHANNEL_x can be used
3667 * as parameter for another function.
3668 * - To get the channel number in decimal format:
3669 * process the returned value with the helper macro
3670 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3671 * Applicable only when the analog watchdog is set to monitor
3672 * one channel.
3673 * @note On this STM32 series, setting of this feature is conditioned to
3674 * ADC state:
3675 * ADC must be disabled or enabled without conversion on going
3676 * on group regular.
3677 * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3678 * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3679 * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
3680 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
3681 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
3682 * @param ADCx ADC instance
3683 * @param AWDy This parameter can be one of the following values:
3684 * @arg @ref LL_ADC_AWD1
3685 * @arg @ref LL_ADC_AWD2 (1)
3686 * @arg @ref LL_ADC_AWD3 (1)
3687 *
3688 * (1) On this AWD number, monitored channel can be retrieved
3689 * if only 1 channel is programmed (or none or all channels).
3690 * This function cannot retrieve monitored channel if
3691 * multiple channels are programmed simultaneously
3692 * by bitfield.
3693 * @retval Returned value can be one of the following values:
3694 * @arg @ref LL_ADC_AWD_DISABLE
3695 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3696 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3697 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3698 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3699 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3700 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3701 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3702 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3703 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3704 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3705 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3706 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3707 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3708 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)3709 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
3710 {
3711 __IO const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
3712 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
3713 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
3714 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
3715
3716 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
3717
3718 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
3719 /* (parameter value LL_ADC_AWD_DISABLE). */
3720 /* Else, the selected AWD is enabled and is monitoring a group of channels */
3721 /* or a single channel. */
3722 if (analog_wd_monit_channels != 0UL)
3723 {
3724 if (AWDy == LL_ADC_AWD1)
3725 {
3726 if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
3727 {
3728 /* AWD monitoring a group of channels */
3729 analog_wd_monit_channels = ((analog_wd_monit_channels
3730 | (ADC_AWD_CR23_CHANNEL_MASK)
3731 )
3732 & (~(ADC_CFGR1_AWD1CH))
3733 );
3734 }
3735 else
3736 {
3737 /* AWD monitoring a single channel */
3738 analog_wd_monit_channels = (analog_wd_monit_channels
3739 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos))
3740 );
3741 }
3742 }
3743 else
3744 {
3745 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
3746 {
3747 /* AWD monitoring a group of channels */
3748 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
3749 | (ADC_CFGR1_AWD1EN)
3750 );
3751 }
3752 else
3753 {
3754 /* AWD monitoring a single channel */
3755 /* AWD monitoring a group of channels */
3756 analog_wd_monit_channels = (analog_wd_monit_channels
3757 | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
3758 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos)
3759 );
3760 }
3761 }
3762 }
3763
3764 return analog_wd_monit_channels;
3765 }
3766
3767 /**
3768 * @brief Set ADC analog watchdog thresholds value of both thresholds
3769 * high and low.
3770 * @note If value of only one threshold high or low must be set,
3771 * use function @ref LL_ADC_SetAnalogWDThresholds().
3772 * @note In case of ADC resolution different of 12 bits,
3773 * analog watchdog thresholds data require a specific shift.
3774 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3775 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
3776 * impacted: the comparison of analog watchdog thresholds is done on
3777 * oversampling final computation (after ratio and shift application):
3778 * ADC data register bitfield [15:4] (12 most significant bits).
3779 * Examples:
3780 * - Oversampling ratio and shift selected to have ADC conversion data
3781 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
3782 * ADC analog watchdog thresholds must be divided by 16.
3783 * - Oversampling ratio and shift selected to have ADC conversion data
3784 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
3785 * ADC analog watchdog thresholds must be divided by 4.
3786 * - Oversampling ratio and shift selected to have ADC conversion data
3787 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
3788 * ADC analog watchdog thresholds match directly to ADC data register.
3789 * @note On this STM32 series, setting of this feature is conditioned to
3790 * ADC state:
3791 * ADC must be disabled or enabled without conversion on going
3792 * on group regular.
3793 * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n
3794 * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n
3795 * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n
3796 * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n
3797 * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n
3798 * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
3799 * @param ADCx ADC instance
3800 * @param AWDy This parameter can be one of the following values:
3801 * @arg @ref LL_ADC_AWD1
3802 * @arg @ref LL_ADC_AWD2
3803 * @arg @ref LL_ADC_AWD3
3804 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
3805 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
3806 * @retval None
3807 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)3808 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
3809 uint32_t AWDThresholdLowValue)
3810 {
3811 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
3812 /* position in register and register position depending on parameter */
3813 /* "AWDy". */
3814 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
3815 /* containing other bits reserved for other purpose. */
3816 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
3817 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
3818 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
3819 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
3820 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
3821 );
3822
3823 MODIFY_REG(*preg,
3824 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
3825 (AWDThresholdHighValue << ADC_AWD1TR_HT1_Pos) | AWDThresholdLowValue);
3826 }
3827
3828 /**
3829 * @brief Set ADC analog watchdog threshold value of threshold
3830 * high or low.
3831 * @note If values of both thresholds high or low must be set,
3832 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
3833 * @note In case of ADC resolution different of 12 bits,
3834 * analog watchdog thresholds data require a specific shift.
3835 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3836 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
3837 * impacted: the comparison of analog watchdog thresholds is done on
3838 * oversampling final computation (after ratio and shift application):
3839 * ADC data register bitfield [15:4] (12 most significant bits).
3840 * Examples:
3841 * - Oversampling ratio and shift selected to have ADC conversion data
3842 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
3843 * ADC analog watchdog thresholds must be divided by 16.
3844 * - Oversampling ratio and shift selected to have ADC conversion data
3845 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
3846 * ADC analog watchdog thresholds must be divided by 4.
3847 * - Oversampling ratio and shift selected to have ADC conversion data
3848 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
3849 * ADC analog watchdog thresholds match directly to ADC data register.
3850 * @note On this STM32 series, setting of this feature is not conditioned to
3851 * ADC state:
3852 * ADC can be disabled, enabled with or without conversion on going
3853 * on ADC group regular.
3854 * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n
3855 * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n
3856 * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n
3857 * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n
3858 * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n
3859 * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
3860 * @param ADCx ADC instance
3861 * @param AWDy This parameter can be one of the following values:
3862 * @arg @ref LL_ADC_AWD1
3863 * @arg @ref LL_ADC_AWD2
3864 * @arg @ref LL_ADC_AWD3
3865 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3866 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3867 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3868 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3869 * @retval None
3870 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3871 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
3872 uint32_t AWDThresholdValue)
3873 {
3874 /* Set bits with content of parameter "AWDThresholdValue" with bits */
3875 /* position in register and register position depending on parameters */
3876 /* "AWDThresholdsHighLow" and "AWDy". */
3877 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
3878 /* containing other bits reserved for other purpose. */
3879 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
3880 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
3881 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
3882 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
3883 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
3884
3885 MODIFY_REG(*preg,
3886 AWDThresholdsHighLow,
3887 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
3888 }
3889
3890 /**
3891 * @brief Get ADC analog watchdog threshold value of threshold high,
3892 * threshold low or raw data with ADC thresholds high and low
3893 * concatenated.
3894 * @note If raw data with ADC thresholds high and low is retrieved,
3895 * the data of each threshold high or low can be isolated
3896 * using helper macro:
3897 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
3898 * @note In case of ADC resolution different of 12 bits,
3899 * analog watchdog thresholds data require a specific shift.
3900 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3901 * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n
3902 * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n
3903 * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n
3904 * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n
3905 * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n
3906 * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
3907 * @param ADCx ADC instance
3908 * @param AWDy This parameter can be one of the following values:
3909 * @arg @ref LL_ADC_AWD1
3910 * @arg @ref LL_ADC_AWD2
3911 * @arg @ref LL_ADC_AWD3
3912 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3913 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3914 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3915 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
3916 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3917 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)3918 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
3919 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
3920 {
3921 /* Set bits with content of parameter "AWDThresholdValue" with bits */
3922 /* position in register and register position depending on parameters */
3923 /* "AWDThresholdsHighLow" and "AWDy". */
3924 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
3925 /* containing other bits reserved for other purpose. */
3926 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
3927 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
3928 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
3929 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
3930 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
3931
3932 return (uint32_t)(READ_BIT(*preg,
3933 (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
3934 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
3935 & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1)));
3936 }
3937
3938 /**
3939 * @}
3940 */
3941
3942 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
3943 * @{
3944 */
3945
3946 /**
3947 * @brief Set ADC oversampling scope.
3948 * @note On this STM32 series, setting of this feature is conditioned to
3949 * ADC state:
3950 * ADC must be disabled.
3951 * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope
3952 * @param ADCx ADC instance
3953 * @param OvsScope This parameter can be one of the following values:
3954 * @arg @ref LL_ADC_OVS_DISABLE
3955 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
3956 * @retval None
3957 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)3958 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
3959 {
3960 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
3961 }
3962
3963 /**
3964 * @brief Get ADC oversampling scope.
3965 * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope
3966 * @param ADCx ADC instance
3967 * @retval Returned value can be one of the following values:
3968 * @arg @ref LL_ADC_OVS_DISABLE
3969 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
3970 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)3971 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
3972 {
3973 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
3974 }
3975
3976 /**
3977 * @brief Set ADC oversampling discontinuous mode (triggered mode)
3978 * on the selected ADC group.
3979 * @note Number of oversampled conversions are done either in:
3980 * - continuous mode (all conversions of oversampling ratio
3981 * are done from 1 trigger)
3982 * - discontinuous mode (each conversion of oversampling ratio
3983 * needs a trigger)
3984 * @note On this STM32 series, setting of this feature is conditioned to
3985 * ADC state:
3986 * ADC must be disabled or enabled without conversion on going
3987 * on group regular.
3988 * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
3989 * @param ADCx ADC instance
3990 * @param OverSamplingDiscont This parameter can be one of the following values:
3991 * @arg @ref LL_ADC_OVS_REG_CONT
3992 * @arg @ref LL_ADC_OVS_REG_DISCONT
3993 * @retval None
3994 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)3995 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
3996 {
3997 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
3998 }
3999
4000 /**
4001 * @brief Get ADC oversampling discontinuous mode (triggered mode)
4002 * on the selected ADC group.
4003 * @note Number of oversampled conversions are done either in:
4004 * - continuous mode (all conversions of oversampling ratio
4005 * are done from 1 trigger)
4006 * - discontinuous mode (each conversion of oversampling ratio
4007 * needs a trigger)
4008 * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
4009 * @param ADCx ADC instance
4010 * @retval Returned value can be one of the following values:
4011 * @arg @ref LL_ADC_OVS_REG_CONT
4012 * @arg @ref LL_ADC_OVS_REG_DISCONT
4013 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)4014 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
4015 {
4016 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
4017 }
4018
4019 /**
4020 * @brief Set ADC oversampling
4021 * @note This function set the 2 items of oversampling configuration:
4022 * - ratio
4023 * - shift
4024 * @note On this STM32 series, setting of this feature is conditioned to
4025 * ADC state:
4026 * ADC must be disabled.
4027 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
4028 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
4029 * @param ADCx ADC instance
4030 * @param Ratio This parameter can be one of the following values:
4031 * @arg @ref LL_ADC_OVS_RATIO_2
4032 * @arg @ref LL_ADC_OVS_RATIO_4
4033 * @arg @ref LL_ADC_OVS_RATIO_8
4034 * @arg @ref LL_ADC_OVS_RATIO_16
4035 * @arg @ref LL_ADC_OVS_RATIO_32
4036 * @arg @ref LL_ADC_OVS_RATIO_64
4037 * @arg @ref LL_ADC_OVS_RATIO_128
4038 * @arg @ref LL_ADC_OVS_RATIO_256
4039 * @param Shift This parameter can be one of the following values:
4040 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4041 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4042 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4043 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4044 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4045 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4046 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4047 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4048 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4049 * @retval None
4050 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)4051 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
4052 {
4053 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
4054 }
4055
4056 /**
4057 * @brief Get ADC oversampling ratio
4058 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
4059 * @param ADCx ADC instance
4060 * @retval Ratio This parameter can be one of the following values:
4061 * @arg @ref LL_ADC_OVS_RATIO_2
4062 * @arg @ref LL_ADC_OVS_RATIO_4
4063 * @arg @ref LL_ADC_OVS_RATIO_8
4064 * @arg @ref LL_ADC_OVS_RATIO_16
4065 * @arg @ref LL_ADC_OVS_RATIO_32
4066 * @arg @ref LL_ADC_OVS_RATIO_64
4067 * @arg @ref LL_ADC_OVS_RATIO_128
4068 * @arg @ref LL_ADC_OVS_RATIO_256
4069 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)4070 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
4071 {
4072 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
4073 }
4074
4075 /**
4076 * @brief Get ADC oversampling shift
4077 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
4078 * @param ADCx ADC instance
4079 * @retval Shift This parameter can be one of the following values:
4080 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4081 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4082 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4083 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4084 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4085 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4086 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4087 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4088 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4089 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)4090 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
4091 {
4092 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
4093 }
4094
4095 /**
4096 * @}
4097 */
4098
4099 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
4100 * @{
4101 */
4102
4103 /**
4104 * @brief Enable ADC instance internal voltage regulator.
4105 * @note On this STM32 series, there are three possibilities to enable
4106 * the voltage regulator:
4107 * - by enabling it manually
4108 * using function @ref LL_ADC_EnableInternalRegulator().
4109 * - by launching a calibration
4110 * using function @ref LL_ADC_StartCalibration().
4111 * - by enabling the ADC
4112 * using function @ref LL_ADC_Enable().
4113 * @note On this STM32 series, after ADC internal voltage regulator enable,
4114 * a delay for ADC internal voltage regulator stabilization
4115 * is required before performing a ADC calibration or ADC enable.
4116 * Refer to device datasheet, parameter "tADCVREG_STUP".
4117 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
4118 * @note On this STM32 series, setting of this feature is conditioned to
4119 * ADC state:
4120 * ADC must be ADC disabled.
4121 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
4122 * @param ADCx ADC instance
4123 * @retval None
4124 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)4125 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
4126 {
4127 /* Note: Write register with some additional bits forced to state reset */
4128 /* instead of modifying only the selected bit for this function, */
4129 /* to not interfere with bits with HW property "rs". */
4130 MODIFY_REG(ADCx->CR,
4131 ADC_CR_BITS_PROPERTY_RS,
4132 ADC_CR_ADVREGEN);
4133 }
4134
4135 /**
4136 * @brief Disable ADC internal voltage regulator.
4137 * @note On this STM32 series, setting of this feature is conditioned to
4138 * ADC state:
4139 * ADC must be ADC disabled.
4140 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
4141 * @param ADCx ADC instance
4142 * @retval None
4143 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)4144 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
4145 {
4146 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
4147 }
4148
4149 /**
4150 * @brief Get the selected ADC instance internal voltage regulator state.
4151 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
4152 * @param ADCx ADC instance
4153 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
4154 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)4155 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
4156 {
4157 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
4158 }
4159
4160 /**
4161 * @brief Enable the selected ADC instance.
4162 * @note On this STM32 series, after ADC enable, a delay for
4163 * ADC internal analog stabilization is required before performing a
4164 * ADC conversion start.
4165 * Refer to device datasheet, parameter tSTAB.
4166 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4167 * is enabled and when conversion clock is active.
4168 * (not only core clock: this ADC has a dual clock domain)
4169 * @note On this STM32 series, setting of this feature is conditioned to
4170 * ADC state:
4171 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
4172 * @rmtoll CR ADEN LL_ADC_Enable
4173 * @param ADCx ADC instance
4174 * @retval None
4175 */
LL_ADC_Enable(ADC_TypeDef * ADCx)4176 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
4177 {
4178 /* Note: Write register with some additional bits forced to state reset */
4179 /* instead of modifying only the selected bit for this function, */
4180 /* to not interfere with bits with HW property "rs". */
4181 MODIFY_REG(ADCx->CR,
4182 ADC_CR_BITS_PROPERTY_RS,
4183 ADC_CR_ADEN);
4184 }
4185
4186 /**
4187 * @brief Disable the selected ADC instance.
4188 * @note On this STM32 series, setting of this feature is conditioned to
4189 * ADC state:
4190 * ADC must be not disabled. Must be enabled without conversion on going
4191 * on group regular.
4192 * @rmtoll CR ADDIS LL_ADC_Disable
4193 * @param ADCx ADC instance
4194 * @retval None
4195 */
LL_ADC_Disable(ADC_TypeDef * ADCx)4196 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
4197 {
4198 /* Note: Write register with some additional bits forced to state reset */
4199 /* instead of modifying only the selected bit for this function, */
4200 /* to not interfere with bits with HW property "rs". */
4201 MODIFY_REG(ADCx->CR,
4202 ADC_CR_BITS_PROPERTY_RS,
4203 ADC_CR_ADDIS);
4204 }
4205
4206 /**
4207 * @brief Get the selected ADC instance enable state.
4208 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4209 * is enabled and when conversion clock is active.
4210 * (not only core clock: this ADC has a dual clock domain)
4211 * @rmtoll CR ADEN LL_ADC_IsEnabled
4212 * @param ADCx ADC instance
4213 * @retval 0: ADC is disabled, 1: ADC is enabled.
4214 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)4215 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
4216 {
4217 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
4218 }
4219
4220 /**
4221 * @brief Get the selected ADC instance disable state.
4222 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
4223 * @param ADCx ADC instance
4224 * @retval 0: no ADC disable command on going.
4225 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)4226 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
4227 {
4228 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
4229 }
4230
4231 /**
4232 * @brief Start ADC calibration in the mode single-ended
4233 * or differential (for devices with differential mode available).
4234 * @note On this STM32 series, a minimum number of ADC clock cycles
4235 * are required between ADC end of calibration and ADC enable.
4236 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
4237 * @note In case of usage of ADC with DMA transfer:
4238 * On this STM32 series, ADC DMA transfer request should be disabled
4239 * during calibration:
4240 * Calibration factor is available in data register
4241 * and also transferred by DMA.
4242 * To not insert ADC calibration factor among ADC conversion data
4243 * in array variable, DMA transfer must be disabled during
4244 * calibration.
4245 * (DMA transfer setting backup and disable before calibration,
4246 * DMA transfer setting restore after calibration.
4247 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
4248 * @ref LL_ADC_REG_SetDMATransfer() ).
4249 * @note In case of usage of feature auto power-off:
4250 * This mode must be disabled during calibration
4251 * Refer to function @ref LL_ADC_SetLowPowerMode().
4252 * @note On this STM32 series, setting of this feature is conditioned to
4253 * ADC state:
4254 * ADC must be ADC disabled.
4255 * @rmtoll CR ADCAL LL_ADC_StartCalibration
4256 * @param ADCx ADC instance
4257 * @retval None
4258 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)4259 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
4260 {
4261 /* Note: Write register with some additional bits forced to state reset */
4262 /* instead of modifying only the selected bit for this function, */
4263 /* to not interfere with bits with HW property "rs". */
4264 MODIFY_REG(ADCx->CR,
4265 ADC_CR_BITS_PROPERTY_RS,
4266 ADC_CR_ADCAL);
4267 }
4268
4269 /**
4270 * @brief Get ADC calibration state.
4271 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
4272 * @param ADCx ADC instance
4273 * @retval 0: calibration complete, 1: calibration in progress.
4274 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)4275 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
4276 {
4277 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
4278 }
4279
4280 /**
4281 * @}
4282 */
4283
4284 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
4285 * @{
4286 */
4287
4288 /**
4289 * @brief Start ADC group regular conversion.
4290 * @note On this STM32 series, this function is relevant for both
4291 * internal trigger (SW start) and external trigger:
4292 * - If ADC trigger has been set to software start, ADC conversion
4293 * starts immediately.
4294 * - If ADC trigger has been set to external trigger, ADC conversion
4295 * will start at next trigger event (on the selected trigger edge)
4296 * following the ADC start conversion command.
4297 * @note On this STM32 series, setting of this feature is conditioned to
4298 * ADC state:
4299 * ADC must be enabled without conversion on going on group regular,
4300 * without conversion stop command on going on group regular,
4301 * without ADC disable command on going.
4302 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
4303 * @param ADCx ADC instance
4304 * @retval None
4305 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)4306 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
4307 {
4308 /* Note: Write register with some additional bits forced to state reset */
4309 /* instead of modifying only the selected bit for this function, */
4310 /* to not interfere with bits with HW property "rs". */
4311 MODIFY_REG(ADCx->CR,
4312 ADC_CR_BITS_PROPERTY_RS,
4313 ADC_CR_ADSTART);
4314 }
4315
4316 /**
4317 * @brief Stop ADC group regular conversion.
4318 * @note On this STM32 series, setting of this feature is conditioned to
4319 * ADC state:
4320 * ADC must be enabled (potentially with conversion on going on group regular),
4321 * without ADC disable command on going.
4322 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
4323 * @param ADCx ADC instance
4324 * @retval None
4325 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)4326 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
4327 {
4328 /* Note: Write register with some additional bits forced to state reset */
4329 /* instead of modifying only the selected bit for this function, */
4330 /* to not interfere with bits with HW property "rs". */
4331 MODIFY_REG(ADCx->CR,
4332 ADC_CR_BITS_PROPERTY_RS,
4333 ADC_CR_ADSTP);
4334 }
4335
4336 /**
4337 * @brief Get ADC group regular conversion state.
4338 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
4339 * @param ADCx ADC instance
4340 * @retval 0: no conversion is on going on ADC group regular.
4341 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)4342 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
4343 {
4344 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
4345 }
4346
4347 /**
4348 * @brief Get ADC group regular command of conversion stop state
4349 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
4350 * @param ADCx ADC instance
4351 * @retval 0: no command of conversion stop is on going on ADC group regular.
4352 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)4353 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
4354 {
4355 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
4356 }
4357
4358 /**
4359 * @brief Get ADC group regular conversion data, range fit for
4360 * all ADC configurations: all ADC resolutions and
4361 * features extending data width (oversampling, data shift,...).
4362 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
4363 * @param ADCx ADC instance
4364 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4365 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)4366 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
4367 {
4368 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4369 }
4370
4371 /**
4372 * @brief Get ADC group regular conversion data, range fit for
4373 * ADC resolution 12 bits.
4374 * @note For devices with feature oversampling: Oversampling
4375 * can increase data width, function for extended range
4376 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4377 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
4378 * @param ADCx ADC instance
4379 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4380 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)4381 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
4382 {
4383 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x00000FFFUL);
4384 }
4385
4386 /**
4387 * @brief Get ADC group regular conversion data, range fit for
4388 * ADC resolution 10 bits.
4389 * @note For devices with feature oversampling: Oversampling
4390 * can increase data width, function for extended range
4391 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4392 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
4393 * @param ADCx ADC instance
4394 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4395 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)4396 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
4397 {
4398 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000003FFUL);
4399 }
4400
4401 /**
4402 * @brief Get ADC group regular conversion data, range fit for
4403 * ADC resolution 8 bits.
4404 * @note For devices with feature oversampling: Oversampling
4405 * can increase data width, function for extended range
4406 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4407 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
4408 * @param ADCx ADC instance
4409 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4410 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)4411 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
4412 {
4413 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL);
4414 }
4415
4416 /**
4417 * @brief Get ADC group regular conversion data, range fit for
4418 * ADC resolution 6 bits.
4419 * @note For devices with feature oversampling: Oversampling
4420 * can increase data width, function for extended range
4421 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4422 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
4423 * @param ADCx ADC instance
4424 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4425 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)4426 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
4427 {
4428 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x0000003FUL);
4429 }
4430
4431 /**
4432 * @}
4433 */
4434
4435 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4436 * @{
4437 */
4438
4439 /**
4440 * @brief Get flag ADC ready.
4441 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4442 * is enabled and when conversion clock is active.
4443 * (not only core clock: this ADC has a dual clock domain)
4444 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
4445 * @param ADCx ADC instance
4446 * @retval State of bit (1 or 0).
4447 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)4448 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
4449 {
4450 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
4451 }
4452
4453 /**
4454 * @brief Get flag ADC internal voltage regulator ready.
4455 * @rmtoll ISR LDORDY LL_ADC_IsActiveFlag_LDORDY
4456 * @param ADCx ADC instance
4457 * @retval State of bit (1 or 0).
4458 */
LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef * ADCx)4459 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx)
4460 {
4461 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL);
4462 }
4463
4464 /**
4465 * @brief Get flag ADC group regular end of unitary conversion.
4466 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
4467 * @param ADCx ADC instance
4468 * @retval State of bit (1 or 0).
4469 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)4470 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
4471 {
4472 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
4473 }
4474
4475 /**
4476 * @brief Get flag ADC group regular end of sequence conversions.
4477 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
4478 * @param ADCx ADC instance
4479 * @retval State of bit (1 or 0).
4480 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)4481 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
4482 {
4483 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
4484 }
4485
4486 /**
4487 * @brief Get flag ADC group regular overrun.
4488 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
4489 * @param ADCx ADC instance
4490 * @retval State of bit (1 or 0).
4491 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)4492 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
4493 {
4494 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
4495 }
4496
4497 /**
4498 * @brief Get flag ADC group regular end of sampling phase.
4499 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
4500 * @param ADCx ADC instance
4501 * @retval State of bit (1 or 0).
4502 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)4503 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
4504 {
4505 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
4506 }
4507
4508 /**
4509 * @brief Get flag ADC analog watchdog 1 flag
4510 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
4511 * @param ADCx ADC instance
4512 * @retval State of bit (1 or 0).
4513 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)4514 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
4515 {
4516 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
4517 }
4518
4519 /**
4520 * @brief Get flag ADC analog watchdog 2.
4521 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
4522 * @param ADCx ADC instance
4523 * @retval State of bit (1 or 0).
4524 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)4525 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
4526 {
4527 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
4528 }
4529
4530 /**
4531 * @brief Get flag ADC analog watchdog 3.
4532 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
4533 * @param ADCx ADC instance
4534 * @retval State of bit (1 or 0).
4535 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)4536 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
4537 {
4538 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
4539 }
4540
4541 /**
4542 * @brief Get flag ADC end of calibration.
4543 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
4544 * @param ADCx ADC instance
4545 * @retval State of bit (1 or 0).
4546 */
LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef * ADCx)4547 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx)
4548 {
4549 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
4550 }
4551
4552 /**
4553 * @brief Clear flag ADC ready.
4554 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4555 * is enabled and when conversion clock is active.
4556 * (not only core clock: this ADC has a dual clock domain)
4557 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
4558 * @param ADCx ADC instance
4559 * @retval None
4560 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)4561 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
4562 {
4563 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
4564 }
4565
4566 /**
4567 * @brief Clear flag ADC internal voltage regulator ready.
4568 * @rmtoll ISR LDORDY LL_ADC_ClearFlag_LDORDY
4569 * @param ADCx ADC instance
4570 * @retval State of bit (1 or 0).
4571 */
LL_ADC_ClearFlag_LDORDY(ADC_TypeDef * ADCx)4572 __STATIC_INLINE void LL_ADC_ClearFlag_LDORDY(ADC_TypeDef *ADCx)
4573 {
4574 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_LDORDY);
4575 }
4576
4577 /**
4578 * @brief Clear flag ADC group regular end of unitary conversion.
4579 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
4580 * @param ADCx ADC instance
4581 * @retval None
4582 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)4583 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
4584 {
4585 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
4586 }
4587
4588 /**
4589 * @brief Clear flag ADC group regular end of sequence conversions.
4590 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
4591 * @param ADCx ADC instance
4592 * @retval None
4593 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)4594 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
4595 {
4596 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
4597 }
4598
4599 /**
4600 * @brief Clear flag ADC group regular overrun.
4601 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
4602 * @param ADCx ADC instance
4603 * @retval None
4604 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4605 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4606 {
4607 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
4608 }
4609
4610 /**
4611 * @brief Clear flag ADC group regular end of sampling phase.
4612 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
4613 * @param ADCx ADC instance
4614 * @retval None
4615 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)4616 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
4617 {
4618 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
4619 }
4620
4621 /**
4622 * @brief Clear flag ADC analog watchdog 1.
4623 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
4624 * @param ADCx ADC instance
4625 * @retval None
4626 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4627 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4628 {
4629 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
4630 }
4631
4632 /**
4633 * @brief Clear flag ADC analog watchdog 2.
4634 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
4635 * @param ADCx ADC instance
4636 * @retval None
4637 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)4638 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
4639 {
4640 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
4641 }
4642
4643 /**
4644 * @brief Clear flag ADC analog watchdog 3.
4645 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
4646 * @param ADCx ADC instance
4647 * @retval None
4648 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)4649 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
4650 {
4651 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
4652 }
4653
4654 /**
4655 * @brief Clear flag ADC end of calibration.
4656 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
4657 * @param ADCx ADC instance
4658 * @retval None
4659 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)4660 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
4661 {
4662 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
4663 }
4664
4665 /**
4666 * @}
4667 */
4668
4669 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4670 * @{
4671 */
4672
4673 /**
4674 * @brief Enable ADC ready.
4675 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
4676 * @param ADCx ADC instance
4677 * @retval None
4678 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)4679 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
4680 {
4681 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
4682 }
4683
4684 /**
4685 * @brief Enable interruption ADC internal voltage regulator ready.
4686 * @rmtoll IER LDORDYIE LL_ADC_EnableIT_LDORDY
4687 * @param ADCx ADC instance
4688 * @retval State of bit (1 or 0).
4689 */
LL_ADC_EnableIT_LDORDY(ADC_TypeDef * ADCx)4690 __STATIC_INLINE void LL_ADC_EnableIT_LDORDY(ADC_TypeDef *ADCx)
4691 {
4692 SET_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY);
4693 }
4694
4695 /**
4696 * @brief Enable interruption ADC group regular end of unitary conversion.
4697 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
4698 * @param ADCx ADC instance
4699 * @retval None
4700 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)4701 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
4702 {
4703 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
4704 }
4705
4706 /**
4707 * @brief Enable interruption ADC group regular end of sequence conversions.
4708 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
4709 * @param ADCx ADC instance
4710 * @retval None
4711 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)4712 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
4713 {
4714 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
4715 }
4716
4717 /**
4718 * @brief Enable ADC group regular interruption overrun.
4719 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
4720 * @param ADCx ADC instance
4721 * @retval None
4722 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4723 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4724 {
4725 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
4726 }
4727
4728 /**
4729 * @brief Enable interruption ADC group regular end of sampling.
4730 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
4731 * @param ADCx ADC instance
4732 * @retval None
4733 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)4734 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
4735 {
4736 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
4737 }
4738
4739 /**
4740 * @brief Enable interruption ADC analog watchdog 1.
4741 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
4742 * @param ADCx ADC instance
4743 * @retval None
4744 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4745 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4746 {
4747 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
4748 }
4749
4750 /**
4751 * @brief Enable interruption ADC analog watchdog 2.
4752 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
4753 * @param ADCx ADC instance
4754 * @retval None
4755 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)4756 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
4757 {
4758 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
4759 }
4760
4761 /**
4762 * @brief Enable interruption ADC analog watchdog 3.
4763 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
4764 * @param ADCx ADC instance
4765 * @retval None
4766 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)4767 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
4768 {
4769 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
4770 }
4771
4772 /**
4773 * @brief Enable interruption ADC end of calibration.
4774 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
4775 * @param ADCx ADC instance
4776 * @retval None
4777 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)4778 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
4779 {
4780 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
4781 }
4782
4783 /**
4784 * @brief Disable interruption ADC ready.
4785 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
4786 * @param ADCx ADC instance
4787 * @retval None
4788 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)4789 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
4790 {
4791 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
4792 }
4793
4794 /**
4795 * @brief Disable interruption ADC internal voltage regulator ready.
4796 * @rmtoll IER LDORDYIE LL_ADC_DisableIT_LDORDY
4797 * @param ADCx ADC instance
4798 * @retval State of bit (1 or 0).
4799 */
LL_ADC_DisableIT_LDORDY(ADC_TypeDef * ADCx)4800 __STATIC_INLINE void LL_ADC_DisableIT_LDORDY(ADC_TypeDef *ADCx)
4801 {
4802 CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY);
4803 }
4804
4805 /**
4806 * @brief Disable interruption ADC group regular end of unitary conversion.
4807 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
4808 * @param ADCx ADC instance
4809 * @retval None
4810 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)4811 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
4812 {
4813 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
4814 }
4815
4816 /**
4817 * @brief Disable interruption ADC group regular end of sequence conversions.
4818 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
4819 * @param ADCx ADC instance
4820 * @retval None
4821 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)4822 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
4823 {
4824 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
4825 }
4826
4827 /**
4828 * @brief Disable interruption ADC group regular overrun.
4829 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
4830 * @param ADCx ADC instance
4831 * @retval None
4832 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4833 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4834 {
4835 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
4836 }
4837
4838 /**
4839 * @brief Disable interruption ADC group regular end of sampling.
4840 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
4841 * @param ADCx ADC instance
4842 * @retval None
4843 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)4844 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
4845 {
4846 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
4847 }
4848
4849 /**
4850 * @brief Disable interruption ADC analog watchdog 1.
4851 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
4852 * @param ADCx ADC instance
4853 * @retval None
4854 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4855 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4856 {
4857 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
4858 }
4859
4860 /**
4861 * @brief Disable interruption ADC analog watchdog 2.
4862 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
4863 * @param ADCx ADC instance
4864 * @retval None
4865 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)4866 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
4867 {
4868 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
4869 }
4870
4871 /**
4872 * @brief Disable interruption ADC analog watchdog 3.
4873 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
4874 * @param ADCx ADC instance
4875 * @retval None
4876 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)4877 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
4878 {
4879 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
4880 }
4881
4882 /**
4883 * @brief Disable interruption ADC end of calibration.
4884 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
4885 * @param ADCx ADC instance
4886 * @retval None
4887 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)4888 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
4889 {
4890 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
4891 }
4892
4893 /**
4894 * @brief Get state of interruption ADC ready
4895 * (0: interrupt disabled, 1: interrupt enabled).
4896 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
4897 * @param ADCx ADC instance
4898 * @retval State of bit (1 or 0).
4899 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)4900 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
4901 {
4902 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
4903 }
4904
4905 /**
4906 * @brief Get state of interruption ADC internal voltage regulator ready.
4907 * @rmtoll IER LDORDYIE LL_ADC_IsEnabledIT_LDORDY
4908 * @param ADCx ADC instance
4909 * @retval State of bit (1 or 0).
4910 */
LL_ADC_IsEnabledIT_LDORDY(const ADC_TypeDef * ADCx)4911 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_LDORDY(const ADC_TypeDef *ADCx)
4912 {
4913 return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL);
4914 }
4915
4916 /**
4917 * @brief Get state of interruption ADC group regular end of unitary conversion
4918 * (0: interrupt disabled, 1: interrupt enabled).
4919 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
4920 * @param ADCx ADC instance
4921 * @retval State of bit (1 or 0).
4922 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)4923 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
4924 {
4925 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
4926 }
4927
4928 /**
4929 * @brief Get state of interruption ADC group regular end of sequence conversions
4930 * (0: interrupt disabled, 1: interrupt enabled).
4931 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
4932 * @param ADCx ADC instance
4933 * @retval State of bit (1 or 0).
4934 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)4935 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
4936 {
4937 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
4938 }
4939
4940 /**
4941 * @brief Get state of interruption ADC group regular overrun
4942 * (0: interrupt disabled, 1: interrupt enabled).
4943 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
4944 * @param ADCx ADC instance
4945 * @retval State of bit (1 or 0).
4946 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)4947 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
4948 {
4949 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
4950 }
4951
4952 /**
4953 * @brief Get state of interruption ADC group regular end of sampling
4954 * (0: interrupt disabled, 1: interrupt enabled).
4955 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
4956 * @param ADCx ADC instance
4957 * @retval State of bit (1 or 0).
4958 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)4959 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
4960 {
4961 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
4962 }
4963
4964 /**
4965 * @brief Get state of interruption ADC analog watchdog 1
4966 * (0: interrupt disabled, 1: interrupt enabled).
4967 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
4968 * @param ADCx ADC instance
4969 * @retval State of bit (1 or 0).
4970 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)4971 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
4972 {
4973 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
4974 }
4975
4976 /**
4977 * @brief Get state of interruption Get ADC analog watchdog 2
4978 * (0: interrupt disabled, 1: interrupt enabled).
4979 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
4980 * @param ADCx ADC instance
4981 * @retval State of bit (1 or 0).
4982 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)4983 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
4984 {
4985 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
4986 }
4987
4988 /**
4989 * @brief Get state of interruption Get ADC analog watchdog 3
4990 * (0: interrupt disabled, 1: interrupt enabled).
4991 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
4992 * @param ADCx ADC instance
4993 * @retval State of bit (1 or 0).
4994 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)4995 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
4996 {
4997 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
4998 }
4999
5000 /**
5001 * @brief Get state of interruption ADC end of calibration
5002 * (0: interrupt disabled, 1: interrupt enabled).
5003 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
5004 * @param ADCx ADC instance
5005 * @retval State of bit (1 or 0).
5006 */
LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef * ADCx)5007 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
5008 {
5009 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
5010 }
5011
5012 /**
5013 * @}
5014 */
5015
5016 #if defined(USE_FULL_LL_DRIVER)
5017 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
5018 * @{
5019 */
5020
5021 /* Initialization of some features of ADC common parameters and multimode */
5022 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
5023 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5024 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5025
5026 /* De-initialization of ADC instance */
5027 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
5028
5029 /* Initialization of some features of ADC instance */
5030 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
5031 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
5032
5033 /* Initialization of some features of ADC instance and ADC group regular */
5034 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5035 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5036
5037 /**
5038 * @}
5039 */
5040 #endif /* USE_FULL_LL_DRIVER */
5041
5042 /**
5043 * @}
5044 */
5045
5046 /**
5047 * @}
5048 */
5049
5050 #endif /* ADC4 */
5051
5052 /**
5053 * @}
5054 */
5055
5056 #ifdef __cplusplus
5057 }
5058 #endif
5059
5060 #endif /* STM32WBAxx_LL_ADC_H */
5061
