Searched refs:IS_QSPI_DDR_HHC (Results 1 – 12 of 12) sorted by relevance
812 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command()901 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT()1523 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling()1623 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT()1727 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped()
809 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command()897 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT()1670 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling()1769 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT()1873 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped()
813 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command()901 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT()1595 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling()1694 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT()1798 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped()
831 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command()920 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT()1542 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling()1642 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT()1746 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped()
820 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command()909 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT()1603 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling()1703 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT()1807 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped()
804 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command()893 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_Command_IT()1579 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling()1679 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_AutoPolling_IT()1783 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); in HAL_QSPI_MemoryMapped()
723 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ macro727 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) macro
708 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ macro
711 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ macro
712 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ macro
