1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_adc.c
4 * @author GPM Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wb0x_ll_adc.h"
22 #include "stm32wb0x_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0UL)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32WB0x_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 #define ADC_SWITCH_SE_VIN_ALL (ADC_SWITCH_SE_VIN_0 | ADC_SWITCH_SE_VIN_1 | \
48 ADC_SWITCH_SE_VIN_2 | ADC_SWITCH_SE_VIN_3 | \
49 ADC_SWITCH_SE_VIN_4 | ADC_SWITCH_SE_VIN_5 | \
50 ADC_SWITCH_SE_VIN_6 | ADC_SWITCH_SE_VIN_7)
51
52 #define ADC_SEQ_1_SEQ_ALL (ADC_SEQ_1_SEQ0 | ADC_SEQ_1_SEQ1 | \
53 ADC_SEQ_1_SEQ2 | ADC_SEQ_1_SEQ3 | \
54 ADC_SEQ_1_SEQ4 | ADC_SEQ_1_SEQ5 | \
55 ADC_SEQ_1_SEQ6 | ADC_SEQ_1_SEQ7)
56
57 #define ADC_SEQ_2_SEQ_ALL (ADC_SEQ_2_SEQ8 | ADC_SEQ_2_SEQ9 | \
58 ADC_SEQ_2_SEQ10 | ADC_SEQ_2_SEQ11 | \
59 ADC_SEQ_2_SEQ12 | ADC_SEQ_2_SEQ13 | \
60 ADC_SEQ_2_SEQ14 | ADC_SEQ_2_SEQ15)
61
62 /**
63 * @}
64 */
65
66 /* Private macros ------------------------------------------------------------*/
67
68 /** @addtogroup ADC_LL_Private_Macros
69 * @{
70 */
71 /* Check of parameters for configuration of ADC hierarchical scope: */
72 /* ADC instance. */
73 #define IS_LL_ADC_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
74
75 #define IS_LL_ADC_DATAWIDTH(__DATA_WIDTH__) (((__DATA_WIDTH__) == LL_ADC_DS_DATA_WIDTH_12_BIT) || \
76 ((__DATA_WIDTH__) == LL_ADC_DS_DATA_WIDTH_13_BIT) || \
77 ((__DATA_WIDTH__) == LL_ADC_DS_DATA_WIDTH_14_BIT) || \
78 ((__DATA_WIDTH__) == LL_ADC_DS_DATA_WIDTH_15_BIT) || \
79 ((__DATA_WIDTH__) == LL_ADC_DS_DATA_WIDTH_16_BIT) )
80
81 #define IS_LL_ADC_DATARATIO(__DATA_RATIO__) (((__DATA_RATIO__) == LL_ADC_DS_RATIO_1) || \
82 ((__DATA_RATIO__) == LL_ADC_DS_RATIO_2) || \
83 ((__DATA_RATIO__) == LL_ADC_DS_RATIO_4) || \
84 ((__DATA_RATIO__) == LL_ADC_DS_RATIO_8) || \
85 ((__DATA_RATIO__) == LL_ADC_DS_RATIO_16) || \
86 ((__DATA_RATIO__) == LL_ADC_DS_RATIO_32) || \
87 ((__DATA_RATIO__) == LL_ADC_DS_RATIO_64) || \
88 ((__DATA_RATIO__) == LL_ADC_DS_RATIO_128) )
89
90 #define IS_LL_ADC_OVERRUN(__OVR__) (((__OVR__) == LL_ADC_NEW_DATA_IS_LOST) || \
91 ((__OVR__) == LL_ADC_NEW_DATA_IS_KEPT) )
92
93 #define IS_LL_ADC_SAMPLINGMODE(__SAMPLING_MODE__) (((__SAMPLING_MODE__) == LL_ADC_SAMPLING_AT_START) || \
94 ((__SAMPLING_MODE__) == LL_ADC_SAMPLING_AT_END) )
95
96 #if defined(ADC_CONF_SAMPLE_RATE_MSB)
97 #define IS_LL_ADC_SAMPLERATE(__SAMPLERATE__) (((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_16) || \
98 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_20) || \
99 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_24) || \
100 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_28) || \
101 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_32) || \
102 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_36) || \
103 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_40) || \
104 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_44) || \
105 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_48) || \
106 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_52) || \
107 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_56) || \
108 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_60) || \
109 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_64) || \
110 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_68) || \
111 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_72) || \
112 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_76) || \
113 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_80) || \
114 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_84) || \
115 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_88) || \
116 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_92) || \
117 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_96) || \
118 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_100) || \
119 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_104) || \
120 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_108) || \
121 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_112) || \
122 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_116) || \
123 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_120) || \
124 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_124) || \
125 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_128) || \
126 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_132) || \
127 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_136) || \
128 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_140) )
129 #else
130 #define IS_LL_ADC_SAMPLERATE(__SAMPLERATE__) (((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_16) || \
131 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_20) || \
132 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_24) || \
133 ((__SAMPLERATE__) == LL_ADC_SAMPLE_RATE_28) )
134 #endif /* ADC_CONF_SAMPLE_RATE_MSB */
135
136 #define IS_LL_ADC_RANK(__RANK__) (((__RANK__) == LL_ADC_RANK_1 ) || \
137 ((__RANK__) == LL_ADC_RANK_2 ) || \
138 ((__RANK__) == LL_ADC_RANK_3 ) || \
139 ((__RANK__) == LL_ADC_RANK_4 ) || \
140 ((__RANK__) == LL_ADC_RANK_5 ) || \
141 ((__RANK__) == LL_ADC_RANK_6 ) || \
142 ((__RANK__) == LL_ADC_RANK_7 ) || \
143 ((__RANK__) == LL_ADC_RANK_8 ) || \
144 ((__RANK__) == LL_ADC_RANK_9 ) || \
145 ((__RANK__) == LL_ADC_RANK_10) || \
146 ((__RANK__) == LL_ADC_RANK_11) || \
147 ((__RANK__) == LL_ADC_RANK_12) || \
148 ((__RANK__) == LL_ADC_RANK_13) || \
149 ((__RANK__) == LL_ADC_RANK_14) || \
150 ((__RANK__) == LL_ADC_RANK_15) || \
151 ((__RANK__) == LL_ADC_RANK_16) )
152
153 #define IS_LL_ADC_VOLTAGE_RANGE(__VOLTAGE_RANGE__) (((__VOLTAGE_RANGE__) == LL_ADC_VIN_RANGE_1V2) || \
154 ((__VOLTAGE_RANGE__) == LL_ADC_VIN_RANGE_2V4) || \
155 ((__VOLTAGE_RANGE__) == LL_ADC_VIN_RANGE_3V6) )
156
157 #define IS_LL_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == LL_ADC_CHANNEL_VINM0) || \
158 ((__CHANNEL__) == LL_ADC_CHANNEL_VINM1) || \
159 ((__CHANNEL__) == LL_ADC_CHANNEL_VINM2) || \
160 ((__CHANNEL__) == LL_ADC_CHANNEL_VINM3) || \
161 ((__CHANNEL__) == LL_ADC_CHANNEL_VINP0) || \
162 ((__CHANNEL__) == LL_ADC_CHANNEL_VINP1) || \
163 ((__CHANNEL__) == LL_ADC_CHANNEL_VINP2) || \
164 ((__CHANNEL__) == LL_ADC_CHANNEL_VINP3) || \
165 ((__CHANNEL__) == LL_ADC_CHANNEL_VINP0_VINM0) || \
166 ((__CHANNEL__) == LL_ADC_CHANNEL_VINP1_VINM1) || \
167 ((__CHANNEL__) == LL_ADC_CHANNEL_VINP2_VINM2) || \
168 ((__CHANNEL__) == LL_ADC_CHANNEL_VINP3_VINM3) || \
169 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
170 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) )
171
172 /**
173 * @}
174 */
175
176
177 /* Private function prototypes -----------------------------------------------*/
178
179 /* Exported functions --------------------------------------------------------*/
180 /** @addtogroup ADC_LL_Exported_Functions
181 * @{
182 */
183
184 /** @addtogroup ADC_LL_EF_Init
185 * @{
186 */
187
188 /**
189 * @brief Initialize some features of ADC instance.
190 * @note These parameters have an impact on ADC scope: ADC instance.
191 * Refer to corresponding unitary functions into
192 * @ref ADC_LL_EF_Configuration_ADC.
193 * @note The setting of these parameters by function @ref LL_ADC_Init()
194 * is conditioned to ADC state:
195 * ADC instance must be disabled.
196 * This condition is applied to all ADC features, for efficiency
197 * and compatibility over all STM32 families. However, the different
198 * features can be set under different ADC state conditions
199 * (setting possible with ADC enabled without conversion on going,
200 * ADC enabled with conversion on going, ...)
201 * Each feature can be updated afterwards with a unitary function
202 * and potentially with ADC in a different state than disabled,
203 * refer to description of each function for setting
204 * conditioned to ADC state.
205 * @param ADCx ADC instance
206 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
207 * @retval An ErrorStatus enumeration value:
208 * - SUCCESS: ADC registers are initialized
209 * - ERROR: ADC registers are not initialized
210 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * pADC_InitStruct)211 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
212 {
213 ErrorStatus status = SUCCESS;
214
215 /* Check the parameters */
216 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
217
218 assert_param(IS_LL_ADC_NB_CONV(pADC_InitStruct->SequenceLength));
219 assert_param(IS_LL_ADC_SAMPLINGMODE(pADC_InitStruct->SamplingMode));
220 assert_param(IS_LL_ADC_SAMPLERATE(pADC_InitStruct->SampleRate));
221 assert_param(IS_LL_ADC_OVERRUN(pADC_InitStruct->Overrun));
222
223 /* Note: Hardware constraint (refer to description of this function): */
224 /* ADC instance must be disabled. */
225 if (LL_ADC_IsEnabled(ADCx) == 0UL)
226 {
227 /* Configuration of ADC hierarchical scope: */
228 /* - ADC instance */
229 /* - Set ADC continuous mode */
230 /* - Set ADC sequence length */
231 /* - Set ADC sampling mode */
232 /* - Set ADC sample rate */
233 /* - Set ADC overrun */
234 MODIFY_REG(ADCx->CONF, (ADC_CONF_SAMPLE_RATE
235 #if defined(ADC_CONF_SAMPLE_RATE_MSB)
236 | ADC_CONF_SAMPLE_RATE_MSB
237 #endif /* ADC_CONF_SAMPLE_RATE_MSB */
238 | ADC_CONF_ADC_CONT_1V2
239 | ADC_CONF_OVR_DS_CFG
240 | ADC_CONF_SEQ_LEN
241 | ADC_CONF_CONT),
242 (pADC_InitStruct->SampleRate
243 | pADC_InitStruct->SamplingMode
244 | pADC_InitStruct->Overrun
245 | ((pADC_InitStruct->SequenceLength - 1UL) << ADC_CONF_SEQ_LEN_Pos)
246 | pADC_InitStruct->ContinuousConvMode));
247 }
248 else
249 {
250 /* Initialization error: ADC instance is not disabled. */
251 status = ERROR;
252 }
253
254 return status;
255 }
256
257 /**
258 * @brief De-initialize registers of the selected ADC instance
259 * to their default reset values.
260 * @note If this functions returns error status, it means that ADC instance
261 * is in an unknown state.
262 * In this case, perform a hard reset using high level
263 * clock source RCC ADC reset.
264 * @param ADCx ADC instance
265 * @retval An ErrorStatus enumeration value:
266 * - SUCCESS: ADC registers are de-initialized
267 * - ERROR: ADC registers are not de-initialized
268 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)269 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
270 {
271 ErrorStatus status = SUCCESS;
272
273 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
274
275 /* ========== Reset ADC registers ========== */
276 /* Reset register IER */
277 LL_ADC_DisableIT(ADCx, (LL_ADC_IRQ_EN_OVRDS
278 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
279 | LL_ADC_IRQ_EN_OVRFL
280 | LL_ADC_IRQ_EN_EODF
281 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
282 | LL_ADC_IRQ_EN_AWD1
283 | LL_ADC_IRQ_EN_EOS
284 | LL_ADC_IRQ_EN_EODS));
285
286 /* Reset register ISR */
287 LL_ADC_ClearActiveFlags(ADCx, (LL_ADC_IRQ_FLAG_OVRDS
288 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
289 | LL_ADC_IRQ_FLAG_OVRFL
290 | LL_ADC_IRQ_FLAG_OVRDF
291 | LL_ADC_IRQ_FLAG_EODF
292 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
293 | LL_ADC_IRQ_FLAG_AWD1
294 | LL_ADC_IRQ_FLAG_EOC
295 | LL_ADC_IRQ_FLAG_EOS
296 | LL_ADC_IRQ_FLAG_EODS));
297
298 /* Reset all the registers */
299 CLEAR_BIT(ADCx->CONF, (ADC_CONF_BIT_INVERT_DIFF
300 #if defined(ADC_CONF_SAMPLE_RATE_MSB)
301 | ADC_CONF_SAMPLE_RATE_MSB
302 #endif /* ADC_CONF_SAMPLE_RATE_MSB */
303 | ADC_CONF_OVR_DS_CFG | ADC_CONF_DMA_DS_ENA
304 | ADC_CONF_SAMPLE_RATE
305 | ADC_CONF_SMPS_SYNCHRO_ENA
306 | ADC_CONF_SEQ_LEN
307 | ADC_CONF_CONT
308 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
309 | ADC_CONF_VBIAS_PRECH_FORCE
310 | ADC_CONF_OVR_DF_CFG | ADC_CONF_DMA_DF_ENA
311 | ADC_CONF_OP_MODE
312 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
313 ));
314
315 SET_BIT(ADCx->CONF, (ADC_CONF_ADC_CONT_1V2 | ADC_CONF_BIT_INVERT_SN | ADC_CONF_SEQUENCE));
316
317 CLEAR_BIT(ADCx->CTRL, (ADC_CTRL_ADC_LDO_ENA
318 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
319 | ADC_CTRL_DIG_AUD_MODE
320 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
321 | ADC_CTRL_STOP_OP_MODE | ADC_CTRL_START_CONV
322 | ADC_CTRL_ADC_ON_OFF));
323
324 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
325 CLEAR_BIT(ADCx->OCM_CTRL, (ADC_OCM_CTRL_OCM_ENA | ADC_OCM_CTRL_OCM_SRC));
326
327 CLEAR_BIT(ADCx->PGA_CONF, (ADC_PGA_CONF_PGA_BIAS | ADC_PGA_CONF_PGA_GAIN));
328 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
329
330 CLEAR_BIT(ADCx->SWITCH, (ADC_SWITCH_SE_VIN_7 | ADC_SWITCH_SE_VIN_6
331 | ADC_SWITCH_SE_VIN_5 | ADC_SWITCH_SE_VIN_4
332 | ADC_SWITCH_SE_VIN_3 | ADC_SWITCH_SE_VIN_2
333 | ADC_SWITCH_SE_VIN_1 | ADC_SWITCH_SE_VIN_0));
334
335 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
336 CLEAR_BIT(ADCx->DF_CONF, (ADC_DF_CONF_DF_HALF_D_EN
337 | ADC_DF_CONF_DF_HPF_EN | ADC_DF_CONF_DF_MICROL_RN
338 | ADC_DF_CONF_PDM_RATE
339 | ADC_DF_CONF_DF_O_S2U
340 | ADC_DF_CONF_DF_I_U2S | ADC_DF_CONF_DF_ITP1P2
341 | ADC_DF_CONF_DF_CIC_DHF | ADC_DF_CONF_DF_CIC_DEC_FACTOR));
342
343 SET_BIT(ADCx->DF_CONF, (ADC_DF_CONF_PDM_RATE_1 | ADC_DF_CONF_PDM_RATE_2));
344 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
345
346 CLEAR_BIT(ADCx->DS_CONF, (ADC_DS_CONF_DS_WIDTH | ADC_DS_CONF_DS_RATIO));
347
348 CLEAR_BIT(ADCx->SEQ_1, (ADC_SEQ_1_SEQ7 | ADC_SEQ_1_SEQ6
349 | ADC_SEQ_1_SEQ5 | ADC_SEQ_1_SEQ4
350 | ADC_SEQ_1_SEQ3 | ADC_SEQ_1_SEQ2
351 | ADC_SEQ_1_SEQ1 | ADC_SEQ_1_SEQ0));
352
353 CLEAR_BIT(ADCx->SEQ_2, (ADC_SEQ_2_SEQ15 | ADC_SEQ_2_SEQ14
354 | ADC_SEQ_2_SEQ13 | ADC_SEQ_2_SEQ12
355 | ADC_SEQ_2_SEQ11 | ADC_SEQ_2_SEQ10
356 | ADC_SEQ_2_SEQ9 | ADC_SEQ_2_SEQ8));
357
358 MODIFY_REG(ADCx->COMP_1, (ADC_COMP_1_OFFSET1 | ADC_COMP_1_GAIN1), 0x555UL);
359 MODIFY_REG(ADCx->COMP_2, (ADC_COMP_1_OFFSET1 | ADC_COMP_1_GAIN1), 0x555UL);
360 MODIFY_REG(ADCx->COMP_3, (ADC_COMP_1_OFFSET1 | ADC_COMP_1_GAIN1), 0x555UL);
361 MODIFY_REG(ADCx->COMP_4, (ADC_COMP_1_OFFSET1 | ADC_COMP_1_GAIN1), 0x555UL);
362
363 CLEAR_BIT(ADCx->COMP_SEL, (ADC_COMP_SEL_OFFSET_GAIN8 | ADC_COMP_SEL_OFFSET_GAIN7
364 | ADC_COMP_SEL_OFFSET_GAIN6 | ADC_COMP_SEL_OFFSET_GAIN5
365 | ADC_COMP_SEL_OFFSET_GAIN4 | ADC_COMP_SEL_OFFSET_GAIN3
366 | ADC_COMP_SEL_OFFSET_GAIN2 | ADC_COMP_SEL_OFFSET_GAIN1
367 | ADC_COMP_SEL_OFFSET_GAIN0));
368
369 MODIFY_REG(ADCx->WD_TH, (ADC_WD_TH_WD_HT | ADC_WD_TH_WD_LT), ADC_WD_TH_WD_HT);
370
371 CLEAR_BIT(ADCx->WD_CONF, (ADC_WD_CONF_AWD_CHX));
372
373 CLEAR_BIT(ADCx->IRQ_STATUS, (ADC_IRQ_STATUS_OVR_DS_IRQ
374 | ADC_IRQ_STATUS_AWD_IRQ
375 | ADC_IRQ_STATUS_EOS_IRQ
376 | ADC_IRQ_STATUS_EODS_IRQ
377 | ADC_IRQ_STATUS_EOC_IRQ
378 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
379 | ADC_IRQ_STATUS_DF_OVRFL_IRQ
380 | ADC_IRQ_STATUS_OVR_DF_IRQ
381 | ADC_IRQ_STATUS_EODF_IRQ
382 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
383 ));
384
385 CLEAR_BIT(ADCx->IRQ_ENABLE, (ADC_IRQ_ENABLE_OVR_DS_IRQ_ENA
386 | ADC_IRQ_ENABLE_AWD_IRQ_ENA
387 | ADC_IRQ_ENABLE_EOS_IRQ_ENA
388 | ADC_IRQ_ENABLE_EODS_IRQ_ENA
389 | ADC_IRQ_ENABLE_EOC_IRQ_ENA
390 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
391 | ADC_IRQ_ENABLE_DF_OVRFL_IRQ_ENA
392 | ADC_IRQ_ENABLE_OVR_DF_IRQ_ENA
393 | ADC_IRQ_ENABLE_EODF_IRQ_ENA
394 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
395 ));
396
397 CLEAR_BIT(ADCx->TIMER_CONF, (ADC_TIMER_CONF_ADC_LDO_DELAY
398 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
399 | ADC_TIMER_CONF_PRECH_DELAY_SEL
400 | ADC_TIMER_CONF_VBIAS_PRECH_DELAY
401 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
402 ));
403 #if defined(ADC_SUPPORT_AUDIO_FEATURES)
404 LL_ADC_SetVbiasPrechargeDelay(ADCx, 0x96UL);
405 #endif /* ADC_SUPPORT_AUDIO_FEATURES */
406 LL_ADC_SetADCLDODelay(ADCx, 0x28UL);
407
408 return status;
409 }
410
411
412 /**
413 * @brief Configure the input voltage range for all the inputs.
414 * @param ADCx ADC instance
415 * @param pVoltRange_InitStruct pointer to a @ref LL_ADC_VoltRangeInitTypeDef structure
416 * that contains the voltage range for all the inputs.
417 * @retval None
418 */
LL_ADC_VoltageRangeInit(ADC_TypeDef * ADCx,const LL_ADC_VoltRangeInitTypeDef * pVoltRange_InitStruct)419 ErrorStatus LL_ADC_VoltageRangeInit(ADC_TypeDef *ADCx, const LL_ADC_VoltRangeInitTypeDef *pVoltRange_InitStruct)
420 {
421 ErrorStatus status = SUCCESS;
422 uint32_t tmpval = 0;
423
424 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
425 assert_param(IS_LL_ADC_VOLTAGE_RANGE(pVoltRange_InitStruct->InputVinm0_Vinp0Vinm0));
426 assert_param(IS_LL_ADC_VOLTAGE_RANGE(pVoltRange_InitStruct->InputVinm1_Vinp1Vinm1));
427 assert_param(IS_LL_ADC_VOLTAGE_RANGE(pVoltRange_InitStruct->InputVinm2_Vinp2Vinm2));
428 assert_param(IS_LL_ADC_VOLTAGE_RANGE(pVoltRange_InitStruct->InputVinm3_Vinp3Vinm3));
429 assert_param(IS_LL_ADC_VOLTAGE_RANGE(pVoltRange_InitStruct->InputVinp0));
430 assert_param(IS_LL_ADC_VOLTAGE_RANGE(pVoltRange_InitStruct->InputVinp1));
431 assert_param(IS_LL_ADC_VOLTAGE_RANGE(pVoltRange_InitStruct->InputVinp2));
432 assert_param(IS_LL_ADC_VOLTAGE_RANGE(pVoltRange_InitStruct->InputVinp3));
433
434 tmpval |= (pVoltRange_InitStruct->InputVinm0_Vinp0Vinm0);
435 tmpval |= (pVoltRange_InitStruct->InputVinm1_Vinp1Vinm1) << ADC_SWITCH_SE_VIN_1_Pos;
436 tmpval |= (pVoltRange_InitStruct->InputVinm2_Vinp2Vinm2) << ADC_SWITCH_SE_VIN_2_Pos;
437 tmpval |= (pVoltRange_InitStruct->InputVinm3_Vinp3Vinm3) << ADC_SWITCH_SE_VIN_3_Pos;
438 tmpval |= (pVoltRange_InitStruct->InputVinp0) << ADC_SWITCH_SE_VIN_4_Pos;
439 tmpval |= (pVoltRange_InitStruct->InputVinp1) << ADC_SWITCH_SE_VIN_5_Pos;
440 tmpval |= (pVoltRange_InitStruct->InputVinp2) << ADC_SWITCH_SE_VIN_6_Pos;
441 tmpval |= (pVoltRange_InitStruct->InputVinp3) << ADC_SWITCH_SE_VIN_7_Pos;
442
443 MODIFY_REG(ADCx->SWITCH, ADC_SWITCH_SE_VIN_ALL, tmpval);
444
445 return (status);
446 }
447
448 /**
449 * @brief Configure the channels for the conversion sequence.
450 * @param ADCx ADC instance
451 * @param pSequence_InitStruct pointer to a @ref LL_ADC_SequenceInitTypeDef structure
452 * that contains the channel codes for the conversion sequence.
453 * @retval ErrorStatus
454 */
LL_ADC_SequenceInit(ADC_TypeDef * ADCx,const LL_ADC_SequenceInitTypeDef * pSequence_InitStruct)455 ErrorStatus LL_ADC_SequenceInit(ADC_TypeDef *ADCx, const LL_ADC_SequenceInitTypeDef *pSequence_InitStruct)
456 {
457 ErrorStatus status = SUCCESS;
458 uint32_t tmpval = 0;
459
460 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
461 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq0));
462 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq1));
463 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq2));
464 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq3));
465 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq4));
466 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq5));
467 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq6));
468 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq7));
469 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq8));
470 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq9));
471 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq10));
472 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq11));
473 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq12));
474 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq13));
475 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq14));
476 assert_param(IS_LL_ADC_CHANNEL(pSequence_InitStruct->ChannelForSeq15));
477
478 tmpval |= (pSequence_InitStruct->ChannelForSeq0) << ADC_SEQ_1_SEQ0_Pos;
479 tmpval |= (pSequence_InitStruct->ChannelForSeq1) << ADC_SEQ_1_SEQ1_Pos;
480 tmpval |= (pSequence_InitStruct->ChannelForSeq2) << ADC_SEQ_1_SEQ2_Pos;
481 tmpval |= (pSequence_InitStruct->ChannelForSeq3) << ADC_SEQ_1_SEQ3_Pos;
482 tmpval |= (pSequence_InitStruct->ChannelForSeq4) << ADC_SEQ_1_SEQ4_Pos;
483 tmpval |= (pSequence_InitStruct->ChannelForSeq5) << ADC_SEQ_1_SEQ5_Pos;
484 tmpval |= (pSequence_InitStruct->ChannelForSeq6) << ADC_SEQ_1_SEQ6_Pos;
485 tmpval |= (pSequence_InitStruct->ChannelForSeq7) << ADC_SEQ_1_SEQ7_Pos;
486
487 MODIFY_REG(ADCx->SEQ_1, ADC_SEQ_1_SEQ_ALL, tmpval);
488
489 tmpval = 0;
490
491 tmpval |= (pSequence_InitStruct->ChannelForSeq8) << ADC_SEQ_2_SEQ8_Pos;
492 tmpval |= (pSequence_InitStruct->ChannelForSeq9) << ADC_SEQ_2_SEQ9_Pos;
493 tmpval |= (pSequence_InitStruct->ChannelForSeq10) << ADC_SEQ_2_SEQ10_Pos;
494 tmpval |= (pSequence_InitStruct->ChannelForSeq11) << ADC_SEQ_2_SEQ11_Pos;
495 tmpval |= (pSequence_InitStruct->ChannelForSeq12) << ADC_SEQ_2_SEQ12_Pos;
496 tmpval |= (pSequence_InitStruct->ChannelForSeq13) << ADC_SEQ_2_SEQ13_Pos;
497 tmpval |= (pSequence_InitStruct->ChannelForSeq14) << ADC_SEQ_2_SEQ14_Pos;
498 tmpval |= (pSequence_InitStruct->ChannelForSeq15) << ADC_SEQ_2_SEQ15_Pos;
499
500 MODIFY_REG(ADCx->SEQ_2, ADC_SEQ_2_SEQ_ALL, tmpval);
501
502 return (status);
503 }
504
505 /**
506 * @}
507 */
508
509 /**
510 * @}
511 */
512
513 /**
514 * @}
515 */
516
517 #endif /* ADC1 */
518
519 /**
520 * @}
521 */
522
523 #endif /* USE_FULL_LL_DRIVER */
524
