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Searched refs:IPCC_C1MR_CH1FM_Pos (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_ipcc.h291 CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_EnableTransmitChannel()
314 SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_DisableTransmitChannel()
337 …return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)… in LL_C1_IPCC_IsEnabledTransmitChannel()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_ipcc.h291 CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_EnableTransmitChannel()
314 SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_DisableTransmitChannel()
337 …return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)… in LL_C1_IPCC_IsEnabledTransmitChannel()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_ipcc.h291 CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_EnableTransmitChannel()
314 SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_DisableTransmitChannel()
337 …return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)… in LL_C1_IPCC_IsEnabledTransmitChannel()
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h9804 #define IPCC_C1MR_CH1FM_Pos (16U) macro
9805 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
10016 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32wb1mxx.h9826 #define IPCC_C1MR_CH1FM_Pos (16U) macro
9827 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
10038 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32wb30xx.h9800 #define IPCC_C1MR_CH1FM_Pos (16U) macro
9801 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
10012 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32wb35xx.h11247 #define IPCC_C1MR_CH1FM_Pos (16U) macro
11248 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
11459 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32wb55xx.h12152 #define IPCC_C1MR_CH1FM_Pos (16U) macro
12153 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
12364 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32wb5mxx.h12152 #define IPCC_C1MR_CH1FM_Pos (16U) macro
12153 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
12364 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h9654 #define IPCC_C1MR_CH1FM_Pos (16U) macro
9655 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
9866 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32wb15xx.h9826 #define IPCC_C1MR_CH1FM_Pos (16U) macro
9827 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
10038 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wl5mxx.h9794 #define IPCC_C1MR_CH1FM_Pos (16U) macro
9795 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
10006 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32wl54xx.h9794 #define IPCC_C1MR_CH1FM_Pos (16U) macro
9795 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
10006 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32wl55xx.h9794 #define IPCC_C1MR_CH1FM_Pos (16U) macro
9795 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
10006 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h21476 #define IPCC_C1MR_CH1FM_Pos (16U) macro
21477 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
21711 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp151fxx_cm4.h21639 #define IPCC_C1MR_CH1FM_Pos (16U) macro
21640 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
21874 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp151axx_ca7.h21476 #define IPCC_C1MR_CH1FM_Pos (16U) macro
21477 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
21711 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp151axx_cm4.h21442 #define IPCC_C1MR_CH1FM_Pos (16U) macro
21443 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
21677 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp151dxx_cm4.h21442 #define IPCC_C1MR_CH1FM_Pos (16U) macro
21443 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
21677 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp151cxx_ca7.h21673 #define IPCC_C1MR_CH1FM_Pos (16U) macro
21674 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
21908 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp151cxx_cm4.h21639 #define IPCC_C1MR_CH1FM_Pos (16U) macro
21640 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
21874 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp151fxx_ca7.h21673 #define IPCC_C1MR_CH1FM_Pos (16U) macro
21674 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
21908 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp153axx_ca7.h23027 #define IPCC_C1MR_CH1FM_Pos (16U) macro
23028 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
23262 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp153axx_cm4.h22993 #define IPCC_C1MR_CH1FM_Pos (16U) macro
22994 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
23228 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
Dstm32mp153cxx_ca7.h23224 #define IPCC_C1MR_CH1FM_Pos (16U) macro
23225 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
23459 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos

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