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Searched refs:IER2 (Results 1 – 25 of 33) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_gtzc.c1820 WRITE_REG(GTZC_TZIC1->IER2, 0U); in HAL_GTZC_TZIC_DisableIT()
1824 WRITE_REG(GTZC_TZIC2->IER2, 0U); in HAL_GTZC_TZIC_DisableIT()
1860 WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL); in HAL_GTZC_TZIC_EnableIT()
1864 WRITE_REG(GTZC_TZIC2->IER2, TZIC2_IER2_ALL); in HAL_GTZC_TZIC_EnableIT()
2052 ier_itsources = READ_REG(GTZC_TZIC1_S->IER2); in HAL_GTZC_IRQHandler()
2152 ier_itsources = READ_REG(GTZC_TZIC2_S->IER2); in HAL_GTZC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_ltdc.h808 #define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER2 |= (__INTERRU…
827 #define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER2 &= ~(__INTER…
846 #define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER2 & (__INTE…
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_gtzc.c1188 WRITE_REG(GTZC_TZIC->IER2, 0U); in HAL_GTZC_TZIC_DisableIT()
1226 WRITE_REG(GTZC_TZIC->IER2, TZIC1_IER2_ALL); in HAL_GTZC_TZIC_EnableIT()
1402 ier_itsources = READ_REG(GTZC_TZIC_S->IER2); in HAL_GTZC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_gtzc.c1231 WRITE_REG(GTZC_TZIC->IER2, 0U); in HAL_GTZC_TZIC_DisableIT()
1266 WRITE_REG(GTZC_TZIC->IER2, TZIC_IER2_ALL); in HAL_GTZC_TZIC_EnableIT()
1425 ier_itsources = READ_REG(GTZC_TZIC->IER2); in HAL_GTZC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_gtzc.c1540 WRITE_REG(GTZC_TZIC1->IER2, 0U); in HAL_GTZC_TZIC_DisableIT()
1578 WRITE_REG(GTZC_TZIC1->IER2, GTZC_CFGR2_MSK); in HAL_GTZC_TZIC_EnableIT()
1750 ier_itsources = READ_REG(GTZC_TZIC1_S->IER2); in HAL_GTZC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_ltdc.c729 uint32_t itsources = READ_REG(hltdc->Instance->IER2); in HAL_LTDC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h426 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32wba54xx.h443 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32wba5mxx.h443 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32wba55xx.h443 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h666 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32l562xx.h700 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h651 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32h562xx.h698 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32h533xx.h688 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32h573xx.h913 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32h563xx.h876 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h600 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32u535xx.h561 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32u575xx.h614 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32u585xx.h654 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32u595xx.h638 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32u5a5xx.h678 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32u5f7xx.h670 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member
Dstm32u599xx.h772 __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ member

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