Home
last modified time | relevance | path

Searched refs:IER1 (Results 1 – 25 of 37) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_gtzc.c565 WRITE_REG(GTZC_TZIC->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
572 register_address = (uint32_t)&(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_DisableIT()
593 WRITE_REG(GTZC_TZIC->IER1, TZIC_IER1_ALL_Msk); in HAL_GTZC_TZIC_EnableIT()
600 register_address = (uint32_t)&(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_EnableIT()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_gtzc.c1819 WRITE_REG(GTZC_TZIC1->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
1823 WRITE_REG(GTZC_TZIC2->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
1829 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1) in HAL_GTZC_TZIC_DisableIT()
1859 WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL); in HAL_GTZC_TZIC_EnableIT()
1863 WRITE_REG(GTZC_TZIC2->IER1, TZIC2_IER1_ALL); in HAL_GTZC_TZIC_EnableIT()
1869 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1) in HAL_GTZC_TZIC_EnableIT()
2028 ier_itsources = READ_REG(GTZC_TZIC1_S->IER1); in HAL_GTZC_IRQHandler()
2128 ier_itsources = READ_REG(GTZC_TZIC2_S->IER1); in HAL_GTZC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_gtzc.c1187 WRITE_REG(GTZC_TZIC->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
1195 register_address = (uint32_t) &(GTZC_TZIC->IER1) in HAL_GTZC_TZIC_DisableIT()
1225 WRITE_REG(GTZC_TZIC->IER1, TZIC1_IER1_ALL); in HAL_GTZC_TZIC_EnableIT()
1233 register_address = (uint32_t) &(GTZC_TZIC->IER1) in HAL_GTZC_TZIC_EnableIT()
1378 ier_itsources = READ_REG(GTZC_TZIC_S->IER1); in HAL_GTZC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_gtzc.c1230 WRITE_REG(GTZC_TZIC->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
1237 register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_DisableIT()
1265 WRITE_REG(GTZC_TZIC->IER1, TZIC_IER1_ALL); in HAL_GTZC_TZIC_EnableIT()
1272 register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_EnableIT()
1401 ier_itsources = READ_REG(GTZC_TZIC->IER1); in HAL_GTZC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_gtzc.c1539 WRITE_REG(GTZC_TZIC1->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
1547 register_address = (uint32_t) &(GTZC_TZIC1->IER1) in HAL_GTZC_TZIC_DisableIT()
1577 WRITE_REG(GTZC_TZIC1->IER1, GTZC_CFGR1_MSK); in HAL_GTZC_TZIC_EnableIT()
1585 register_address = (uint32_t) &(GTZC_TZIC1->IER1) in HAL_GTZC_TZIC_EnableIT()
1726 ier_itsources = READ_REG(GTZC_TZIC1_S->IER1); in HAL_GTZC_IRQHandler()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_dcmipp.h1697 #define __HAL_DCMIPP_CSI_DPHY_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->IER1 |= (__INTERR…
1715 #define __HAL_DCMIPP_CSI_DPHY_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->IER1 &= ~(__INTE…
1733 #define __HAL_DCMIPP_CSI_GET_DPHY_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->IER1 & (__FLAG__))
1769 #define __HAL_DCMIPP_CSI_GET_DPHY_IT_SOURCE(__HANDLE__, __INTERRUPT__)((((__HANDLE__)->IER1 & (__I…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_dcmipp.c2483 uint32_t ier1_flags = READ_REG(csi_instance->IER1); in HAL_DCMIPP_CSI_IRQHandler()
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wl5mxx.h505 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32wl54xx.h505 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32wl55xx.h505 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h425 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32wba54xx.h442 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32wba5mxx.h442 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32wba55xx.h442 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h665 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32l562xx.h699 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h650 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32h562xx.h697 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32h533xx.h687 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32h573xx.h912 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32h563xx.h875 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h599 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32u535xx.h560 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32u575xx.h613 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member
Dstm32u585xx.h653 __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ member

12