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Searched refs:ICACHE_CRRx_RSIZE_Pos (Results 1 – 25 of 36) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_icache.c211 WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
212 WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
213 WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
214 WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
595 value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ in HAL_ICACHE_EnableRemapRegion()
Dstm32u5xx_ll_icache.c116 …value |= (pICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | pICACHE_RegionStruct->TrafficRout… in LL_ICACHE_ConfigRegion()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_icache.c211 WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
212 WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
213 WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
214 WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
595 value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ in HAL_ICACHE_EnableRemapRegion()
Dstm32l5xx_ll_icache.c116 …value |= (pICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | pICACHE_RegionStruct->TrafficRout… in LL_ICACHE_ConfigRegion()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_icache.c211 WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
212 WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
213 WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
214 WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
595 value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ in HAL_ICACHE_EnableRemapRegion()
Dstm32wbaxx_ll_icache.c116 …value |= (pICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | pICACHE_RegionStruct->TrafficRout… in LL_ICACHE_ConfigRegion()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_icache.c214 WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
215 WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
216 WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
217 WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); in HAL_ICACHE_DeInit()
600 value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ in HAL_ICACHE_EnableRemapRegion()
Dstm32h5xx_ll_icache.c119 …value |= (pICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | pICACHE_RegionStruct->TrafficRout… in LL_ICACHE_ConfigRegion()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_icache.h653 ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); in LL_ICACHE_SetRegionSize()
676 ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); in LL_ICACHE_GetRegionSize()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_icache.h648 ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); in LL_ICACHE_SetRegionSize()
671 ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); in LL_ICACHE_GetRegionSize()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_icache.h648 ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); in LL_ICACHE_SetRegionSize()
671 ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); in LL_ICACHE_GetRegionSize()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_icache.h648 ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); in LL_ICACHE_SetRegionSize()
671 ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); in LL_ICACHE_GetRegionSize()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h4560 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
4561 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
4563 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
4564 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
4565 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
Dstm32wba52xx.h8161 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
8162 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
8164 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
8165 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
8166 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
Dstm32wba54xx.h8395 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
8396 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
8398 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
8399 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
8400 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
Dstm32wba5mxx.h8395 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
8396 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
8398 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
8399 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
8400 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
Dstm32wba55xx.h8395 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
8396 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
8398 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
8399 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
8400 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h9176 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
9177 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */
9179 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */
9180 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */
9181 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */
Dstm32l562xx.h9508 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
9509 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */
9511 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */
9512 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */
9513 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h8891 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
8892 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
8894 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
8895 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
8896 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
Dstm32h562xx.h9617 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
9618 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
9620 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
9621 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
9622 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
Dstm32h533xx.h9300 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
9301 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
9303 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
9304 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
9305 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h9597 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
9598 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
9600 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
9601 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
9602 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
Dstm32u535xx.h9197 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
9198 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
9200 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
9201 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
9202 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…
Dstm32u575xx.h10219 #define ICACHE_CRRx_RSIZE_Pos (9U) macro
10220 #define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00…
10222 #define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200…
10223 #define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400…
10224 #define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800…

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