1 /** 2 ********************************************************************************************************************** 3 * @file stm32h7rsxx_hal_dma_ex.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL extension module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32H7RSxx_HAL_DMA_EX_H 21 #define STM32H7RSxx_HAL_DMA_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32h7rsxx_hal_def.h" 29 30 /** @addtogroup STM32H7RSxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMAEx 35 * @{ 36 */ 37 38 /* Exported types ----------------------------------------------------------------------------------------------------*/ 39 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types 40 * @brief DMAEx Exported types 41 * @{ 42 */ 43 44 /** 45 * @brief DMAEx Data Handling Configuration Structure Definition. 46 */ 47 typedef struct 48 { 49 uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. 50 This parameter can be a value of @ref DMAEx_Data_Exchange */ 51 52 uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode 53 This parameter can be a value of @ref DMAEx_Data_Alignment */ 54 55 } DMA_DataHandlingConfTypeDef; 56 57 /** 58 * @brief DMAEx Trigger Configuration Structure Definition. 59 */ 60 typedef struct 61 { 62 uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. 63 This parameter can be a value of @ref DMAEx_Trigger_Mode */ 64 65 uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. 66 This parameter can be a value of @ref DMAEx_Trigger_Polarity */ 67 68 uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. 69 This parameter can be a value of @ref DMAEx_Trigger_Selection */ 70 71 } DMA_TriggerConfTypeDef; 72 73 /** 74 * @brief DMAEx Repeated Block Configuration Structure Definition. 75 */ 76 typedef struct 77 { 78 uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block). 79 This parameter can be a value between 1 and 2048 */ 80 81 int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset : 82 This parameter can be a value between -8191 and 8191. 83 * If source address offset > 0 => Increment the source address by offset from where 84 the last single/burst transfer ends. 85 * If source address offset < 0 => Decrement the source address by offset from where 86 the last single/burst transfer ends. 87 * If source address offset == 0 => The next single/burst source address starts from 88 where the last transfer ends */ 89 90 int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value : 91 This parameter can be a value between -8191 and 8191. 92 * If destination address offset > 0 => Increment the destination address by offset 93 from where the last single/burst transfer ends. 94 * If destination address offset < 0 => Decrement the destination address by offset 95 from where the last single/burst transfer ends. 96 * If destination address offset == 0 => The next single/burst destination address 97 starts from where the last transfer ends. */ 98 99 int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value : 100 This parameter can be a value between -65535 and 65535. 101 * If block source address offset > 0 => Increment the block source address by offset 102 from where the last block ends. 103 * If block source address offset < 0 => Decrement the next block source address by 104 offset from where the last block ends. 105 * If block source address offset == 0 => the next block source address starts from 106 where the last block ends */ 107 108 int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value : 109 This parameter can be a value between -65535 and 65535. 110 * If block destination address offset > 0 => Increment the block destination address 111 by offset from where the last block ends. 112 * If block destination address offset < 0 => Decrement the next block destination 113 address by offset from where the last block ends. 114 * If block destination address offset == 0 => the next block destination address 115 starts from where the last block ends */ 116 117 } DMA_RepeatBlockConfTypeDef; 118 119 /** 120 * @brief DMAEx Queue State Enumeration Definition. 121 */ 122 typedef enum 123 { 124 HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ 125 HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ 126 HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ 127 128 } HAL_DMA_QStateTypeDef; 129 130 /** 131 * @brief DMAEx Linked-List Node Configuration Structure Definition. 132 */ 133 typedef struct 134 { 135 uint32_t NodeType; /*!< Specifies the DMA channel node type. 136 This parameter can be a value of @ref DMAEx_Node_Type */ 137 138 DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ 139 140 DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ 141 142 DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ 143 144 DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */ 145 146 uint32_t SrcAddress; /*!< Specifies the source memory address */ 147 uint32_t DstAddress; /*!< Specifies the destination memory address */ 148 uint32_t DataSize; /*!< Specifies the source data size in bytes */ 149 150 } DMA_NodeConfTypeDef; 151 152 /** 153 * @brief DMAEx Linked-List Node Structure Definition. 154 */ 155 typedef struct 156 { 157 uint32_t LinkRegisters[8U]; /*!< Physical Node register description */ 158 uint32_t NodeInfo; /*!< Node information */ 159 160 } DMA_NodeTypeDef; 161 162 /** 163 * @brief DMAEx Linked-List Queue Structure Definition. 164 */ 165 typedef struct __DMA_QListTypeDef 166 { 167 DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ 168 169 DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ 170 171 uint32_t NodeNumber; /*!< Specifies the queue node number */ 172 173 __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ 174 175 __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ 176 177 __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ 178 179 } DMA_QListTypeDef; 180 /** 181 * @} 182 */ 183 184 /* Exported constants ------------------------------------------------------------------------------------------------*/ 185 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants 186 * @brief DMAEx Exported Constants 187 * @{ 188 */ 189 190 /** @defgroup Queue_Error_Codes Queue Error Codes 191 * @brief Queue Error Codes 192 * @{ 193 */ 194 #define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ 195 #define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ 196 #define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ 197 #define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ 198 #define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization 199 and queue circular types are incompatible */ 200 #define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ 201 #define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ 202 /** 203 * @} 204 */ 205 206 /** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode 207 * @brief DMAEx LinkedList Mode 208 * @{ 209 */ 210 #define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ 211 #define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ 212 /** 213 * @} 214 */ 215 216 /** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment 217 * @brief DMAEx Data Alignment 218 * @{ 219 */ 220 #define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width 221 => Right aligned padded with 0 up to destination data 222 width */ 223 #define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width 224 => Right aligned left Truncated down to destination 225 data width */ 226 #define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width 227 => Right Aligned padded with sign extended up to 228 destination data width */ 229 #define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width 230 => Left Aligned Right Truncated down to the 231 destination data width */ 232 #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width 233 => Packed at the destination data width */ 234 #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width 235 => Unpacked at the destination data width */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange 241 * @brief DMAEx Data Exchange 242 * @{ 243 */ 244 #define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ 245 #define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ 246 #define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ 247 #define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ 248 #define DMA_EXCHANGE_DEST_WORD DMA_CTR1_DWX /*!< Destination Word exchange when destination data width is > Word */ 249 /** 250 * @} 251 */ 252 253 /** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity 254 * @brief DMAEx Trigger Polarity 255 * @{ 256 */ 257 #define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ 258 #define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ 259 #define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode 265 * @brief DMAEx Trigger Mode 266 * @{ 267 */ 268 #define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ 269 #define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */ 270 #define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ 271 #define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ 272 /** 273 * @} 274 */ 275 276 /** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection 277 * @brief DMAEx Trigger Selection 278 * @{ 279 */ 280 /* HPDMA1 triggers */ 281 #define HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_FRAMEEND */ 282 #define HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_HSYNC */ 283 #define HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_LINEEND */ 284 #define HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_VSYNC */ 285 #define HPDMA1_TRIGGER_DMA2D_CTC_FLAG 4U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC_FLAG */ 286 #define HPDMA1_TRIGGER_DMA2D_TC_FLAG 5U /*!< HPDMA1 HW Trigger signal is DMA2D_TC_FLAG */ 287 #define HPDMA1_TRIGGER_DMA2D_TW_FLAG 6U /*!< HPDMA1 HW Trigger signal is DMA2D_TW_FLAG */ 288 #define HPDMA1_TRIGGER_JPEG_EOC_FLAG 7U /*!< HPDMA1 HW Trigger signal is JPEG_EOC_FLAG */ 289 #define HPDMA1_TRIGGER_JPEG_IFNF_FLAG 8U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF_FLAG */ 290 #define HPDMA1_TRIGGER_JPEG_IFT_FLAG 9U /*!< HPDMA1 HW Trigger signal is JPEG_IFT_FLAG */ 291 #define HPDMA1_TRIGGER_JPEG_OFNE_FLAG 10U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE_FLAG */ 292 #define HPDMA1_TRIGGER_JPEG_OFT_FLAG 11U /*!< HPDMA1 HW Trigger signal is JPEG_OFT_FLAG */ 293 #define HPDMA1_TRIGGER_LCD 12U /*!< HPDMA1 HW Trigger signal is LCD */ 294 #define HPDMA1_TRIGGER_GPU2D1_GP_FLAG0 13U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG0 */ 295 #define HPDMA1_TRIGGER_GPU2D1_GP_FLAG1 14U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG1 */ 296 #define HPDMA1_TRIGGER_GPU2D1_GP_FLAG2 15U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG2 */ 297 #define HPDMA1_TRIGGER_GPU2D1_GP_FLAG3 16U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG3 */ 298 #define HPDMA1_TRIGGER_GFXTIM_0_EVT_4 17U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_4 */ 299 #define HPDMA1_TRIGGER_GFXTIM_0_EVT_3 18U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_3 */ 300 #define HPDMA1_TRIGGER_GFXTIM_0_EVT_2 19U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_2 */ 301 #define HPDMA1_TRIGGER_GFXTIM_0_EVT_1 20U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_1 */ 302 #define HPDMA1_TRIGGER_GPDMA1_CH0_TCF 21U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ 303 #define HPDMA1_TRIGGER_GPDMA1_CH1_TCF 22U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ 304 #define HPDMA1_TRIGGER_GPDMA1_CH2_TCF 23U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ 305 #define HPDMA1_TRIGGER_GPDMA1_CH3_TCF 24U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ 306 #define HPDMA1_TRIGGER_GPDMA1_CH4_TCF 25U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ 307 #define HPDMA1_TRIGGER_GPDMA1_CH5_TCF 26U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ 308 #define HPDMA1_TRIGGER_GPDMA1_CH6_TCF 27U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ 309 #define HPDMA1_TRIGGER_GPDMA1_CH7_TCF 28U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ 310 #define HPDMA1_TRIGGER_GPDMA1_CH8_TCF 29U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ 311 #define HPDMA1_TRIGGER_GPDMA1_CH9_TCF 30U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ 312 #define HPDMA1_TRIGGER_GPDMA1_CH10_TCF 31U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ 313 #define HPDMA1_TRIGGER_GPDMA1_CH11_TCF 32U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ 314 #define HPDMA1_TRIGGER_GPDMA1_CH12_TCF 33U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ 315 #define HPDMA1_TRIGGER_GPDMA1_CH13_TCF 34U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ 316 #define HPDMA1_TRIGGER_GPDMA1_CH14_TCF 35U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ 317 #define HPDMA1_TRIGGER_GPDMA1_CH15_TCF 36U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ 318 #define HPDMA1_TRIGGER_HPDMA1_CH0_TCF 37U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ 319 #define HPDMA1_TRIGGER_HPDMA1_CH1_TCF 38U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ 320 #define HPDMA1_TRIGGER_HPDMA1_CH2_TCF 39U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ 321 #define HPDMA1_TRIGGER_HPDMA1_CH3_TCF 40U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ 322 #define HPDMA1_TRIGGER_HPDMA1_CH4_TCF 41U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ 323 #define HPDMA1_TRIGGER_HPDMA1_CH5_TCF 42U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ 324 #define HPDMA1_TRIGGER_HPDMA1_CH6_TCF 43U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ 325 #define HPDMA1_TRIGGER_HPDMA1_CH7_TCF 44U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ 326 #define HPDMA1_TRIGGER_HPDMA1_CH8_TCF 45U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ 327 #define HPDMA1_TRIGGER_HPDMA1_CH9_TCF 46U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ 328 #define HPDMA1_TRIGGER_HPDMA1_CH10_TCF 47U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ 329 #define HPDMA1_TRIGGER_HPDMA1_CH11_TCF 48U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ 330 #define HPDMA1_TRIGGER_HPDMA1_CH12_TCF 49U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ 331 #define HPDMA1_TRIGGER_HPDMA1_CH13_TCF 50U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ 332 #define HPDMA1_TRIGGER_HPDMA1_CH14_TCF 51U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ 333 #define HPDMA1_TRIGGER_HPDMA1_CH15_TCF 52U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ 334 335 /* GPDMA1 triggers */ 336 #define GPDMA1_TRIGGER_HPDMA1_CH0_TCF 0U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ 337 #define GPDMA1_TRIGGER_HPDMA1_CH1_TCF 1U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ 338 #define GPDMA1_TRIGGER_HPDMA1_CH2_TCF 2U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ 339 #define GPDMA1_TRIGGER_HPDMA1_CH3_TCF 3U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ 340 #define GPDMA1_TRIGGER_HPDMA1_CH4_TCF 4U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ 341 #define GPDMA1_TRIGGER_HPDMA1_CH5_TCF 5U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ 342 #define GPDMA1_TRIGGER_HPDMA1_CH6_TCF 6U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ 343 #define GPDMA1_TRIGGER_HPDMA1_CH7_TCF 7U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ 344 #define GPDMA1_TRIGGER_HPDMA1_CH8_TCF 8U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ 345 #define GPDMA1_TRIGGER_HPDMA1_CH9_TCF 9U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ 346 #define GPDMA1_TRIGGER_HPDMA1_CH10_TCF 10U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ 347 #define GPDMA1_TRIGGER_HPDMA1_CH11_TCF 11U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ 348 #define GPDMA1_TRIGGER_HPDMA1_CH12_TCF 12U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ 349 #define GPDMA1_TRIGGER_HPDMA1_CH13_TCF 13U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ 350 #define GPDMA1_TRIGGER_HPDMA1_CH14_TCF 14U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ 351 #define GPDMA1_TRIGGER_HPDMA1_CH15_TCF 15U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ 352 #define GPDMA1_TRIGGER_LPTIM1_CH1 16U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ 353 #define GPDMA1_TRIGGER_LPTIM1_CH2 17U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ 354 #define GPDMA1_TRIGGER_LPTIM2_CH1 18U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ 355 #define GPDMA1_TRIGGER_LPTIM2_CH2 19U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ 356 #define GPDMA1_TRIGGER_LPTIM3_CH1 20U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */ 357 #define GPDMA1_TRIGGER_LPTIM3_CH2 21U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */ 358 #define GPDMA1_TRIGGER_LPTIM4_OUT 22U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ 359 #define GPDMA1_TRIGGER_LPTIM5_OUT 23U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */ 360 #define GPDMA1_TRIGGER_EXTIT0_SYNC 24U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */ 361 #define GPDMA1_TRIGGER_RTC_WKUP 25U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */ 362 #define GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 26U /*!< GPDMA1 HW Trigger signal is R_WUP_ASYNC */ 363 #define GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 27U /*!< GPDMA1 HW Trigger signal is T_WUP_ASYNC */ 364 #define GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 28U /*!< GPDMA1 HW Trigger signal is SPI6_OR_SPI6_AIT_SYNC */ 365 #define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ 366 #define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ 367 #define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ 368 #define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ 369 #define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ 370 #define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ 371 #define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ 372 #define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ 373 #define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ 374 #define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 38U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ 375 #define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 39U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ 376 #define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 40U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ 377 #define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 41U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ 378 #define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 42U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ 379 #define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 43U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ 380 #define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 44U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ 381 #define GPDMA1_TRIGGER_TIM1_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */ 382 #define GPDMA1_TRIGGER_TIM1_TRGO2 46U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */ 383 #define GPDMA1_TRIGGER_TIM2_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ 384 #define GPDMA1_TRIGGER_TIM3_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ 385 #define GPDMA1_TRIGGER_TIM4_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ 386 #define GPDMA1_TRIGGER_TIM5_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ 387 #define GPDMA1_TRIGGER_TIM6_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */ 388 #define GPDMA1_TRIGGER_TIM7_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */ 389 #define GPDMA1_TRIGGER_TIM9_TRGO 53U /*!< GPDMA1 HW Trigger signal is TIM9_TRGO */ 390 #define GPDMA1_TRIGGER_TIM12_TRGO 54U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */ 391 #define GPDMA1_TRIGGER_TIM15_TRGO 55U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ 392 393 #define GPDMA1_MAX_TRIGGER 55U 394 /** 395 * @} 396 */ 397 398 /** @defgroup DMAEx_Node_Type DMAEx Node Type 399 * @brief DMAEx Node Type 400 * @{ 401 */ 402 #define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ 403 #define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */ 404 #define DMA_HPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the HPDMA linear addressing node type */ 405 #define DMA_HPDMA_2D_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the HPDMA 2 dimension addressing node type */ 406 /** 407 * @} 408 */ 409 410 /** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port 411 * @brief DMAEx Linked-List Allocated Port 412 * @{ 413 */ 414 #define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ 415 #define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ 416 /** 417 * @} 418 */ 419 420 /** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode 421 * @brief DMAEx Link Step Mode 422 * @{ 423 */ 424 #define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ 425 #define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ 426 /** 427 * @} 428 */ 429 430 /** 431 * @} 432 */ 433 434 /* Exported functions ------------------------------------------------------------------------------------------------*/ 435 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions 436 * @brief DMAEx Exported functions 437 * @{ 438 */ 439 440 /** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions 441 * @brief Linked-List Initialization and De-Initialization Functions 442 * @{ 443 */ 444 HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); 445 HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); 446 /** 447 * @} 448 */ 449 450 /** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions 451 * @brief Linked-List IO Operation Functions 452 * @{ 453 */ 454 HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); 455 HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); 456 /** 457 * @} 458 */ 459 460 /** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions 461 * @brief Linked-List Management Functions 462 * @{ 463 */ 464 HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, 465 DMA_NodeTypeDef *const pNode); 466 HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, 467 DMA_NodeTypeDef const *const pNode); 468 469 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, 470 DMA_NodeTypeDef *const pPrevNode, 471 DMA_NodeTypeDef *const pNewNode); 472 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, 473 DMA_NodeTypeDef *const pNewNode); 474 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, 475 DMA_NodeTypeDef *const pNewNode); 476 477 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, 478 DMA_NodeTypeDef *const pNode); 479 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); 480 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); 481 482 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, 483 DMA_NodeTypeDef *const pOldNode, 484 DMA_NodeTypeDef *const pNewNode); 485 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, 486 DMA_NodeTypeDef *const pNewNode); 487 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, 488 DMA_NodeTypeDef *const pNewNode); 489 490 HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); 491 492 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, 493 DMA_NodeTypeDef const *const pPrevNode, 494 DMA_QListTypeDef *const pDestQList); 495 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, 496 DMA_QListTypeDef *const pDestQList); 497 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, 498 DMA_QListTypeDef *const pDestQList); 499 500 HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, 501 DMA_NodeTypeDef *const pFirstCircularNode); 502 HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); 503 HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); 504 505 HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); 506 HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); 507 508 HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, 509 DMA_QListTypeDef *const pQList); 510 HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); 511 /** 512 * @} 513 */ 514 515 /** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions 516 * @brief Data Handling, Repeated Block and Trigger Configuration Functions 517 * @{ 518 */ 519 HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, 520 DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); 521 HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, 522 DMA_TriggerConfTypeDef const *const pConfigTrigger); 523 HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, 524 DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock); 525 /** 526 * @} 527 */ 528 529 /** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions 530 * @brief Suspend and Resume Operation Functions 531 * @{ 532 */ 533 HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); 534 HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); 535 HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); 536 /** 537 * @} 538 */ 539 540 /** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function 541 * @brief FIFO Status Function 542 * @{ 543 */ 544 uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); 545 /** 546 * @} 547 */ 548 549 /** 550 * @} 551 */ 552 553 /* Private types -----------------------------------------------------------------------------------------------------*/ 554 /** @defgroup DMAEx_Private_Types DMAEx Private Types 555 * @brief DMAEx Private Types 556 * @{ 557 */ 558 559 /** 560 * @brief DMA Node in Queue Information Structure Definition. 561 */ 562 typedef struct 563 { 564 uint32_t cllr_offset; /* CLLR register offset */ 565 566 uint32_t previousnode_addr; /* Previous node address */ 567 568 uint32_t currentnode_pos; /* Current node position */ 569 570 uint32_t currentnode_addr; /* Current node address */ 571 572 uint32_t nextnode_addr; /* Next node address */ 573 574 } DMA_NodeInQInfoTypeDef; 575 /** 576 * @} 577 */ 578 579 /* Private constants -------------------------------------------------------------------------------------------------*/ 580 /** @defgroup DMAEx_Private_Constants DMAEx Private Constants 581 * @brief DMAEx Private Constants 582 * @{ 583 */ 584 #define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ 585 586 #define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ 587 #define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ 588 #define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ 589 #define DMA_CHANNEL_TYPE_HPDMA (0x0040U) /* HPDMA channel node */ 590 591 #define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ 592 #define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ 593 #define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ 594 595 #define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ 596 597 #define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ 598 #define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ 599 600 #define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ 601 #define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ 602 603 #define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ 604 #define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ 605 606 #define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ 607 #define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ 608 609 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ 610 #define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ 611 #define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ 612 #define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ 613 #define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ 614 #define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ 615 #define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ 616 #define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */ 617 #define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ 618 619 #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ 620 #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ 621 #define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ 622 #define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ 623 /** 624 * @} 625 */ 626 627 /* Private macros ----------------------------------------------------------------------------------------------------*/ 628 /** @defgroup DMAEx_Private_Macros DMAEx Private Macros 629 * @brief DMAEx Private Macros 630 * @{ 631 */ 632 #define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ 633 (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ 634 ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ 635 ((ALIGNMENT) == DMA_DATA_PACK)) 636 637 #define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ 638 (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD | \ 639 DMA_EXCHANGE_DEST_WORD))) == 0U) 640 641 #define IS_DMA_REPEAT_COUNT(COUNT) \ 642 (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) 643 644 #define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ 645 (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ 646 ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) 647 648 #define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ 649 (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ 650 ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) 651 652 #define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ 653 (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) 654 655 #define IS_DMA_LINK_STEP_MODE(MODE) \ 656 (((MODE) == DMA_LSM_FULL_EXECUTION) || \ 657 ((MODE) == DMA_LSM_1LINK_EXECUTION)) 658 659 #define IS_DMA_TRIGGER_MODE(MODE) \ 660 (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ 661 ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \ 662 ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ 663 ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) 664 665 #define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ 666 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 667 ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ 668 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 669 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 670 671 #define IS_DMA_LINKEDLIST_MODE(MODE) \ 672 (((MODE) == DMA_LINKEDLIST_NORMAL) || \ 673 ((MODE) == DMA_LINKEDLIST_CIRCULAR)) 674 675 #define IS_DMA_TRIGGER_POLARITY(POLARITY) \ 676 (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ 677 ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ 678 ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) 679 680 #define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ 681 ((TRIGGER) <= GPDMA1_TRIGGER_TIM15_TRGO) 682 683 #define IS_DMA_NODE_TYPE(TYPE) \ 684 (((TYPE) == DMA_GPDMA_LINEAR_NODE) || \ 685 ((TYPE) == DMA_GPDMA_2D_NODE) || \ 686 ((TYPE) == DMA_HPDMA_LINEAR_NODE) || \ 687 ((TYPE) == DMA_HPDMA_2D_NODE)) 688 /** 689 * @} 690 */ 691 692 693 /* Private functions -------------------------------------------------------------------------------------------------*/ 694 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions 695 * @brief DMAEx Private Functions 696 * @{ 697 */ 698 699 /** 700 * @} 701 */ 702 703 /** 704 * @} 705 */ 706 707 /** 708 * @} 709 */ 710 711 /** 712 * @} 713 */ 714 715 #ifdef __cplusplus 716 } 717 #endif /* __cplusplus */ 718 719 #endif /* STM32H7RSxx_HAL_DMA_EX_H */ 720
