1 /** 2 ********************************************************************************************************************** 3 * @file stm32n6xx_hal_dma_ex.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL extension module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32N6xx_HAL_DMA_EX_H 21 #define STM32N6xx_HAL_DMA_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMAEx 35 * @{ 36 */ 37 38 /* Exported types ----------------------------------------------------------------------------------------------------*/ 39 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types 40 * @brief DMAEx Exported types 41 * @{ 42 */ 43 44 /** 45 * @brief DMAEx Data Handling Configuration Structure Definition. 46 */ 47 typedef struct 48 { 49 uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. 50 This parameter can be a value of @ref DMAEx_Data_Exchange */ 51 52 uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode 53 This parameter can be a value of @ref DMAEx_Data_Alignment */ 54 55 } DMA_DataHandlingConfTypeDef; 56 57 /** 58 * @brief DMAEx Trigger Configuration Structure Definition. 59 */ 60 typedef struct 61 { 62 uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. 63 This parameter can be a value of @ref DMAEx_Trigger_Mode */ 64 65 uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. 66 This parameter can be a value of @ref DMAEx_Trigger_Polarity */ 67 68 uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. 69 This parameter can be a value of @ref DMAEx_Trigger_Selection */ 70 71 } DMA_TriggerConfTypeDef; 72 73 /** 74 * @brief DMAEx Repeated Block Configuration Structure Definition. 75 */ 76 typedef struct 77 { 78 uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block). 79 This parameter can be a value between 1 and 2048 */ 80 81 int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset : 82 This parameter can be a value between -8191 and 8191. 83 * If source address offset > 0 => Increment the source address by offset from where 84 the last single/burst transfer ends. 85 * If source address offset < 0 => Decrement the source address by offset from where 86 the last single/burst transfer ends. 87 * If source address offset == 0 => The next single/burst source address starts from 88 where the last transfer ends */ 89 90 int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value : 91 This parameter can be a value between -8191 and 8191. 92 * If destination address offset > 0 => Increment the destination address by offset 93 from where the last single/burst transfer ends. 94 * If destination address offset < 0 => Decrement the destination address by offset 95 from where the last single/burst transfer ends. 96 * If destination address offset == 0 => The next single/burst destination address 97 starts from where the last transfer ends. */ 98 99 int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value : 100 This parameter can be a value between -65535 and 65535. 101 * If block source address offset > 0 => Increment the block source address by offset 102 from where the last block ends. 103 * If block source address offset < 0 => Decrement the next block source address by 104 offset from where the last block ends. 105 * If block source address offset == 0 => the next block source address starts from 106 where the last block ends */ 107 108 int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value : 109 This parameter can be a value between -65535 and 65535. 110 * If block destination address offset > 0 => Increment the block destination address 111 by offset from where the last block ends. 112 * If block destination address offset < 0 => Decrement the next block destination 113 address by offset from where the last block ends. 114 * If block destination address offset == 0 => the next block destination address 115 starts from where the last block ends */ 116 117 } DMA_RepeatBlockConfTypeDef; 118 119 /** 120 * @brief DMAEx Queue State Enumeration Definition. 121 */ 122 typedef enum 123 { 124 HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ 125 HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ 126 HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ 127 128 } HAL_DMA_QStateTypeDef; 129 130 /** 131 * @brief DMAEx Linked-List Node Configuration Structure Definition. 132 */ 133 typedef struct 134 { 135 uint32_t NodeType; /*!< Specifies the DMA channel node type. 136 This parameter can be a value of @ref DMAEx_Node_Type */ 137 138 DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ 139 140 DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ 141 142 DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ 143 144 DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */ 145 146 uint32_t SrcAddress; /*!< Specifies the source memory address */ 147 uint32_t DstAddress; /*!< Specifies the destination memory address */ 148 uint32_t DataSize; /*!< Specifies the source data size in bytes */ 149 150 #if defined (CPU_IN_SECURE_STATE) 151 uint32_t SrcSecure; /*!< Specifies the source security attribute */ 152 uint32_t DestSecure; /*!< Specifies the destination security attribute */ 153 #endif /* CPU_IN_SECURE_STATE */ 154 155 } DMA_NodeConfTypeDef; 156 157 /** 158 * @brief DMAEx Linked-List Node Structure Definition. 159 */ 160 typedef struct 161 { 162 uint32_t LinkRegisters[8U]; /*!< Physical Node register description */ 163 uint32_t NodeInfo; /*!< Node information */ 164 165 } DMA_NodeTypeDef; 166 167 /** 168 * @brief DMAEx Linked-List Queue Structure Definition. 169 */ 170 typedef struct __DMA_QListTypeDef 171 { 172 DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ 173 174 DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ 175 176 uint32_t NodeNumber; /*!< Specifies the queue node number */ 177 178 __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ 179 180 __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ 181 182 __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ 183 184 } DMA_QListTypeDef; 185 /** 186 * @} 187 */ 188 189 /* Exported constants ------------------------------------------------------------------------------------------------*/ 190 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants 191 * @brief DMAEx Exported Constants 192 * @{ 193 */ 194 195 /** @defgroup Queue_Error_Codes Queue Error Codes 196 * @brief Queue Error Codes 197 * @{ 198 */ 199 #define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ 200 #define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ 201 #define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ 202 #define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ 203 #define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization 204 and queue circular types are incompatible */ 205 #define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ 206 #define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ 207 /** 208 * @} 209 */ 210 211 /** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode 212 * @brief DMAEx LinkedList Mode 213 * @{ 214 */ 215 #define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ 216 #define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ 217 /** 218 * @} 219 */ 220 221 /** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment 222 * @brief DMAEx Data Alignment 223 * @{ 224 */ 225 #define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width 226 => Right aligned padded with 0 up to destination data 227 width */ 228 #define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width 229 => Right aligned left Truncated down to destination 230 data width */ 231 #define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width 232 => Right Aligned padded with sign extended up to 233 destination data width */ 234 #define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width 235 => Left Aligned Right Truncated down to the 236 destination data width */ 237 #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width 238 => Packed at the destination data width */ 239 #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width 240 => Unpacked at the destination data width */ 241 /** 242 * @} 243 */ 244 245 /** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange 246 * @brief DMAEx Data Exchange 247 * @{ 248 */ 249 #define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ 250 #define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ 251 #define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ 252 #define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ 253 #define DMA_EXCHANGE_DEST_WORD DMA_CTR1_DWX /*!< Destination Word exchange when destination data width is > Word */ 254 /** 255 * @} 256 */ 257 258 /** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity 259 * @brief DMAEx Trigger Polarity 260 * @{ 261 */ 262 #define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ 263 #define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ 264 #define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode 270 * @brief DMAEx Trigger Mode 271 * @{ 272 */ 273 #define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ 274 #define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */ 275 #define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ 276 #define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ 277 /** 278 * @} 279 */ 280 281 /** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection 282 * @brief DMAEx Trigger Selection 283 * @{ 284 */ 285 /* HPDMA1 triggers */ 286 #define HPDMA1_TRIGGER_DCMIPP_P0_FEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_FEND */ 287 #define HPDMA1_TRIGGER_DCMIPP_P0_LEND 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_LEND */ 288 #define HPDMA1_TRIGGER_DCMIPP_P0_HSYNC 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC */ 289 #define HPDMA1_TRIGGER_DCMIPP_P0_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC */ 290 291 #define HPDMA1_TRIGGER_DCMIPP_P1_FEND 4U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_FEND */ 292 #define HPDMA1_TRIGGER_DCMIPP_P1_LEND 5U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_LEND */ 293 #define HPDMA1_TRIGGER_DCMIPP_P1_HSYNC 6U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC */ 294 #define HPDMA1_TRIGGER_DCMIPP_P1_VSYNC 7U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC */ 295 296 #define HPDMA1_TRIGGER_DCMIPP_P2_FEND 8U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_FEND */ 297 #define HPDMA1_TRIGGER_DCMIPP_P2_LEND 9U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_LEND */ 298 #define HPDMA1_TRIGGER_DCMIPP_P2_HSYNC 10U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC */ 299 #define HPDMA1_TRIGGER_DCMIPP_P2_VSYNC 11U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC */ 300 301 #define HPDMA1_TRIGGER_DMA2D_CTC 12U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC */ 302 #define HPDMA1_TRIGGER_DMA2D_TC 13U /*!< HPDMA1 HW Trigger signal is DMA2D_TC */ 303 #define HPDMA1_TRIGGER_DMA2D_TW 14U /*!< HPDMA1 HW Trigger signal is DMA2D_TW */ 304 305 #define HPDMA1_TRIGGER_JPEG_EOC 15U /*!< HPDMA1 HW Trigger signal is JPEG_EOC */ 306 #define HPDMA1_TRIGGER_JPEG_IFNF 16U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF */ 307 #define HPDMA1_TRIGGER_JPEG_IFT 17U /*!< HPDMA1 HW Trigger signal is JPEG_IFT */ 308 #define HPDMA1_TRIGGER_JPEG_OFNE 18U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE */ 309 #define HPDMA1_TRIGGER_JPEG_OFT 19U /*!< HPDMA1 HW Trigger signal is JPEG_OFT */ 310 311 #define HPDMA1_LCD_LI 20U /*!< HPDMA1 HW Trigger signal is LCD_LI */ 312 313 #define HPDMA1_TRIGGER_GPU2D1_GP_0 21U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_0 */ 314 #define HPDMA1_TRIGGER_GPU2D1_GP_1 22U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_1 */ 315 #define HPDMA1_TRIGGER_GPU2D1_GP_2 23U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_2 */ 316 #define HPDMA1_TRIGGER_GPU2D1_GP_3 24U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_3 */ 317 318 #define HPDMA1_TRIGGER_GFXTIM_3 25U /*!< HPDMA1 HW Trigger signal is GFXTIM_3 */ 319 #define HPDMA1_TRIGGER_GFXTIM_2 26U /*!< HPDMA1 HW Trigger signal is GFXTIM_2 */ 320 #define HPDMA1_TRIGGER_GFXTIM_1 27U /*!< HPDMA1 HW Trigger signal is GFXTIM_1 */ 321 #define HPDMA1_TRIGGER_GFXTIM_0 28U /*!< HPDMA1 HW Trigger signal is GFXTIM_0 */ 322 323 /* reserved 29U */ 324 325 #define HPDMA1_TRIGGER_LPTIM1_CH1 30U /*!< HPDMA1 HW Trigger signal is LPTIM1_CH1 */ 326 #define HPDMA1_TRIGGER_LPTIM1_CH2 31U /*!< HPDMA1 HW Trigger signal is LPTIM1_CH2 */ 327 #define HPDMA1_TRIGGER_LPTIM2_CH1 32U /*!< HPDMA1 HW Trigger signal is LPTIM2_CH1 */ 328 #define HPDMA1_TRIGGER_LPTIM2_CH2 33U /*!< HPDMA1 HW Trigger signal is LPTIM2_CH2 */ 329 #define HPDMA1_TRIGGER_LPTIM3_CH1 34U /*!< HPDMA1 HW Trigger signal is LPTIM3_CH1 */ 330 #define HPDMA1_TRIGGER_LPTIM3_CH2 35U /*!< HPDMA1 HW Trigger signal is LPTIM3_CH2 */ 331 #define HPDMA1_TRIGGER_LPTIM4_OUT 36U /*!< HPDMA1 HW Trigger signal is LPTIM4_OUT */ 332 #define HPDMA1_TRIGGER_LPTIM5_OUT 37U /*!< HPDMA1 HW Trigger signal is LPTIM5_OUT */ 333 334 /* reserved 38U */ 335 336 #define HPDMA1_TRIGGER_RTC_WKUP 39U /*!< HPDMA1 HW Trigger signal is RTC_WKUP */ 337 338 #define HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 40U /*!< HPDMA1 HW Trigger signal is IT_R_WUP_ASYNC */ 339 #define HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 41U /*!< HPDMA1 HW Trigger signal is IT_T_WUP_ASYNC */ 340 341 #define HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U /*!< HPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */ 342 343 /* reserved 43U */ 344 345 #define HPDMA1_TRIGGER_TIM1_TRGO 44U /*!< HPDMA1 HW Trigger signal is TIM1_TRGO */ 346 #define HPDMA1_TRIGGER_TIM1_TRGO2 45U /*!< HPDMA1 HW Trigger signal is TIM1_TRGO2 */ 347 #define HPDMA1_TRIGGER_TIM2_TRGO 46U /*!< HPDMA1 HW Trigger signal is TIM2_TRGO */ 348 #define HPDMA1_TRIGGER_TIM3_TRGO 47U /*!< HPDMA1 HW Trigger signal is TIM3_TRGO */ 349 #define HPDMA1_TRIGGER_TIM4_TRGO 48U /*!< HPDMA1 HW Trigger signal is TIM4_TRGO */ 350 #define HPDMA1_TRIGGER_TIM5_TRGO 49U /*!< HPDMA1 HW Trigger signal is TIM5_TRGO */ 351 #define HPDMA1_TRIGGER_TIM6_TRGO 50U /*!< HPDMA1 HW Trigger signal is TIM6_TRGO */ 352 #define HPDMA1_TRIGGER_TIM7_TRGO 51U /*!< HPDMA1 HW Trigger signal is TIM7_TRGO */ 353 #define HPDMA1_TRIGGER_TIM8_TRGO 52U /*!< HPDMA1 HW Trigger signal is TIM8_TRGO */ 354 #define HPDMA1_TRIGGER_TIM8_TRGO2 53U /*!< HPDMA1 HW Trigger signal is TIM8_TRGO2 */ 355 356 /* reserved 54U */ 357 /* reserved 55U */ 358 /* reserved 56U */ 359 360 #define HPDMA1_TRIGGER_TIM12_TRGO 57U /*!< HPDMA1 HW Trigger signal is TIM12_TRGO */ 361 #define HPDMA1_TRIGGER_TIM15_TRGO 58U /*!< HPDMA1 HW Trigger signal is TIM15_TRGO */ 362 363 /* reserved 59U */ 364 365 #define HPDMA1_TRIGGER_HPDMA1_CH0_TCF 60U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ 366 #define HPDMA1_TRIGGER_HPDMA1_CH1_TCF 61U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ 367 #define HPDMA1_TRIGGER_HPDMA1_CH2_TCF 62U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ 368 #define HPDMA1_TRIGGER_HPDMA1_CH3_TCF 63U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ 369 #define HPDMA1_TRIGGER_HPDMA1_CH4_TCF 64U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ 370 #define HPDMA1_TRIGGER_HPDMA1_CH5_TCF 65U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ 371 #define HPDMA1_TRIGGER_HPDMA1_CH6_TCF 66U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ 372 #define HPDMA1_TRIGGER_HPDMA1_CH7_TCF 67U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ 373 #define HPDMA1_TRIGGER_HPDMA1_CH8_TCF 68U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ 374 #define HPDMA1_TRIGGER_HPDMA1_CH9_TCF 69U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ 375 #define HPDMA1_TRIGGER_HPDMA1_CH10_TCF 70U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ 376 #define HPDMA1_TRIGGER_HPDMA1_CH11_TCF 71U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ 377 #define HPDMA1_TRIGGER_HPDMA1_CH12_TCF 72U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ 378 #define HPDMA1_TRIGGER_HPDMA1_CH13_TCF 73U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ 379 #define HPDMA1_TRIGGER_HPDMA1_CH14_TCF 74U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ 380 #define HPDMA1_TRIGGER_HPDMA1_CH15_TCF 75U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ 381 382 #define HPDMA1_TRIGGER_GPDMA1_CH0_TCF 76U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ 383 #define HPDMA1_TRIGGER_GPDMA1_CH1_TCF 77U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ 384 #define HPDMA1_TRIGGER_GPDMA1_CH2_TCF 78U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ 385 #define HPDMA1_TRIGGER_GPDMA1_CH3_TCF 79U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ 386 #define HPDMA1_TRIGGER_GPDMA1_CH4_TCF 80U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ 387 #define HPDMA1_TRIGGER_GPDMA1_CH5_TCF 81U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ 388 #define HPDMA1_TRIGGER_GPDMA1_CH6_TCF 82U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ 389 #define HPDMA1_TRIGGER_GPDMA1_CH7_TCF 83U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ 390 #define HPDMA1_TRIGGER_GPDMA1_CH8_TCF 84U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ 391 #define HPDMA1_TRIGGER_GPDMA1_CH9_TCF 85U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ 392 #define HPDMA1_TRIGGER_GPDMA1_CH10_TCF 86U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ 393 #define HPDMA1_TRIGGER_GPDMA1_CH11_TCF 87U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ 394 #define HPDMA1_TRIGGER_GPDMA1_CH12_TCF 88U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ 395 #define HPDMA1_TRIGGER_GPDMA1_CH13_TCF 89U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ 396 #define HPDMA1_TRIGGER_GPDMA1_CH14_TCF 90U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ 397 #define HPDMA1_TRIGGER_GPDMA1_CH15_TCF 91U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ 398 399 /* reserved 92U */ 400 401 #define HPDMA1_TRIGGER_EXTIT0_SYNC 93U /*!< HPDMA1 HW Trigger signal is EXTIT0_SYNC */ 402 #define HPDMA1_TRIGGER_EXTIT1_SYNC 94U /*!< HPDMA1 HW Trigger signal is EXTIT1_SYNC */ 403 #define HPDMA1_TRIGGER_EXTIT2_SYNC 95U /*!< HPDMA1 HW Trigger signal is EXTIT2_SYNC */ 404 #define HPDMA1_TRIGGER_EXTIT3_SYNC 96U /*!< HPDMA1 HW Trigger signal is EXTIT3_SYNC */ 405 #define HPDMA1_TRIGGER_EXTIT4_SYNC 97U /*!< HPDMA1 HW Trigger signal is EXTIT4_SYNC */ 406 #define HPDMA1_TRIGGER_EXTIT5_SYNC 98U /*!< HPDMA1 HW Trigger signal is EXTIT5_SYNC */ 407 #define HPDMA1_TRIGGER_EXTIT6_SYNC 99U /*!< HPDMA1 HW Trigger signal is EXTIT6_SYNC */ 408 #define HPDMA1_TRIGGER_EXTIT7_SYNC 100U /*!< HPDMA1 HW Trigger signal is EXTIT7_SYNC */ 409 #define HPDMA1_TRIGGER_EXTIT8_SYNC 101U /*!< HPDMA1 HW Trigger signal is EXTIT8_SYNC */ 410 #define HPDMA1_TRIGGER_EXTIT9_SYNC 102U /*!< HPDMA1 HW Trigger signal is EXTIT9_SYNC */ 411 #define HPDMA1_TRIGGER_EXTIT10_SYNC 103U /*!< HPDMA1 HW Trigger signal is EXTIT10_SYNC */ 412 #define HPDMA1_TRIGGER_EXTIT11_SYNC 104U /*!< HPDMA1 HW Trigger signal is EXTIT11_SYNC */ 413 #define HPDMA1_TRIGGER_EXTIT12_SYNC 105U /*!< HPDMA1 HW Trigger signal is EXTIT12_SYNC */ 414 #define HPDMA1_TRIGGER_EXTIT13_SYNC 106U /*!< HPDMA1 HW Trigger signal is EXTIT13_SYNC */ 415 #define HPDMA1_TRIGGER_EXTIT14_SYNC 107U /*!< HPDMA1 HW Trigger signal is EXTIT14_SYNC */ 416 #define HPDMA1_TRIGGER_EXTIT15_SYNC 108U /*!< HPDMA1 HW Trigger signal is EXTIT15_SYNC */ 417 418 419 /* GPDMA1 triggers */ 420 #define GPDMA1_TRIGGER_DCMIPP_P0_FEND 0U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_FEND */ 421 #define GPDMA1_TRIGGER_DCMIPP_P0_LEND 1U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_LEND */ 422 #define GPDMA1_TRIGGER_DCMIPP_P0_HSYNC 2U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC */ 423 #define GPDMA1_TRIGGER_DCMIPP_P0_VSYNC 3U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC */ 424 425 #define GPDMA1_TRIGGER_DCMIPP_P1_FEND 4U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_FEND */ 426 #define GPDMA1_TRIGGER_DCMIPP_P1_LEND 5U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_LEND */ 427 #define GPDMA1_TRIGGER_DCMIPP_P1_HSYNC 6U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC */ 428 #define GPDMA1_TRIGGER_DCMIPP_P1_VSYNC 7U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC */ 429 430 #define GPDMA1_TRIGGER_DCMIPP_P2_FEND 8U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_FEND */ 431 #define GPDMA1_TRIGGER_DCMIPP_P2_LEND 9U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_LEND */ 432 #define GPDMA1_TRIGGER_DCMIPP_P2_HSYNC 10U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC */ 433 #define GPDMA1_TRIGGER_DCMIPP_P2_VSYNC 11U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC */ 434 435 #define GPDMA1_TRIGGER_DMA2D_CTC 12U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ 436 #define GPDMA1_TRIGGER_DMA2D_TC 13U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ 437 #define GPDMA1_TRIGGER_DMA2D_TW 14U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ 438 439 #define GPDMA1_TRIGGER_JPEG_EOC 15U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ 440 #define GPDMA1_TRIGGER_JPEG_IFNF 16U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ 441 #define GPDMA1_TRIGGER_JPEG_IFT 17U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ 442 #define GPDMA1_TRIGGER_JPEG_OFNE 18U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ 443 #define GPDMA1_TRIGGER_JPEG_OFT 19U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ 444 445 #define GPDMA1_LCD_LI 20U /*!< GPDMA1 HW Trigger signal is LCD_LI */ 446 447 #define GPDMA1_TRIGGER_GPU2D1_GP_0 21U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_0 */ 448 #define GPDMA1_TRIGGER_GPU2D1_GP_1 22U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_1 */ 449 #define GPDMA1_TRIGGER_GPU2D1_GP_2 23U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_2 */ 450 #define GPDMA1_TRIGGER_GPU2D1_GP_3 24U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_3 */ 451 452 #define GPDMA1_TRIGGER_GFXTIM_3 25U /*!< GPDMA1 HW Trigger signal is GFXTIM_3 */ 453 #define GPDMA1_TRIGGER_GFXTIM_2 26U /*!< GPDMA1 HW Trigger signal is GFXTIM_2 */ 454 #define GPDMA1_TRIGGER_GFXTIM_1 27U /*!< GPDMA1 HW Trigger signal is GFXTIM_1 */ 455 #define GPDMA1_TRIGGER_GFXTIM_0 28U /*!< GPDMA1 HW Trigger signal is GFXTIM_0 */ 456 457 /* reserved 29U */ 458 459 #define GPDMA1_TRIGGER_LPTIM1_CH1 30U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ 460 #define GPDMA1_TRIGGER_LPTIM1_CH2 31U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ 461 #define GPDMA1_TRIGGER_LPTIM2_CH1 32U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ 462 #define GPDMA1_TRIGGER_LPTIM2_CH2 33U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ 463 #define GPDMA1_TRIGGER_LPTIM3_CH1 34U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */ 464 #define GPDMA1_TRIGGER_LPTIM3_CH2 35U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */ 465 #define GPDMA1_TRIGGER_LPTIM4_OUT 36U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ 466 #define GPDMA1_TRIGGER_LPTIM5_OUT 37U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */ 467 468 /* reserved 38U */ 469 470 #define GPDMA1_TRIGGER_RTC_WKUP 39U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */ 471 472 #define GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 40U /*!< GPDMA1 HW Trigger signal is IT_R_WUP_ASYNC */ 473 #define GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 41U /*!< GPDMA1 HW Trigger signal is IT_T_WUP_ASYNC */ 474 475 #define GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U /*!< GPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */ 476 477 /* reserved 43U */ 478 479 #define GPDMA1_TRIGGER_TIM1_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */ 480 #define GPDMA1_TRIGGER_TIM1_TRGO2 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */ 481 #define GPDMA1_TRIGGER_TIM2_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ 482 #define GPDMA1_TRIGGER_TIM3_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ 483 #define GPDMA1_TRIGGER_TIM4_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ 484 #define GPDMA1_TRIGGER_TIM5_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ 485 #define GPDMA1_TRIGGER_TIM6_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */ 486 #define GPDMA1_TRIGGER_TIM7_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */ 487 #define GPDMA1_TRIGGER_TIM8_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO */ 488 #define GPDMA1_TRIGGER_TIM8_TRGO2 53U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO2 */ 489 490 /* reserved 54U */ 491 /* reserved 55U */ 492 /* reserved 56U */ 493 494 #define GPDMA1_TRIGGER_TIM12_TRGO 57U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */ 495 #define GPDMA1_TRIGGER_TIM15_TRGO 58U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ 496 497 /* reserved 59U */ 498 499 #define GPDMA1_TRIGGER_HPDMA1_CH0_TCF 60U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ 500 #define GPDMA1_TRIGGER_HPDMA1_CH1_TCF 61U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ 501 #define GPDMA1_TRIGGER_HPDMA1_CH2_TCF 62U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ 502 #define GPDMA1_TRIGGER_HPDMA1_CH3_TCF 63U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ 503 #define GPDMA1_TRIGGER_HPDMA1_CH4_TCF 64U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ 504 #define GPDMA1_TRIGGER_HPDMA1_CH5_TCF 65U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ 505 #define GPDMA1_TRIGGER_HPDMA1_CH6_TCF 66U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ 506 #define GPDMA1_TRIGGER_HPDMA1_CH7_TCF 67U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ 507 #define GPDMA1_TRIGGER_HPDMA1_CH8_TCF 68U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ 508 #define GPDMA1_TRIGGER_HPDMA1_CH9_TCF 69U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ 509 #define GPDMA1_TRIGGER_HPDMA1_CH10_TCF 70U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ 510 #define GPDMA1_TRIGGER_HPDMA1_CH11_TCF 71U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ 511 #define GPDMA1_TRIGGER_HPDMA1_CH12_TCF 72U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ 512 #define GPDMA1_TRIGGER_HPDMA1_CH13_TCF 73U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ 513 #define GPDMA1_TRIGGER_HPDMA1_CH14_TCF 74U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ 514 #define GPDMA1_TRIGGER_HPDMA1_CH15_TCF 75U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ 515 516 #define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 76U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ 517 #define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 77U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ 518 #define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 78U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ 519 #define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 79U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ 520 #define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 80U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ 521 #define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 81U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ 522 #define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 82U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ 523 #define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 83U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ 524 #define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 84U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ 525 #define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 85U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ 526 #define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 86U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ 527 #define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 87U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ 528 #define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 88U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ 529 #define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 89U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ 530 #define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 90U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ 531 #define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 91U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ 532 533 /* reserved 92U */ 534 535 #define GPDMA1_TRIGGER_EXTIT0_SYNC 93U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */ 536 #define GPDMA1_TRIGGER_EXTIT1_SYNC 94U /*!< GPDMA1 HW Trigger signal is EXTIT1_SYNC */ 537 #define GPDMA1_TRIGGER_EXTIT2_SYNC 95U /*!< GPDMA1 HW Trigger signal is EXTIT2_SYNC */ 538 #define GPDMA1_TRIGGER_EXTIT3_SYNC 96U /*!< GPDMA1 HW Trigger signal is EXTIT3_SYNC */ 539 #define GPDMA1_TRIGGER_EXTIT4_SYNC 97U /*!< GPDMA1 HW Trigger signal is EXTIT4_SYNC */ 540 #define GPDMA1_TRIGGER_EXTIT5_SYNC 98U /*!< GPDMA1 HW Trigger signal is EXTIT5_SYNC */ 541 #define GPDMA1_TRIGGER_EXTIT6_SYNC 99U /*!< GPDMA1 HW Trigger signal is EXTIT6_SYNC */ 542 #define GPDMA1_TRIGGER_EXTIT7_SYNC 100U /*!< GPDMA1 HW Trigger signal is EXTIT7_SYNC */ 543 #define GPDMA1_TRIGGER_EXTIT8_SYNC 101U /*!< GPDMA1 HW Trigger signal is EXTIT8_SYNC */ 544 #define GPDMA1_TRIGGER_EXTIT9_SYNC 102U /*!< GPDMA1 HW Trigger signal is EXTIT9_SYNC */ 545 #define GPDMA1_TRIGGER_EXTIT10_SYNC 103U /*!< GPDMA1 HW Trigger signal is EXTIT10_SYNC */ 546 #define GPDMA1_TRIGGER_EXTIT11_SYNC 104U /*!< GPDMA1 HW Trigger signal is EXTIT11_SYNC */ 547 #define GPDMA1_TRIGGER_EXTIT12_SYNC 105U /*!< GPDMA1 HW Trigger signal is EXTIT12_SYNC */ 548 #define GPDMA1_TRIGGER_EXTIT13_SYNC 106U /*!< GPDMA1 HW Trigger signal is EXTIT13_SYNC */ 549 #define GPDMA1_TRIGGER_EXTIT14_SYNC 107U /*!< GPDMA1 HW Trigger signal is EXTIT14_SYNC */ 550 #define GPDMA1_TRIGGER_EXTIT15_SYNC 108U /*!< GPDMA1 HW Trigger signal is EXTIT15_SYNC */ 551 /** 552 * @} 553 */ 554 555 /** @defgroup DMAEx_Node_Type DMAEx Node Type 556 * @brief DMAEx Node Type 557 * @{ 558 */ 559 #define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ 560 #define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */ 561 #define DMA_HPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the HPDMA linear addressing node type */ 562 #define DMA_HPDMA_2D_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the HPDMA 2 dimension addressing node type */ 563 /** 564 * @} 565 */ 566 567 /** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port 568 * @brief DMAEx Linked-List Allocated Port 569 * @{ 570 */ 571 #define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ 572 #define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ 573 /** 574 * @} 575 */ 576 577 /** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode 578 * @brief DMAEx Link Step Mode 579 * @{ 580 */ 581 #define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ 582 #define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ 583 /** 584 * @} 585 */ 586 587 /** 588 * @} 589 */ 590 591 /* Exported functions ------------------------------------------------------------------------------------------------*/ 592 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions 593 * @brief DMAEx Exported functions 594 * @{ 595 */ 596 597 /** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions 598 * @brief Linked-List Initialization and De-Initialization Functions 599 * @{ 600 */ 601 HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); 602 HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); 603 /** 604 * @} 605 */ 606 607 /** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions 608 * @brief Linked-List IO Operation Functions 609 * @{ 610 */ 611 HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); 612 HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); 613 /** 614 * @} 615 */ 616 617 /** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions 618 * @brief Linked-List Management Functions 619 * @{ 620 */ 621 HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, 622 DMA_NodeTypeDef *const pNode); 623 HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, 624 DMA_NodeTypeDef const *const pNode); 625 626 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, 627 DMA_NodeTypeDef *const pPrevNode, 628 DMA_NodeTypeDef *const pNewNode); 629 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, 630 DMA_NodeTypeDef *const pNewNode); 631 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, 632 DMA_NodeTypeDef *const pNewNode); 633 634 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, 635 DMA_NodeTypeDef *const pNode); 636 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); 637 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); 638 639 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, 640 DMA_NodeTypeDef *const pOldNode, 641 DMA_NodeTypeDef *const pNewNode); 642 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, 643 DMA_NodeTypeDef *const pNewNode); 644 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, 645 DMA_NodeTypeDef *const pNewNode); 646 647 HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); 648 649 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, 650 DMA_NodeTypeDef const *const pPrevNode, 651 DMA_QListTypeDef *const pDestQList); 652 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, 653 DMA_QListTypeDef *const pDestQList); 654 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, 655 DMA_QListTypeDef *const pDestQList); 656 657 HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, 658 DMA_NodeTypeDef *const pFirstCircularNode); 659 HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); 660 HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); 661 662 HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); 663 HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); 664 665 HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, 666 DMA_QListTypeDef *const pQList); 667 HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); 668 /** 669 * @} 670 */ 671 672 /** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions 673 * @brief Data Handling, Repeated Block and Trigger Configuration Functions 674 * @{ 675 */ 676 HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, 677 DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); 678 HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, 679 DMA_TriggerConfTypeDef const *const pConfigTrigger); 680 HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, 681 DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock); 682 /** 683 * @} 684 */ 685 686 /** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions 687 * @brief Suspend and Resume Operation Functions 688 * @{ 689 */ 690 HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); 691 HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); 692 HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); 693 /** 694 * @} 695 */ 696 697 /** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function 698 * @brief FIFO Status Function 699 * @{ 700 */ 701 uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); 702 /** 703 * @} 704 */ 705 706 /** 707 * @} 708 */ 709 710 /* Private types -----------------------------------------------------------------------------------------------------*/ 711 /** @defgroup DMAEx_Private_Types DMAEx Private Types 712 * @brief DMAEx Private Types 713 * @{ 714 */ 715 716 /** 717 * @brief DMA Node in Queue Information Structure Definition. 718 */ 719 typedef struct 720 { 721 uint32_t cllr_offset; /* CLLR register offset */ 722 723 uint32_t previousnode_addr; /* Previous node address */ 724 725 uint32_t currentnode_pos; /* Current node position */ 726 727 uint32_t currentnode_addr; /* Current node address */ 728 729 uint32_t nextnode_addr; /* Next node address */ 730 731 } DMA_NodeInQInfoTypeDef; 732 /** 733 * @} 734 */ 735 736 /* Private constants -------------------------------------------------------------------------------------------------*/ 737 /** @defgroup DMAEx_Private_Constants DMAEx Private Constants 738 * @brief DMAEx Private Constants 739 * @{ 740 */ 741 #define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ 742 743 #define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ 744 #define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ 745 #define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ 746 #define DMA_CHANNEL_TYPE_HPDMA (0x0040U) /* HPDMA channel node */ 747 748 #define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ 749 #define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ 750 #define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ 751 752 #define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ 753 754 #define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ 755 #define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ 756 757 #define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ 758 #define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ 759 760 #define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ 761 #define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ 762 763 #define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ 764 #define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ 765 766 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ 767 #define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ 768 #define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ 769 #define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ 770 #define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ 771 #define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ 772 #define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ 773 #define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */ 774 #define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ 775 776 #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ 777 #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ 778 #define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ 779 #define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ 780 /** 781 * @} 782 */ 783 784 /* Private macros ----------------------------------------------------------------------------------------------------*/ 785 /** @defgroup DMAEx_Private_Macros DMAEx Private Macros 786 * @brief DMAEx Private Macros 787 * @{ 788 */ 789 #define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ 790 (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ 791 ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ 792 ((ALIGNMENT) == DMA_DATA_PACK)) 793 794 #define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ 795 (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD | \ 796 DMA_EXCHANGE_DEST_WORD))) == 0U) 797 798 #define IS_DMA_REPEAT_COUNT(COUNT) \ 799 (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) 800 801 #define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ 802 (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ 803 ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) 804 805 #define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ 806 (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ 807 ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) 808 809 #define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ 810 (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) 811 812 #define IS_DMA_LINK_STEP_MODE(MODE) \ 813 (((MODE) == DMA_LSM_FULL_EXECUTION) || \ 814 ((MODE) == DMA_LSM_1LINK_EXECUTION)) 815 816 #define IS_DMA_TRIGGER_MODE(MODE) \ 817 (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ 818 ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \ 819 ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ 820 ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) 821 822 #define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ 823 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 824 ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ 825 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 826 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 827 828 #define IS_DMA_LINKEDLIST_MODE(MODE) \ 829 (((MODE) == DMA_LINKEDLIST_NORMAL) || \ 830 ((MODE) == DMA_LINKEDLIST_CIRCULAR)) 831 832 #define IS_DMA_TRIGGER_POLARITY(POLARITY) \ 833 (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ 834 ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ 835 ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) 836 837 #define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ 838 ((TRIGGER) <= HPDMA1_TRIGGER_EXTIT15_SYNC) 839 840 #define IS_DMA_NODE_TYPE(TYPE) \ 841 (((TYPE) == DMA_GPDMA_LINEAR_NODE) || \ 842 ((TYPE) == DMA_GPDMA_2D_NODE) || \ 843 ((TYPE) == DMA_HPDMA_LINEAR_NODE) || \ 844 ((TYPE) == DMA_HPDMA_2D_NODE)) 845 /** 846 * @} 847 */ 848 849 850 /* Private functions -------------------------------------------------------------------------------------------------*/ 851 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions 852 * @brief DMAEx Private Functions 853 * @{ 854 */ 855 856 /** 857 * @} 858 */ 859 860 /** 861 * @} 862 */ 863 864 /** 865 * @} 866 */ 867 868 /** 869 * @} 870 */ 871 872 #ifdef __cplusplus 873 } 874 #endif /* __cplusplus */ 875 876 #endif /* STM32N6xx_HAL_DMA_EX_H */ 877
