1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32C0xx_HAL_H 22 #define STM32C0xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32c0xx_ll_system.h" 30 #include "stm32c0xx_hal_conf.h" 31 32 /** @addtogroup STM32C0xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @defgroup HAL HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /* Exported constants --------------------------------------------------------*/ 42 43 /** @defgroup HAL_Exported_Constants HAL Exported Constants 44 * @{ 45 */ 46 47 /** @defgroup HAL_TICK_FREQ Tick Frequency 48 * @{ 49 */ 50 51 typedef enum 52 { 53 HAL_TICK_FREQ_10HZ = 100U, 54 HAL_TICK_FREQ_100HZ = 10U, 55 HAL_TICK_FREQ_1KHZ = 1U, 56 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 57 } HAL_TickFreqTypeDef; 58 59 /** 60 * @} 61 */ 62 63 /** @defgroup HAL_BIND_CFG Bind Pin config 64 * @{ 65 */ 66 67 #if (DEV_ID == 0x443UL) 68 #define HAL_BIND_SO8_PIN1_PB7 LL_PINMUX_SO8_PIN1_PB7 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PB7 */ 69 #define HAL_BIND_SO8_PIN1_PC14 LL_PINMUX_SO8_PIN1_PC14 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PC14 */ 70 #define HAL_BIND_SO8_PIN4_PF2 LL_PINMUX_SO8_PIN4_PF2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PF2 */ 71 #define HAL_BIND_SO8_PIN4_PA0 LL_PINMUX_SO8_PIN4_PA0 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA0 */ 72 #define HAL_BIND_SO8_PIN4_PA1 LL_PINMUX_SO8_PIN4_PA1 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA1 */ 73 #define HAL_BIND_SO8_PIN4_PA2 LL_PINMUX_SO8_PIN4_PA2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA2 */ 74 #define HAL_BIND_SO8_PIN5_PA8 LL_PINMUX_SO8_PIN5_PA8 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA8*/ 75 #define HAL_BIND_SO8_PIN5_PA11 LL_PINMUX_SO8_PIN5_PA11 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA11 */ 76 #define HAL_BIND_SO8_PIN8_PA14 LL_PINMUX_SO8_PIN8_PA14 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PA14 */ 77 #define HAL_BIND_SO8_PIN8_PB6 LL_PINMUX_SO8_PIN8_PB6 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PB6 */ 78 #define HAL_BIND_SO8_PIN8_PC15 LL_PINMUX_SO8_PIN8_PC15 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PC15 */ 79 #define HAL_BIND_WLCSP12_PINE2_PA7 LL_PINMUX_WLCSP12_PINE2_PA7 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA7 */ 80 #define HAL_BIND_WLCSP12_PINE2_PA12 LL_PINMUX_WLCSP12_PINE2_PA12 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA12*/ 81 #define HAL_BIND_WLCSP12_PINF1_PA3 LL_PINMUX_WLCSP12_PINF1_PA3 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA3 */ 82 #define HAL_BIND_WLCSP12_PINF1_PA4 LL_PINMUX_WLCSP12_PINF1_PA4 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA4 */ 83 #define HAL_BIND_WLCSP12_PINF1_PA5 LL_PINMUX_WLCSP12_PINF1_PA5 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA5 */ 84 #define HAL_BIND_WLCSP12_PINF1_PA6 LL_PINMUX_WLCSP12_PINF1_PA6 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA6 */ 85 #elif (DEV_ID == 0x453UL) 86 #define HAL_BIND_WLCSP14_PINF2_PA1 LL_PINMUX_WLCSP14_PINF2_PA1 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA1 */ 87 #define HAL_BIND_WLCSP14_PINF2_PA2 LL_PINMUX_WLCSP14_PINF2_PA2 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA2 */ 88 #define HAL_BIND_WLCSP14_PING3_PF2 LL_PINMUX_WLCSP14_PING3_PF2 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PF2 */ 89 #define HAL_BIND_WLCSP14_PING3_PA0 LL_PINMUX_WLCSP14_PING3_PA0 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PA0 */ 90 #define HAL_BIND_WLCSP14_PINJ1_PA8 LL_PINMUX_WLCSP14_PINJ1_PA8 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA8 */ 91 #define HAL_BIND_WLCSP14_PINJ1_PA11 LL_PINMUX_WLCSP14_PINJ1_PA11 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA11 */ 92 #define HAL_BIND_WLCSP14_PINH2_PA5 LL_PINMUX_WLCSP14_PINH2_PA5 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA5 */ 93 #define HAL_BIND_WLCSP14_PINH2_PA6 LL_PINMUX_WLCSP14_PINH2_PA6 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA6 */ 94 #define HAL_BIND_WLCSP14_PING1_PA7 LL_PINMUX_WLCSP14_PING1_PA7 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA7 */ 95 #define HAL_BIND_WLCSP14_PING1_PA12 LL_PINMUX_WLCSP14_PING1_PA12 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA12 */ 96 #define HAL_BIND_WLCSP14_PINJ3_PA3 LL_PINMUX_WLCSP14_PINJ3_PA3 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA3 */ 97 #define HAL_BIND_WLCSP14_PINJ3_PA4 LL_PINMUX_WLCSP14_PINJ3_PA4 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA4 */ 98 #elif (DEV_ID == 0x493UL) 99 #define HAL_BIND_WLCSP19_PINH3_PF2 LL_PINMUX_WLCSP19_PINH3_PF2 /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PF2 */ 100 #define HAL_BIND_WLCSP19_PINH3_PA0 LL_PINMUX_WLCSP19_PINH3_PA0 /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PA0 */ 101 #define HAL_BIND_WLCSP19_PINB1_PA14 LL_PINMUX_WLCSP19_PINB1_PA14 /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA14 */ 102 #define HAL_BIND_WLCSP19_PINB1_PA15 LL_PINMUX_WLCSP19_PINB1_PA15 /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA15 */ 103 #define HAL_BIND_TSSOP20_PIN19_PA14 LL_PINMUX_TSSOP20_PIN19_PA14 104 #define HAL_BIND_TSSOP20_PIN19_PA15 LL_PINMUX_TSSOP20_PIN19_PA15 105 #define HAL_BIND_TSSOP20_PIN20_PB6 LL_PINMUX_TSSOP20_PIN20_PB6 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB6 */ 106 #define HAL_BIND_TSSOP20_PIN20_PB3 LL_PINMUX_TSSOP20_PIN20_PB3 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB3 */ 107 #define HAL_BIND_TSSOP20_PIN20_PB4 LL_PINMUX_TSSOP20_PIN20_PB4 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB4 */ 108 #define HAL_BIND_TSSOP20_PIN20_PB5 LL_PINMUX_TSSOP20_PIN20_PB5 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB5 */ 109 #define HAL_BIND_WLCSP19_PINB3_PB LL_PINMUX_WLCSP19_PINB3_PB7 /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB7 */ 110 #define HAL_BIND_WLCSP19_PINB3_PB8 LL_PINMUX_WLCSP19_PINB3_PB8 /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB8 */ 111 #define HAL_BIND_TSSOP20_PIN1_PB7 LL_PINMUX_TSSOP20_PIN1_PB7 /*!< STM32C071 TSSOP20 package, Pin1 assigned to GPIO PB7 */ 112 #define HAL_BIND_TSSOP20_PIN1_PB8 LL_PINMUX_TSSOP20_PIN1_PB8 /*!< STM32C071 TSSOP20 package, Pin1 assigned to GPIO PB8 */ 113 #endif /* DEV_ID == 0x443UL */ 114 115 /** 116 * @} 117 */ 118 119 /** @defgroup HAL_BIND_SCOURCE Bind Pin Source 120 * @{ 121 */ 122 #if (DEV_ID == 0x443UL) 123 #define HAL_BIND_SO8_PIN1 LL_PINMUX_SO8_PIN1 /*!< STM32C011 SO8 package, GPIO Pin1 multiplexer */ 124 #define HAL_BIND_SO8_PIN4 LL_PINMUX_SO8_PIN4 /*!< STM32C011 SO8 package, GPIO Pin4 multiplexer */ 125 #define HAL_BIND_SO8_PIN5 LL_PINMUX_SO8_PIN5 /*!< STM32C011 SO8 package, GPIO Pin5 multiplexer */ 126 #define HAL_BIND_SO8_PIN8 LL_PINMUX_SO8_PIN8 /*!< STM32C011 SO8 package, GPIO Pin8 multiplexer */ 127 #define HAL_BIND_WLCSP12_PINE2 LL_PINMUX_WLCSP12_PINE2 /*!< STM32C011 WLCSP12 package, GPIO PinE2 multiplexer */ 128 #define HAL_BIND_WLCSP12_PINF1 LL_PINMUX_WLCSP12_PINF1 /*!< STM32C011 WLCSP12 package, GPIO PinF1 multiplexer */ 129 #elif (DEV_ID == 0x453UL) 130 #define HAL_BIND_WLCSP14_PINF2 LL_PINMUX_WLCSP14_PINF2 /*!< STM32C031 WLCSP14 package, GPIO PinF2 multiplexer */ 131 #define HAL_BIND_WLCSP14_PING3 LL_PINMUX_WLCSP14_PING3 /*!< STM32C031 WLCSP14 package, GPIO PinG3 multiplexer */ 132 #define HAL_BIND_WLCSP14_PINJ1 LL_PINMUX_WLCSP14_PINJ1 /*!< STM32C031 WLCSP14 package, GPIO PinJ1 multiplexer */ 133 #define HAL_BIND_WLCSP14_PINH2 LL_PINMUX_WLCSP14_PINH2 /*!< STM32C031 WLCSP14 package, GPIO PinH2 multiplexer */ 134 #define HAL_BIND_WLCSP14_PING1 LL_PINMUX_WLCSP14_PING1 /*!< STM32C031 WLCSP14 package, GPIO PinG1 multiplexer */ 135 #define HAL_BIND_WLCSP14_PINJ3 LL_PINMUX_WLCSP14_PINJ3 /*!< STM32C031 WLCSP14 package, GPIO PinJ3 multiplexer */ 136 #elif (DEV_ID == 0x493UL) 137 #define HAL_BIND_WLCSP19_PINH3 LL_PINMUX_WLCSP19_PINH3 /*!< STM32C071 WLCSP19 package, GPIO PinH3 multiplexer */ 138 #define HAL_BIND_WLCSP19_PINB1 LL_PINMUX_WLCSP19_PINB1 /*!< STM32C071 WLCSP19 package, GPIO PinB1 multiplexer */ 139 #define HAL_BIND_TSSOP20_PIN19 LL_PINMUX_TSSOP20_PIN19 /*!< STM32C071 TSSOP20 package, GPIO Pin19 multiplexer */ 140 #define HAL_BIND_TSSOP20_PIN20 LL_PINMUX_TSSOP20_PIN20 /*!< STM32C071 TSSOP20 package, GPIO Pin20 multiplexer */ 141 #define HAL_BIND_WLCSP19_PINB3 LL_PINMUX_WLCSP19_PINB3 /*!< STM32C071 WLCSP19 package, GPIO PinB3 multiplexer */ 142 #define HAL_BIND_TSSOP20_PIN1 LL_PINMUX_TSSOP20_PIN1 /*!< STM32C071 TSSOP20 package, GPIO Pin1 multiplexer */ 143 #endif /* DEV_ID == 0x443UL */ 144 /** 145 * @} 146 */ 147 148 /** 149 * @} 150 */ 151 152 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 153 * @{ 154 */ 155 156 /** @defgroup SYSCFG_BootMode Boot Mode 157 * @{ 158 */ 159 #define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */ 160 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */ 161 #define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */ 162 163 /** 164 * @} 165 */ 166 167 /** @defgroup SYSCFG_Break Break 168 * @{ 169 */ 170 #define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/16/17 */ 171 /** 172 * @} 173 */ 174 175 /** @defgroup HAL_Pin_remapping Pin remapping 176 * @{ 177 */ 178 #define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */ 179 #define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */ 180 /** 181 * @} 182 */ 183 184 /** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection 185 * @{ 186 */ 187 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */ 188 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */ 189 #define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */ 190 191 /** 192 * @} 193 */ 194 195 /** @defgroup HAL_IR_POL_SEL IR output polarity selection 196 * @{ 197 */ 198 #define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */ 199 #define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */ 200 201 /** 202 * @} 203 */ 204 /** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO 205 * @{ 206 */ 207 208 /** @brief Fast mode Plus driving capability on a specific GPIO 209 */ 210 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */ 211 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */ 212 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */ 213 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */ 214 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */ 215 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */ 216 #define SYSCFG_FASTMODEPLUS_PC14 SYSCFG_CFGR1_I2C_PC14_FMP /*!< Enable Fast mode Plus on PC14 */ 217 /** 218 * @} 219 */ 220 221 /** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx 222 * @{ 223 */ 224 225 /** @brief Fast mode Plus driving capability on a specific GPIO 226 */ 227 #define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */ 228 #if defined(I2C2) 229 #define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */ 230 #endif /* I2C2 */ 231 /** 232 * @} 233 */ 234 235 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper 236 * @brief ISR Wrapper 237 * @{ 238 */ 239 #define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */ 240 #define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */ 241 #define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */ 242 #define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */ 243 #define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */ 244 #define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */ 245 #define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */ 246 #if defined(USB) 247 #define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */ 248 #endif /* USB */ 249 #define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */ 250 #define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */ 251 #define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */ 252 #define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */ 253 #define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */ 254 #define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */ 255 #if defined(TIM2) 256 #define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */ 257 #endif /* TIM2 */ 258 #define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */ 259 #define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */ 260 #define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */ 261 #define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */ 262 #define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */ 263 #if defined(I2C2) 264 #define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */ 265 #endif /* I2C2 */ 266 #define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */ 267 #if defined(SPI2) 268 #define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */ 269 #endif /* SPI2 */ 270 #define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */ 271 #define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */ 272 273 #define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_WWDG) /*!< WWDG Interrupt */ 274 #define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC Interrupt */ 275 #define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */ 276 #define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */ 277 #if defined(CRS) 278 #define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< CRS Interrupt */ 279 #endif /* CRS */ 280 #define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */ 281 #define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */ 282 #define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */ 283 #define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */ 284 #define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */ 285 #define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */ 286 #define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */ 287 #define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */ 288 #define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */ 289 #define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */ 290 #define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */ 291 #define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */ 292 #define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */ 293 #define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */ 294 #define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */ 295 #define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */ 296 #if defined(USB) 297 #define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */ 298 #endif /* USB */ 299 #define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */ 300 #define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */ 301 #define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */ 302 #define HAL_ITLINE_DMAMUX ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX) /*!< DMAMUX Interrupt */ 303 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) 304 #define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */ 305 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ 306 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) 307 #define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */ 308 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ 309 #define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */ 310 #define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */ 311 #define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */ 312 #define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */ 313 #define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */ 314 #define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC) /*!< TIM1 CC Interrupt */ 315 #if defined(TIM2) 316 #define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2) /*!< TIM2 Interrupt */ 317 #endif /* TIM2 */ 318 #define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */ 319 #define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */ 320 #define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */ 321 #define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */ 322 #define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt */ 323 #if defined(I2C2) 324 #define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C1 Interrupt */ 325 #endif /* I2C2 */ 326 #define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */ 327 #if defined(SPI2) 328 #define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE25_SR_SPI2) /*!< SPI1 Interrupt */ 329 #endif /* SPI2 */ 330 #define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt */ 331 #define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt */ 332 333 /** 334 * @} 335 */ 336 337 /** 338 * @} 339 */ 340 341 /* Exported macros -----------------------------------------------------------*/ 342 /** @defgroup HAL_Exported_Macros HAL Exported Macros 343 * @{ 344 */ 345 346 /** @defgroup DBG_Exported_Macros DBG Exported Macros 347 * @{ 348 */ 349 350 /** @brief Freeze and Unfreeze Peripherals in Debug mode 351 */ 352 353 #if defined(DBG_APB_FZ1_DBG_TIM2_STOP) 354 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) 355 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) 356 #endif /* DBG_APB_FZ1_DBG_TIM2_STOP */ 357 358 #if defined(DBG_APB_FZ1_DBG_TIM3_STOP) 359 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) 360 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) 361 #endif /* DBG_APB_FZ1_DBG_TIM3_STOP */ 362 363 #if defined(DBG_APB_FZ1_DBG_RTC_STOP) 364 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) 365 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) 366 #endif /* DBG_APB_FZ1_DBG_RTC_STOP */ 367 368 #if defined(DBG_APB_FZ1_DBG_WWDG_STOP) 369 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) 370 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) 371 #endif /* DBG_APB_FZ1_DBG_RTC_STOP */ 372 373 #if defined(DBG_APB_FZ1_DBG_IWDG_STOP) 374 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) 375 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) 376 #endif /* DBG_APB_FZ1_DBG_IWDG_STOP */ 377 378 #if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 379 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 380 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 381 #endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */ 382 383 #if defined(DBG_APB_FZ2_DBG_TIM1_STOP) 384 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) 385 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) 386 #endif /* DBG_APB_FZ2_DBG_TIM1_STOP */ 387 388 #if defined(DBG_APB_FZ2_DBG_TIM14_STOP) 389 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) 390 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) 391 #endif /* DBG_APB_FZ2_DBG_TIM14_STOP */ 392 393 #if defined(DBG_APB_FZ2_DBG_TIM16_STOP) 394 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) 395 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) 396 #endif /* DBG_APB_FZ2_DBG_TIM16_STOP */ 397 398 #if defined(DBG_APB_FZ2_DBG_TIM17_STOP) 399 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) 400 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) 401 #endif /* DBG_APB_FZ2_DBG_TIM17_STOP */ 402 403 /** 404 * @} 405 */ 406 407 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 408 * @{ 409 */ 410 411 /** 412 * @brief ISR wrapper check 413 * @note Allow to determine interrupt source per line. 414 */ 415 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) 416 417 /** @brief Main Flash memory mapped at 0x00000000 418 */ 419 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 420 421 /** @brief System Flash memory mapped at 0x00000000 422 */ 423 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) 424 425 /** @brief Embedded SRAM mapped at 0x00000000 426 */ 427 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() \ 428 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)) 429 430 /** 431 * @brief Return the boot mode as configured by user. 432 * @retval The boot mode as configured by user. The returned value can be one 433 * of the following values @ref SYSCFG_BootMode 434 */ 435 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 436 437 /** @brief SYSCFG Break Cortex-M0+ Lockup lock. 438 * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/16/17 Break input 439 * @note The selected configuration is locked and can be unlocked only by system reset. 440 */ 441 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 442 443 /** @brief Fast-mode Plus driving capability enable/disable macros 444 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO 445 */ 446 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 447 do { \ 448 assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 449 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 450 }while(0U) 451 452 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 453 do { \ 454 assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 455 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 456 }while(0U) 457 458 459 /** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register 460 * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL 461 */ 462 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\ 463 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\ 464 SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\ 465 }while(0U) 466 467 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U) 468 469 /** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register 470 * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL 471 */ 472 #define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\ 473 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\ 474 SET_BIT(SYSCFG->CFGR1,(__SEL__));\ 475 }while(0U) 476 477 /** 478 * @brief Return the IROut Polarity mode as configured by user. 479 * @retval The IROut polarity as configured by user. The returned value can be one 480 * of @ref HAL_IR_POL_SEL 481 */ 482 #define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL) 483 484 /** @brief Break input to TIM1/16/17 capability enable/disable macros 485 * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break 486 */ 487 #define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ 488 SET_BIT(SYSCFG->CFGR2, (__BREAK__));\ 489 }while(0U) 490 491 #define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ 492 CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\ 493 }while(0U) 494 /** 495 * @} 496 */ 497 498 /* Private macros ------------------------------------------------------------*/ 499 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 500 * @{ 501 */ 502 503 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) ((__CONFIG__) == SYSCFG_BREAK_LOCKUP) 504 505 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ 506 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ 507 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2)) 508 509 #define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \ 510 ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED)) 511 512 513 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PC14) == SYSCFG_FASTMODEPLUS_PC14) || \ 514 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ 515 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ 516 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 517 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 518 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 519 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 520 521 #define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \ 522 ((RMP) == SYSCFG_REMAP_PA12) || \ 523 ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12))) 524 #if (DEV_ID == 0x443UL) 525 #define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_SO8_PIN1_PB7) || \ 526 ((PIN) == HAL_BIND_SO8_PIN1_PC14) || \ 527 ((PIN) == HAL_BIND_SO8_PIN4_PF2) || \ 528 ((PIN) == HAL_BIND_SO8_PIN4_PA0) || \ 529 ((PIN) == HAL_BIND_SO8_PIN4_PA1) || \ 530 ((PIN) == HAL_BIND_SO8_PIN4_PA2) || \ 531 ((PIN) == HAL_BIND_SO8_PIN5_PA8) || \ 532 ((PIN) == HAL_BIND_SO8_PIN5_PA11) || \ 533 ((PIN) == HAL_BIND_SO8_PIN8_PA14) || \ 534 ((PIN) == HAL_BIND_SO8_PIN8_PB6) || \ 535 ((PIN) == HAL_BIND_SO8_PIN8_PC15) || \ 536 ((PIN) == HAL_BIND_WLCSP12_PINE2_PA7) || \ 537 ((PIN) == HAL_BIND_WLCSP12_PINE2_PA12) || \ 538 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA3) || \ 539 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA4) || \ 540 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA5) || \ 541 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA6)) 542 #elif (DEV_ID == 0x453UL) 543 #define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_WLCSP14_PINF2_PA1) || \ 544 ((PIN) == HAL_BIND_WLCSP14_PINF2_PA2) || \ 545 ((PIN) == HAL_BIND_WLCSP14_PING3_PF2) || \ 546 ((PIN) == HAL_BIND_WLCSP14_PING3_PA0) || \ 547 ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA8) || \ 548 ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA11) || \ 549 ((PIN) == HAL_BIND_WLCSP14_PINH2_PA5) || \ 550 ((PIN) == HAL_BIND_WLCSP14_PINH2_PA6) || \ 551 ((PIN) == HAL_BIND_WLCSP14_PING1_PA7) || \ 552 ((PIN) == HAL_BIND_WLCSP14_PING1_PA12)|| \ 553 ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA3) || \ 554 ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA4)) 555 #elif (DEV_ID == 0x493UL) 556 #define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_WLCSP19_PINH3_PF2) || \ 557 ((PIN) == LL_PINMUX_WLCSP19_PINH3_PA0) || \ 558 ((PIN) == LL_PINMUX_WLCSP19_PINB1_PA14) || \ 559 ((PIN) == LL_PINMUX_WLCSP19_PINB1_PA15) || \ 560 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB6) || \ 561 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB3) || \ 562 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB4) || \ 563 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB5) || \ 564 ((PIN) == LL_PINMUX_WLCSP19_PINB3_PB7) || \ 565 ((PIN) == LL_PINMUX_WLCSP19_PINB3_PB8)) 566 #endif /* DEV_ID == 0x443UL | DEV_ID == 0x453UL | DEV_ID == 0x493UL */ 567 /** 568 * @} 569 */ 570 571 /** @defgroup HAL_Private_Macros HAL Private Macros 572 * @{ 573 */ 574 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 575 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 576 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 577 /** 578 * @} 579 */ 580 /* Exported functions --------------------------------------------------------*/ 581 582 /** @defgroup HAL_Exported_Functions HAL Exported Functions 583 * @{ 584 */ 585 586 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions 587 * @{ 588 */ 589 590 /* Initialization and Configuration functions ******************************/ 591 HAL_StatusTypeDef HAL_Init(void); 592 HAL_StatusTypeDef HAL_DeInit(void); 593 void HAL_MspInit(void); 594 void HAL_MspDeInit(void); 595 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 596 597 /** 598 * @} 599 */ 600 601 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 602 * @{ 603 */ 604 605 /* Peripheral Control functions ************************************************/ 606 void HAL_IncTick(void); 607 void HAL_Delay(uint32_t Delay); 608 uint32_t HAL_GetTick(void); 609 uint32_t HAL_GetTickPrio(void); 610 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 611 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 612 void HAL_SuspendTick(void); 613 void HAL_ResumeTick(void); 614 uint32_t HAL_GetHalVersion(void); 615 uint32_t HAL_GetREVID(void); 616 uint32_t HAL_GetDEVID(void); 617 uint32_t HAL_GetUIDw0(void); 618 uint32_t HAL_GetUIDw1(void); 619 uint32_t HAL_GetUIDw2(void); 620 621 /** 622 * @} 623 */ 624 625 /** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions 626 * @{ 627 */ 628 629 /* DBGMCU Peripheral Control functions *****************************************/ 630 void HAL_DBGMCU_EnableDBGStopMode(void); 631 void HAL_DBGMCU_DisableDBGStopMode(void); 632 void HAL_DBGMCU_EnableDBGStandbyMode(void); 633 void HAL_DBGMCU_DisableDBGStandbyMode(void); 634 635 /** 636 * @} 637 */ 638 639 /* Exported variables ---------------------------------------------------------*/ 640 /** @addtogroup HAL_Exported_Variables 641 * @{ 642 */ 643 extern __IO uint32_t uwTick; 644 extern uint32_t uwTickPrio; 645 extern HAL_TickFreqTypeDef uwTickFreq; 646 /** 647 * @} 648 */ 649 650 /** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions 651 * @{ 652 */ 653 654 /* SYSCFG Control functions ****************************************************/ 655 void HAL_SYSCFG_EnableRemap(uint32_t PinRemap); 656 void HAL_SYSCFG_DisableRemap(uint32_t PinRemap); 657 void HAL_SYSCFG_SetPinBinding(uint32_t pin_binding); 658 uint32_t HAL_SYSCFG_GetPinBinding(uint32_t pin_binding_source); 659 /** 660 * @} 661 */ 662 663 /** 664 * @} 665 */ 666 667 /** 668 * @} 669 */ 670 671 /** 672 * @} 673 */ 674 675 /** 676 * @} 677 */ 678 #ifdef __cplusplus 679 } 680 #endif 681 682 #endif /* STM32C0xx_HAL_H */ 683
