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Searched refs:GPIO_ADVCFGRL_1_Pos (Results 1 – 6 of 6) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_gpio.c351 GPIOx->ADVCFGR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)) ; in HAL_GPIO_DeInit()
547 << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); in HAL_GPIO_SetRetime()
548 temp |= (pRet_Init->Retime << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); in HAL_GPIO_SetRetime()
549 temp |= (pRet_Init->Edge << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); in HAL_GPIO_SetRetime()
583 index = (position & 0x07u) * GPIO_ADVCFGRL_1_Pos; in HAL_GPIO_GetRetime()
623 temp &= ~(GPIO_ADVCFGRL_DLYPATH0 << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); in HAL_GPIO_SetDelay()
624 temp |= (pDly_Init->Path << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); in HAL_GPIO_SetDelay()
629 temp &= ~(GPIO_DELAYRL_DLY0_Msk << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); in HAL_GPIO_SetDelay()
630 temp |= (pDly_Init->Delay << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); in HAL_GPIO_SetDelay()
664 index = (position & 0x07u) * GPIO_ADVCFGRL_1_Pos; in HAL_GPIO_GetDelay()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_gpio.h1036 MODIFY_REG(GPIOx->ADVCFGR[0], GPIO_ADVCFGRL_0 << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos), in LL_GPIO_SetPIOControlPin_0_7()
1037 (CfgMask << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos))); in LL_GPIO_SetPIOControlPin_0_7()
1061 (GPIO_ADVCFGRL_0 << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos))) in LL_GPIO_GetPIOControlPin_0_7()
1062 >> (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos)); in LL_GPIO_GetPIOControlPin_0_7()
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h20190 #define GPIO_ADVCFGRL_1_Pos (4U) macro
20191 #define GPIO_ADVCFGRL_1_Msk (0xFUL << GPIO_ADVCFGRL_1_Pos) /*!< 0x000000F0 */
20193 #define GPIO_ADVCFGRL_DLYPATH1 (0x1UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000010 */
20194 #define GPIO_ADVCFGRL_DE1 (0x2UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000020 */
20195 #define GPIO_ADVCFGRL_INVCLK1 (0x4UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000040 */
20196 #define GPIO_ADVCFGRL_RET1 (0x8UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000080 */
Dstm32n657xx.h21132 #define GPIO_ADVCFGRL_1_Pos (4U) macro
21133 #define GPIO_ADVCFGRL_1_Msk (0xFUL << GPIO_ADVCFGRL_1_Pos) /*!< 0x000000F0 */
21135 #define GPIO_ADVCFGRL_DLYPATH1 (0x1UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000010 */
21136 #define GPIO_ADVCFGRL_DE1 (0x2UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000020 */
21137 #define GPIO_ADVCFGRL_INVCLK1 (0x4UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000040 */
21138 #define GPIO_ADVCFGRL_RET1 (0x8UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000080 */
Dstm32n655xx.h20890 #define GPIO_ADVCFGRL_1_Pos (4U) macro
20891 #define GPIO_ADVCFGRL_1_Msk (0xFUL << GPIO_ADVCFGRL_1_Pos) /*!< 0x000000F0 */
20893 #define GPIO_ADVCFGRL_DLYPATH1 (0x1UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000010 */
20894 #define GPIO_ADVCFGRL_DE1 (0x2UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000020 */
20895 #define GPIO_ADVCFGRL_INVCLK1 (0x4UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000040 */
20896 #define GPIO_ADVCFGRL_RET1 (0x8UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000080 */
Dstm32n647xx.h20432 #define GPIO_ADVCFGRL_1_Pos (4U) macro
20433 #define GPIO_ADVCFGRL_1_Msk (0xFUL << GPIO_ADVCFGRL_1_Pos) /*!< 0x000000F0 */
20435 #define GPIO_ADVCFGRL_DLYPATH1 (0x1UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000010 */
20436 #define GPIO_ADVCFGRL_DE1 (0x2UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000020 */
20437 #define GPIO_ADVCFGRL_INVCLK1 (0x4UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000040 */
20438 #define GPIO_ADVCFGRL_RET1 (0x8UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000080 */