1 /** 2 ********************************************************************************************************************** 3 * @file stm32u5xx_hal_dma_ex.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL extension module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32U5xx_HAL_DMA_EX_H 21 #define STM32U5xx_HAL_DMA_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMAEx 35 * @{ 36 */ 37 38 /* Exported types ----------------------------------------------------------------------------------------------------*/ 39 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types 40 * @brief DMAEx Exported types 41 * @{ 42 */ 43 44 /** 45 * @brief DMAEx Data Handling Configuration Structure Definition. 46 */ 47 typedef struct 48 { 49 uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. 50 This parameter can be a value of @ref DMAEx_Data_Exchange */ 51 52 uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode 53 This parameter can be a value of @ref DMAEx_Data_Alignment */ 54 55 } DMA_DataHandlingConfTypeDef; 56 57 /** 58 * @brief DMAEx Trigger Configuration Structure Definition. 59 */ 60 typedef struct 61 { 62 uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. 63 This parameter can be a value of @ref DMAEx_Trigger_Mode */ 64 65 uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. 66 This parameter can be a value of @ref DMAEx_Trigger_Polarity */ 67 68 uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. 69 This parameter can be a value of @ref DMAEx_Trigger_Selection */ 70 71 } DMA_TriggerConfTypeDef; 72 73 /** 74 * @brief DMAEx Repeated Block Configuration Structure Definition. 75 */ 76 typedef struct 77 { 78 uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block). 79 This parameter can be a value between 1 and 2048 */ 80 81 int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset : 82 This parameter can be a value between -8191 and 8191. 83 * If source address offset > 0 => Increment the source address by offset from where 84 the last single/burst transfer ends. 85 * If source address offset < 0 => Decrement the source address by offset from where 86 the last single/burst transfer ends. 87 * If source address offset == 0 => The next single/burst source address starts from 88 where the last transfer ends */ 89 90 int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value : 91 This parameter can be a value between -8191 and 8191. 92 * If destination address offset > 0 => Increment the destination address by offset 93 from where the last single/burst transfer ends. 94 * If destination address offset < 0 => Decrement the destination address by offset 95 from where the last single/burst transfer ends. 96 * If destination address offset == 0 => The next single/burst destination address 97 starts from where the last transfer ends. */ 98 99 int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value : 100 This parameter can be a value between -65535 and 65535. 101 * If block source address offset > 0 => Increment the block source address by offset 102 from where the last block ends. 103 * If block source address offset < 0 => Decrement the next block source address by 104 offset from where the last block ends. 105 * If block source address offset == 0 => the next block source address starts from 106 where the last block ends */ 107 108 int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value : 109 This parameter can be a value between -65535 and 65535. 110 * If block destination address offset > 0 => Increment the block destination address 111 by offset from where the last block ends. 112 * If block destination address offset < 0 => Decrement the next block destination 113 address by offset from where the last block ends. 114 * If block destination address offset == 0 => the next block destination address 115 starts from where the last block ends */ 116 117 } DMA_RepeatBlockConfTypeDef; 118 119 /** 120 * @brief DMAEx Queue State Enumeration Definition. 121 */ 122 typedef enum 123 { 124 HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ 125 HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ 126 HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ 127 128 } HAL_DMA_QStateTypeDef; 129 130 /** 131 * @brief DMAEx Linked-List Node Configuration Structure Definition. 132 */ 133 typedef struct 134 { 135 uint32_t NodeType; /*!< Specifies the DMA channel node type. 136 This parameter can be a value of @ref DMAEx_Node_Type */ 137 138 DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ 139 140 DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ 141 142 DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ 143 144 DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */ 145 146 uint32_t SrcAddress; /*!< Specifies the source memory address */ 147 uint32_t DstAddress; /*!< Specifies the destination memory address */ 148 uint32_t DataSize; /*!< Specifies the source data size in bytes */ 149 150 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 151 uint32_t SrcSecure; /*!< Specifies the source security attribute */ 152 uint32_t DestSecure; /*!< Specifies the destination security attribute */ 153 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 154 155 } DMA_NodeConfTypeDef; 156 157 /** 158 * @brief DMAEx Linked-List Node Structure Definition. 159 */ 160 typedef struct 161 { 162 uint32_t LinkRegisters[8U]; /*!< Physical Node register description */ 163 uint32_t NodeInfo; /*!< Node information */ 164 165 } DMA_NodeTypeDef; 166 167 /** 168 * @brief DMAEx Linked-List Queue Structure Definition. 169 */ 170 typedef struct __DMA_QListTypeDef 171 { 172 DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ 173 174 DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ 175 176 uint32_t NodeNumber; /*!< Specifies the queue node number */ 177 178 __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ 179 180 __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ 181 182 __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ 183 184 } DMA_QListTypeDef; 185 /** 186 * @} 187 */ 188 189 /* Exported constants ------------------------------------------------------------------------------------------------*/ 190 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants 191 * @brief DMAEx Exported Constants 192 * @{ 193 */ 194 195 /** @defgroup Queue_Error_Codes Queue Error Codes 196 * @brief Queue Error Codes 197 * @{ 198 */ 199 #define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ 200 #define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ 201 #define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ 202 #define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ 203 #define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization 204 and queue circular types are incompatible */ 205 #define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ 206 #define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ 207 /** 208 * @} 209 */ 210 211 /** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode 212 * @brief DMAEx LinkedList Mode 213 * @{ 214 */ 215 #define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ 216 #define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ 217 /** 218 * @} 219 */ 220 221 /** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment 222 * @brief DMAEx Data Alignment 223 * @{ 224 */ 225 #define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width 226 => Right aligned padded with 0 up to destination data 227 width */ 228 #define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width 229 => Right aligned left Truncated down to destination 230 data width */ 231 #define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width 232 => Right Aligned padded with sign extended up to 233 destination data width */ 234 #define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width 235 => Left Aligned Right Truncated down to the 236 destination data width */ 237 #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width 238 => Packed at the destination data width 239 (Not available on LPDMA) */ 240 #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width 241 => Unpacked at the destination data width 242 (Not available on LPDMA) */ 243 /** 244 * @} 245 */ 246 247 /** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange 248 * @brief DMAEx Data Exchange 249 * @{ 250 */ 251 #define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ 252 #define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ 253 #define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ 254 #define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ 255 /** 256 * @} 257 */ 258 259 /** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity 260 * @brief DMAEx Trigger Polarity 261 * @{ 262 */ 263 #define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ 264 #define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ 265 #define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ 266 /** 267 * @} 268 */ 269 270 /** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode 271 * @brief DMAEx Trigger Mode 272 * @{ 273 */ 274 #define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ 275 #define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */ 276 #define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ 277 #define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ 278 /** 279 * @} 280 */ 281 282 /** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection 283 * @brief DMAEx Trigger Selection 284 * @{ 285 */ 286 /* GPDMA1 triggers */ 287 #define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ 288 #define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ 289 #define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ 290 #define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ 291 #define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ 292 #define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ 293 #define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ 294 #define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ 295 #define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ 296 #define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ 297 #define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ 298 #define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ 299 #define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ 300 #define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ 301 #define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ 302 #define GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ 303 #define GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ 304 #if defined(COMP2) 305 #define GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ 306 #endif /* COMP2 */ 307 #define GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ 308 #define GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ 309 #define GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ 310 #define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ 311 #define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ 312 #define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ 313 #define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ 314 #define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ 315 #define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ 316 #define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ 317 #define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ 318 #define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ 319 #define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ 320 #define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ 321 #define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ 322 #define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ 323 #define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ 324 #define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ 325 #define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ 326 #define GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ 327 #define GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ 328 #define GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ 329 #define GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ 330 #define GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ 331 #define GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ 332 #if defined (TIM3_TRGO_TRIGGER_SUPPORT) 333 #define GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ 334 #endif /* TIM3_TRGO_TRIGGER_SUPPORT */ 335 #if defined (TIM4_TRGO_TRIGGER_SUPPORT) 336 #define GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ 337 #endif /* TIM4_TRGO_TRIGGER_SUPPORT */ 338 #if defined (TIM5_TRGO_TRIGGER_SUPPORT) 339 #define GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ 340 #endif /* TIM5_TRGO_TRIGGER_SUPPORT */ 341 #if defined (LTDC) 342 #define GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ 343 #endif /* LTDC */ 344 #if defined (DSI) 345 #define GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ 346 #define GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ 347 #endif /* DSI */ 348 #if defined (DMA2D_TRIGGER_SUPPORT) 349 #define GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ 350 #define GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ 351 #define GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ 352 #endif /* DMA2D_TRIGGER_SUPPORT */ 353 #if defined (GPU2D) 354 #define GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ 355 #define GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ 356 #define GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ 357 #define GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ 358 #endif /* GPU2D */ 359 #define GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ 360 #define GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ 361 #if defined (GFXTIM) 362 #define GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ 363 #define GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ 364 #define GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ 365 #define GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ 366 #endif /* GFXTIM */ 367 #if defined (JPEG) 368 #define GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ 369 #define GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ 370 #define GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ 371 #define GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ 372 #define GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ 373 #endif /* JPEG */ 374 375 /* LPDMA1 triggers */ 376 #define LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ 377 #define LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ 378 #define LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ 379 #define LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ 380 #define LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ 381 #define LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ 382 #define LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ 383 #define LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ 384 #define LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ 385 #define LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ 386 #define LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */ 387 #define LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */ 388 #define LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger signal is COMP1_OUT */ 389 #if defined(COMP2) 390 #define LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger signal is COMP2_OUT */ 391 #endif /* COMP2 */ 392 #define LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ 393 #define LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ 394 #define LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ 395 #define LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger signal is ADC4_AWD1 */ 396 #define LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ 397 #define LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ 398 #define LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ 399 #define LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ 400 #define LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ 401 #define LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ 402 #define LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ 403 #define LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ 404 #define LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ 405 #define LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ 406 #define LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ 407 #define LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ 408 #define LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ 409 #define LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger signal is TIM15_TRGO */ 410 /** 411 * @} 412 */ 413 414 /** @defgroup DMAEx_Node_Type DMAEx Node Type 415 * @brief DMAEx Node Type 416 * @{ 417 */ 418 #define DMA_LPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_LPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the LPDMA linear addressing node type */ 419 #define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ 420 #define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */ 421 /** 422 * @} 423 */ 424 425 /** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port 426 * @brief DMAEx Linked-List Allocated Port 427 * @{ 428 */ 429 #define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ 430 #define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ 431 /** 432 * @} 433 */ 434 435 /** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode 436 * @brief DMAEx Link Step Mode 437 * @{ 438 */ 439 #define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ 440 #define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ 441 /** 442 * @} 443 */ 444 445 /** 446 * @} 447 */ 448 449 /* Exported functions ------------------------------------------------------------------------------------------------*/ 450 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions 451 * @brief DMAEx Exported functions 452 * @{ 453 */ 454 455 /** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions 456 * @brief Linked-List Initialization and De-Initialization Functions 457 * @{ 458 */ 459 HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); 460 HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); 461 /** 462 * @} 463 */ 464 465 /** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions 466 * @brief Linked-List IO Operation Functions 467 * @{ 468 */ 469 HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); 470 HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); 471 /** 472 * @} 473 */ 474 475 /** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions 476 * @brief Linked-List Management Functions 477 * @{ 478 */ 479 HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, 480 DMA_NodeTypeDef *const pNode); 481 HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, 482 DMA_NodeTypeDef const *const pNode); 483 484 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, 485 DMA_NodeTypeDef *const pPrevNode, 486 DMA_NodeTypeDef *const pNewNode); 487 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, 488 DMA_NodeTypeDef *const pNewNode); 489 HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, 490 DMA_NodeTypeDef *const pNewNode); 491 492 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, 493 DMA_NodeTypeDef *const pNode); 494 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); 495 HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); 496 497 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, 498 DMA_NodeTypeDef *const pOldNode, 499 DMA_NodeTypeDef *const pNewNode); 500 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, 501 DMA_NodeTypeDef *const pNewNode); 502 HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, 503 DMA_NodeTypeDef *const pNewNode); 504 505 HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); 506 507 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, 508 DMA_NodeTypeDef const *const pPrevNode, 509 DMA_QListTypeDef *const pDestQList); 510 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, 511 DMA_QListTypeDef *const pDestQList); 512 HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, 513 DMA_QListTypeDef *const pDestQList); 514 515 HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, 516 DMA_NodeTypeDef *const pFirstCircularNode); 517 HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); 518 HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); 519 520 HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); 521 HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); 522 523 HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, 524 DMA_QListTypeDef *const pQList); 525 HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); 526 /** 527 * @} 528 */ 529 530 /** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions 531 * @brief Data Handling, Repeated Block and Trigger Configuration Functions 532 * @{ 533 */ 534 HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, 535 DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); 536 HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, 537 DMA_TriggerConfTypeDef const *const pConfigTrigger); 538 HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, 539 DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock); 540 /** 541 * @} 542 */ 543 544 /** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions 545 * @brief Suspend and Resume Operation Functions 546 * @{ 547 */ 548 HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); 549 HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); 550 HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); 551 /** 552 * @} 553 */ 554 555 /** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function 556 * @brief FIFO Status Function 557 * @{ 558 */ 559 uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); 560 /** 561 * @} 562 */ 563 564 /** 565 * @} 566 */ 567 568 /* Private types -----------------------------------------------------------------------------------------------------*/ 569 /** @defgroup DMAEx_Private_Types DMAEx Private Types 570 * @brief DMAEx Private Types 571 * @{ 572 */ 573 574 /** 575 * @brief DMA Node in Queue Information Structure Definition. 576 */ 577 typedef struct 578 { 579 uint32_t cllr_offset; /* CLLR register offset */ 580 581 uint32_t previousnode_addr; /* Previous node address */ 582 583 uint32_t currentnode_pos; /* Current node position */ 584 585 uint32_t currentnode_addr; /* Current node address */ 586 587 uint32_t nextnode_addr; /* Next node address */ 588 589 } DMA_NodeInQInfoTypeDef; 590 /** 591 * @} 592 */ 593 594 /* Private constants -------------------------------------------------------------------------------------------------*/ 595 /** @defgroup DMAEx_Private_Constants DMAEx Private Constants 596 * @brief DMAEx Private Constants 597 * @{ 598 */ 599 #define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ 600 601 #define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ 602 #define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ 603 #define DMA_CHANNEL_TYPE_LPDMA (0x0010U) /* LPDMA channel node */ 604 #define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ 605 606 #define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ 607 #define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ 608 #define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ 609 610 #define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ 611 612 #define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ 613 #define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ 614 615 #define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ 616 #define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ 617 618 #define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ 619 #define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ 620 621 #define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ 622 #define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ 623 624 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ 625 #define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ 626 #define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ 627 #define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ 628 #define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ 629 #define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ 630 #define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ 631 #define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */ 632 #define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ 633 634 #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ 635 #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ 636 #define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ 637 #define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ 638 /** 639 * @} 640 */ 641 642 /* Private macros ----------------------------------------------------------------------------------------------------*/ 643 /** @defgroup DMAEx_Private_Macros DMAEx Private Macros 644 * @brief DMAEx Private Macros 645 * @{ 646 */ 647 #define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ 648 (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ 649 ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ 650 ((ALIGNMENT) == DMA_DATA_PACK)) 651 652 #define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ 653 (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U) 654 655 #define IS_DMA_REPEAT_COUNT(COUNT) \ 656 (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) 657 658 #define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ 659 (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ 660 ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) 661 662 #define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ 663 (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ 664 ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) 665 666 #define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ 667 (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) 668 669 #define IS_DMA_LINK_STEP_MODE(MODE) \ 670 (((MODE) == DMA_LSM_FULL_EXECUTION) || \ 671 ((MODE) == DMA_LSM_1LINK_EXECUTION)) 672 673 #define IS_DMA_TRIGGER_MODE(MODE) \ 674 (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ 675 ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \ 676 ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ 677 ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) 678 679 #define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ 680 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 681 ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ 682 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 683 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 684 685 #define IS_DMA_LINKEDLIST_MODE(MODE) \ 686 (((MODE) == DMA_LINKEDLIST_NORMAL) || \ 687 ((MODE) == DMA_LINKEDLIST_CIRCULAR)) 688 689 #define IS_DMA_TRIGGER_POLARITY(POLARITY) \ 690 (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ 691 ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ 692 ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) 693 694 #if defined (GPDMA1_TRIGGER_JPEG_OFT) 695 #define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_JPEG_OFT) 696 #else 697 #define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1) 698 #endif /* GPDMA1_TRIGGER_JPEG_OFT */ 699 700 #define IS_DMA_NODE_TYPE(TYPE) \ 701 (((TYPE) == DMA_LPDMA_LINEAR_NODE) || \ 702 ((TYPE) == DMA_GPDMA_LINEAR_NODE) || \ 703 ((TYPE) == DMA_GPDMA_2D_NODE)) 704 /** 705 * @} 706 */ 707 708 709 /* Private functions -------------------------------------------------------------------------------------------------*/ 710 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions 711 * @brief DMAEx Private Functions 712 * @{ 713 */ 714 715 /** 716 * @} 717 */ 718 719 /** 720 * @} 721 */ 722 723 /** 724 * @} 725 */ 726 727 /** 728 * @} 729 */ 730 731 #ifdef __cplusplus 732 } 733 #endif /* __cplusplus */ 734 735 #endif /* STM32U5xx_HAL_DMA_EX_H */ 736
