1 /** 2 ********************************************************************************************************************** 3 * @file stm32h7rsxx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32H7RSxx_HAL_DMA_H 21 #define STM32H7RSxx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32h7rsxx_hal_def.h" 29 30 /** @addtogroup STM32H7RSxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 39 /* Exported types ----------------------------------------------------------------------------------------------------*/ 40 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @brief DMA Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief DMA Transfer Configuration Structure definition. 48 */ 49 typedef struct 50 { 51 uint32_t Request; /*!< Specifies the DMA channel request. 52 This parameter can be a value of @ref DMA_Request_Selection */ 53 54 uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. 55 Block Hardware request feature can be used only with dedicated peripherals. 56 This parameter can be a value of @ref DMA_Block_Request */ 57 58 uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. 59 This parameter can be a value of @ref DMA_Transfer_Direction */ 60 61 uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. 62 This parameter can be a value of @ref DMA_Source_Increment_Mode */ 63 64 uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. 65 This parameter can be a value of @ref DMA_Destination_Increment_Mode */ 66 67 uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. 68 This parameter can be a value of @ref DMA_Source_Data_Width */ 69 70 uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. 71 This parameter can be a value of @ref DMA_Destination_Data_Width */ 72 73 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 74 This parameter can be a value of @ref DMA_Priority_Level */ 75 76 uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA 77 channel. 78 This parameter can be a value between 1 and 64 */ 79 80 uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the 81 DMA channel. 82 This parameter can be a value between 1 and 64 */ 83 84 uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. 85 This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ 86 87 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 88 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 89 90 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. 91 This parameter can be a value of @ref DMA_Transfer_Mode */ 92 93 } DMA_InitTypeDef; 94 95 /** 96 * @brief DMA Linked-List Configuration Structure Definition. 97 */ 98 typedef struct 99 { 100 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 101 This parameter can be a value of @ref DMA_Priority_Level */ 102 103 uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. 104 This parameter can be a value of @ref DMAEx_Link_Step_Mode */ 105 106 uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. 107 This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ 108 109 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 110 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 111 112 uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. 113 This parameter can be a value of @ref DMAEx_LinkedList_Mode */ 114 115 } DMA_InitLinkedListTypeDef; 116 117 /** 118 * @brief HAL DMA State Enumeration Definition. 119 */ 120 typedef enum 121 { 122 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 123 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 124 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 125 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 126 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 127 HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ 128 129 } HAL_DMA_StateTypeDef; 130 131 /** 132 * @brief HAL DMA Level Complete Enumeration Definition. 133 */ 134 typedef enum 135 { 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ 137 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ 138 139 } HAL_DMA_LevelCompleteTypeDef; 140 141 /** 142 * @brief HAL DMA Callbacks IDs Enumeration Definition. 143 */ 144 typedef enum 145 { 146 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ 147 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ 148 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ 149 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ 150 HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ 151 HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ 152 153 } HAL_DMA_CallbackIDTypeDef; 154 155 /** 156 * @brief DMA handle Structure definition 157 */ 158 typedef struct __DMA_HandleTypeDef 159 { 160 DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ 161 162 DMA_InitTypeDef Init; /*!< DMA channel init parameters */ 163 164 DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ 165 166 HAL_LockTypeDef Lock; /*!< DMA locking object */ 167 168 uint32_t Mode; /*!< DMA transfer mode */ 169 170 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 171 172 __IO uint32_t ErrorCode; /*!< DMA error code */ 173 174 void *Parent; /*!< Parent object state */ 175 176 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 177 178 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ 179 180 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 181 182 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ 183 184 void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ 185 186 struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ 187 188 } DMA_HandleTypeDef; 189 /** 190 * @} 191 */ 192 193 194 /* Exported constants ------------------------------------------------------------------------------------------------*/ 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants 196 * @brief DMA Exported constants 197 * @{ 198 */ 199 200 /** @defgroup DMA_Error_Codes DMA Error Codes 201 * @brief DMA Error Codes 202 * @{ 203 */ 204 #define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ 205 #define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ 206 #define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ 207 #define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ 208 #define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ 209 #define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ 210 #define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ 211 #define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ 212 #define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ 213 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition 219 * @brief DMA Interrupt Enable Definition 220 * @{ 221 */ 222 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ 223 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ 224 #define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ 225 #define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ 226 #define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ 227 #define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ 228 #define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup DMA_Flag_Definition DMA Flag Definition 234 * @brief DMA Flag Definition 235 * @{ 236 */ 237 #define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ 238 #define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ 239 #define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ 240 #define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ 241 #define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ 242 #define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ 243 #define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ 244 #define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup DMA_Request_Selection DMA Request Selection 250 * @brief DMA Request Selection 251 * @{ 252 */ 253 /* HPDMA1 requests */ 254 #define HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_DMA_RX */ 255 #define HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_DMA_TX */ 256 #define HPDMA1_REQUEST_XSPI1 2U /*!< HPDMA1 HW request is XSPI1 */ 257 #define HPDMA1_REQUEST_XSPI2 3U /*!< HPDMA1 HW request is XSPI2 */ 258 #define HPDMA1_REQUEST_SPI3_RX 4U /*!< HPDMA1 HW request is SPI3_RX */ 259 #define HPDMA1_REQUEST_SPI3_TX 5U /*!< HPDMA1 HW request is SPI3_TX */ 260 #define HPDMA1_REQUEST_SPI4_RX 6U /*!< HPDMA1 HW request is SPI4_RX */ 261 #define HPDMA1_REQUEST_SPI4_TX 7U /*!< HPDMA1 HW request is SPI4_TX */ 262 #define HPDMA1_REQUEST_ADC1 8U /*!< HPDMA1 HW request is ADC1 */ 263 #define HPDMA1_REQUEST_ADC2 9U /*!< HPDMA1 HW request is ADC2 */ 264 #define HPDMA1_REQUEST_ADF1_FLT0 10U /*!< HPDMA1 HW request is ADF1_FLT0 */ 265 #define HPDMA1_REQUEST_UART4_RX 11U /*!< HPDMA1 HW request is UART4_RX */ 266 #define HPDMA1_REQUEST_UART4_TX 12U /*!< HPDMA1 HW request is UART4_TX */ 267 #define HPDMA1_REQUEST_UART5_RX 13U /*!< HPDMA1 HW request is UART5_RX */ 268 #define HPDMA1_REQUEST_UART5_TX 14U /*!< HPDMA1 HW request is UART5_TX */ 269 #define HPDMA1_REQUEST_UART7_RX 15U /*!< HPDMA1 HW request is UART7_RX */ 270 #define HPDMA1_REQUEST_UART7_TX 16U /*!< HPDMA1 HW request is UART7_TX */ 271 #define HPDMA1_REQUEST_LPTIM2_IC1 17U /*!< HPDMA1 HW request is LPTIM2_IC1 */ 272 #define HPDMA1_REQUEST_LPTIM2_IC2 18U /*!< HPDMA1 HW request is LPTIM2_IC2 */ 273 #define HPDMA1_REQUEST_LPTIM2_UE 19U /*!< HPDMA1 HW request is LPTIM2_UE */ 274 275 /* GPDMA1 requests */ 276 #define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ 277 #define GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */ 278 #define GPDMA1_REQUEST_CRYP_IN 2U /*!< GPDMA1 HW request is CRYP_IN */ 279 #define GPDMA1_REQUEST_CRYP_OUT 3U /*!< GPDMA1 HW request is CRYP_OUT */ 280 #define GPDMA1_REQUEST_SAES_IN 4U /*!< GPDMA1 HW request is SAES_IN */ 281 #define GPDMA1_REQUEST_SAES_OUT 5U /*!< GPDMA1 HW request is SAES_OUT */ 282 #define GPDMA1_REQUEST_HASH_IN 6U /*!< GPDMA1 HW request is HASH_IN */ 283 #define GPDMA1_REQUEST_TIM1_CH1 7U /*!< GPDMA1 HW request is TIM1_CH1 */ 284 #define GPDMA1_REQUEST_TIM1_CH2 8U /*!< GPDMA1 HW request is TIM1_CH2 */ 285 #define GPDMA1_REQUEST_TIM1_CH3 9U /*!< GPDMA1 HW request is TIM1_CH3 */ 286 #define GPDMA1_REQUEST_TIM1_CH4 10U /*!< GPDMA1 HW request is TIM1_CH4 */ 287 #define GPDMA1_REQUEST_TIM1_UP 11U /*!< GPDMA1 HW request is TIM1_UP */ 288 #define GPDMA1_REQUEST_TIM1_TRIG 12U /*!< GPDMA1 HW request is TIM1_TRIG */ 289 #define GPDMA1_REQUEST_TIM1_COM 13U /*!< GPDMA1 HW request is TIM1_COM */ 290 #define GPDMA1_REQUEST_TIM2_CH1 14U /*!< GPDMA1 HW request is TIM2_CH1 */ 291 #define GPDMA1_REQUEST_TIM2_CH2 15U /*!< GPDMA1 HW request is TIM2_CH2 */ 292 #define GPDMA1_REQUEST_TIM2_CH3 16U /*!< GPDMA1 HW request is TIM2_CH3 */ 293 #define GPDMA1_REQUEST_TIM2_CH4 17U /*!< GPDMA1 HW request is TIM2_CH4 */ 294 #define GPDMA1_REQUEST_TIM2_UP 18U /*!< GPDMA1 HW request is TIM2_UP */ 295 #define GPDMA1_REQUEST_TIM2_TRIG 19U /*!< GPDMA1 HW request is TIM2_TRIG */ 296 #define GPDMA1_REQUEST_TIM3_CH1 20U /*!< GPDMA1 HW request is TIM3_CH1 */ 297 #define GPDMA1_REQUEST_TIM3_CH2 21U /*!< GPDMA1 HW request is TIM3_CH2 */ 298 #define GPDMA1_REQUEST_TIM3_CH3 22U /*!< GPDMA1 HW request is TIM3_CH3 */ 299 #define GPDMA1_REQUEST_TIM3_CH4 23U /*!< GPDMA1 HW request is TIM3_CH4 */ 300 #define GPDMA1_REQUEST_TIM3_UP 24U /*!< GPDMA1 HW request is TIM3_UP */ 301 #define GPDMA1_REQUEST_TIM3_TRIG 25U /*!< GPDMA1 HW request is TIM3_TRIG */ 302 #define GPDMA1_REQUEST_TIM4_CH1 26U /*!< GPDMA1 HW request is TIM4_CH1 */ 303 #define GPDMA1_REQUEST_TIM4_CH2 27U /*!< GPDMA1 HW request is TIM4_CH2 */ 304 #define GPDMA1_REQUEST_TIM4_CH3 28U /*!< GPDMA1 HW request is TIM4_CH3 */ 305 #define GPDMA1_REQUEST_TIM4_CH4 29U /*!< GPDMA1 HW request is TIM4_CH4 */ 306 #define GPDMA1_REQUEST_TIM4_UP 30U /*!< GPDMA1 HW request is TIM4_UP */ 307 #define GPDMA1_REQUEST_TIM4_TRIG 31U /*!< GPDMA1 HW request is TIM4_TRIG */ 308 #define GPDMA1_REQUEST_TIM5_CH1 32U /*!< GPDMA1 HW request is TIM5_CH1 */ 309 #define GPDMA1_REQUEST_TIM5_CH2 33U /*!< GPDMA1 HW request is TIM5_CH2 */ 310 #define GPDMA1_REQUEST_TIM5_CH3 34U /*!< GPDMA1 HW request is TIM5_CH3 */ 311 #define GPDMA1_REQUEST_TIM5_CH4 35U /*!< GPDMA1 HW request is TIM5_CH4 */ 312 #define GPDMA1_REQUEST_TIM5_UP 36U /*!< GPDMA1 HW request is TIM5_UP */ 313 #define GPDMA1_REQUEST_TIM5_TRIG 37U /*!< GPDMA1 HW request is TIM5_TRIG */ 314 #define GPDMA1_REQUEST_TIM6_UP 38U /*!< GPDMA1 HW request is TIM6_UP */ 315 #define GPDMA1_REQUEST_TIM7_UP 39U /*!< GPDMA1 HW request is TIM7_UP */ 316 #define GPDMA1_REQUEST_TIM15_CH1 40U /*!< GPDMA1 HW request is TIM15_CH1 */ 317 #define GPDMA1_REQUEST_TIM15_CH2 41U /*!< GPDMA1 HW request is TIM15_CH2 */ 318 #define GPDMA1_REQUEST_TIM15_UP 42U /*!< GPDMA1 HW request is TIM15_UP */ 319 #define GPDMA1_REQUEST_TIM15_TRIG 43U /*!< GPDMA1 HW request is TIM15_TRIG */ 320 #define GPDMA1_REQUEST_TIM15_COM 44U /*!< GPDMA1 HW request is TIM15_COM */ 321 #define GPDMA1_REQUEST_TIM16_CH1 45U /*!< GPDMA1 HW request is TIM16_CH1 */ 322 #define GPDMA1_REQUEST_TIM16_UP 46U /*!< GPDMA1 HW request is TIM16_UP */ 323 #define GPDMA1_REQUEST_TIM16_COM 47U /*!< GPDMA1 HW request is TIM16_COM */ 324 #define GPDMA1_REQUEST_TIM17_CH1 48U /*!< GPDMA1 HW request is TIM17_CH1 */ 325 #define GPDMA1_REQUEST_TIM17_UP 49U /*!< GPDMA1 HW request is TIM17_UP */ 326 #define GPDMA1_REQUEST_TIM17_COM 50U /*!< GPDMA1 HW request is TIM17_COM */ 327 #define GPDMA1_REQUEST_SPI1_RX 51U /*!< GPDMA1 HW request is SPI1_RX */ 328 #define GPDMA1_REQUEST_SPI1_TX 52U /*!< GPDMA1 HW request is SPI1_TX */ 329 #define GPDMA1_REQUEST_SPI2_RX 53U /*!< GPDMA1 HW request is SPI2_RX */ 330 #define GPDMA1_REQUEST_SPI2_TX 54U /*!< GPDMA1 HW request is SPI2_TX */ 331 #define GPDMA1_REQUEST_SPI3_RX 55U /*!< GPDMA1 HW request is SPI3_RX */ 332 #define GPDMA1_REQUEST_SPI3_TX 56U /*!< GPDMA1 HW request is SPI3_TX */ 333 #define GPDMA1_REQUEST_SPI4_RX 57U /*!< GPDMA1 HW request is SPI4_RX */ 334 #define GPDMA1_REQUEST_SPI4_TX 58U /*!< GPDMA1 HW request is SPI4_TX */ 335 #define GPDMA1_REQUEST_SPI5_RX 59U /*!< GPDMA1 HW request is SPI5_RX */ 336 #define GPDMA1_REQUEST_SPI5_TX 60U /*!< GPDMA1 HW request is SPI5_TX */ 337 #define GPDMA1_REQUEST_SPI6_RX 61U /*!< GPDMA1 HW request is SPI6_RX */ 338 #define GPDMA1_REQUEST_SPI6_TX 62U /*!< GPDMA1 HW request is SPI6_TX */ 339 #define GPDMA1_REQUEST_SAI1_A 63U /*!< GPDMA1 HW request is SAI1_A */ 340 #define GPDMA1_REQUEST_SAI1_B 64U /*!< GPDMA1 HW request is SAI1_B */ 341 #define GPDMA1_REQUEST_SAI2_A 65U /*!< GPDMA1 HW request is SAI2_A */ 342 #define GPDMA1_REQUEST_SAI2_B 66U /*!< GPDMA1 HW request is SAI2_B */ 343 #define GPDMA1_REQUEST_I2C1_RX 67U /*!< GPDMA1 HW request is I2C1_RX */ 344 #define GPDMA1_REQUEST_I2C1_TX 68U /*!< GPDMA1 HW request is I2C1_TX */ 345 #define GPDMA1_REQUEST_I2C2_RX 69U /*!< GPDMA1 HW request is I2C2_RX */ 346 #define GPDMA1_REQUEST_I2C2_TX 70U /*!< GPDMA1 HW request is I2C2_TX */ 347 #define GPDMA1_REQUEST_I2C3_RX 71U /*!< GPDMA1 HW request is I2C3_RX */ 348 #define GPDMA1_REQUEST_I2C3_TX 72U /*!< GPDMA1 HW request is I2C3_TX */ 349 #define GPDMA1_REQUEST_USART1_RX 73U /*!< GPDMA1 HW request is USART1_RX */ 350 #define GPDMA1_REQUEST_USART1_TX 74U /*!< GPDMA1 HW request is USART1_TX */ 351 #define GPDMA1_REQUEST_USART2_RX 75U /*!< GPDMA1 HW request is USART2_RX */ 352 #define GPDMA1_REQUEST_USART2_TX 76U /*!< GPDMA1 HW request is USART2_TX */ 353 #define GPDMA1_REQUEST_USART3_RX 77U /*!< GPDMA1 HW request is USART3_RX */ 354 #define GPDMA1_REQUEST_USART3_TX 78U /*!< GPDMA1 HW request is USART3_TX */ 355 #define GPDMA1_REQUEST_UART4_RX 79U /*!< GPDMA1 HW request is UART4_RX */ 356 #define GPDMA1_REQUEST_UART4_TX 80U /*!< GPDMA1 HW request is UART4_TX */ 357 #define GPDMA1_REQUEST_UART5_RX 81U /*!< GPDMA1 HW request is UART5_RX */ 358 #define GPDMA1_REQUEST_UART5_TX 82U /*!< GPDMA1 HW request is UART5_TX */ 359 #define GPDMA1_REQUEST_UART7_RX 83U /*!< GPDMA1 HW request is UART7_RX */ 360 #define GPDMA1_REQUEST_UART7_TX 84U /*!< GPDMA1 HW request is UART7_TX */ 361 #define GPDMA1_REQUEST_UART8_RX 85U /*!< GPDMA1 HW request is UART8_RX */ 362 #define GPDMA1_REQUEST_UART8_TX 86U /*!< GPDMA1 HW request is UART8_TX */ 363 #define GPDMA1_REQUEST_CORDIC_READ 87U /*!< GPDMA1 HW request is CORDIC_READ */ 364 #define GPDMA1_REQUEST_CORDIC_WRITE 88U /*!< GPDMA1 HW request is CORDIC_WRITE */ 365 #define GPDMA1_REQUEST_LPTIM1_IC1 89U /*!< GPDMA1 HW request is LPTIM1_IC1 */ 366 #define GPDMA1_REQUEST_LPTIM1_IC2 90U /*!< GPDMA1 HW request is LPTIM1_IC2 */ 367 #define GPDMA1_REQUEST_LPTIM1_UE 91U /*!< GPDMA1 HW request is LPTIM1_UE */ 368 #define GPDMA1_REQUEST_LPTIM2_IC1 92U /*!< GPDMA1 HW request is LPTIM2_IC1 */ 369 #define GPDMA1_REQUEST_LPTIM2_IC2 93U /*!< GPDMA1 HW request is LPTIM2_IC2 */ 370 #define GPDMA1_REQUEST_LPTIM2_UE 94U /*!< GPDMA1 HW request is LPTIM2_UE */ 371 #define GPDMA1_REQUEST_SPDIF_RX_DT 95U /*!< GPDMA1 HW request is SPDIF_RX_DT */ 372 #define GPDMA1_REQUEST_SPDIF_RX_CS 96U /*!< GPDMA1 HW request is SPDIF_RX_CS */ 373 #define GPDMA1_REQUEST_ADF1_FLT0 97U /*!< GPDMA1 HW request is ADF1_FLT0 */ 374 #define GPDMA1_REQUEST_UCPD1_TX 98U /*!< GPDMA1 HW request is UCPD1_TX */ 375 #define GPDMA1_REQUEST_UCPD1_RX 99U /*!< GPDMA1 HW request is UCPD1_RX */ 376 #define GPDMA1_REQUEST_PSSI 100U /*!< GPDMA1 HW request is PSSI */ 377 #define GPDMA1_REQUEST_LPUART1_RX 101U /*!< GPDMA1 HW request is LPUART1_RX */ 378 #define GPDMA1_REQUEST_LPUART1_TX 102U /*!< GPDMA1 HW request is LPUART1_TX */ 379 #define GPDMA1_REQUEST_LPTIM3_IC1 103U /*!< GPDMA1 HW request is LPTIM3_IC1 */ 380 #define GPDMA1_REQUEST_LPTIM3_IC2 104U /*!< GPDMA1 HW request is LPTIM3_IC2 */ 381 #define GPDMA1_REQUEST_LPTIM3_UE 105U /*!< GPDMA1 HW request is LPTIM3_UE */ 382 #define GPDMA1_REQUEST_I3C1_RX 106U /*!< GPDMA1 HW request is I3C1_RX */ 383 #define GPDMA1_REQUEST_I3C1_TX 107U /*!< GPDMA1 HW request is I3C1_TX */ 384 #define GPDMA1_REQUEST_I3C1_TC 108U /*!< GPDMA1 HW request is I3C1_TC */ 385 #define GPDMA1_REQUEST_I3C1_RS 109U /*!< GPDMA1 HW request is I3C1_RS */ 386 387 #define GPDMA1_MAX_REQUEST 109U 388 389 /* Software request */ 390 #define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ 391 /** 392 * @} 393 */ 394 395 /** @defgroup DMA_Block_Request DMA Block Request 396 * @brief DMA Block Request 397 * @{ 398 */ 399 #define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ 400 #define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ 401 /** 402 * @} 403 */ 404 405 /** @defgroup DMA_Transfer_Direction DMA Transfer Direction 406 * @brief DMA transfer direction 407 * @{ 408 */ 409 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 410 #define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ 411 #define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ 412 /** 413 * @} 414 */ 415 416 /** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode 417 * @brief DMA Source Increment Mode 418 * @{ 419 */ 420 #define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ 421 #define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode 427 * @brief DMA Destination Increment Mode 428 * @{ 429 */ 430 #define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ 431 #define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ 432 /** 433 * @} 434 */ 435 436 /** @defgroup DMA_Source_Data_Width DMA Source Data Width 437 * @brief DMA Source Data Width 438 * @{ 439 */ 440 #define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ 441 #define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ 442 #define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ 443 #define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source data width : DoubleWord */ 444 /** 445 * @} 446 */ 447 448 /** @defgroup DMA_Destination_Data_Width DMA destination Data Width 449 * @brief DMA destination Data Width 450 * @{ 451 */ 452 #define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ 453 #define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ 454 #define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ 455 #define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination data width : DoubleWord */ 456 457 /** 458 * @} 459 */ 460 461 /** @defgroup DMA_Priority_Level DMA Priority Level 462 * @brief DMA Priority Level 463 * @{ 464 */ 465 #define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ 466 #define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ 467 #define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ 468 #define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ 469 /** 470 * @} 471 */ 472 473 /** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port 474 * @brief DMA Transfer Allocated Port 475 * @{ 476 */ 477 #define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ 478 #define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ 479 #define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ 480 #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode 486 * @brief DMA Transfer Event Mode 487 * @{ 488 */ 489 #define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the 490 HT event is generated at the half of each block */ 491 #define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block 492 and the HT event is generated at the half of the repeated 493 block */ 494 #define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list 495 item and the HT event is generated at the half of each 496 linked-list item */ 497 #define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last 498 linked-list item and the HT event is generated at the half 499 of the last linked-list item */ 500 /** 501 * @} 502 */ 503 504 /** @defgroup DMA_Transfer_Mode DMA Transfer Mode 505 * @brief DMA Transfer Mode 506 * @{ 507 */ 508 #define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ 509 #define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ 510 /** 511 * @} 512 */ 513 514 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 515 * @brief DMA Channel Privilege Attribute 516 * @{ 517 */ 518 519 520 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | (1U<<DMA_CHANNEL_PRIV_VAL_POS)) /*!< Channel is privileged */ 521 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 522 523 #define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ 524 #define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ 525 526 /** 527 * @} 528 */ 529 530 531 /* Exported macro ----------------------------------------------------------------------------------------------------*/ 532 /** @defgroup DMA_Exported_Macros DMA Exported Macros 533 * @brief DMA Exported Macros 534 * @{ 535 */ 536 537 /** @brief Reset DMA handle state. 538 * @param __HANDLE__ : DMA handle. 539 * @retval None. 540 */ 541 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ 542 ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 543 544 /** 545 * @brief Enable the specified DMA Channel. 546 * @param __HANDLE__ : DMA handle. 547 * @retval None 548 */ 549 #define __HAL_DMA_ENABLE(__HANDLE__) \ 550 ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 551 552 /** 553 * @brief Disable the specified DMA Channel. 554 * @param __HANDLE__ : DMA handle. 555 * @retval None 556 */ 557 #define __HAL_DMA_DISABLE(__HANDLE__) \ 558 ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) 559 560 /** 561 * @brief Get the DMA channel pending flags. 562 * @param __HANDLE__ : DMA handle. 563 * @param __FLAG__ : Get the specified flag. 564 * This parameter can be any combination of the following values: 565 * @arg DMA_FLAG_TC : Transfer Complete flag. 566 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 567 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 568 * @arg DMA_FLAG_ULE : Update linked-list Error flag. 569 * @arg DMA_FLAG_USE : User Setting Error flag. 570 * @arg DMA_FLAG_TO : Trigger Overrun flag. 571 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 572 * @arg DMA_FLAG_IDLEF : Idle flag. 573 * @retval The state of FLAG (SET or RESET). 574 */ 575 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ 576 ((__HANDLE__)->Instance->CSR & (__FLAG__)) 577 578 /** 579 * @brief Clear the DMA Channel pending flags. 580 * @param __HANDLE__ : DMA handle. 581 * @param __FLAG__ : Specifies the flag to clear. 582 * This parameter can be any combination of the following values: 583 * @arg DMA_FLAG_TC : Transfer Complete flag. 584 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 585 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 586 * @arg DMA_FLAG_ULE : Update Linked-List Error flag. 587 * @arg DMA_FLAG_USE : User Setting Error flag. 588 * @arg DMA_FLAG_TO : Trigger Overrun flag. 589 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 590 * @retval None 591 */ 592 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 593 ((__HANDLE__)->Instance->CFCR = (__FLAG__)) 594 595 /** 596 * @brief Enable the specified DMA Channel interrupts. 597 * @param __HANDLE__ : DMA handle. 598 * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. 599 * This parameter can be any combination of the following values: 600 * @arg DMA_IT_TC : Transfer Complete interrupt. 601 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 602 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 603 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 604 * @arg DMA_IT_USE : User Setting Error interrupt. 605 * @arg DMA_IT_TO : Trigger Overrun interrupt. 606 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 607 * @retval None 608 */ 609 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 610 ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 611 612 /** 613 * @brief Disable the specified DMA Channel interrupts. 614 * @param __HANDLE__ : DMA handle. 615 * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. 616 * This parameter can be any combination of the following values: 617 * @arg DMA_IT_TC : Transfer Complete interrupt. 618 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 619 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 620 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 621 * @arg DMA_IT_USE : User Setting Error interrupt. 622 * @arg DMA_IT_TO : Trigger Overrun interrupt. 623 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 624 * @retval None 625 */ 626 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 627 ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 628 629 /** 630 * @brief Checks whether the specified DMA Channel interrupt is enabled or not. 631 * @param __HANDLE__ : DMA handle. 632 * @param __INTERRUPT__ : specifies the DMA interrupt source to check. 633 * @arg DMA_IT_TC : Transfer Complete interrupt. 634 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 635 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 636 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 637 * @arg DMA_IT_USE : User Setting Error interrupt. 638 * @arg DMA_IT_TO : Trigger Overrun interrupt. 639 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 640 * @retval The state of DMA_IT (SET or RESET). 641 */ 642 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 643 (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 644 645 /** 646 * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. 647 * @param __HANDLE__ : DMA handle. 648 * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). 649 */ 650 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ 651 MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) 652 653 /** 654 * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. 655 * @param __HANDLE__ : DMA handle. 656 * @retval The number of remaining data units in the current DMA Stream transfer. 657 */ 658 #define __HAL_DMA_GET_COUNTER(__HANDLE__) \ 659 (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) 660 /** 661 * @} 662 */ 663 664 665 /* Include DMA HAL Extension module */ 666 #include "stm32h7rsxx_hal_dma_ex.h" 667 668 669 /* Exported functions ------------------------------------------------------------------------------------------------*/ 670 /** @defgroup DMA_Exported_Functions DMA Exported Functions 671 * @brief DMA Exported Functions 672 * @{ 673 */ 674 675 /** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions 676 * @brief Initialization and De-Initialization Functions 677 * @{ 678 */ 679 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); 680 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); 681 /** 682 * @} 683 */ 684 685 /** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions 686 * @brief I/O Operation Functions 687 * @{ 688 */ 689 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, 690 uint32_t SrcAddress, 691 uint32_t DstAddress, 692 uint32_t SrcDataSize); 693 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, 694 uint32_t SrcAddress, 695 uint32_t DstAddress, 696 uint32_t SrcDataSize); 697 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); 698 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); 699 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, 700 HAL_DMA_LevelCompleteTypeDef CompleteLevel, 701 uint32_t Timeout); 702 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); 703 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, 704 HAL_DMA_CallbackIDTypeDef CallbackID, 705 void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); 706 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, 707 HAL_DMA_CallbackIDTypeDef CallbackID); 708 /** 709 * @} 710 */ 711 712 /** @defgroup DMA_Exported_Functions_Group3 State and Error Functions 713 * @brief State and Error Functions 714 * @{ 715 */ 716 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); 717 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); 718 /** 719 * @} 720 */ 721 722 /** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions 723 * @brief DMA Attributes Functions 724 * @{ 725 */ 726 727 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, 728 uint32_t ChannelAttributes); 729 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, 730 uint32_t *const pChannelAttributes); 731 732 HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); 733 HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, 734 uint32_t *const pLockState); 735 736 737 /** 738 * @} 739 */ 740 741 /** 742 * @} 743 */ 744 745 746 /* Private constants -------------------------------------------------------------------------------------------------*/ 747 /** @defgroup DMA_Private_Constants DMA Private Constants 748 * @brief DMA Private Constants 749 * @{ 750 */ 751 #define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ 752 #define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ 753 #define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ 754 #define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ 755 #define DMA_CHANNEL_ATTR_PRIV_MASK (0x01000000U) /* DMA channel privilege */ 756 #define DMA_CHANNEL_PRIV_VAL_POS 0U 757 #define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ 758 #define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ 759 /** 760 * @} 761 */ 762 763 764 /* Private macros ----------------------------------------------------------------------------------------------------*/ 765 /** @defgroup DMA_Private_Macros DMA Private Macros 766 * @brief DMA Private Macros 767 * @{ 768 */ 769 #define GET_DMA_INSTANCE(__HANDLE__) \ 770 ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) 771 772 #define GET_DMA_CHANNEL(__HANDLE__) \ 773 ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) 774 775 #define IS_DMA_MODE(MODE) \ 776 (((MODE) == DMA_NORMAL) || \ 777 ((MODE) == DMA_PFCTRL)) 778 779 #define IS_DMA_DIRECTION(DIRECTION) \ 780 (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ 781 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 782 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 783 784 #define IS_DMA_LEVEL_COMPLETE(LEVEL) \ 785 (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ 786 ((LEVEL) == HAL_DMA_HALF_TRANSFER)) 787 788 #define IS_DMA_SOURCE_INC(INC) \ 789 (((INC) == DMA_SINC_FIXED) || \ 790 ((INC) == DMA_SINC_INCREMENTED)) 791 792 #define IS_DMA_DESTINATION_INC(INC) \ 793 (((INC) == DMA_DINC_FIXED) || \ 794 ((INC) == DMA_DINC_INCREMENTED)) 795 796 #define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ 797 (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ 798 ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ 799 ((WIDTH) == DMA_SRC_DATAWIDTH_WORD) || \ 800 ((WIDTH) == DMA_SRC_DATAWIDTH_DOUBLEWORD)) 801 802 #define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ 803 (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ 804 ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ 805 ((WIDTH) == DMA_DEST_DATAWIDTH_WORD) || \ 806 ((WIDTH) == DMA_DEST_DATAWIDTH_DOUBLEWORD)) 807 808 #define IS_DMA_BURST_LENGTH(LENGTH) \ 809 (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ 810 ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) 811 812 #define IS_DMA_PRIORITY(PRIORITY) \ 813 (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ 814 ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ 815 ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ 816 ((PRIORITY) == DMA_HIGH_PRIORITY)) 817 818 #define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ 819 (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) 820 821 #define IS_DMA_REQUEST(REQUEST) \ 822 (((REQUEST) == DMA_REQUEST_SW) || \ 823 ((REQUEST) <= GPDMA1_REQUEST_I3C1_RS)) 824 825 #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ 826 (((MODE) == DMA_BREQ_SINGLE_BURST) || \ 827 ((MODE) == DMA_BREQ_BLOCK)) 828 829 #define IS_DMA_TCEM_EVENT_MODE(MODE) \ 830 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 831 ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ 832 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 833 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 834 835 #define IS_DMA_BLOCK_SIZE(SIZE) \ 836 (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) 837 838 #define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \ 839 (((INSTANCE)->MISR & (GLOBAL_FLAG))) 840 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 841 (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ 842 ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) 843 844 /** 845 * @} 846 */ 847 848 849 /* Private functions -------------------------------------------------------------------------------------------------*/ 850 /** @defgroup DMA_Private_Functions DMA Private Functions 851 * @brief DMA Private Functions 852 * @{ 853 */ 854 855 /** 856 * @} 857 */ 858 859 /** 860 * @} 861 */ 862 863 /** 864 * @} 865 */ 866 867 /** 868 * @} 869 */ 870 871 #ifdef __cplusplus 872 } 873 #endif 874 875 #endif /* STM32H7RSxx_HAL_DMA_H */ 876
