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Searched refs:FifoThreshold (Results 1 – 25 of 47) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_hal_qspi.c304 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
346 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
1274 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1291 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1419 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1436 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
2391 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2395 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_qspi.c306 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
354 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
1291 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1308 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1459 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1476 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
2493 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2497 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_qspi.c306 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
354 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
1299 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1316 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1444 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1461 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
2418 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2422 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_qspi.c305 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
355 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
1307 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1324 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1452 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1469 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
2427 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2431 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
Dstm32l4xx_hal_ospi.c333 assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold)); in HAL_OSPI_Init()
407 …MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR… in HAL_OSPI_Init()
1424 if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) in HAL_OSPI_Transmit_DMA()
1438 if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) in HAL_OSPI_Transmit_DMA()
1548 if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) in HAL_OSPI_Receive_DMA()
1562 if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) in HAL_OSPI_Receive_DMA()
2410 hospi->Init.FifoThreshold = Threshold; in HAL_OSPI_SetFifoThreshold()
2413 …MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR… in HAL_OSPI_SetFifoThreshold()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_qspi.c305 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
353 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
1283 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1300 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1428 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1445 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
2403 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2407 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_ospi.c323 assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold)); in HAL_OSPI_Init()
390 …MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR… in HAL_OSPI_Init()
1411 if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) in HAL_OSPI_Transmit_DMA()
1425 if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) in HAL_OSPI_Transmit_DMA()
1535 if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) in HAL_OSPI_Receive_DMA()
1549 if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) in HAL_OSPI_Receive_DMA()
2395 hospi->Init.FifoThreshold = Threshold; in HAL_OSPI_SetFifoThreshold()
2398 …MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR… in HAL_OSPI_SetFifoThreshold()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_ospi.c335 assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold)); in HAL_OSPI_Init()
404 …MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR… in HAL_OSPI_Init()
1449 if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) in HAL_OSPI_Transmit_DMA()
1463 if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) in HAL_OSPI_Transmit_DMA()
1631 if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) in HAL_OSPI_Receive_DMA()
1645 if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) in HAL_OSPI_Receive_DMA()
2528 hospi->Init.FifoThreshold = Threshold; in HAL_OSPI_SetFifoThreshold()
2531 …MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR… in HAL_OSPI_SetFifoThreshold()
Dstm32u5xx_hal_spi.c260 assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
265 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
413 hspi->Init.FifoThreshold | hspi->Init.DataSize)); in HAL_SPI_Init()
952 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
996 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) in HAL_SPI_Transmit()
1002 … else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
1077 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); in HAL_SPI_Receive()
1393 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); in HAL_SPI_TransmitReceive()
4027 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; in SPI_GetPacketSize()
Dstm32u5xx_hal_mdf.c3331 assert_param(IS_MDF_FIFO_THRESHOLD(pFilterConfig->FifoThreshold)); in MDF_AcqStart()
3336 hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | in MDF_AcqStart()
3351 hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | in MDF_AcqStart()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_spi.c260 assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
265 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
413 hspi->Init.FifoThreshold | hspi->Init.DataSize)); in HAL_SPI_Init()
942 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
986 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) in HAL_SPI_Transmit()
992 … else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
1067 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); in HAL_SPI_Receive()
1346 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); in HAL_SPI_TransmitReceive()
3898 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; in SPI_GetPacketSize()
Dstm32n6xx_hal_mdf.c3320 assert_param(IS_MDF_FIFO_THRESHOLD(pFilterConfig->FifoThreshold)); in MDF_AcqStart()
3325 hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | in MDF_AcqStart()
3340 hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | in MDF_AcqStart()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_spi.c262 assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
267 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
415 hspi->Init.FifoThreshold | hspi->Init.DataSize)); in HAL_SPI_Init()
954 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
998 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) in HAL_SPI_Transmit()
1004 … else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
1079 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); in HAL_SPI_Receive()
1368 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); in HAL_SPI_TransmitReceive()
4020 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; in SPI_GetPacketSize()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_spi.c258 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
395 hspi->Init.FifoThreshold | hspi->Init.DataSize)); in HAL_SPI_Init()
928 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
972 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) in HAL_SPI_Transmit()
978 … else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
1053 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); in HAL_SPI_Receive()
1332 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); in HAL_SPI_TransmitReceive()
3995 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; in SPI_GetPacketSize()
Dstm32h7xx_hal_qspi.c320 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
364 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
2304 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2308 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
Dstm32h7xx_hal_ospi.c364 assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold)); in HAL_OSPI_Init()
433 …MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR… in HAL_OSPI_Init()
2401 hospi->Init.FifoThreshold = Threshold; in HAL_OSPI_SetFifoThreshold()
2404 …MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR… in HAL_OSPI_SetFifoThreshold()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_spi.c257 assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
262 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
407 hspi->Init.FifoThreshold | hspi->Init.DataSize)); in HAL_SPI_Init()
930 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
974 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) in HAL_SPI_Transmit()
980 … else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
3732 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; in SPI_GetPacketSize()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_spi.c259 assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
264 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
409 hspi->Init.FifoThreshold | hspi->Init.DataSize)); in HAL_SPI_Init()
941 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
984 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) in HAL_SPI_Transmit()
990 … else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
3775 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; in SPI_GetPacketSize()
Dstm32h7rsxx_hal_mdf.c2024 assert_param(IS_MDF_FIFO_THRESHOLD(pFilterConfig->FifoThreshold)); in MDF_AcqStart()
2029 hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | in MDF_AcqStart()
2037 hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | in MDF_AcqStart()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_spi.c257 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); in HAL_SPI_Init()
391 hspi->Init.FifoThreshold | hspi->Init.DataSize)); in HAL_SPI_Init()
927 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
970 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) in HAL_SPI_Transmit()
976 … else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) in HAL_SPI_Transmit()
3881 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; in SPI_GetPacketSize()
Dstm32mp1xx_hal_qspi.c326 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
377 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
2366 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2370 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_dma.h1364 …id LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) in LL_DMA_ConfigFifo() argument
1366 …t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); in LL_DMA_ConfigFifo()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma.h1397 …id LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) in LL_DMA_ConfigFifo() argument
1399 …t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); in LL_DMA_ConfigFifo()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma.h1374 …id LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) in LL_DMA_ConfigFifo() argument
1376 …t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); in LL_DMA_ConfigFifo()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_dma.h1631 …id LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) in LL_DMA_ConfigFifo() argument
1635 …+ LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold); in LL_DMA_ConfigFifo()

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