Searched refs:FSMC_PATTx_ATTHOLDx_Pos (Results 1 – 5 of 5) sorted by relevance
634 … ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()642 … ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()936 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | in FSMC_PCCARD_AttributeSpace_Timing_Init()
5280 #define FSMC_PATTx_ATTHOLDx_Pos (16U) macro5281 #define FSMC_PATTx_ATTHOLDx_Msk (0xFFUL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */5283 #define FSMC_PATTx_ATTHOLDx_0 (0x01UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */5284 #define FSMC_PATTx_ATTHOLDx_1 (0x02UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */5285 #define FSMC_PATTx_ATTHOLDx_2 (0x04UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */5286 #define FSMC_PATTx_ATTHOLDx_3 (0x08UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */5287 #define FSMC_PATTx_ATTHOLDx_4 (0x10UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */5288 #define FSMC_PATTx_ATTHOLDx_5 (0x20UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */5289 #define FSMC_PATTx_ATTHOLDx_6 (0x40UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */5290 #define FSMC_PATTx_ATTHOLDx_7 (0x80UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
5205 #define FSMC_PATTx_ATTHOLDx_Pos (16U) macro5206 #define FSMC_PATTx_ATTHOLDx_Msk (0xFFUL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */5208 #define FSMC_PATTx_ATTHOLDx_0 (0x01UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */5209 #define FSMC_PATTx_ATTHOLDx_1 (0x02UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */5210 #define FSMC_PATTx_ATTHOLDx_2 (0x04UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */5211 #define FSMC_PATTx_ATTHOLDx_3 (0x08UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */5212 #define FSMC_PATTx_ATTHOLDx_4 (0x10UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */5213 #define FSMC_PATTx_ATTHOLDx_5 (0x20UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */5214 #define FSMC_PATTx_ATTHOLDx_6 (0x40UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */5215 #define FSMC_PATTx_ATTHOLDx_7 (0x80UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
5433 #define FSMC_PATTx_ATTHOLDx_Pos (16U) macro5434 #define FSMC_PATTx_ATTHOLDx_Msk (0xFFUL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */5436 #define FSMC_PATTx_ATTHOLDx_0 (0x01UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */5437 #define FSMC_PATTx_ATTHOLDx_1 (0x02UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */5438 #define FSMC_PATTx_ATTHOLDx_2 (0x04UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */5439 #define FSMC_PATTx_ATTHOLDx_3 (0x08UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */5440 #define FSMC_PATTx_ATTHOLDx_4 (0x10UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */5441 #define FSMC_PATTx_ATTHOLDx_5 (0x20UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */5442 #define FSMC_PATTx_ATTHOLDx_6 (0x40UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */5443 #define FSMC_PATTx_ATTHOLDx_7 (0x80UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
5503 #define FSMC_PATTx_ATTHOLDx_Pos (16U) macro5504 #define FSMC_PATTx_ATTHOLDx_Msk (0xFFUL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */5506 #define FSMC_PATTx_ATTHOLDx_0 (0x01UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */5507 #define FSMC_PATTx_ATTHOLDx_1 (0x02UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */5508 #define FSMC_PATTx_ATTHOLDx_2 (0x04UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */5509 #define FSMC_PATTx_ATTHOLDx_3 (0x08UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */5510 #define FSMC_PATTx_ATTHOLDx_4 (0x10UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */5511 #define FSMC_PATTx_ATTHOLDx_5 (0x20UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */5512 #define FSMC_PATTx_ATTHOLDx_6 (0x40UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */5513 #define FSMC_PATTx_ATTHOLDx_7 (0x80UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
