Searched refs:FSMC_BWTR3_ADDSET_Pos (Results 1 – 13 of 13) sorted by relevance
7205 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7206 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7208 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7209 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7210 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7211 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7055 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7056 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7058 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7059 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7060 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7061 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7354 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7355 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7357 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7358 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7359 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7360 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7504 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7505 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7507 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7508 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7509 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7510 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7099 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7100 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7102 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7103 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7104 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7105 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7281 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7282 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7284 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7285 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7286 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7287 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7573 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7574 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7576 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7577 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7578 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7579 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7399 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7400 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7402 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7403 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7404 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7405 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7217 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7218 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7220 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7221 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7222 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7223 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7211 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7212 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7214 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7215 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7216 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7217 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7213 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7214 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7216 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7217 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7218 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7219 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7537 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7538 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7540 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7541 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7542 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7543 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7578 #define FSMC_BWTR3_ADDSET_Pos (0U) macro7579 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */7581 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */7582 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */7583 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */7584 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
