Searched refs:FSMC_BTR4_ADDSET_Pos (Results 1 – 13 of 13) sorted by relevance
7060 #define FSMC_BTR4_ADDSET_Pos (0U) macro7061 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7063 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7064 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7065 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7066 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
6910 #define FSMC_BTR4_ADDSET_Pos (0U) macro6911 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */6913 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */6914 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */6915 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */6916 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7209 #define FSMC_BTR4_ADDSET_Pos (0U) macro7210 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7212 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7213 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7214 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7215 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7359 #define FSMC_BTR4_ADDSET_Pos (0U) macro7360 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7362 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7363 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7364 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7365 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
6954 #define FSMC_BTR4_ADDSET_Pos (0U) macro6955 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */6957 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */6958 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */6959 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */6960 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7136 #define FSMC_BTR4_ADDSET_Pos (0U) macro7137 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7139 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7140 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7141 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7142 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7428 #define FSMC_BTR4_ADDSET_Pos (0U) macro7429 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7431 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7432 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7433 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7434 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7254 #define FSMC_BTR4_ADDSET_Pos (0U) macro7255 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7257 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7258 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7259 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7260 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7072 #define FSMC_BTR4_ADDSET_Pos (0U) macro7073 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7075 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7076 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7077 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7078 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7066 #define FSMC_BTR4_ADDSET_Pos (0U) macro7067 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7069 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7070 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7071 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7072 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7068 #define FSMC_BTR4_ADDSET_Pos (0U) macro7069 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7071 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7072 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7073 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7074 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7392 #define FSMC_BTR4_ADDSET_Pos (0U) macro7393 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7395 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7396 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7397 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7398 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7433 #define FSMC_BTR4_ADDSET_Pos (0U) macro7434 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */7436 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */7437 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */7438 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */7439 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
