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Searched refs:FSMC_BTR3_ADDHLD_Pos (Results 1 – 13 of 13) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h7009 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7010 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7012 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7013 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7014 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7015 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f205xx.h6859 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
6860 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
6862 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
6863 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
6864 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
6865 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f207xx.h7158 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7159 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7161 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7162 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7163 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7164 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f217xx.h7308 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7309 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7311 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7312 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7313 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7314 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h6903 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
6904 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
6906 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
6907 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
6908 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
6909 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f415xx.h7085 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7086 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7088 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7089 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7090 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7091 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f423xx.h7377 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7378 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7380 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7381 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7382 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7383 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f407xx.h7203 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7204 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7206 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7207 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7208 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7209 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f412zx.h7021 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7022 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7024 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7025 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7026 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7027 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f412rx.h7015 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7016 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7018 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7019 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7020 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7021 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f412vx.h7017 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7018 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7020 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7021 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7022 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7023 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f413xx.h7341 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7342 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7344 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7345 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7346 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7347 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f417xx.h7382 #define FSMC_BTR3_ADDHLD_Pos (4U) macro
7383 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7385 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7386 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7387 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7388 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */