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Searched refs:FSMC_BCR3_MTYP_Pos (Results 1 – 13 of 13) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h6788 #define FSMC_BCR3_MTYP_Pos (2U) macro
6789 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6791 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6792 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f205xx.h6638 #define FSMC_BCR3_MTYP_Pos (2U) macro
6639 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6641 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6642 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f207xx.h6937 #define FSMC_BCR3_MTYP_Pos (2U) macro
6938 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6940 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6941 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f217xx.h7087 #define FSMC_BCR3_MTYP_Pos (2U) macro
7088 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
7090 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
7091 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h6670 #define FSMC_BCR3_MTYP_Pos (2U) macro
6671 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6673 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6674 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f415xx.h6852 #define FSMC_BCR3_MTYP_Pos (2U) macro
6853 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6855 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6856 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f423xx.h7150 #define FSMC_BCR3_MTYP_Pos (2U) macro
7151 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
7153 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
7154 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f407xx.h6970 #define FSMC_BCR3_MTYP_Pos (2U) macro
6971 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6973 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6974 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f412zx.h6794 #define FSMC_BCR3_MTYP_Pos (2U) macro
6795 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6797 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6798 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f412rx.h6788 #define FSMC_BCR3_MTYP_Pos (2U) macro
6789 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6791 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6792 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f412vx.h6790 #define FSMC_BCR3_MTYP_Pos (2U) macro
6791 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6793 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6794 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f413xx.h7114 #define FSMC_BCR3_MTYP_Pos (2U) macro
7115 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
7117 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
7118 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
Dstm32f417xx.h7149 #define FSMC_BCR3_MTYP_Pos (2U) macro
7150 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
7152 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
7153 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */