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Searched refs:FSMC_BCR2_MWID_Pos (Results 1 – 13 of 13) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h6743 #define FSMC_BCR2_MWID_Pos (4U) macro
6744 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6746 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6747 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f205xx.h6593 #define FSMC_BCR2_MWID_Pos (4U) macro
6594 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6596 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6597 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f207xx.h6892 #define FSMC_BCR2_MWID_Pos (4U) macro
6893 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6895 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6896 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f217xx.h7042 #define FSMC_BCR2_MWID_Pos (4U) macro
7043 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
7045 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
7046 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h6619 #define FSMC_BCR2_MWID_Pos (4U) macro
6620 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6622 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6623 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f415xx.h6801 #define FSMC_BCR2_MWID_Pos (4U) macro
6802 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6804 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6805 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f423xx.h7102 #define FSMC_BCR2_MWID_Pos (4U) macro
7103 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
7105 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
7106 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f407xx.h6919 #define FSMC_BCR2_MWID_Pos (4U) macro
6920 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6922 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6923 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f412zx.h6746 #define FSMC_BCR2_MWID_Pos (4U) macro
6747 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6749 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6750 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f412rx.h6740 #define FSMC_BCR2_MWID_Pos (4U) macro
6741 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6743 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6744 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f412vx.h6742 #define FSMC_BCR2_MWID_Pos (4U) macro
6743 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6745 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6746 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f413xx.h7066 #define FSMC_BCR2_MWID_Pos (4U) macro
7067 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
7069 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
7070 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
Dstm32f417xx.h7098 #define FSMC_BCR2_MWID_Pos (4U) macro
7099 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
7101 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
7102 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */