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Searched refs:FSMC_BCR2_MTYP_Pos (Results 1 – 13 of 13) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h6737 #define FSMC_BCR2_MTYP_Pos (2U) macro
6738 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6740 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6741 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f205xx.h6587 #define FSMC_BCR2_MTYP_Pos (2U) macro
6588 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6590 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6591 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f207xx.h6886 #define FSMC_BCR2_MTYP_Pos (2U) macro
6887 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6889 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6890 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f217xx.h7036 #define FSMC_BCR2_MTYP_Pos (2U) macro
7037 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
7039 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
7040 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h6613 #define FSMC_BCR2_MTYP_Pos (2U) macro
6614 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6616 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6617 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f415xx.h6795 #define FSMC_BCR2_MTYP_Pos (2U) macro
6796 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6798 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6799 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f423xx.h7096 #define FSMC_BCR2_MTYP_Pos (2U) macro
7097 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
7099 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
7100 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f407xx.h6913 #define FSMC_BCR2_MTYP_Pos (2U) macro
6914 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6916 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6917 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f412zx.h6740 #define FSMC_BCR2_MTYP_Pos (2U) macro
6741 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6743 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6744 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f412rx.h6734 #define FSMC_BCR2_MTYP_Pos (2U) macro
6735 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6737 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6738 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f412vx.h6736 #define FSMC_BCR2_MTYP_Pos (2U) macro
6737 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6739 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6740 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f413xx.h7060 #define FSMC_BCR2_MTYP_Pos (2U) macro
7061 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
7063 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
7064 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
Dstm32f417xx.h7092 #define FSMC_BCR2_MTYP_Pos (2U) macro
7093 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
7095 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
7096 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */