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Searched refs:FMC_SDTR2_TWR_Pos (Results 1 – 21 of 21) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h7458 #define FMC_SDTR2_TWR_Pos (16U) macro
7459 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
7461 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
7462 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
7463 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f722xx.h7442 #define FMC_SDTR2_TWR_Pos (16U) macro
7443 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
7445 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
7446 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
7447 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f730xx.h7672 #define FMC_SDTR2_TWR_Pos (16U) macro
7673 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
7675 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
7676 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
7677 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f733xx.h7672 #define FMC_SDTR2_TWR_Pos (16U) macro
7673 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
7675 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
7676 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
7677 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f732xx.h7656 #define FMC_SDTR2_TWR_Pos (16U) macro
7657 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
7659 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
7660 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
7661 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f750xx.h8476 #define FMC_SDTR2_TWR_Pos (16U) macro
8477 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8479 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8480 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8481 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f745xx.h8233 #define FMC_SDTR2_TWR_Pos (16U) macro
8234 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8236 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8237 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8238 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f756xx.h8476 #define FMC_SDTR2_TWR_Pos (16U) macro
8477 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8479 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8480 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8481 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f746xx.h8288 #define FMC_SDTR2_TWR_Pos (16U) macro
8289 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8291 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8292 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8293 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f765xx.h8746 #define FMC_SDTR2_TWR_Pos (16U) macro
8747 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8749 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8750 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8751 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f777xx.h9028 #define FMC_SDTR2_TWR_Pos (16U) macro
9029 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
9031 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
9032 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
9033 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f767xx.h8840 #define FMC_SDTR2_TWR_Pos (16U) macro
8841 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8843 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8844 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8845 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f779xx.h9111 #define FMC_SDTR2_TWR_Pos (16U) macro
9112 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
9114 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
9115 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
9116 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f769xx.h8923 #define FMC_SDTR2_TWR_Pos (16U) macro
8924 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8926 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8927 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8928 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h8622 #define FMC_SDTR2_TWR_Pos (16U) macro
8623 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8625 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8626 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8627 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f446xx.h8005 #define FMC_SDTR2_TWR_Pos (16U) macro
8006 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8008 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8009 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8010 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f429xx.h8681 #define FMC_SDTR2_TWR_Pos (16U) macro
8682 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8684 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8685 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8686 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f439xx.h8868 #define FMC_SDTR2_TWR_Pos (16U) macro
8869 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8871 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8872 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8873 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f437xx.h8814 #define FMC_SDTR2_TWR_Pos (16U) macro
8815 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8817 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8818 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8819 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f469xx.h11445 #define FMC_SDTR2_TWR_Pos (16U) macro
11446 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
11448 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
11449 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
11450 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
Dstm32f479xx.h11635 #define FMC_SDTR2_TWR_Pos (16U) macro
11636 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
11638 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
11639 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
11640 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */