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Searched refs:FMC_SDTR2_TRC_Pos (Results 1 – 21 of 21) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h7452 #define FMC_SDTR2_TRC_Pos (12U) macro
7453 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
7455 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
7456 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
7457 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f722xx.h7436 #define FMC_SDTR2_TRC_Pos (12U) macro
7437 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
7439 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
7440 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
7441 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f730xx.h7666 #define FMC_SDTR2_TRC_Pos (12U) macro
7667 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
7669 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
7670 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
7671 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f733xx.h7666 #define FMC_SDTR2_TRC_Pos (12U) macro
7667 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
7669 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
7670 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
7671 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f732xx.h7650 #define FMC_SDTR2_TRC_Pos (12U) macro
7651 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
7653 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
7654 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
7655 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f750xx.h8470 #define FMC_SDTR2_TRC_Pos (12U) macro
8471 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8473 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8474 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8475 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f745xx.h8227 #define FMC_SDTR2_TRC_Pos (12U) macro
8228 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8230 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8231 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8232 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f756xx.h8470 #define FMC_SDTR2_TRC_Pos (12U) macro
8471 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8473 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8474 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8475 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f746xx.h8282 #define FMC_SDTR2_TRC_Pos (12U) macro
8283 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8285 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8286 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8287 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f765xx.h8740 #define FMC_SDTR2_TRC_Pos (12U) macro
8741 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8743 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8744 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8745 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f777xx.h9022 #define FMC_SDTR2_TRC_Pos (12U) macro
9023 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
9025 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
9026 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
9027 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f767xx.h8834 #define FMC_SDTR2_TRC_Pos (12U) macro
8835 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8837 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8838 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8839 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f779xx.h9105 #define FMC_SDTR2_TRC_Pos (12U) macro
9106 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
9108 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
9109 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
9110 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f769xx.h8917 #define FMC_SDTR2_TRC_Pos (12U) macro
8918 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8920 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8921 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8922 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h8615 #define FMC_SDTR2_TRC_Pos (12U) macro
8616 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8618 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8619 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8620 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f446xx.h7998 #define FMC_SDTR2_TRC_Pos (12U) macro
7999 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8001 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8002 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8003 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f429xx.h8674 #define FMC_SDTR2_TRC_Pos (12U) macro
8675 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8677 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8678 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8679 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f439xx.h8861 #define FMC_SDTR2_TRC_Pos (12U) macro
8862 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8864 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8865 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8866 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f437xx.h8807 #define FMC_SDTR2_TRC_Pos (12U) macro
8808 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8810 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8811 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8812 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f469xx.h11438 #define FMC_SDTR2_TRC_Pos (12U) macro
11439 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
11441 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
11442 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
11443 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
Dstm32f479xx.h11628 #define FMC_SDTR2_TRC_Pos (12U) macro
11629 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
11631 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
11632 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
11633 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */