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Searched refs:FMC_SDTR2_TRAS_Pos (Results 1 – 21 of 21) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h7445 #define FMC_SDTR2_TRAS_Pos (8U) macro
7446 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
7448 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
7449 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
7450 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
7451 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f722xx.h7429 #define FMC_SDTR2_TRAS_Pos (8U) macro
7430 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
7432 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
7433 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
7434 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
7435 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f730xx.h7659 #define FMC_SDTR2_TRAS_Pos (8U) macro
7660 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
7662 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
7663 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
7664 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
7665 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f733xx.h7659 #define FMC_SDTR2_TRAS_Pos (8U) macro
7660 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
7662 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
7663 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
7664 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
7665 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f732xx.h7643 #define FMC_SDTR2_TRAS_Pos (8U) macro
7644 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
7646 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
7647 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
7648 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
7649 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f750xx.h8463 #define FMC_SDTR2_TRAS_Pos (8U) macro
8464 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8466 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8467 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8468 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8469 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f745xx.h8220 #define FMC_SDTR2_TRAS_Pos (8U) macro
8221 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8223 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8224 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8225 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8226 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f756xx.h8463 #define FMC_SDTR2_TRAS_Pos (8U) macro
8464 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8466 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8467 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8468 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8469 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f746xx.h8275 #define FMC_SDTR2_TRAS_Pos (8U) macro
8276 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8278 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8279 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8280 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8281 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f765xx.h8733 #define FMC_SDTR2_TRAS_Pos (8U) macro
8734 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8736 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8737 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8738 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8739 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f777xx.h9015 #define FMC_SDTR2_TRAS_Pos (8U) macro
9016 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
9018 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
9019 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
9020 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
9021 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f767xx.h8827 #define FMC_SDTR2_TRAS_Pos (8U) macro
8828 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8830 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8831 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8832 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8833 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f779xx.h9098 #define FMC_SDTR2_TRAS_Pos (8U) macro
9099 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
9101 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
9102 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
9103 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
9104 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f769xx.h8910 #define FMC_SDTR2_TRAS_Pos (8U) macro
8911 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8913 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8914 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8915 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8916 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h8607 #define FMC_SDTR2_TRAS_Pos (8U) macro
8608 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8610 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8611 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8612 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8613 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f446xx.h7990 #define FMC_SDTR2_TRAS_Pos (8U) macro
7991 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
7993 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
7994 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
7995 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
7996 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f429xx.h8666 #define FMC_SDTR2_TRAS_Pos (8U) macro
8667 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8669 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8670 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8671 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8672 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f439xx.h8853 #define FMC_SDTR2_TRAS_Pos (8U) macro
8854 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8856 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8857 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8858 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8859 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f437xx.h8799 #define FMC_SDTR2_TRAS_Pos (8U) macro
8800 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
8802 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8803 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8804 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8805 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f469xx.h11430 #define FMC_SDTR2_TRAS_Pos (8U) macro
11431 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
11433 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
11434 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
11435 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
11436 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
Dstm32f479xx.h11620 #define FMC_SDTR2_TRAS_Pos (8U) macro
11621 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
11623 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
11624 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
11625 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
11626 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */