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Searched refs:FMC_SDTR1_TWR_Pos (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c874 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | in FMC_SDRAM_Timing_Init()
891 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | in FMC_SDRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fmc.c1266 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | in FMC_SDRAM_Timing_Init()
1283 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | in FMC_SDRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h7411 #define FMC_SDTR1_TWR_Pos (16U) macro
7412 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
7414 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
7415 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
7416 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f722xx.h7395 #define FMC_SDTR1_TWR_Pos (16U) macro
7396 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
7398 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
7399 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
7400 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f730xx.h7625 #define FMC_SDTR1_TWR_Pos (16U) macro
7626 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
7628 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
7629 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
7630 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f733xx.h7625 #define FMC_SDTR1_TWR_Pos (16U) macro
7626 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
7628 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
7629 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
7630 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f732xx.h7609 #define FMC_SDTR1_TWR_Pos (16U) macro
7610 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
7612 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
7613 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
7614 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f750xx.h8429 #define FMC_SDTR1_TWR_Pos (16U) macro
8430 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8432 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8433 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8434 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f745xx.h8186 #define FMC_SDTR1_TWR_Pos (16U) macro
8187 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8189 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8190 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8191 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f756xx.h8429 #define FMC_SDTR1_TWR_Pos (16U) macro
8430 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8432 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8433 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8434 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f746xx.h8241 #define FMC_SDTR1_TWR_Pos (16U) macro
8242 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8244 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8245 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8246 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f765xx.h8699 #define FMC_SDTR1_TWR_Pos (16U) macro
8700 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8702 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8703 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8704 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f777xx.h8981 #define FMC_SDTR1_TWR_Pos (16U) macro
8982 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8984 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8985 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8986 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f767xx.h8793 #define FMC_SDTR1_TWR_Pos (16U) macro
8794 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8796 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8797 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8798 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f779xx.h9064 #define FMC_SDTR1_TWR_Pos (16U) macro
9065 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
9067 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
9068 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
9069 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f769xx.h8876 #define FMC_SDTR1_TWR_Pos (16U) macro
8877 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8879 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8880 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8881 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h8569 #define FMC_SDTR1_TWR_Pos (16U) macro
8570 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8572 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8573 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8574 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f446xx.h7952 #define FMC_SDTR1_TWR_Pos (16U) macro
7953 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
7955 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
7956 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
7957 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f429xx.h8628 #define FMC_SDTR1_TWR_Pos (16U) macro
8629 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8631 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8632 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8633 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f439xx.h8815 #define FMC_SDTR1_TWR_Pos (16U) macro
8816 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8818 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8819 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8820 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f437xx.h8761 #define FMC_SDTR1_TWR_Pos (16U) macro
8762 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
8764 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
8765 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
8766 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f469xx.h11392 #define FMC_SDTR1_TWR_Pos (16U) macro
11393 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
11395 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
11396 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
11397 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
Dstm32f479xx.h11582 #define FMC_SDTR1_TWR_Pos (16U) macro
11583 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
11585 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
11586 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
11587 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */