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Searched refs:FMC_SDTR1_TRCD_Pos (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c876 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); in FMC_SDRAM_Timing_Init()
892 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); in FMC_SDRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fmc.c1268 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); in FMC_SDRAM_Timing_Init()
1284 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); in FMC_SDRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h7423 #define FMC_SDTR1_TRCD_Pos (24U) macro
7424 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
7426 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
7427 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
7428 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f722xx.h7407 #define FMC_SDTR1_TRCD_Pos (24U) macro
7408 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
7410 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
7411 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
7412 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f730xx.h7637 #define FMC_SDTR1_TRCD_Pos (24U) macro
7638 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
7640 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
7641 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
7642 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f733xx.h7637 #define FMC_SDTR1_TRCD_Pos (24U) macro
7638 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
7640 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
7641 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
7642 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f732xx.h7621 #define FMC_SDTR1_TRCD_Pos (24U) macro
7622 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
7624 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
7625 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
7626 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f750xx.h8441 #define FMC_SDTR1_TRCD_Pos (24U) macro
8442 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8444 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8445 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8446 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f745xx.h8198 #define FMC_SDTR1_TRCD_Pos (24U) macro
8199 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8201 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8202 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8203 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f756xx.h8441 #define FMC_SDTR1_TRCD_Pos (24U) macro
8442 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8444 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8445 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8446 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f746xx.h8253 #define FMC_SDTR1_TRCD_Pos (24U) macro
8254 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8256 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8257 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8258 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f765xx.h8711 #define FMC_SDTR1_TRCD_Pos (24U) macro
8712 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8714 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8715 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8716 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f777xx.h8993 #define FMC_SDTR1_TRCD_Pos (24U) macro
8994 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8996 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8997 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8998 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f767xx.h8805 #define FMC_SDTR1_TRCD_Pos (24U) macro
8806 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8808 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8809 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8810 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f779xx.h9076 #define FMC_SDTR1_TRCD_Pos (24U) macro
9077 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
9079 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
9080 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
9081 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f769xx.h8888 #define FMC_SDTR1_TRCD_Pos (24U) macro
8889 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8891 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8892 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8893 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h8583 #define FMC_SDTR1_TRCD_Pos (24U) macro
8584 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8586 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8587 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8588 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f446xx.h7966 #define FMC_SDTR1_TRCD_Pos (24U) macro
7967 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
7969 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
7970 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
7971 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f429xx.h8642 #define FMC_SDTR1_TRCD_Pos (24U) macro
8643 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8645 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8646 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8647 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f439xx.h8829 #define FMC_SDTR1_TRCD_Pos (24U) macro
8830 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8832 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8833 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8834 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f437xx.h8775 #define FMC_SDTR1_TRCD_Pos (24U) macro
8776 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
8778 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
8779 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
8780 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f469xx.h11406 #define FMC_SDTR1_TRCD_Pos (24U) macro
11407 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
11409 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
11410 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
11411 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
Dstm32f479xx.h11596 #define FMC_SDTR1_TRCD_Pos (24U) macro
11597 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
11599 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
11600 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
11601 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */