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Searched refs:FMC_SDCR1_SDCLK_Pos (Results 1 – 21 of 21) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h7328 #define FMC_SDCR1_SDCLK_Pos (10U) macro
7329 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
7331 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
7332 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f722xx.h7312 #define FMC_SDCR1_SDCLK_Pos (10U) macro
7313 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
7315 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
7316 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f730xx.h7542 #define FMC_SDCR1_SDCLK_Pos (10U) macro
7543 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
7545 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
7546 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f733xx.h7542 #define FMC_SDCR1_SDCLK_Pos (10U) macro
7543 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
7545 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
7546 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f732xx.h7526 #define FMC_SDCR1_SDCLK_Pos (10U) macro
7527 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
7529 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
7530 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f750xx.h8346 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8347 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8349 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8350 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f745xx.h8103 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8104 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8106 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8107 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f756xx.h8346 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8347 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8349 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8350 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f746xx.h8158 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8159 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8161 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8162 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f765xx.h8616 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8617 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8619 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8620 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f777xx.h8898 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8899 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8901 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8902 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f767xx.h8710 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8711 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8713 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8714 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f779xx.h8981 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8982 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8984 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8985 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f769xx.h8793 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8794 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8796 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8797 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h8472 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8473 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8475 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8476 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f446xx.h7855 #define FMC_SDCR1_SDCLK_Pos (10U) macro
7856 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
7858 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
7859 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f429xx.h8531 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8532 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8534 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8535 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f439xx.h8718 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8719 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8721 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8722 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f437xx.h8664 #define FMC_SDCR1_SDCLK_Pos (10U) macro
8665 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8667 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8668 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f469xx.h11295 #define FMC_SDCR1_SDCLK_Pos (10U) macro
11296 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
11298 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
11299 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
Dstm32f479xx.h11485 #define FMC_SDCR1_SDCLK_Pos (10U) macro
11486 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
11488 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
11489 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */